Module Definition
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Module Instance : tb.dut.i_reg_wrap.u_reg.u_reg_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 100.00 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
TOTAL3434100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
ALWAYS6566100.00
ALWAYS7188100.00
ALWAYS8466100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11311100.00
ALWAYS12033100.00

51 52 1/1 assign a_ack = tl_i.a_valid & tl_o.a_ready; 53 1/1 assign d_ack = tl_o.d_valid & tl_i.d_ready; 54 // Request signal 55 1/1 assign wr_req = a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)); 56 1/1 assign rd_req = a_ack & (tl_i.a_opcode == Get); 57 58 1/1 assign we_o = wr_req & ~err_internal; 59 1/1 assign re_o = rd_req & ~err_internal; 60 1/1 assign addr_o = {tl_i.a_address[RegAw-1:2], 2'b00}; // generate always word-align 61 1/1 assign wdata_o = tl_i.a_data; 62 1/1 assign be_o = tl_i.a_mask; 63 64 always_ff @(posedge clk_i or negedge rst_ni) begin 65 2/2 if (!rst_ni) outstanding <= 1'b0; 66 2/2 else if (a_ack) outstanding <= 1'b1; 67 2/2 else if (d_ack) outstanding <= 1'b0; MISSING_ELSE 68 end 69 70 always_ff @(posedge clk_i or negedge rst_ni) begin 71 1/1 if (!rst_ni) begin 72 1/1 reqid <= '0; 73 1/1 reqsz <= '0; 74 1/1 rspop <= AccessAck; 75 1/1 end else if (a_ack) begin 76 1/1 reqid <= tl_i.a_source; 77 1/1 reqsz <= tl_i.a_size; 78 // Return AccessAckData regardless of error 79 1/1 rspop <= (rd_req) ? AccessAckData : AccessAck ; 80 end MISSING_ELSE 81 end 82 83 always_ff @(posedge clk_i or negedge rst_ni) begin 84 1/1 if (!rst_ni) begin 85 1/1 rdata <= '0; 86 1/1 error <= 1'b0; 87 1/1 end else if (a_ack) begin 88 1/1 rdata <= (err_internal) ? '1 : rdata_i; 89 1/1 error <= error_i | err_internal; 90 end MISSING_ELSE 91 end 92 93 assign tl_o = '{ 94 a_ready: ~outstanding, 95 d_valid: outstanding, 96 d_opcode: rspop, 97 d_param: '0, 98 d_size: reqsz, 99 d_source: reqid, 100 d_sink: '0, 101 d_data: rdata, 102 d_user: '0, 103 d_error: error 104 }; 105 106 //////////////////// 107 // Error Handling // 108 //////////////////// 109 1/1 assign err_internal = addr_align_err | malformed_meta_err | tl_err ; 110 111 // malformed_meta_err 112 // Raised if not supported feature is turned on or user signal has malformed 113 1/1 assign malformed_meta_err = (tl_i.a_user.parity_en == 1'b1); 114 115 // addr_align_err 116 // Raised if addr isn't aligned with the size 117 // Read size error is checked in tlul_assert.sv 118 // Here is it added due to the limitation of register interface. 119 always_comb begin 120 1/1 if (wr_req) begin 121 // Only word-align is accepted based on comportability spec 122 1/1 addr_align_err = |tl_i.a_address[1:0]; 123 end else begin 124 // No request 125 1/1 addr_align_err = 1'b0;

Cond Coverage for Module : tlul_adapter_reg
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       79
 EXPRESSION (rd_req ? AccessAckData : AccessAck)
             ---1--
-1-Status
0Covered
1Covered

 LINE       88
 EXPRESSION (err_internal ? '1 : rdata_i)
             ------1-----
-1-Status
0Covered
1Covered

Branch Coverage for Module : tlul_adapter_reg
Line No.TotalCoveredPercent
Branches 14 14 100.00
IF 65 4 4 100.00
IF 71 4 4 100.00
IF 84 4 4 100.00
IF 120 2 2 100.00


65 if (!rst_ni) outstanding <= 1'b0; -1- ==> 66 else if (a_ack) outstanding <= 1'b1; -2- ==> 67 else if (d_ack) outstanding <= 1'b0; -3- ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 - Covered
0 0 1 Covered
0 0 0 Covered


71 if (!rst_ni) begin -1- 72 reqid <= '0; ==> 73 reqsz <= '0; 74 rspop <= AccessAck; 75 end else if (a_ack) begin -2- 76 reqid <= tl_i.a_source; 77 reqsz <= tl_i.a_size; 78 // Return AccessAckData regardless of error 79 rspop <= (rd_req) ? AccessAckData : AccessAck ; -3- ==> ==> 80 end MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Covered
0 1 0 Covered
0 0 - Covered


84 if (!rst_ni) begin -1- 85 rdata <= '0; ==> 86 error <= 1'b0; 87 end else if (a_ack) begin -2- 88 rdata <= (err_internal) ? '1 : rdata_i; -3- ==> ==> 89 error <= error_i | err_internal; 90 end MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Covered
0 1 0 Covered
0 0 - Covered


120 if (wr_req) begin -1- 121 // Only word-align is accepted based on comportability spec 122 addr_align_err = |tl_i.a_address[1:0]; ==> 123 end else begin 124 // No request 125 addr_align_err = 1'b0; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Module : tlul_adapter_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
MatchedWidthAssert 919 919 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%