Module Definition
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Module Instance : tb.dut.gen_alerts[0].i_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 100.00 100.00 66.67 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 100.00 66.67 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_decode_alert 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_alerts[1].i_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 100.00 100.00 66.67 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 100.00 66.67 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_decode_alert 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_alerts[2].i_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 100.00 100.00 66.67 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 100.00 66.67 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_decode_alert 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_alerts[3].i_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.90 100.00 100.00 66.67 92.86 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.22 100.00 100.00 66.67 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
i_decode_alert 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_alert_receiver
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
ALWAYS1102323100.00
ALWAYS1551111100.00

86 // signalling is performed by a level change event on the diff output 87 1/1 assign ping_en_d = ping_en_i; 88 1/1 assign ping_rise = ping_en_i && !ping_en_q; 89 1/1 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; 90 91 // the ping pending signal is used to in the FSM to distinguish whether the 92 // incoming handshake shall be treated as an alert or a ping response. 93 // it is important that this is only set on a rising ping_en level change, since 94 // otherwise the ping enable signal could be abused to "mask" all native alerts 95 // as ping responses by constantly tying it to 1. 96 1/1 assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q); 97 98 // diff pair outputs 99 1/1 assign alert_rx_o.ack_p = ack_q; 100 1/1 assign alert_rx_o.ack_n = ~ack_q; 101 1/1 assign alert_rx_o.ping_p = ping_tog_q; 102 1/1 assign alert_rx_o.ping_n = ~ping_tog_q; 103 104 // this FSM receives the four phase handshakes from the alert receiver 105 // note that the latency of the alert_p/n input diff pair is at least one 106 // cycle until it enters the receiver FSM. the same holds for the ack_* diff 107 // pair outputs. 108 always_comb begin : p_fsm 109 // default 110 1/1 state_d = state_q; 111 1/1 ack_d = 1'b0; 112 1/1 ping_ok_o = 1'b0; 113 1/1 integ_fail_o = 1'b0; 114 1/1 alert_o = 1'b0; 115 116 1/1 unique case (state_q) 117 Idle: begin 118 // wait for handshake to be initiated 119 1/1 if (alert_level) begin 120 1/1 state_d = HsAckWait; 121 1/1 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 1/1 if (ping_pending_q) begin 124 1/1 ping_ok_o = 1'b1; 125 end else begin 126 1/1 alert_o = 1'b1; 127 end 128 end MISSING_ELSE 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 1/1 if (!alert_level) begin 133 1/1 state_d = Pause0; 134 end else begin 135 1/1 ack_d = 1'b1; 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 1/1 Pause0: state_d = Pause1; 140 1/1 Pause1: state_d = Idle; 141 default : ; // full case 142 endcase 143 144 // override in case of sigint 145 1/1 if (alert_sigint) begin 146 1/1 state_d = Idle; 147 1/1 ack_d = 1'b0; 148 1/1 ping_ok_o = 1'b0; 149 1/1 integ_fail_o = 1'b1; 150 1/1 alert_o = 1'b0; 151 end MISSING_ELSE 152 end 153 154 always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 155 1/1 if (!rst_ni) begin 156 1/1 state_q <= Idle; 157 1/1 ack_q <= 1'b0; 158 1/1 ping_tog_q <= 1'b0; 159 1/1 ping_en_q <= 1'b0; 160 1/1 ping_pending_q <= 1'b0; 161 end else begin 162 1/1 state_q <= state_d; 163 1/1 ack_q <= ack_d; 164 1/1 ping_tog_q <= ping_tog_d; 165 1/1 ping_en_q <= ping_en_d; 166 1/1 ping_pending_q <= ping_pending_d;

Cond Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (ping_en_i && ((!ping_en_q)))
             ----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

 LINE       89
 EXPRESSION (ping_rise ? ((~ping_tog_q)) : ping_tog_q)
             ----1----
-1-Status
0Covered
1Covered

FSM Coverage for Module : prim_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.Covered
HsAckWait 120 Covered
Idle 156 Covered
Pause0 133 Covered
Pause1 139 Covered


transitionsLine No.Covered
HsAckWait->Idle 156 Not Covered
HsAckWait->Pause0 133 Covered
Idle->HsAckWait 120 Covered
Pause0->Idle 156 Not Covered
Pause0->Pause1 139 Covered
Pause1->Idle 156 Covered



Branch Coverage for Module : prim_alert_receiver
Line No.TotalCoveredPercent
Branches 14 13 92.86
TERNARY 89 2 2 100.00
CASE 116 8 7 87.50
IF 145 2 2 100.00
IF 155 2 2 100.00


89 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


116 unique case (state_q) -1- 117 Idle: begin 118 // wait for handshake to be initiated 119 if (alert_level) begin -2- 120 state_d = HsAckWait; 121 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 if (ping_pending_q) begin -3- 124 ping_ok_o = 1'b1; ==> 125 end else begin 126 alert_o = 1'b1; ==> 127 end 128 end MISSING_ELSE ==> 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 if (!alert_level) begin -4- 133 state_d = Pause0; ==> 134 end else begin 135 ack_d = 1'b1; ==> 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 Pause0: state_d = Pause1; ==> 140 Pause1: state_d = Idle; ==> 141 default : ; // full case ==>

Branches:
-1--2--3--4-Status
Idle 1 1 - Covered
Idle 1 0 - Covered
Idle 0 - - Covered
HsAckWait - - 1 Covered
HsAckWait - - 0 Covered
Pause0 - - - Covered
Pause1 - - - Covered
default - - - Not Covered


145 if (alert_sigint) begin -1- 146 state_d = Idle; ==> 147 ack_d = 1'b0; 148 ping_ok_o = 1'b0; 149 integ_fail_o = 1'b1; 150 alert_o = 1'b0; 151 end MISSING_ELSE ==>

Branches:
-1-Status
1 Covered
0 Covered


155 if (!rst_ni) begin -1- 156 state_q <= Idle; ==> 157 ack_q <= 1'b0; 158 ping_tog_q <= 1'b0; 159 ping_en_q <= 1'b0; 160 ping_pending_q <= 1'b0; 161 end else begin 162 state_q <= state_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Module : prim_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 2147483647 2147483647 0 0
AlertKnownO_A 2147483647 2147483647 0 0
IntegFailKnownO_A 2147483647 2147483647 0 0
PingDiffOk_A 2147483647 2147483647 0 0
PingOkKnownO_A 2147483647 2147483647 0 0
PingPKnownO_A 2147483647 2147483647 0 0
PingPending_A 2147483647 225 0 3676
PingRequest0_A 2147483647 225 0 3676
PingResponse0_A 2147483647 153 0 0
gen_sync_assert.Alert_A 2147483647 9234763 0 3676
gen_sync_assert.PingResponse1_A 2147483647 153 0 3676
gen_sync_assert.SigInt_A 2147483647 32200807 0 0

Line Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
ALWAYS1102323100.00
ALWAYS1551111100.00

86 // signalling is performed by a level change event on the diff output 87 1/1 assign ping_en_d = ping_en_i; 88 1/1 assign ping_rise = ping_en_i && !ping_en_q; 89 1/1 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; 90 91 // the ping pending signal is used to in the FSM to distinguish whether the 92 // incoming handshake shall be treated as an alert or a ping response. 93 // it is important that this is only set on a rising ping_en level change, since 94 // otherwise the ping enable signal could be abused to "mask" all native alerts 95 // as ping responses by constantly tying it to 1. 96 1/1 assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q); 97 98 // diff pair outputs 99 1/1 assign alert_rx_o.ack_p = ack_q; 100 1/1 assign alert_rx_o.ack_n = ~ack_q; 101 1/1 assign alert_rx_o.ping_p = ping_tog_q; 102 1/1 assign alert_rx_o.ping_n = ~ping_tog_q; 103 104 // this FSM receives the four phase handshakes from the alert receiver 105 // note that the latency of the alert_p/n input diff pair is at least one 106 // cycle until it enters the receiver FSM. the same holds for the ack_* diff 107 // pair outputs. 108 always_comb begin : p_fsm 109 // default 110 1/1 state_d = state_q; 111 1/1 ack_d = 1'b0; 112 1/1 ping_ok_o = 1'b0; 113 1/1 integ_fail_o = 1'b0; 114 1/1 alert_o = 1'b0; 115 116 1/1 unique case (state_q) 117 Idle: begin 118 // wait for handshake to be initiated 119 1/1 if (alert_level) begin 120 1/1 state_d = HsAckWait; 121 1/1 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 1/1 if (ping_pending_q) begin 124 1/1 ping_ok_o = 1'b1; 125 end else begin 126 1/1 alert_o = 1'b1; 127 end 128 end MISSING_ELSE 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 1/1 if (!alert_level) begin 133 1/1 state_d = Pause0; 134 end else begin 135 1/1 ack_d = 1'b1; 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 1/1 Pause0: state_d = Pause1; 140 1/1 Pause1: state_d = Idle; 141 default : ; // full case 142 endcase 143 144 // override in case of sigint 145 1/1 if (alert_sigint) begin 146 1/1 state_d = Idle; 147 1/1 ack_d = 1'b0; 148 1/1 ping_ok_o = 1'b0; 149 1/1 integ_fail_o = 1'b1; 150 1/1 alert_o = 1'b0; 151 end MISSING_ELSE 152 end 153 154 always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 155 1/1 if (!rst_ni) begin 156 1/1 state_q <= Idle; 157 1/1 ack_q <= 1'b0; 158 1/1 ping_tog_q <= 1'b0; 159 1/1 ping_en_q <= 1'b0; 160 1/1 ping_pending_q <= 1'b0; 161 end else begin 162 1/1 state_q <= state_d; 163 1/1 ack_q <= ack_d; 164 1/1 ping_tog_q <= ping_tog_d; 165 1/1 ping_en_q <= ping_en_d; 166 1/1 ping_pending_q <= ping_pending_d;

Cond Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (ping_en_i && ((!ping_en_q)))
             ----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

 LINE       89
 EXPRESSION (ping_rise ? ((~ping_tog_q)) : ping_tog_q)
             ----1----
-1-Status
0Covered
1Covered

FSM Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.Covered
HsAckWait 120 Covered
Idle 156 Covered
Pause0 133 Covered
Pause1 139 Covered


transitionsLine No.Covered
HsAckWait->Idle 156 Not Covered
HsAckWait->Pause0 133 Covered
Idle->HsAckWait 120 Covered
Pause0->Idle 156 Not Covered
Pause0->Pause1 139 Covered
Pause1->Idle 156 Covered



Branch Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver
Line No.TotalCoveredPercent
Branches 14 13 92.86
TERNARY 89 2 2 100.00
CASE 116 8 7 87.50
IF 145 2 2 100.00
IF 155 2 2 100.00


89 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


116 unique case (state_q) -1- 117 Idle: begin 118 // wait for handshake to be initiated 119 if (alert_level) begin -2- 120 state_d = HsAckWait; 121 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 if (ping_pending_q) begin -3- 124 ping_ok_o = 1'b1; ==> 125 end else begin 126 alert_o = 1'b1; ==> 127 end 128 end MISSING_ELSE ==> 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 if (!alert_level) begin -4- 133 state_d = Pause0; ==> 134 end else begin 135 ack_d = 1'b1; ==> 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 Pause0: state_d = Pause1; ==> 140 Pause1: state_d = Idle; ==> 141 default : ; // full case ==>

Branches:
-1--2--3--4-Status
Idle 1 1 - Covered
Idle 1 0 - Covered
Idle 0 - - Covered
HsAckWait - - 1 Covered
HsAckWait - - 0 Covered
Pause0 - - - Covered
Pause1 - - - Covered
default - - - Not Covered


145 if (alert_sigint) begin -1- 146 state_d = Idle; ==> 147 ack_d = 1'b0; 148 ping_ok_o = 1'b0; 149 integ_fail_o = 1'b1; 150 alert_o = 1'b0; 151 end MISSING_ELSE ==>

Branches:
-1-Status
1 Covered
0 Covered


155 if (!rst_ni) begin -1- 156 state_q <= Idle; ==> 157 ack_q <= 1'b0; 158 ping_tog_q <= 1'b0; 159 ping_en_q <= 1'b0; 160 ping_pending_q <= 1'b0; 161 end else begin 162 state_q <= state_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 2147483647 2147483647 0 0
AlertKnownO_A 2147483647 2147483647 0 0
IntegFailKnownO_A 2147483647 2147483647 0 0
PingDiffOk_A 2147483647 2147483647 0 0
PingOkKnownO_A 2147483647 2147483647 0 0
PingPKnownO_A 2147483647 2147483647 0 0
PingPending_A 2147483647 18 0 919
PingRequest0_A 2147483647 18 0 919
PingResponse0_A 2147483647 8 0 0
gen_sync_assert.Alert_A 2147483647 2310182 0 919
gen_sync_assert.PingResponse1_A 2147483647 8 0 919
gen_sync_assert.SigInt_A 2147483647 8045902 0 0

Line Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
ALWAYS1102323100.00
ALWAYS1551111100.00

86 // signalling is performed by a level change event on the diff output 87 1/1 assign ping_en_d = ping_en_i; 88 1/1 assign ping_rise = ping_en_i && !ping_en_q; 89 1/1 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; 90 91 // the ping pending signal is used to in the FSM to distinguish whether the 92 // incoming handshake shall be treated as an alert or a ping response. 93 // it is important that this is only set on a rising ping_en level change, since 94 // otherwise the ping enable signal could be abused to "mask" all native alerts 95 // as ping responses by constantly tying it to 1. 96 1/1 assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q); 97 98 // diff pair outputs 99 1/1 assign alert_rx_o.ack_p = ack_q; 100 1/1 assign alert_rx_o.ack_n = ~ack_q; 101 1/1 assign alert_rx_o.ping_p = ping_tog_q; 102 1/1 assign alert_rx_o.ping_n = ~ping_tog_q; 103 104 // this FSM receives the four phase handshakes from the alert receiver 105 // note that the latency of the alert_p/n input diff pair is at least one 106 // cycle until it enters the receiver FSM. the same holds for the ack_* diff 107 // pair outputs. 108 always_comb begin : p_fsm 109 // default 110 1/1 state_d = state_q; 111 1/1 ack_d = 1'b0; 112 1/1 ping_ok_o = 1'b0; 113 1/1 integ_fail_o = 1'b0; 114 1/1 alert_o = 1'b0; 115 116 1/1 unique case (state_q) 117 Idle: begin 118 // wait for handshake to be initiated 119 1/1 if (alert_level) begin 120 1/1 state_d = HsAckWait; 121 1/1 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 1/1 if (ping_pending_q) begin 124 1/1 ping_ok_o = 1'b1; 125 end else begin 126 1/1 alert_o = 1'b1; 127 end 128 end MISSING_ELSE 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 1/1 if (!alert_level) begin 133 1/1 state_d = Pause0; 134 end else begin 135 1/1 ack_d = 1'b1; 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 1/1 Pause0: state_d = Pause1; 140 1/1 Pause1: state_d = Idle; 141 default : ; // full case 142 endcase 143 144 // override in case of sigint 145 1/1 if (alert_sigint) begin 146 1/1 state_d = Idle; 147 1/1 ack_d = 1'b0; 148 1/1 ping_ok_o = 1'b0; 149 1/1 integ_fail_o = 1'b1; 150 1/1 alert_o = 1'b0; 151 end MISSING_ELSE 152 end 153 154 always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 155 1/1 if (!rst_ni) begin 156 1/1 state_q <= Idle; 157 1/1 ack_q <= 1'b0; 158 1/1 ping_tog_q <= 1'b0; 159 1/1 ping_en_q <= 1'b0; 160 1/1 ping_pending_q <= 1'b0; 161 end else begin 162 1/1 state_q <= state_d; 163 1/1 ack_q <= ack_d; 164 1/1 ping_tog_q <= ping_tog_d; 165 1/1 ping_en_q <= ping_en_d; 166 1/1 ping_pending_q <= ping_pending_d;

Cond Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (ping_en_i && ((!ping_en_q)))
             ----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

 LINE       89
 EXPRESSION (ping_rise ? ((~ping_tog_q)) : ping_tog_q)
             ----1----
-1-Status
0Covered
1Covered

FSM Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.Covered
HsAckWait 120 Covered
Idle 156 Covered
Pause0 133 Covered
Pause1 139 Covered


transitionsLine No.Covered
HsAckWait->Idle 156 Not Covered
HsAckWait->Pause0 133 Covered
Idle->HsAckWait 120 Covered
Pause0->Idle 156 Not Covered
Pause0->Pause1 139 Covered
Pause1->Idle 156 Covered



Branch Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver
Line No.TotalCoveredPercent
Branches 14 13 92.86
TERNARY 89 2 2 100.00
CASE 116 8 7 87.50
IF 145 2 2 100.00
IF 155 2 2 100.00


89 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


116 unique case (state_q) -1- 117 Idle: begin 118 // wait for handshake to be initiated 119 if (alert_level) begin -2- 120 state_d = HsAckWait; 121 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 if (ping_pending_q) begin -3- 124 ping_ok_o = 1'b1; ==> 125 end else begin 126 alert_o = 1'b1; ==> 127 end 128 end MISSING_ELSE ==> 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 if (!alert_level) begin -4- 133 state_d = Pause0; ==> 134 end else begin 135 ack_d = 1'b1; ==> 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 Pause0: state_d = Pause1; ==> 140 Pause1: state_d = Idle; ==> 141 default : ; // full case ==>

Branches:
-1--2--3--4-Status
Idle 1 1 - Covered
Idle 1 0 - Covered
Idle 0 - - Covered
HsAckWait - - 1 Covered
HsAckWait - - 0 Covered
Pause0 - - - Covered
Pause1 - - - Covered
default - - - Not Covered


145 if (alert_sigint) begin -1- 146 state_d = Idle; ==> 147 ack_d = 1'b0; 148 ping_ok_o = 1'b0; 149 integ_fail_o = 1'b1; 150 alert_o = 1'b0; 151 end MISSING_ELSE ==>

Branches:
-1-Status
1 Covered
0 Covered


155 if (!rst_ni) begin -1- 156 state_q <= Idle; ==> 157 ack_q <= 1'b0; 158 ping_tog_q <= 1'b0; 159 ping_en_q <= 1'b0; 160 ping_pending_q <= 1'b0; 161 end else begin 162 state_q <= state_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 2147483647 2147483647 0 0
AlertKnownO_A 2147483647 2147483647 0 0
IntegFailKnownO_A 2147483647 2147483647 0 0
PingDiffOk_A 2147483647 2147483647 0 0
PingOkKnownO_A 2147483647 2147483647 0 0
PingPKnownO_A 2147483647 2147483647 0 0
PingPending_A 2147483647 12 0 919
PingRequest0_A 2147483647 12 0 919
PingResponse0_A 2147483647 10 0 0
gen_sync_assert.Alert_A 2147483647 2307564 0 919
gen_sync_assert.PingResponse1_A 2147483647 10 0 919
gen_sync_assert.SigInt_A 2147483647 8050629 0 0

Line Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
ALWAYS1102323100.00
ALWAYS1551111100.00

86 // signalling is performed by a level change event on the diff output 87 1/1 assign ping_en_d = ping_en_i; 88 1/1 assign ping_rise = ping_en_i && !ping_en_q; 89 1/1 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; 90 91 // the ping pending signal is used to in the FSM to distinguish whether the 92 // incoming handshake shall be treated as an alert or a ping response. 93 // it is important that this is only set on a rising ping_en level change, since 94 // otherwise the ping enable signal could be abused to "mask" all native alerts 95 // as ping responses by constantly tying it to 1. 96 1/1 assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q); 97 98 // diff pair outputs 99 1/1 assign alert_rx_o.ack_p = ack_q; 100 1/1 assign alert_rx_o.ack_n = ~ack_q; 101 1/1 assign alert_rx_o.ping_p = ping_tog_q; 102 1/1 assign alert_rx_o.ping_n = ~ping_tog_q; 103 104 // this FSM receives the four phase handshakes from the alert receiver 105 // note that the latency of the alert_p/n input diff pair is at least one 106 // cycle until it enters the receiver FSM. the same holds for the ack_* diff 107 // pair outputs. 108 always_comb begin : p_fsm 109 // default 110 1/1 state_d = state_q; 111 1/1 ack_d = 1'b0; 112 1/1 ping_ok_o = 1'b0; 113 1/1 integ_fail_o = 1'b0; 114 1/1 alert_o = 1'b0; 115 116 1/1 unique case (state_q) 117 Idle: begin 118 // wait for handshake to be initiated 119 1/1 if (alert_level) begin 120 1/1 state_d = HsAckWait; 121 1/1 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 1/1 if (ping_pending_q) begin 124 1/1 ping_ok_o = 1'b1; 125 end else begin 126 1/1 alert_o = 1'b1; 127 end 128 end MISSING_ELSE 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 1/1 if (!alert_level) begin 133 1/1 state_d = Pause0; 134 end else begin 135 1/1 ack_d = 1'b1; 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 1/1 Pause0: state_d = Pause1; 140 1/1 Pause1: state_d = Idle; 141 default : ; // full case 142 endcase 143 144 // override in case of sigint 145 1/1 if (alert_sigint) begin 146 1/1 state_d = Idle; 147 1/1 ack_d = 1'b0; 148 1/1 ping_ok_o = 1'b0; 149 1/1 integ_fail_o = 1'b1; 150 1/1 alert_o = 1'b0; 151 end MISSING_ELSE 152 end 153 154 always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 155 1/1 if (!rst_ni) begin 156 1/1 state_q <= Idle; 157 1/1 ack_q <= 1'b0; 158 1/1 ping_tog_q <= 1'b0; 159 1/1 ping_en_q <= 1'b0; 160 1/1 ping_pending_q <= 1'b0; 161 end else begin 162 1/1 state_q <= state_d; 163 1/1 ack_q <= ack_d; 164 1/1 ping_tog_q <= ping_tog_d; 165 1/1 ping_en_q <= ping_en_d; 166 1/1 ping_pending_q <= ping_pending_d;

Cond Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (ping_en_i && ((!ping_en_q)))
             ----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

 LINE       89
 EXPRESSION (ping_rise ? ((~ping_tog_q)) : ping_tog_q)
             ----1----
-1-Status
0Covered
1Covered

FSM Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.Covered
HsAckWait 120 Covered
Idle 156 Covered
Pause0 133 Covered
Pause1 139 Covered


transitionsLine No.Covered
HsAckWait->Idle 156 Not Covered
HsAckWait->Pause0 133 Covered
Idle->HsAckWait 120 Covered
Pause0->Idle 156 Not Covered
Pause0->Pause1 139 Covered
Pause1->Idle 156 Covered



Branch Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver
Line No.TotalCoveredPercent
Branches 14 13 92.86
TERNARY 89 2 2 100.00
CASE 116 8 7 87.50
IF 145 2 2 100.00
IF 155 2 2 100.00


89 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


116 unique case (state_q) -1- 117 Idle: begin 118 // wait for handshake to be initiated 119 if (alert_level) begin -2- 120 state_d = HsAckWait; 121 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 if (ping_pending_q) begin -3- 124 ping_ok_o = 1'b1; ==> 125 end else begin 126 alert_o = 1'b1; ==> 127 end 128 end MISSING_ELSE ==> 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 if (!alert_level) begin -4- 133 state_d = Pause0; ==> 134 end else begin 135 ack_d = 1'b1; ==> 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 Pause0: state_d = Pause1; ==> 140 Pause1: state_d = Idle; ==> 141 default : ; // full case ==>

Branches:
-1--2--3--4-Status
Idle 1 1 - Covered
Idle 1 0 - Covered
Idle 0 - - Covered
HsAckWait - - 1 Covered
HsAckWait - - 0 Covered
Pause0 - - - Covered
Pause1 - - - Covered
default - - - Not Covered


145 if (alert_sigint) begin -1- 146 state_d = Idle; ==> 147 ack_d = 1'b0; 148 ping_ok_o = 1'b0; 149 integ_fail_o = 1'b1; 150 alert_o = 1'b0; 151 end MISSING_ELSE ==>

Branches:
-1-Status
1 Covered
0 Covered


155 if (!rst_ni) begin -1- 156 state_q <= Idle; ==> 157 ack_q <= 1'b0; 158 ping_tog_q <= 1'b0; 159 ping_en_q <= 1'b0; 160 ping_pending_q <= 1'b0; 161 end else begin 162 state_q <= state_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 2147483647 2147483647 0 0
AlertKnownO_A 2147483647 2147483647 0 0
IntegFailKnownO_A 2147483647 2147483647 0 0
PingDiffOk_A 2147483647 2147483647 0 0
PingOkKnownO_A 2147483647 2147483647 0 0
PingPKnownO_A 2147483647 2147483647 0 0
PingPending_A 2147483647 98 0 919
PingRequest0_A 2147483647 98 0 919
PingResponse0_A 2147483647 59 0 0
gen_sync_assert.Alert_A 2147483647 2307934 0 919
gen_sync_assert.PingResponse1_A 2147483647 59 0 919
gen_sync_assert.SigInt_A 2147483647 8055266 0 0

Line Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver
Line No.TotalCoveredPercent
TOTAL4242100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10211100.00
ALWAYS1102323100.00
ALWAYS1551111100.00

86 // signalling is performed by a level change event on the diff output 87 1/1 assign ping_en_d = ping_en_i; 88 1/1 assign ping_rise = ping_en_i && !ping_en_q; 89 1/1 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; 90 91 // the ping pending signal is used to in the FSM to distinguish whether the 92 // incoming handshake shall be treated as an alert or a ping response. 93 // it is important that this is only set on a rising ping_en level change, since 94 // otherwise the ping enable signal could be abused to "mask" all native alerts 95 // as ping responses by constantly tying it to 1. 96 1/1 assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_en_i & ping_pending_q); 97 98 // diff pair outputs 99 1/1 assign alert_rx_o.ack_p = ack_q; 100 1/1 assign alert_rx_o.ack_n = ~ack_q; 101 1/1 assign alert_rx_o.ping_p = ping_tog_q; 102 1/1 assign alert_rx_o.ping_n = ~ping_tog_q; 103 104 // this FSM receives the four phase handshakes from the alert receiver 105 // note that the latency of the alert_p/n input diff pair is at least one 106 // cycle until it enters the receiver FSM. the same holds for the ack_* diff 107 // pair outputs. 108 always_comb begin : p_fsm 109 // default 110 1/1 state_d = state_q; 111 1/1 ack_d = 1'b0; 112 1/1 ping_ok_o = 1'b0; 113 1/1 integ_fail_o = 1'b0; 114 1/1 alert_o = 1'b0; 115 116 1/1 unique case (state_q) 117 Idle: begin 118 // wait for handshake to be initiated 119 1/1 if (alert_level) begin 120 1/1 state_d = HsAckWait; 121 1/1 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 1/1 if (ping_pending_q) begin 124 1/1 ping_ok_o = 1'b1; 125 end else begin 126 1/1 alert_o = 1'b1; 127 end 128 end MISSING_ELSE 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 1/1 if (!alert_level) begin 133 1/1 state_d = Pause0; 134 end else begin 135 1/1 ack_d = 1'b1; 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 1/1 Pause0: state_d = Pause1; 140 1/1 Pause1: state_d = Idle; 141 default : ; // full case 142 endcase 143 144 // override in case of sigint 145 1/1 if (alert_sigint) begin 146 1/1 state_d = Idle; 147 1/1 ack_d = 1'b0; 148 1/1 ping_ok_o = 1'b0; 149 1/1 integ_fail_o = 1'b1; 150 1/1 alert_o = 1'b0; 151 end MISSING_ELSE 152 end 153 154 always_ff @(posedge clk_i or negedge rst_ni) begin : p_reg 155 1/1 if (!rst_ni) begin 156 1/1 state_q <= Idle; 157 1/1 ack_q <= 1'b0; 158 1/1 ping_tog_q <= 1'b0; 159 1/1 ping_en_q <= 1'b0; 160 1/1 ping_pending_q <= 1'b0; 161 end else begin 162 1/1 state_q <= state_d; 163 1/1 ack_q <= ack_d; 164 1/1 ping_tog_q <= ping_tog_d; 165 1/1 ping_en_q <= ping_en_d; 166 1/1 ping_pending_q <= ping_pending_d;

Cond Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (ping_en_i && ((!ping_en_q)))
             ----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

 LINE       89
 EXPRESSION (ping_rise ? ((~ping_tog_q)) : ping_tog_q)
             ----1----
-1-Status
0Covered
1Covered

FSM Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 4 66.67
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.Covered
HsAckWait 120 Covered
Idle 156 Covered
Pause0 133 Covered
Pause1 139 Covered


transitionsLine No.Covered
HsAckWait->Idle 156 Not Covered
HsAckWait->Pause0 133 Covered
Idle->HsAckWait 120 Covered
Pause0->Idle 156 Not Covered
Pause0->Pause1 139 Covered
Pause1->Idle 156 Covered



Branch Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver
Line No.TotalCoveredPercent
Branches 14 13 92.86
TERNARY 89 2 2 100.00
CASE 116 8 7 87.50
IF 145 2 2 100.00
IF 155 2 2 100.00


89 assign ping_tog_d = (ping_rise) ? ~ping_tog_q : ping_tog_q; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


116 unique case (state_q) -1- 117 Idle: begin 118 // wait for handshake to be initiated 119 if (alert_level) begin -2- 120 state_d = HsAckWait; 121 ack_d = 1'b1; 122 // signal either an alert or ping received on the output 123 if (ping_pending_q) begin -3- 124 ping_ok_o = 1'b1; ==> 125 end else begin 126 alert_o = 1'b1; ==> 127 end 128 end MISSING_ELSE ==> 129 end 130 // waiting for deassertion of alert to complete HS 131 HsAckWait: begin 132 if (!alert_level) begin -4- 133 state_d = Pause0; ==> 134 end else begin 135 ack_d = 1'b1; ==> 136 end 137 end 138 // pause cycles between back-to-back handshakes 139 Pause0: state_d = Pause1; ==> 140 Pause1: state_d = Idle; ==> 141 default : ; // full case ==>

Branches:
-1--2--3--4-Status
Idle 1 1 - Covered
Idle 1 0 - Covered
Idle 0 - - Covered
HsAckWait - - 1 Covered
HsAckWait - - 0 Covered
Pause0 - - - Covered
Pause1 - - - Covered
default - - - Not Covered


145 if (alert_sigint) begin -1- 146 state_d = Idle; ==> 147 ack_d = 1'b0; 148 ping_ok_o = 1'b0; 149 integ_fail_o = 1'b1; 150 alert_o = 1'b0; 151 end MISSING_ELSE ==>

Branches:
-1-Status
1 Covered
0 Covered


155 if (!rst_ni) begin -1- 156 state_q <= Idle; ==> 157 ack_q <= 1'b0; 158 ping_tog_q <= 1'b0; 159 ping_en_q <= 1'b0; 160 ping_pending_q <= 1'b0; 161 end else begin 162 state_q <= state_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 12 12 100.00 12 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 12 12 100.00 12 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckDiffOk_A 2147483647 2147483647 0 0
AlertKnownO_A 2147483647 2147483647 0 0
IntegFailKnownO_A 2147483647 2147483647 0 0
PingDiffOk_A 2147483647 2147483647 0 0
PingOkKnownO_A 2147483647 2147483647 0 0
PingPKnownO_A 2147483647 2147483647 0 0
PingPending_A 2147483647 97 0 919
PingRequest0_A 2147483647 97 0 919
PingResponse0_A 2147483647 76 0 0
gen_sync_assert.Alert_A 2147483647 2309083 0 919
gen_sync_assert.PingResponse1_A 2147483647 76 0 919
gen_sync_assert.SigInt_A 2147483647 8049010 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%