Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Source File(s) :
/edascratch/chencindy-opentitan/nightly_openTitan/alert_handler.sim.vcs/master/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].i_esc_timer	94.47	100.00	76.19		100.00	96.15	100.00
tb.dut.gen_classes[0].i_esc_timer	95.42	100.00	80.95		100.00	96.15	100.00
tb.dut.gen_classes[1].i_esc_timer	95.42	100.00	80.95		100.00	96.15	100.00
tb.dut.gen_classes[3].i_esc_timer	95.42	100.00	80.95		100.00	96.15	100.00

---

Module Instance : tb.dut.gen_classes[2].i_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00	76.19		100.00	96.15	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.47	100.00	76.19		100.00	96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.20	100.00		76.60			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].i_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.20	100.00		76.60			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].i_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.20	100.00		76.60			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].i_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	100.00	80.95		100.00	96.15	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.20	100.00		76.60			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		92	92	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	71	70	70	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	203	10	10	100.00

51                        // escalation counter, used for all phases and the timeout
52         1/1            assign cnt_d = cnt_q + 1'b1;
53                      
54                        // current state output
55         1/1            assign esc_state_o = state_q;
56         1/1            assign esc_cnt_o   = cnt_q;
57                      
58                        // threshold test, the thresholds are muxed further below
59                        // depending on the current state
60                        logic [EscCntDw-1:0] thresh;
61         1/1            assign cnt_ge    = (cnt_q >= thresh);
62                      
63                        //////////////
64                        // Main FSM //
65                        //////////////
66                      
67                        logic [N_PHASES-1:0] phase_oh;
68                      
69                        always_comb begin : p_fsm
70                          // default
71         1/1              state_d    = state_q;
72         1/1              cnt_en     = 1'b0;
73         1/1              cnt_clr    = 1'b0;
74         1/1              esc_trig_o = 1'b0;
75         1/1              phase_oh   = '0;
76         1/1              thresh     = timeout_cyc_i;
77                      
78         1/1              unique case (state_q)
79                            // wait for an escalation trigger or an alert trigger
80                            // the latter will trigger an interrupt timeout
81                            Idle: begin
82         1/1                  cnt_clr = 1'b1;
83                      
84         1/1                  if (accum_trig_i && en_i && !clr_i) begin
85         1/1                    state_d    = Phase0;
86         1/1                    cnt_en     = 1'b1;
87         1/1                    esc_trig_o = 1'b1;
88                              // the counter is zero in this state. so if the
89                              // timeout count is zero (==disabled), cnt_ge will be true.
90         1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
91         1/1                    cnt_en  = 1'b1;
92         1/1                    state_d = Timeout;
93                              end
                        MISSING_ELSE
94                            end
95                            // we are in interrupt timeout state
96                            // in case an escalation comes in, we immediately have to
97                            // switch over to the first escalation phase.
98                            // in case the interrupt timeout hits it's cycle count, we
99                            // also enter escalation phase0.
100                           // ongoing timeouts can always be cleared.
101                           Timeout: begin
102        1/1                  if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
103        1/1                    state_d    = Phase0;
104        1/1                    cnt_en     = 1'b1;
105        1/1                    cnt_clr    = 1'b1;
106        1/1                    esc_trig_o = 1'b1;
107                             // the timeout enable is connected to the irq state
108                             // if that is cleared, stop the timeout counter
109        1/1                  end else if (timeout_en_i) begin
110        1/1                    cnt_en  = 1'b1;
111                             end else begin
112        1/1                    state_d = Idle;
113        1/1                    cnt_clr = 1'b1;
114                             end
115                           end
116                           // note: autolocking the clear signal is done in the regfile
117                           Phase0: begin
118        1/1                  cnt_en      = 1'b1;
119        1/1                  phase_oh[0] = 1'b1;
120        1/1                  thresh      = phase_cyc_i[0];
121                     
122        1/1                  if (clr_i) begin
123        1/1                    state_d = Idle;
124        1/1                    cnt_clr = 1'b1;
125        1/1                    cnt_en  = 1'b0;
126        1/1                  end else if (cnt_ge) begin
127        1/1                    state_d = Phase1;
128        1/1                    cnt_clr = 1'b1;
129        1/1                    cnt_en  = 1'b1;
130                             end
                        MISSING_ELSE
131                           end
132                           Phase1: begin
133        1/1                  cnt_en      = 1'b1;
134        1/1                  phase_oh[1] = 1'b1;
135        1/1                  thresh      = phase_cyc_i[1];
136                     
137        1/1                  if (clr_i) begin
138        1/1                    state_d = Idle;
139        1/1                    cnt_clr = 1'b1;
140        1/1                    cnt_en  = 1'b0;
141        1/1                  end else if (cnt_ge) begin
142        1/1                    state_d = Phase2;
143        1/1                    cnt_clr = 1'b1;
144        1/1                    cnt_en  = 1'b1;
145                             end
                        MISSING_ELSE
146                           end
147                           Phase2: begin
148        1/1                  cnt_en      = 1'b1;
149        1/1                  phase_oh[2] = 1'b1;
150        1/1                  thresh      = phase_cyc_i[2];
151                     
152        1/1                  if (clr_i) begin
153        1/1                    state_d = Idle;
154        1/1                    cnt_clr = 1'b1;
155        1/1                    cnt_en  = 1'b0;
156        1/1                  end else if (cnt_ge) begin
157        1/1                    state_d = Phase3;
158        1/1                    cnt_clr = 1'b1;
159                             end
                        MISSING_ELSE
160                           end
161                           Phase3: begin
162        1/1                  cnt_en      = 1'b1;
163        1/1                  phase_oh[3] = 1'b1;
164        1/1                  thresh      = phase_cyc_i[3];
165                     
166        1/1                  if (clr_i) begin
167        1/1                    state_d = Idle;
168        1/1                    cnt_clr = 1'b1;
169        1/1                    cnt_en  = 1'b0;
170        1/1                  end else if (cnt_ge) begin
171        1/1                    state_d = Terminal;
172        1/1                    cnt_clr = 1'b1;
173        1/1                    cnt_en  = 1'b0;
174                             end
                        MISSING_ELSE
175                           end
176                           // final, terminal state after escalation.
177                           // if clr is locked down, only a system reset
178                           // will get us out of this state
179                           Terminal: begin
180        1/1                  cnt_clr = 1'b1;
181        1/1                  if (clr_i) begin
182        1/1                    state_d = Idle;
183                             end
                        MISSING_ELSE
184                           end
185                           default: state_d = Idle;
186                         endcase
187                       end
188                     
189                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
190                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
191                         // generate configuration mask for escalation enable signals
192        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
193                         // mask reduce current phase state vector
194        4/4              assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
195                       end
196                     
197                       ///////////////
198                       // Registers //
199                       ///////////////
200                     
201                       // switch interrupt / escalation mode
202                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
203        1/1              if (!rst_ni) begin
204        1/1                state_q <= Idle;
205        1/1                cnt_q   <= '0;
206                         end else begin
207        1/1                state_q <= state_d;
208                     
209                           // escalation counter
210        1/1                if (cnt_en && cnt_clr) begin
211        1/1                  cnt_q <= EscCntDw'(1'b1);
212        1/1                end else if (cnt_clr) begin
213        1/1                  cnt_q <= '0;
214        1/1                end else if (cnt_en) begin
215        1/1                  cnt_q <= cnt_d;
216                           end
                   ==>  MISSING_ELSE

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
             ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       90
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Covered
1	1	0	Covered
1	1	1	Covered

 LINE       102
 EXPRESSION ((accum_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             ------------------1-----------------    ------------2-----------

-1-	-2-	Status
0	0	Covered
0	1	Covered
1	0	Covered

 LINE       102
 SUB-EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
                 ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       102
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

 LINE       210
 EXPRESSION (cnt_en && cnt_clr)
             ---1--    ---2---

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered
Idle	204	Covered
Phase0	85	Covered
Phase1	127	Covered
Phase2	142	Covered
Phase3	157	Covered
Terminal	171	Covered
Timeout	92	Covered

transitions	Line No.	Covered
Idle->Phase0	85	Covered
Idle->Timeout	92	Covered
Phase0->Idle	204	Covered
Phase0->Phase1	127	Covered
Phase1->Idle	204	Covered
Phase1->Phase2	142	Covered
Phase2->Idle	204	Covered
Phase2->Phase3	157	Covered
Phase3->Idle	204	Covered
Phase3->Terminal	171	Covered
Terminal->Idle	204	Covered
Timeout->Idle	204	Covered
Timeout->Phase0	103	Covered

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	78	21	21	100.00
IF	203	5	4	80.00

78             unique case (state_q)
                      -1-  
79               // wait for an escalation trigger or an alert trigger
80               // the latter will trigger an interrupt timeout
81               Idle: begin
82                 cnt_clr = 1'b1;
83         
84                 if (accum_trig_i && en_i && !clr_i) begin
                   -2-  
85                   state_d    = Phase0;
                     ==>
86                   cnt_en     = 1'b1;
87                   esc_trig_o = 1'b1;
88                 // the counter is zero in this state. so if the
89                 // timeout count is zero (==disabled), cnt_ge will be true.
90                 end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
91                   cnt_en  = 1'b1;
                     ==>
92                   state_d = Timeout;
93                 end
                   MISSING_ELSE
                   ==>
94               end
95               // we are in interrupt timeout state
96               // in case an escalation comes in, we immediately have to
97               // switch over to the first escalation phase.
98               // in case the interrupt timeout hits it's cycle count, we
99               // also enter escalation phase0.
100              // ongoing timeouts can always be cleared.
101              Timeout: begin
102                if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
103                  state_d    = Phase0;
                     ==>
104                  cnt_en     = 1'b1;
105                  cnt_clr    = 1'b1;
106                  esc_trig_o = 1'b1;
107                // the timeout enable is connected to the irq state
108                // if that is cleared, stop the timeout counter
109                end else if (timeout_en_i) begin
                            -5-  
110                  cnt_en  = 1'b1;
                     ==>
111                end else begin
112                  state_d = Idle;
                     ==>
113                  cnt_clr = 1'b1;
114                end
115              end
116              // note: autolocking the clear signal is done in the regfile
117              Phase0: begin
118                cnt_en      = 1'b1;
119                phase_oh[0] = 1'b1;
120                thresh      = phase_cyc_i[0];
121        
122                if (clr_i) begin
                   -6-  
123                  state_d = Idle;
                     ==>
124                  cnt_clr = 1'b1;
125                  cnt_en  = 1'b0;
126                end else if (cnt_ge) begin
                            -7-  
127                  state_d = Phase1;
                     ==>
128                  cnt_clr = 1'b1;
129                  cnt_en  = 1'b1;
130                end
                   MISSING_ELSE
                   ==>
131              end
132              Phase1: begin
133                cnt_en      = 1'b1;
134                phase_oh[1] = 1'b1;
135                thresh      = phase_cyc_i[1];
136        
137                if (clr_i) begin
                   -8-  
138                  state_d = Idle;
                     ==>
139                  cnt_clr = 1'b1;
140                  cnt_en  = 1'b0;
141                end else if (cnt_ge) begin
                            -9-  
142                  state_d = Phase2;
                     ==>
143                  cnt_clr = 1'b1;
144                  cnt_en  = 1'b1;
145                end
                   MISSING_ELSE
                   ==>
146              end
147              Phase2: begin
148                cnt_en      = 1'b1;
149                phase_oh[2] = 1'b1;
150                thresh      = phase_cyc_i[2];
151        
152                if (clr_i) begin
                   -10-  
153                  state_d = Idle;
                     ==>
154                  cnt_clr = 1'b1;
155                  cnt_en  = 1'b0;
156                end else if (cnt_ge) begin
                            -11-  
157                  state_d = Phase3;
                     ==>
158                  cnt_clr = 1'b1;
159                end
                   MISSING_ELSE
                   ==>
160              end
161              Phase3: begin
162                cnt_en      = 1'b1;
163                phase_oh[3] = 1'b1;
164                thresh      = phase_cyc_i[3];
165        
166                if (clr_i) begin
                   -12-  
167                  state_d = Idle;
                     ==>
168                  cnt_clr = 1'b1;
169                  cnt_en  = 1'b0;
170                end else if (cnt_ge) begin
                            -13-  
171                  state_d = Terminal;
                     ==>
172                  cnt_clr = 1'b1;
173                  cnt_en  = 1'b0;
174                end
                   MISSING_ELSE
                   ==>
175              end
176              // final, terminal state after escalation.
177              // if clr is locked down, only a system reset
178              // will get us out of this state
179              Terminal: begin
180                cnt_clr = 1'b1;
181                if (clr_i) begin
                   -14-  
182                  state_d = Idle;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184              end
185              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered

203            if (!rst_ni) begin
               -1-  
204              state_q <= Idle;
                 ==>
205              cnt_q   <= '0;
206            end else begin
207              state_q <= state_d;
208        
209              // escalation counter
210              if (cnt_en && cnt_clr) begin
                 -2-  
211                cnt_q <= EscCntDw'(1'b1);
                   ==>
212              end else if (cnt_clr) begin
                          -3-  
213                cnt_q <= '0;
                   ==>
214              end else if (cnt_en) begin
                          -4-  
215                cnt_q <= cnt_d;
                   ==>
216              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status
1	-	-	-	Covered
0	1	-	-	Covered
0	0	1	-	Covered
0	0	0	1	Covered
0	0	0	0	Not Covered

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckAccumTrig0	2147483647	293088	0	0
CheckAccumTrig1	2147483647	9589	0	0
CheckClr	2147483647	331142	0	0
CheckEn	2147483647	2147483647	0	2764
CheckPhase0	2147483647	317359	0	0
CheckPhase1	2147483647	301911	0	0
CheckPhase2	2147483647	283539	0	0
CheckPhase3	2147483647	266387	0	0
CheckTimeout0	2147483647	176731	0	0
CheckTimeout1	2147483647	3266602	0	0
CheckTimeout2	2147483647	138326	0	0
CheckTimeoutTrig	2147483647	28785	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].i_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		92	92	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	71	70	70	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	203	10	10	100.00

51                        // escalation counter, used for all phases and the timeout
52         1/1            assign cnt_d = cnt_q + 1'b1;
53                      
54                        // current state output
55         1/1            assign esc_state_o = state_q;
56         1/1            assign esc_cnt_o   = cnt_q;
57                      
58                        // threshold test, the thresholds are muxed further below
59                        // depending on the current state
60                        logic [EscCntDw-1:0] thresh;
61         1/1            assign cnt_ge    = (cnt_q >= thresh);
62                      
63                        //////////////
64                        // Main FSM //
65                        //////////////
66                      
67                        logic [N_PHASES-1:0] phase_oh;
68                      
69                        always_comb begin : p_fsm
70                          // default
71         1/1              state_d    = state_q;
72         1/1              cnt_en     = 1'b0;
73         1/1              cnt_clr    = 1'b0;
74         1/1              esc_trig_o = 1'b0;
75         1/1              phase_oh   = '0;
76         1/1              thresh     = timeout_cyc_i;
77                      
78         1/1              unique case (state_q)
79                            // wait for an escalation trigger or an alert trigger
80                            // the latter will trigger an interrupt timeout
81                            Idle: begin
82         1/1                  cnt_clr = 1'b1;
83                      
84         1/1                  if (accum_trig_i && en_i && !clr_i) begin
85         1/1                    state_d    = Phase0;
86         1/1                    cnt_en     = 1'b1;
87         1/1                    esc_trig_o = 1'b1;
88                              // the counter is zero in this state. so if the
89                              // timeout count is zero (==disabled), cnt_ge will be true.
90         1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
91         1/1                    cnt_en  = 1'b1;
92         1/1                    state_d = Timeout;
93                              end
                        MISSING_ELSE
94                            end
95                            // we are in interrupt timeout state
96                            // in case an escalation comes in, we immediately have to
97                            // switch over to the first escalation phase.
98                            // in case the interrupt timeout hits it's cycle count, we
99                            // also enter escalation phase0.
100                           // ongoing timeouts can always be cleared.
101                           Timeout: begin
102        1/1                  if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
103        1/1                    state_d    = Phase0;
104        1/1                    cnt_en     = 1'b1;
105        1/1                    cnt_clr    = 1'b1;
106        1/1                    esc_trig_o = 1'b1;
107                             // the timeout enable is connected to the irq state
108                             // if that is cleared, stop the timeout counter
109        1/1                  end else if (timeout_en_i) begin
110        1/1                    cnt_en  = 1'b1;
111                             end else begin
112        1/1                    state_d = Idle;
113        1/1                    cnt_clr = 1'b1;
114                             end
115                           end
116                           // note: autolocking the clear signal is done in the regfile
117                           Phase0: begin
118        1/1                  cnt_en      = 1'b1;
119        1/1                  phase_oh[0] = 1'b1;
120        1/1                  thresh      = phase_cyc_i[0];
121                     
122        1/1                  if (clr_i) begin
123        1/1                    state_d = Idle;
124        1/1                    cnt_clr = 1'b1;
125        1/1                    cnt_en  = 1'b0;
126        1/1                  end else if (cnt_ge) begin
127        1/1                    state_d = Phase1;
128        1/1                    cnt_clr = 1'b1;
129        1/1                    cnt_en  = 1'b1;
130                             end
                        MISSING_ELSE
131                           end
132                           Phase1: begin
133        1/1                  cnt_en      = 1'b1;
134        1/1                  phase_oh[1] = 1'b1;
135        1/1                  thresh      = phase_cyc_i[1];
136                     
137        1/1                  if (clr_i) begin
138        1/1                    state_d = Idle;
139        1/1                    cnt_clr = 1'b1;
140        1/1                    cnt_en  = 1'b0;
141        1/1                  end else if (cnt_ge) begin
142        1/1                    state_d = Phase2;
143        1/1                    cnt_clr = 1'b1;
144        1/1                    cnt_en  = 1'b1;
145                             end
                        MISSING_ELSE
146                           end
147                           Phase2: begin
148        1/1                  cnt_en      = 1'b1;
149        1/1                  phase_oh[2] = 1'b1;
150        1/1                  thresh      = phase_cyc_i[2];
151                     
152        1/1                  if (clr_i) begin
153        1/1                    state_d = Idle;
154        1/1                    cnt_clr = 1'b1;
155        1/1                    cnt_en  = 1'b0;
156        1/1                  end else if (cnt_ge) begin
157        1/1                    state_d = Phase3;
158        1/1                    cnt_clr = 1'b1;
159                             end
                        MISSING_ELSE
160                           end
161                           Phase3: begin
162        1/1                  cnt_en      = 1'b1;
163        1/1                  phase_oh[3] = 1'b1;
164        1/1                  thresh      = phase_cyc_i[3];
165                     
166        1/1                  if (clr_i) begin
167        1/1                    state_d = Idle;
168        1/1                    cnt_clr = 1'b1;
169        1/1                    cnt_en  = 1'b0;
170        1/1                  end else if (cnt_ge) begin
171        1/1                    state_d = Terminal;
172        1/1                    cnt_clr = 1'b1;
173        1/1                    cnt_en  = 1'b0;
174                             end
                        MISSING_ELSE
175                           end
176                           // final, terminal state after escalation.
177                           // if clr is locked down, only a system reset
178                           // will get us out of this state
179                           Terminal: begin
180        1/1                  cnt_clr = 1'b1;
181        1/1                  if (clr_i) begin
182        1/1                    state_d = Idle;
183                             end
                        MISSING_ELSE
184                           end
185                           default: state_d = Idle;
186                         endcase
187                       end
188                     
189                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
190                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
191                         // generate configuration mask for escalation enable signals
192        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
193                         // mask reduce current phase state vector
194        4/4              assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
195                       end
196                     
197                       ///////////////
198                       // Registers //
199                       ///////////////
200                     
201                       // switch interrupt / escalation mode
202                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
203        1/1              if (!rst_ni) begin
204        1/1                state_q <= Idle;
205        1/1                cnt_q   <= '0;
206                         end else begin
207        1/1                state_q <= state_d;
208                     
209                           // escalation counter
210        1/1                if (cnt_en && cnt_clr) begin
211        1/1                  cnt_q <= EscCntDw'(1'b1);
212        1/1                end else if (cnt_clr) begin
213        1/1                  cnt_q <= '0;
214        1/1                end else if (cnt_en) begin
215        1/1                  cnt_q <= cnt_d;
216                           end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_classes[2].i_esc_timer

	Total	Covered	Percent
Conditions	21	16	76.19
Logical	21	16	76.19
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
             ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       90
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Covered
1	1	0	Covered
1	1	1	Covered

 LINE       102
 EXPRESSION ((accum_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             ------------------1-----------------    ------------2-----------

-1-	-2-	Status
0	0	Covered
0	1	Covered
1	0	Covered

 LINE       102
 SUB-EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
                 ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       102
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status
0	1	Covered
1	0	Not Covered
1	1	Covered

 LINE       210
 EXPRESSION (cnt_en && cnt_clr)
             ---1--    ---2---

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

---

FSM Coverage for Instance : tb.dut.gen_classes[2].i_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered
Idle	204	Covered
Phase0	85	Covered
Phase1	127	Covered
Phase2	142	Covered
Phase3	157	Covered
Terminal	171	Covered
Timeout	92	Covered

transitions	Line No.	Covered
Idle->Phase0	85	Covered
Idle->Timeout	92	Covered
Phase0->Idle	204	Covered
Phase0->Phase1	127	Covered
Phase1->Idle	204	Covered
Phase1->Phase2	142	Covered
Phase2->Idle	204	Covered
Phase2->Phase3	157	Covered
Phase3->Idle	204	Covered
Phase3->Terminal	171	Covered
Terminal->Idle	204	Covered
Timeout->Idle	204	Covered
Timeout->Phase0	103	Covered

---

Branch Coverage for Instance : tb.dut.gen_classes[2].i_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	78	21	21	100.00
IF	203	5	4	80.00

78             unique case (state_q)
                      -1-  
79               // wait for an escalation trigger or an alert trigger
80               // the latter will trigger an interrupt timeout
81               Idle: begin
82                 cnt_clr = 1'b1;
83         
84                 if (accum_trig_i && en_i && !clr_i) begin
                   -2-  
85                   state_d    = Phase0;
                     ==>
86                   cnt_en     = 1'b1;
87                   esc_trig_o = 1'b1;
88                 // the counter is zero in this state. so if the
89                 // timeout count is zero (==disabled), cnt_ge will be true.
90                 end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
91                   cnt_en  = 1'b1;
                     ==>
92                   state_d = Timeout;
93                 end
                   MISSING_ELSE
                   ==>
94               end
95               // we are in interrupt timeout state
96               // in case an escalation comes in, we immediately have to
97               // switch over to the first escalation phase.
98               // in case the interrupt timeout hits it's cycle count, we
99               // also enter escalation phase0.
100              // ongoing timeouts can always be cleared.
101              Timeout: begin
102                if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
103                  state_d    = Phase0;
                     ==>
104                  cnt_en     = 1'b1;
105                  cnt_clr    = 1'b1;
106                  esc_trig_o = 1'b1;
107                // the timeout enable is connected to the irq state
108                // if that is cleared, stop the timeout counter
109                end else if (timeout_en_i) begin
                            -5-  
110                  cnt_en  = 1'b1;
                     ==>
111                end else begin
112                  state_d = Idle;
                     ==>
113                  cnt_clr = 1'b1;
114                end
115              end
116              // note: autolocking the clear signal is done in the regfile
117              Phase0: begin
118                cnt_en      = 1'b1;
119                phase_oh[0] = 1'b1;
120                thresh      = phase_cyc_i[0];
121        
122                if (clr_i) begin
                   -6-  
123                  state_d = Idle;
                     ==>
124                  cnt_clr = 1'b1;
125                  cnt_en  = 1'b0;
126                end else if (cnt_ge) begin
                            -7-  
127                  state_d = Phase1;
                     ==>
128                  cnt_clr = 1'b1;
129                  cnt_en  = 1'b1;
130                end
                   MISSING_ELSE
                   ==>
131              end
132              Phase1: begin
133                cnt_en      = 1'b1;
134                phase_oh[1] = 1'b1;
135                thresh      = phase_cyc_i[1];
136        
137                if (clr_i) begin
                   -8-  
138                  state_d = Idle;
                     ==>
139                  cnt_clr = 1'b1;
140                  cnt_en  = 1'b0;
141                end else if (cnt_ge) begin
                            -9-  
142                  state_d = Phase2;
                     ==>
143                  cnt_clr = 1'b1;
144                  cnt_en  = 1'b1;
145                end
                   MISSING_ELSE
                   ==>
146              end
147              Phase2: begin
148                cnt_en      = 1'b1;
149                phase_oh[2] = 1'b1;
150                thresh      = phase_cyc_i[2];
151        
152                if (clr_i) begin
                   -10-  
153                  state_d = Idle;
                     ==>
154                  cnt_clr = 1'b1;
155                  cnt_en  = 1'b0;
156                end else if (cnt_ge) begin
                            -11-  
157                  state_d = Phase3;
                     ==>
158                  cnt_clr = 1'b1;
159                end
                   MISSING_ELSE
                   ==>
160              end
161              Phase3: begin
162                cnt_en      = 1'b1;
163                phase_oh[3] = 1'b1;
164                thresh      = phase_cyc_i[3];
165        
166                if (clr_i) begin
                   -12-  
167                  state_d = Idle;
                     ==>
168                  cnt_clr = 1'b1;
169                  cnt_en  = 1'b0;
170                end else if (cnt_ge) begin
                            -13-  
171                  state_d = Terminal;
                     ==>
172                  cnt_clr = 1'b1;
173                  cnt_en  = 1'b0;
174                end
                   MISSING_ELSE
                   ==>
175              end
176              // final, terminal state after escalation.
177              // if clr is locked down, only a system reset
178              // will get us out of this state
179              Terminal: begin
180                cnt_clr = 1'b1;
181                if (clr_i) begin
                   -14-  
182                  state_d = Idle;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184              end
185              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered

203            if (!rst_ni) begin
               -1-  
204              state_q <= Idle;
                 ==>
205              cnt_q   <= '0;
206            end else begin
207              state_q <= state_d;
208        
209              // escalation counter
210              if (cnt_en && cnt_clr) begin
                 -2-  
211                cnt_q <= EscCntDw'(1'b1);
                   ==>
212              end else if (cnt_clr) begin
                          -3-  
213                cnt_q <= '0;
                   ==>
214              end else if (cnt_en) begin
                          -4-  
215                cnt_q <= cnt_d;
                   ==>
216              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status
1	-	-	-	Covered
0	1	-	-	Covered
0	0	1	-	Covered
0	0	0	1	Covered
0	0	0	0	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_classes[2].i_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckAccumTrig0	2147483647	74953	0	0
CheckAccumTrig1	2147483647	6314	0	0
CheckClr	2147483647	81239	0	0
CheckEn	2147483647	2147483647	0	711
CheckPhase0	2147483647	78946	0	0
CheckPhase1	2147483647	75016	0	0
CheckPhase2	2147483647	68659	0	0
CheckPhase3	2147483647	63308	0	0
CheckTimeout0	2147483647	50998	0	0
CheckTimeout1	2147483647	1083901	0	0
CheckTimeout2	2147483647	44649	0	0
CheckTimeoutTrig	2147483647	24	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].i_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		92	92	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	71	70	70	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	203	10	10	100.00

51                        // escalation counter, used for all phases and the timeout
52         1/1            assign cnt_d = cnt_q + 1'b1;
53                      
54                        // current state output
55         1/1            assign esc_state_o = state_q;
56         1/1            assign esc_cnt_o   = cnt_q;
57                      
58                        // threshold test, the thresholds are muxed further below
59                        // depending on the current state
60                        logic [EscCntDw-1:0] thresh;
61         1/1            assign cnt_ge    = (cnt_q >= thresh);
62                      
63                        //////////////
64                        // Main FSM //
65                        //////////////
66                      
67                        logic [N_PHASES-1:0] phase_oh;
68                      
69                        always_comb begin : p_fsm
70                          // default
71         1/1              state_d    = state_q;
72         1/1              cnt_en     = 1'b0;
73         1/1              cnt_clr    = 1'b0;
74         1/1              esc_trig_o = 1'b0;
75         1/1              phase_oh   = '0;
76         1/1              thresh     = timeout_cyc_i;
77                      
78         1/1              unique case (state_q)
79                            // wait for an escalation trigger or an alert trigger
80                            // the latter will trigger an interrupt timeout
81                            Idle: begin
82         1/1                  cnt_clr = 1'b1;
83                      
84         1/1                  if (accum_trig_i && en_i && !clr_i) begin
85         1/1                    state_d    = Phase0;
86         1/1                    cnt_en     = 1'b1;
87         1/1                    esc_trig_o = 1'b1;
88                              // the counter is zero in this state. so if the
89                              // timeout count is zero (==disabled), cnt_ge will be true.
90         1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
91         1/1                    cnt_en  = 1'b1;
92         1/1                    state_d = Timeout;
93                              end
                        MISSING_ELSE
94                            end
95                            // we are in interrupt timeout state
96                            // in case an escalation comes in, we immediately have to
97                            // switch over to the first escalation phase.
98                            // in case the interrupt timeout hits it's cycle count, we
99                            // also enter escalation phase0.
100                           // ongoing timeouts can always be cleared.
101                           Timeout: begin
102        1/1                  if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
103        1/1                    state_d    = Phase0;
104        1/1                    cnt_en     = 1'b1;
105        1/1                    cnt_clr    = 1'b1;
106        1/1                    esc_trig_o = 1'b1;
107                             // the timeout enable is connected to the irq state
108                             // if that is cleared, stop the timeout counter
109        1/1                  end else if (timeout_en_i) begin
110        1/1                    cnt_en  = 1'b1;
111                             end else begin
112        1/1                    state_d = Idle;
113        1/1                    cnt_clr = 1'b1;
114                             end
115                           end
116                           // note: autolocking the clear signal is done in the regfile
117                           Phase0: begin
118        1/1                  cnt_en      = 1'b1;
119        1/1                  phase_oh[0] = 1'b1;
120        1/1                  thresh      = phase_cyc_i[0];
121                     
122        1/1                  if (clr_i) begin
123        1/1                    state_d = Idle;
124        1/1                    cnt_clr = 1'b1;
125        1/1                    cnt_en  = 1'b0;
126        1/1                  end else if (cnt_ge) begin
127        1/1                    state_d = Phase1;
128        1/1                    cnt_clr = 1'b1;
129        1/1                    cnt_en  = 1'b1;
130                             end
                        MISSING_ELSE
131                           end
132                           Phase1: begin
133        1/1                  cnt_en      = 1'b1;
134        1/1                  phase_oh[1] = 1'b1;
135        1/1                  thresh      = phase_cyc_i[1];
136                     
137        1/1                  if (clr_i) begin
138        1/1                    state_d = Idle;
139        1/1                    cnt_clr = 1'b1;
140        1/1                    cnt_en  = 1'b0;
141        1/1                  end else if (cnt_ge) begin
142        1/1                    state_d = Phase2;
143        1/1                    cnt_clr = 1'b1;
144        1/1                    cnt_en  = 1'b1;
145                             end
                        MISSING_ELSE
146                           end
147                           Phase2: begin
148        1/1                  cnt_en      = 1'b1;
149        1/1                  phase_oh[2] = 1'b1;
150        1/1                  thresh      = phase_cyc_i[2];
151                     
152        1/1                  if (clr_i) begin
153        1/1                    state_d = Idle;
154        1/1                    cnt_clr = 1'b1;
155        1/1                    cnt_en  = 1'b0;
156        1/1                  end else if (cnt_ge) begin
157        1/1                    state_d = Phase3;
158        1/1                    cnt_clr = 1'b1;
159                             end
                        MISSING_ELSE
160                           end
161                           Phase3: begin
162        1/1                  cnt_en      = 1'b1;
163        1/1                  phase_oh[3] = 1'b1;
164        1/1                  thresh      = phase_cyc_i[3];
165                     
166        1/1                  if (clr_i) begin
167        1/1                    state_d = Idle;
168        1/1                    cnt_clr = 1'b1;
169        1/1                    cnt_en  = 1'b0;
170        1/1                  end else if (cnt_ge) begin
171        1/1                    state_d = Terminal;
172        1/1                    cnt_clr = 1'b1;
173        1/1                    cnt_en  = 1'b0;
174                             end
                        MISSING_ELSE
175                           end
176                           // final, terminal state after escalation.
177                           // if clr is locked down, only a system reset
178                           // will get us out of this state
179                           Terminal: begin
180        1/1                  cnt_clr = 1'b1;
181        1/1                  if (clr_i) begin
182        1/1                    state_d = Idle;
183                             end
                        MISSING_ELSE
184                           end
185                           default: state_d = Idle;
186                         endcase
187                       end
188                     
189                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
190                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
191                         // generate configuration mask for escalation enable signals
192        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
193                         // mask reduce current phase state vector
194        4/4              assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
195                       end
196                     
197                       ///////////////
198                       // Registers //
199                       ///////////////
200                     
201                       // switch interrupt / escalation mode
202                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
203        1/1              if (!rst_ni) begin
204        1/1                state_q <= Idle;
205        1/1                cnt_q   <= '0;
206                         end else begin
207        1/1                state_q <= state_d;
208                     
209                           // escalation counter
210        1/1                if (cnt_en && cnt_clr) begin
211        1/1                  cnt_q <= EscCntDw'(1'b1);
212        1/1                end else if (cnt_clr) begin
213        1/1                  cnt_q <= '0;
214        1/1                end else if (cnt_en) begin
215        1/1                  cnt_q <= cnt_d;
216                           end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_classes[0].i_esc_timer

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
             ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       90
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Covered
1	1	0	Covered
1	1	1	Covered

 LINE       102
 EXPRESSION ((accum_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             ------------------1-----------------    ------------2-----------

-1-	-2-	Status
0	0	Covered
0	1	Covered
1	0	Covered

 LINE       102
 SUB-EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
                 ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       102
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

 LINE       210
 EXPRESSION (cnt_en && cnt_clr)
             ---1--    ---2---

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

---

FSM Coverage for Instance : tb.dut.gen_classes[0].i_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered
Idle	204	Covered
Phase0	85	Covered
Phase1	127	Covered
Phase2	142	Covered
Phase3	157	Covered
Terminal	171	Covered
Timeout	92	Covered

transitions	Line No.	Covered
Idle->Phase0	85	Covered
Idle->Timeout	92	Covered
Phase0->Idle	204	Covered
Phase0->Phase1	127	Covered
Phase1->Idle	204	Covered
Phase1->Phase2	142	Covered
Phase2->Idle	204	Covered
Phase2->Phase3	157	Covered
Phase3->Idle	204	Covered
Phase3->Terminal	171	Covered
Terminal->Idle	204	Covered
Timeout->Idle	204	Covered
Timeout->Phase0	103	Covered

---

Branch Coverage for Instance : tb.dut.gen_classes[0].i_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	78	21	21	100.00
IF	203	5	4	80.00

78             unique case (state_q)
                      -1-  
79               // wait for an escalation trigger or an alert trigger
80               // the latter will trigger an interrupt timeout
81               Idle: begin
82                 cnt_clr = 1'b1;
83         
84                 if (accum_trig_i && en_i && !clr_i) begin
                   -2-  
85                   state_d    = Phase0;
                     ==>
86                   cnt_en     = 1'b1;
87                   esc_trig_o = 1'b1;
88                 // the counter is zero in this state. so if the
89                 // timeout count is zero (==disabled), cnt_ge will be true.
90                 end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
91                   cnt_en  = 1'b1;
                     ==>
92                   state_d = Timeout;
93                 end
                   MISSING_ELSE
                   ==>
94               end
95               // we are in interrupt timeout state
96               // in case an escalation comes in, we immediately have to
97               // switch over to the first escalation phase.
98               // in case the interrupt timeout hits it's cycle count, we
99               // also enter escalation phase0.
100              // ongoing timeouts can always be cleared.
101              Timeout: begin
102                if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
103                  state_d    = Phase0;
                     ==>
104                  cnt_en     = 1'b1;
105                  cnt_clr    = 1'b1;
106                  esc_trig_o = 1'b1;
107                // the timeout enable is connected to the irq state
108                // if that is cleared, stop the timeout counter
109                end else if (timeout_en_i) begin
                            -5-  
110                  cnt_en  = 1'b1;
                     ==>
111                end else begin
112                  state_d = Idle;
                     ==>
113                  cnt_clr = 1'b1;
114                end
115              end
116              // note: autolocking the clear signal is done in the regfile
117              Phase0: begin
118                cnt_en      = 1'b1;
119                phase_oh[0] = 1'b1;
120                thresh      = phase_cyc_i[0];
121        
122                if (clr_i) begin
                   -6-  
123                  state_d = Idle;
                     ==>
124                  cnt_clr = 1'b1;
125                  cnt_en  = 1'b0;
126                end else if (cnt_ge) begin
                            -7-  
127                  state_d = Phase1;
                     ==>
128                  cnt_clr = 1'b1;
129                  cnt_en  = 1'b1;
130                end
                   MISSING_ELSE
                   ==>
131              end
132              Phase1: begin
133                cnt_en      = 1'b1;
134                phase_oh[1] = 1'b1;
135                thresh      = phase_cyc_i[1];
136        
137                if (clr_i) begin
                   -8-  
138                  state_d = Idle;
                     ==>
139                  cnt_clr = 1'b1;
140                  cnt_en  = 1'b0;
141                end else if (cnt_ge) begin
                            -9-  
142                  state_d = Phase2;
                     ==>
143                  cnt_clr = 1'b1;
144                  cnt_en  = 1'b1;
145                end
                   MISSING_ELSE
                   ==>
146              end
147              Phase2: begin
148                cnt_en      = 1'b1;
149                phase_oh[2] = 1'b1;
150                thresh      = phase_cyc_i[2];
151        
152                if (clr_i) begin
                   -10-  
153                  state_d = Idle;
                     ==>
154                  cnt_clr = 1'b1;
155                  cnt_en  = 1'b0;
156                end else if (cnt_ge) begin
                            -11-  
157                  state_d = Phase3;
                     ==>
158                  cnt_clr = 1'b1;
159                end
                   MISSING_ELSE
                   ==>
160              end
161              Phase3: begin
162                cnt_en      = 1'b1;
163                phase_oh[3] = 1'b1;
164                thresh      = phase_cyc_i[3];
165        
166                if (clr_i) begin
                   -12-  
167                  state_d = Idle;
                     ==>
168                  cnt_clr = 1'b1;
169                  cnt_en  = 1'b0;
170                end else if (cnt_ge) begin
                            -13-  
171                  state_d = Terminal;
                     ==>
172                  cnt_clr = 1'b1;
173                  cnt_en  = 1'b0;
174                end
                   MISSING_ELSE
                   ==>
175              end
176              // final, terminal state after escalation.
177              // if clr is locked down, only a system reset
178              // will get us out of this state
179              Terminal: begin
180                cnt_clr = 1'b1;
181                if (clr_i) begin
                   -14-  
182                  state_d = Idle;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184              end
185              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered

203            if (!rst_ni) begin
               -1-  
204              state_q <= Idle;
                 ==>
205              cnt_q   <= '0;
206            end else begin
207              state_q <= state_d;
208        
209              // escalation counter
210              if (cnt_en && cnt_clr) begin
                 -2-  
211                cnt_q <= EscCntDw'(1'b1);
                   ==>
212              end else if (cnt_clr) begin
                          -3-  
213                cnt_q <= '0;
                   ==>
214              end else if (cnt_en) begin
                          -4-  
215                cnt_q <= cnt_d;
                   ==>
216              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status
1	-	-	-	Covered
0	1	-	-	Covered
0	0	1	-	Covered
0	0	0	1	Covered
0	0	0	0	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_classes[0].i_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckAccumTrig0	2147483647	85076	0	0
CheckAccumTrig1	2147483647	1257	0	0
CheckClr	2147483647	86196	0	0
CheckEn	2147483647	2147483647	0	682
CheckPhase0	2147483647	81597	0	0
CheckPhase1	2147483647	78863	0	0
CheckPhase2	2147483647	74825	0	0
CheckPhase3	2147483647	71999	0	0
CheckTimeout0	2147483647	46089	0	0
CheckTimeout1	2147483647	1024820	0	0
CheckTimeout2	2147483647	44814	0	0
CheckTimeoutTrig	2147483647	10	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].i_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		92	92	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	71	70	70	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	203	10	10	100.00

51                        // escalation counter, used for all phases and the timeout
52         1/1            assign cnt_d = cnt_q + 1'b1;
53                      
54                        // current state output
55         1/1            assign esc_state_o = state_q;
56         1/1            assign esc_cnt_o   = cnt_q;
57                      
58                        // threshold test, the thresholds are muxed further below
59                        // depending on the current state
60                        logic [EscCntDw-1:0] thresh;
61         1/1            assign cnt_ge    = (cnt_q >= thresh);
62                      
63                        //////////////
64                        // Main FSM //
65                        //////////////
66                      
67                        logic [N_PHASES-1:0] phase_oh;
68                      
69                        always_comb begin : p_fsm
70                          // default
71         1/1              state_d    = state_q;
72         1/1              cnt_en     = 1'b0;
73         1/1              cnt_clr    = 1'b0;
74         1/1              esc_trig_o = 1'b0;
75         1/1              phase_oh   = '0;
76         1/1              thresh     = timeout_cyc_i;
77                      
78         1/1              unique case (state_q)
79                            // wait for an escalation trigger or an alert trigger
80                            // the latter will trigger an interrupt timeout
81                            Idle: begin
82         1/1                  cnt_clr = 1'b1;
83                      
84         1/1                  if (accum_trig_i && en_i && !clr_i) begin
85         1/1                    state_d    = Phase0;
86         1/1                    cnt_en     = 1'b1;
87         1/1                    esc_trig_o = 1'b1;
88                              // the counter is zero in this state. so if the
89                              // timeout count is zero (==disabled), cnt_ge will be true.
90         1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
91         1/1                    cnt_en  = 1'b1;
92         1/1                    state_d = Timeout;
93                              end
                        MISSING_ELSE
94                            end
95                            // we are in interrupt timeout state
96                            // in case an escalation comes in, we immediately have to
97                            // switch over to the first escalation phase.
98                            // in case the interrupt timeout hits it's cycle count, we
99                            // also enter escalation phase0.
100                           // ongoing timeouts can always be cleared.
101                           Timeout: begin
102        1/1                  if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
103        1/1                    state_d    = Phase0;
104        1/1                    cnt_en     = 1'b1;
105        1/1                    cnt_clr    = 1'b1;
106        1/1                    esc_trig_o = 1'b1;
107                             // the timeout enable is connected to the irq state
108                             // if that is cleared, stop the timeout counter
109        1/1                  end else if (timeout_en_i) begin
110        1/1                    cnt_en  = 1'b1;
111                             end else begin
112        1/1                    state_d = Idle;
113        1/1                    cnt_clr = 1'b1;
114                             end
115                           end
116                           // note: autolocking the clear signal is done in the regfile
117                           Phase0: begin
118        1/1                  cnt_en      = 1'b1;
119        1/1                  phase_oh[0] = 1'b1;
120        1/1                  thresh      = phase_cyc_i[0];
121                     
122        1/1                  if (clr_i) begin
123        1/1                    state_d = Idle;
124        1/1                    cnt_clr = 1'b1;
125        1/1                    cnt_en  = 1'b0;
126        1/1                  end else if (cnt_ge) begin
127        1/1                    state_d = Phase1;
128        1/1                    cnt_clr = 1'b1;
129        1/1                    cnt_en  = 1'b1;
130                             end
                        MISSING_ELSE
131                           end
132                           Phase1: begin
133        1/1                  cnt_en      = 1'b1;
134        1/1                  phase_oh[1] = 1'b1;
135        1/1                  thresh      = phase_cyc_i[1];
136                     
137        1/1                  if (clr_i) begin
138        1/1                    state_d = Idle;
139        1/1                    cnt_clr = 1'b1;
140        1/1                    cnt_en  = 1'b0;
141        1/1                  end else if (cnt_ge) begin
142        1/1                    state_d = Phase2;
143        1/1                    cnt_clr = 1'b1;
144        1/1                    cnt_en  = 1'b1;
145                             end
                        MISSING_ELSE
146                           end
147                           Phase2: begin
148        1/1                  cnt_en      = 1'b1;
149        1/1                  phase_oh[2] = 1'b1;
150        1/1                  thresh      = phase_cyc_i[2];
151                     
152        1/1                  if (clr_i) begin
153        1/1                    state_d = Idle;
154        1/1                    cnt_clr = 1'b1;
155        1/1                    cnt_en  = 1'b0;
156        1/1                  end else if (cnt_ge) begin
157        1/1                    state_d = Phase3;
158        1/1                    cnt_clr = 1'b1;
159                             end
                        MISSING_ELSE
160                           end
161                           Phase3: begin
162        1/1                  cnt_en      = 1'b1;
163        1/1                  phase_oh[3] = 1'b1;
164        1/1                  thresh      = phase_cyc_i[3];
165                     
166        1/1                  if (clr_i) begin
167        1/1                    state_d = Idle;
168        1/1                    cnt_clr = 1'b1;
169        1/1                    cnt_en  = 1'b0;
170        1/1                  end else if (cnt_ge) begin
171        1/1                    state_d = Terminal;
172        1/1                    cnt_clr = 1'b1;
173        1/1                    cnt_en  = 1'b0;
174                             end
                        MISSING_ELSE
175                           end
176                           // final, terminal state after escalation.
177                           // if clr is locked down, only a system reset
178                           // will get us out of this state
179                           Terminal: begin
180        1/1                  cnt_clr = 1'b1;
181        1/1                  if (clr_i) begin
182        1/1                    state_d = Idle;
183                             end
                        MISSING_ELSE
184                           end
185                           default: state_d = Idle;
186                         endcase
187                       end
188                     
189                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
190                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
191                         // generate configuration mask for escalation enable signals
192        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
193                         // mask reduce current phase state vector
194        4/4              assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
195                       end
196                     
197                       ///////////////
198                       // Registers //
199                       ///////////////
200                     
201                       // switch interrupt / escalation mode
202                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
203        1/1              if (!rst_ni) begin
204        1/1                state_q <= Idle;
205        1/1                cnt_q   <= '0;
206                         end else begin
207        1/1                state_q <= state_d;
208                     
209                           // escalation counter
210        1/1                if (cnt_en && cnt_clr) begin
211        1/1                  cnt_q <= EscCntDw'(1'b1);
212        1/1                end else if (cnt_clr) begin
213        1/1                  cnt_q <= '0;
214        1/1                end else if (cnt_en) begin
215        1/1                  cnt_q <= cnt_d;
216                           end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_classes[1].i_esc_timer

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
             ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       90
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Covered
1	1	0	Covered
1	1	1	Covered

 LINE       102
 EXPRESSION ((accum_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             ------------------1-----------------    ------------2-----------

-1-	-2-	Status
0	0	Covered
0	1	Covered
1	0	Covered

 LINE       102
 SUB-EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
                 ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       102
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

 LINE       210
 EXPRESSION (cnt_en && cnt_clr)
             ---1--    ---2---

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

---

FSM Coverage for Instance : tb.dut.gen_classes[1].i_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered
Idle	204	Covered
Phase0	85	Covered
Phase1	127	Covered
Phase2	142	Covered
Phase3	157	Covered
Terminal	171	Covered
Timeout	92	Covered

transitions	Line No.	Covered
Idle->Phase0	85	Covered
Idle->Timeout	92	Covered
Phase0->Idle	204	Covered
Phase0->Phase1	127	Covered
Phase1->Idle	204	Covered
Phase1->Phase2	142	Covered
Phase2->Idle	204	Covered
Phase2->Phase3	157	Covered
Phase3->Idle	204	Covered
Phase3->Terminal	171	Covered
Terminal->Idle	204	Covered
Timeout->Idle	204	Covered
Timeout->Phase0	103	Covered

---

Branch Coverage for Instance : tb.dut.gen_classes[1].i_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	78	21	21	100.00
IF	203	5	4	80.00

78             unique case (state_q)
                      -1-  
79               // wait for an escalation trigger or an alert trigger
80               // the latter will trigger an interrupt timeout
81               Idle: begin
82                 cnt_clr = 1'b1;
83         
84                 if (accum_trig_i && en_i && !clr_i) begin
                   -2-  
85                   state_d    = Phase0;
                     ==>
86                   cnt_en     = 1'b1;
87                   esc_trig_o = 1'b1;
88                 // the counter is zero in this state. so if the
89                 // timeout count is zero (==disabled), cnt_ge will be true.
90                 end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
91                   cnt_en  = 1'b1;
                     ==>
92                   state_d = Timeout;
93                 end
                   MISSING_ELSE
                   ==>
94               end
95               // we are in interrupt timeout state
96               // in case an escalation comes in, we immediately have to
97               // switch over to the first escalation phase.
98               // in case the interrupt timeout hits it's cycle count, we
99               // also enter escalation phase0.
100              // ongoing timeouts can always be cleared.
101              Timeout: begin
102                if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
103                  state_d    = Phase0;
                     ==>
104                  cnt_en     = 1'b1;
105                  cnt_clr    = 1'b1;
106                  esc_trig_o = 1'b1;
107                // the timeout enable is connected to the irq state
108                // if that is cleared, stop the timeout counter
109                end else if (timeout_en_i) begin
                            -5-  
110                  cnt_en  = 1'b1;
                     ==>
111                end else begin
112                  state_d = Idle;
                     ==>
113                  cnt_clr = 1'b1;
114                end
115              end
116              // note: autolocking the clear signal is done in the regfile
117              Phase0: begin
118                cnt_en      = 1'b1;
119                phase_oh[0] = 1'b1;
120                thresh      = phase_cyc_i[0];
121        
122                if (clr_i) begin
                   -6-  
123                  state_d = Idle;
                     ==>
124                  cnt_clr = 1'b1;
125                  cnt_en  = 1'b0;
126                end else if (cnt_ge) begin
                            -7-  
127                  state_d = Phase1;
                     ==>
128                  cnt_clr = 1'b1;
129                  cnt_en  = 1'b1;
130                end
                   MISSING_ELSE
                   ==>
131              end
132              Phase1: begin
133                cnt_en      = 1'b1;
134                phase_oh[1] = 1'b1;
135                thresh      = phase_cyc_i[1];
136        
137                if (clr_i) begin
                   -8-  
138                  state_d = Idle;
                     ==>
139                  cnt_clr = 1'b1;
140                  cnt_en  = 1'b0;
141                end else if (cnt_ge) begin
                            -9-  
142                  state_d = Phase2;
                     ==>
143                  cnt_clr = 1'b1;
144                  cnt_en  = 1'b1;
145                end
                   MISSING_ELSE
                   ==>
146              end
147              Phase2: begin
148                cnt_en      = 1'b1;
149                phase_oh[2] = 1'b1;
150                thresh      = phase_cyc_i[2];
151        
152                if (clr_i) begin
                   -10-  
153                  state_d = Idle;
                     ==>
154                  cnt_clr = 1'b1;
155                  cnt_en  = 1'b0;
156                end else if (cnt_ge) begin
                            -11-  
157                  state_d = Phase3;
                     ==>
158                  cnt_clr = 1'b1;
159                end
                   MISSING_ELSE
                   ==>
160              end
161              Phase3: begin
162                cnt_en      = 1'b1;
163                phase_oh[3] = 1'b1;
164                thresh      = phase_cyc_i[3];
165        
166                if (clr_i) begin
                   -12-  
167                  state_d = Idle;
                     ==>
168                  cnt_clr = 1'b1;
169                  cnt_en  = 1'b0;
170                end else if (cnt_ge) begin
                            -13-  
171                  state_d = Terminal;
                     ==>
172                  cnt_clr = 1'b1;
173                  cnt_en  = 1'b0;
174                end
                   MISSING_ELSE
                   ==>
175              end
176              // final, terminal state after escalation.
177              // if clr is locked down, only a system reset
178              // will get us out of this state
179              Terminal: begin
180                cnt_clr = 1'b1;
181                if (clr_i) begin
                   -14-  
182                  state_d = Idle;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184              end
185              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered

203            if (!rst_ni) begin
               -1-  
204              state_q <= Idle;
                 ==>
205              cnt_q   <= '0;
206            end else begin
207              state_q <= state_d;
208        
209              // escalation counter
210              if (cnt_en && cnt_clr) begin
                 -2-  
211                cnt_q <= EscCntDw'(1'b1);
                   ==>
212              end else if (cnt_clr) begin
                          -3-  
213                cnt_q <= '0;
                   ==>
214              end else if (cnt_en) begin
                          -4-  
215                cnt_q <= cnt_d;
                   ==>
216              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status
1	-	-	-	Covered
0	1	-	-	Covered
0	0	1	-	Covered
0	0	0	1	Covered
0	0	0	0	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_classes[1].i_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckAccumTrig0	2147483647	87520	0	0
CheckAccumTrig1	2147483647	2004	0	0
CheckClr	2147483647	89761	0	0
CheckEn	2147483647	2147483647	0	698
CheckPhase0	2147483647	86303	0	0
CheckPhase1	2147483647	81832	0	0
CheckPhase2	2147483647	77930	0	0
CheckPhase3	2147483647	73009	0	0
CheckTimeout0	2147483647	25707	0	0
CheckTimeout1	2147483647	579799	0	0
CheckTimeout2	2147483647	23399	0	0
CheckTimeoutTrig	2147483647	294	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].i_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		92	92	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	61	1	1	100.00
ALWAYS	71	70	70	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	192	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	194	1	1	100.00
ALWAYS	203	10	10	100.00

51                        // escalation counter, used for all phases and the timeout
52         1/1            assign cnt_d = cnt_q + 1'b1;
53                      
54                        // current state output
55         1/1            assign esc_state_o = state_q;
56         1/1            assign esc_cnt_o   = cnt_q;
57                      
58                        // threshold test, the thresholds are muxed further below
59                        // depending on the current state
60                        logic [EscCntDw-1:0] thresh;
61         1/1            assign cnt_ge    = (cnt_q >= thresh);
62                      
63                        //////////////
64                        // Main FSM //
65                        //////////////
66                      
67                        logic [N_PHASES-1:0] phase_oh;
68                      
69                        always_comb begin : p_fsm
70                          // default
71         1/1              state_d    = state_q;
72         1/1              cnt_en     = 1'b0;
73         1/1              cnt_clr    = 1'b0;
74         1/1              esc_trig_o = 1'b0;
75         1/1              phase_oh   = '0;
76         1/1              thresh     = timeout_cyc_i;
77                      
78         1/1              unique case (state_q)
79                            // wait for an escalation trigger or an alert trigger
80                            // the latter will trigger an interrupt timeout
81                            Idle: begin
82         1/1                  cnt_clr = 1'b1;
83                      
84         1/1                  if (accum_trig_i && en_i && !clr_i) begin
85         1/1                    state_d    = Phase0;
86         1/1                    cnt_en     = 1'b1;
87         1/1                    esc_trig_o = 1'b1;
88                              // the counter is zero in this state. so if the
89                              // timeout count is zero (==disabled), cnt_ge will be true.
90         1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
91         1/1                    cnt_en  = 1'b1;
92         1/1                    state_d = Timeout;
93                              end
                        MISSING_ELSE
94                            end
95                            // we are in interrupt timeout state
96                            // in case an escalation comes in, we immediately have to
97                            // switch over to the first escalation phase.
98                            // in case the interrupt timeout hits it's cycle count, we
99                            // also enter escalation phase0.
100                           // ongoing timeouts can always be cleared.
101                           Timeout: begin
102        1/1                  if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
103        1/1                    state_d    = Phase0;
104        1/1                    cnt_en     = 1'b1;
105        1/1                    cnt_clr    = 1'b1;
106        1/1                    esc_trig_o = 1'b1;
107                             // the timeout enable is connected to the irq state
108                             // if that is cleared, stop the timeout counter
109        1/1                  end else if (timeout_en_i) begin
110        1/1                    cnt_en  = 1'b1;
111                             end else begin
112        1/1                    state_d = Idle;
113        1/1                    cnt_clr = 1'b1;
114                             end
115                           end
116                           // note: autolocking the clear signal is done in the regfile
117                           Phase0: begin
118        1/1                  cnt_en      = 1'b1;
119        1/1                  phase_oh[0] = 1'b1;
120        1/1                  thresh      = phase_cyc_i[0];
121                     
122        1/1                  if (clr_i) begin
123        1/1                    state_d = Idle;
124        1/1                    cnt_clr = 1'b1;
125        1/1                    cnt_en  = 1'b0;
126        1/1                  end else if (cnt_ge) begin
127        1/1                    state_d = Phase1;
128        1/1                    cnt_clr = 1'b1;
129        1/1                    cnt_en  = 1'b1;
130                             end
                        MISSING_ELSE
131                           end
132                           Phase1: begin
133        1/1                  cnt_en      = 1'b1;
134        1/1                  phase_oh[1] = 1'b1;
135        1/1                  thresh      = phase_cyc_i[1];
136                     
137        1/1                  if (clr_i) begin
138        1/1                    state_d = Idle;
139        1/1                    cnt_clr = 1'b1;
140        1/1                    cnt_en  = 1'b0;
141        1/1                  end else if (cnt_ge) begin
142        1/1                    state_d = Phase2;
143        1/1                    cnt_clr = 1'b1;
144        1/1                    cnt_en  = 1'b1;
145                             end
                        MISSING_ELSE
146                           end
147                           Phase2: begin
148        1/1                  cnt_en      = 1'b1;
149        1/1                  phase_oh[2] = 1'b1;
150        1/1                  thresh      = phase_cyc_i[2];
151                     
152        1/1                  if (clr_i) begin
153        1/1                    state_d = Idle;
154        1/1                    cnt_clr = 1'b1;
155        1/1                    cnt_en  = 1'b0;
156        1/1                  end else if (cnt_ge) begin
157        1/1                    state_d = Phase3;
158        1/1                    cnt_clr = 1'b1;
159                             end
                        MISSING_ELSE
160                           end
161                           Phase3: begin
162        1/1                  cnt_en      = 1'b1;
163        1/1                  phase_oh[3] = 1'b1;
164        1/1                  thresh      = phase_cyc_i[3];
165                     
166        1/1                  if (clr_i) begin
167        1/1                    state_d = Idle;
168        1/1                    cnt_clr = 1'b1;
169        1/1                    cnt_en  = 1'b0;
170        1/1                  end else if (cnt_ge) begin
171        1/1                    state_d = Terminal;
172        1/1                    cnt_clr = 1'b1;
173        1/1                    cnt_en  = 1'b0;
174                             end
                        MISSING_ELSE
175                           end
176                           // final, terminal state after escalation.
177                           // if clr is locked down, only a system reset
178                           // will get us out of this state
179                           Terminal: begin
180        1/1                  cnt_clr = 1'b1;
181        1/1                  if (clr_i) begin
182        1/1                    state_d = Idle;
183                             end
                        MISSING_ELSE
184                           end
185                           default: state_d = Idle;
186                         endcase
187                       end
188                     
189                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
190                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
191                         // generate configuration mask for escalation enable signals
192        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
193                         // mask reduce current phase state vector
194        4/4              assign esc_sig_en_o[k] = |(esc_map_oh[k] & phase_oh);
195                       end
196                     
197                       ///////////////
198                       // Registers //
199                       ///////////////
200                     
201                       // switch interrupt / escalation mode
202                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
203        1/1              if (!rst_ni) begin
204        1/1                state_q <= Idle;
205        1/1                cnt_q   <= '0;
206                         end else begin
207        1/1                state_q <= state_d;
208                     
209                           // escalation counter
210        1/1                if (cnt_en && cnt_clr) begin
211        1/1                  cnt_q <= EscCntDw'(1'b1);
212        1/1                end else if (cnt_clr) begin
213        1/1                  cnt_q <= '0;
214        1/1                end else if (cnt_en) begin
215        1/1                  cnt_q <= cnt_d;
216                           end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_classes[3].i_esc_timer

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       84
 EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
             ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       90
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Covered
1	1	0	Covered
1	1	1	Covered

 LINE       102
 EXPRESSION ((accum_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             ------------------1-----------------    ------------2-----------

-1-	-2-	Status
0	0	Covered
0	1	Covered
1	0	Covered

 LINE       102
 SUB-EXPRESSION (accum_trig_i && en_i && ((!clr_i)))
                 ------1-----    --2-    -----3----

-1-	-2-	-3-	Status
0	1	1	Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered

 LINE       102
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

 LINE       210
 EXPRESSION (cnt_en && cnt_clr)
             ---1--    ---2---

-1-	-2-	Status
0	1	Covered
1	0	Covered
1	1	Covered

---

FSM Coverage for Instance : tb.dut.gen_classes[3].i_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	13	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered
Idle	204	Covered
Phase0	85	Covered
Phase1	127	Covered
Phase2	142	Covered
Phase3	157	Covered
Terminal	171	Covered
Timeout	92	Covered

transitions	Line No.	Covered
Idle->Phase0	85	Covered
Idle->Timeout	92	Covered
Phase0->Idle	204	Covered
Phase0->Phase1	127	Covered
Phase1->Idle	204	Covered
Phase1->Phase2	142	Covered
Phase2->Idle	204	Covered
Phase2->Phase3	157	Covered
Phase3->Idle	204	Covered
Phase3->Terminal	171	Covered
Terminal->Idle	204	Covered
Timeout->Idle	204	Covered
Timeout->Phase0	103	Covered

---

Branch Coverage for Instance : tb.dut.gen_classes[3].i_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	25	96.15
CASE	78	21	21	100.00
IF	203	5	4	80.00

78             unique case (state_q)
                      -1-  
79               // wait for an escalation trigger or an alert trigger
80               // the latter will trigger an interrupt timeout
81               Idle: begin
82                 cnt_clr = 1'b1;
83         
84                 if (accum_trig_i && en_i && !clr_i) begin
                   -2-  
85                   state_d    = Phase0;
                     ==>
86                   cnt_en     = 1'b1;
87                   esc_trig_o = 1'b1;
88                 // the counter is zero in this state. so if the
89                 // timeout count is zero (==disabled), cnt_ge will be true.
90                 end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
91                   cnt_en  = 1'b1;
                     ==>
92                   state_d = Timeout;
93                 end
                   MISSING_ELSE
                   ==>
94               end
95               // we are in interrupt timeout state
96               // in case an escalation comes in, we immediately have to
97               // switch over to the first escalation phase.
98               // in case the interrupt timeout hits it's cycle count, we
99               // also enter escalation phase0.
100              // ongoing timeouts can always be cleared.
101              Timeout: begin
102                if ((accum_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
103                  state_d    = Phase0;
                     ==>
104                  cnt_en     = 1'b1;
105                  cnt_clr    = 1'b1;
106                  esc_trig_o = 1'b1;
107                // the timeout enable is connected to the irq state
108                // if that is cleared, stop the timeout counter
109                end else if (timeout_en_i) begin
                            -5-  
110                  cnt_en  = 1'b1;
                     ==>
111                end else begin
112                  state_d = Idle;
                     ==>
113                  cnt_clr = 1'b1;
114                end
115              end
116              // note: autolocking the clear signal is done in the regfile
117              Phase0: begin
118                cnt_en      = 1'b1;
119                phase_oh[0] = 1'b1;
120                thresh      = phase_cyc_i[0];
121        
122                if (clr_i) begin
                   -6-  
123                  state_d = Idle;
                     ==>
124                  cnt_clr = 1'b1;
125                  cnt_en  = 1'b0;
126                end else if (cnt_ge) begin
                            -7-  
127                  state_d = Phase1;
                     ==>
128                  cnt_clr = 1'b1;
129                  cnt_en  = 1'b1;
130                end
                   MISSING_ELSE
                   ==>
131              end
132              Phase1: begin
133                cnt_en      = 1'b1;
134                phase_oh[1] = 1'b1;
135                thresh      = phase_cyc_i[1];
136        
137                if (clr_i) begin
                   -8-  
138                  state_d = Idle;
                     ==>
139                  cnt_clr = 1'b1;
140                  cnt_en  = 1'b0;
141                end else if (cnt_ge) begin
                            -9-  
142                  state_d = Phase2;
                     ==>
143                  cnt_clr = 1'b1;
144                  cnt_en  = 1'b1;
145                end
                   MISSING_ELSE
                   ==>
146              end
147              Phase2: begin
148                cnt_en      = 1'b1;
149                phase_oh[2] = 1'b1;
150                thresh      = phase_cyc_i[2];
151        
152                if (clr_i) begin
                   -10-  
153                  state_d = Idle;
                     ==>
154                  cnt_clr = 1'b1;
155                  cnt_en  = 1'b0;
156                end else if (cnt_ge) begin
                            -11-  
157                  state_d = Phase3;
                     ==>
158                  cnt_clr = 1'b1;
159                end
                   MISSING_ELSE
                   ==>
160              end
161              Phase3: begin
162                cnt_en      = 1'b1;
163                phase_oh[3] = 1'b1;
164                thresh      = phase_cyc_i[3];
165        
166                if (clr_i) begin
                   -12-  
167                  state_d = Idle;
                     ==>
168                  cnt_clr = 1'b1;
169                  cnt_en  = 1'b0;
170                end else if (cnt_ge) begin
                            -13-  
171                  state_d = Terminal;
                     ==>
172                  cnt_clr = 1'b1;
173                  cnt_en  = 1'b0;
174                end
                   MISSING_ELSE
                   ==>
175              end
176              // final, terminal state after escalation.
177              // if clr is locked down, only a system reset
178              // will get us out of this state
179              Terminal: begin
180                cnt_clr = 1'b1;
181                if (clr_i) begin
                   -14-  
182                  state_d = Idle;
                     ==>
183                end
                   MISSING_ELSE
                   ==>
184              end
185              default: state_d = Idle;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered
Idle	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered
Timeout	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered
Phase0	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered
Phase1	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered
Phase2	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered
Phase3	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered
Terminal	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered

203            if (!rst_ni) begin
               -1-  
204              state_q <= Idle;
                 ==>
205              cnt_q   <= '0;
206            end else begin
207              state_q <= state_d;
208        
209              // escalation counter
210              if (cnt_en && cnt_clr) begin
                 -2-  
211                cnt_q <= EscCntDw'(1'b1);
                   ==>
212              end else if (cnt_clr) begin
                          -3-  
213                cnt_q <= '0;
                   ==>
214              end else if (cnt_en) begin
                          -4-  
215                cnt_q <= cnt_d;
                   ==>
216              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	-4-	Status
1	-	-	-	Covered
0	1	-	-	Covered
0	0	1	-	Covered
0	0	0	1	Covered
0	0	0	0	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_classes[3].i_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	12	12	100.00	12	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	12	12	100.00	12	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckAccumTrig0	2147483647	45539	0	0
CheckAccumTrig1	2147483647	14	0	0
CheckClr	2147483647	73946	0	0
CheckEn	2147483647	2147483647	0	673
CheckPhase0	2147483647	70513	0	0
CheckPhase1	2147483647	66200	0	0
CheckPhase2	2147483647	62125	0	0
CheckPhase3	2147483647	58071	0	0
CheckTimeout0	2147483647	53937	0	0
CheckTimeout1	2147483647	578082	0	0
CheckTimeout2	2147483647	25464	0	0
CheckTimeoutTrig	2147483647	28457	0	0