Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : alert_handler
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.69 100.00 69.06 100.00

Source File(s) :
/edascratch/chencindy-opentitan/nightly_openTitan/alert_handler.sim.vcs/master/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.20 100.00 76.60 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.20 100.00 76.60 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.03 99.96 95.77 76.60 83.22 98.97 97.65


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alerts[0].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
gen_alerts[1].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
gen_alerts[2].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
gen_alerts[3].i_alert_receiver 92.22 100.00 100.00 66.67 94.44 100.00
gen_classes[0].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[0].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_classes[1].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[1].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_classes[2].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[2].i_esc_timer 94.47 100.00 76.19 100.00 96.15 100.00
gen_classes[3].i_accu 100.00 100.00 100.00 100.00 100.00
gen_classes[3].i_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
gen_esc_sev[0].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
gen_esc_sev[1].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
gen_esc_sev[2].i_esc_sender 91.56 100.00 93.33 76.47 100.00 88.00
gen_esc_sev[3].i_esc_sender 92.89 100.00 100.00 76.47 100.00 88.00
i_class 100.00 100.00
i_ping_timer 82.89 99.07 60.87 80.00 80.77 93.75
i_reg_wrap 100.00 100.00 100.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00

Line Coverage for Module : alert_handler
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN20311100.00

48 // TODO: make this fully parametric at some point 49 1/1 assign {intr_classd_o, 50 intr_classc_o, 51 intr_classb_o, 52 intr_classa_o} = irq; 53 54 alert_handler_reg_wrap i_reg_wrap ( 55 .clk_i, 56 .rst_ni, 57 .tl_i, 58 .tl_o, 59 .irq_o ( irq ), 60 .crashdump_o, 61 .hw2reg_wrap, 62 .reg2hw_wrap 63 ); 64 65 //////////////// 66 // Ping Timer // 67 //////////////// 68 69 logic [N_LOC_ALERT-1:0] loc_alert_trig; 70 71 logic [NAlerts-1:0] alert_ping_en; 72 logic [NAlerts-1:0] alert_ping_ok; 73 logic [N_ESC_SEV-1:0] esc_ping_en; 74 logic [N_ESC_SEV-1:0] esc_ping_ok; 75 76 alert_handler_ping_timer i_ping_timer ( 77 .clk_i, 78 .rst_ni, 79 .entropy_i, 80 // we enable ping testing as soon as the config 81 // regs have been locked 82 .en_i ( reg2hw_wrap.config_locked ), 83 .alert_en_i ( reg2hw_wrap.alert_en ), 84 .ping_timeout_cyc_i ( reg2hw_wrap.ping_timeout_cyc ), 85 // this determines the range of the randomly generated 86 // wait period between ping. maximum mask width is PING_CNT_DW. 87 .wait_cyc_mask_i ( PING_CNT_DW'(24'hFFFFFF) ), 88 .alert_ping_en_o ( alert_ping_en ), 89 .esc_ping_en_o ( esc_ping_en ), 90 .alert_ping_ok_i ( alert_ping_ok ), 91 .esc_ping_ok_i ( esc_ping_ok ), 92 .alert_ping_fail_o ( loc_alert_trig[0] ), 93 .esc_ping_fail_o ( loc_alert_trig[1] ) 94 ); 95 96 ///////////////////// 97 // Alert Receivers // 98 ///////////////////// 99 100 logic [NAlerts-1:0] alert_integfail; 101 logic [NAlerts-1:0] alert_trig; 102 103 // Target interrupt notification 104 for (genvar k = 0 ; k < NAlerts ; k++) begin : gen_alerts 105 prim_alert_receiver #( 106 .AsyncOn(AsyncOn[k]) 107 ) i_alert_receiver ( 108 .clk_i , 109 .rst_ni , 110 .ping_en_i ( alert_ping_en[k] ), 111 .ping_ok_o ( alert_ping_ok[k] ), 112 .integ_fail_o ( alert_integfail[k] ), 113 .alert_o ( alert_trig[k] ), 114 .alert_rx_o ( alert_rx_o[k] ), 115 .alert_tx_i ( alert_tx_i[k] ) 116 ); 117 end 118 119 1/1 assign loc_alert_trig[2] = |(reg2hw_wrap.alert_en & alert_integfail); 120 121 /////////////////////////////////////// 122 // Set alert cause bits and classify // 123 /////////////////////////////////////// 124 125 alert_handler_class i_class ( 126 .alert_trig_i ( alert_trig ), 127 .loc_alert_trig_i ( loc_alert_trig ), 128 .alert_en_i ( reg2hw_wrap.alert_en ), 129 .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ), 130 .alert_class_i ( reg2hw_wrap.alert_class ), 131 .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ), 132 .alert_cause_o ( hw2reg_wrap.alert_cause ), 133 .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ), 134 .class_trig_o ( hw2reg_wrap.class_trig ) 135 ); 136 137 //////////////////////////////////// 138 // Escalation Handling of Classes // 139 //////////////////////////////////// 140 141 logic [N_CLASSES-1:0] class_accum_trig; 142 logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_en; 143 144 for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes 145 alert_handler_accu i_accu ( 146 .clk_i, 147 .rst_ni, 148 .class_en_i ( reg2hw_wrap.class_en[k] ), 149 .clr_i ( reg2hw_wrap.class_clr[k] ), 150 .class_trig_i ( hw2reg_wrap.class_trig[k] ), 151 .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ), 152 .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ), 153 .accu_trig_o ( class_accum_trig[k] ) 154 ); 155 156 alert_handler_esc_timer i_esc_timer ( 157 .clk_i, 158 .rst_ni, 159 .en_i ( reg2hw_wrap.class_en[k] ), 160 // this clear does not apply to interrupts 161 .clr_i ( reg2hw_wrap.class_clr[k] ), 162 // an interrupt enables the timeout 163 .timeout_en_i ( irq[k] ), 164 .accum_trig_i ( class_accum_trig[k] ), 165 .timeout_cyc_i ( reg2hw_wrap.class_timeout_cyc[k] ), 166 .esc_en_i ( reg2hw_wrap.class_esc_en[k] ), 167 .esc_map_i ( reg2hw_wrap.class_esc_map[k] ), 168 .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ), 169 .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ), 170 .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ), 171 .esc_state_o ( hw2reg_wrap.class_esc_state[k] ), 172 .esc_sig_en_o ( class_esc_sig_en[k] ) 173 ); 174 end 175 176 //////////////////////// 177 // Escalation Senders // 178 //////////////////////// 179 180 logic [N_ESC_SEV-1:0] esc_sig_en; 181 logic [N_ESC_SEV-1:0] esc_integfail; 182 logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_en_trsp; 183 184 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev 185 for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp 186 16/16 assign esc_sig_en_trsp[k][j] = class_esc_sig_en[j][k]; 187 end 188 189 4/4 assign esc_sig_en[k] = |esc_sig_en_trsp[k]; 190 191 prim_esc_sender i_esc_sender ( 192 .clk_i, 193 .rst_ni, 194 .ping_en_i ( esc_ping_en[k] ), 195 .ping_ok_o ( esc_ping_ok[k] ), 196 .integ_fail_o ( esc_integfail[k] ), 197 .esc_en_i ( esc_sig_en[k] ), 198 .esc_rx_i ( esc_rx_i[k] ), 199 .esc_tx_o ( esc_tx_o[k] ) 200 ); 201 end 202 203 1/1 assign loc_alert_trig[3] = |esc_integfail;

Toggle Coverage for Module : alert_handler
TotalCoveredPercent
Totals 73 64 87.67
Total Bits 834 576 69.06
Total Bits 0->1 417 288 69.06
Total Bits 1->0 417 288 69.06

Ports 73 64 87.67
Port Bits 834 576 69.06
Port Bits 0->1 417 288 69.06
Port Bits 1->0 417 288 69.06

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
clk_i Yes Yes Yes INPUT
rst_ni Yes Yes Yes INPUT
tl_i.d_ready Yes Yes Yes INPUT
tl_i.a_user.parity[7:0] No No No INPUT
tl_i.a_user.parity_en No No No INPUT
tl_i.a_user.rsvd1[6:0] No No No INPUT
tl_i.a_data[31:0] Yes Yes Yes INPUT
tl_i.a_mask[3:0] Yes Yes Yes INPUT
tl_i.a_address[31:0] Yes Yes Yes INPUT
tl_i.a_source[7:0] Yes Yes Yes INPUT
tl_i.a_size[1:0] Yes Yes Yes INPUT
tl_i.a_param[2:0] No No No INPUT
tl_i.a_opcode[2:0] Yes Yes Yes INPUT
tl_i.a_valid Yes Yes Yes INPUT
tl_o.a_ready Yes Yes Yes OUTPUT
tl_o.d_error Yes Yes Yes OUTPUT
tl_o.d_user[15:0] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes Yes OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[7:0] Yes Yes Yes OUTPUT
tl_o.d_size[1:0] Yes Yes Yes OUTPUT
tl_o.d_param[2:0] No No No OUTPUT
tl_o.d_opcode[0] Yes Yes Yes OUTPUT
tl_o.d_opcode[2:1] No No No OUTPUT
tl_o.d_valid Yes Yes Yes OUTPUT
intr_classa_o Yes Yes Yes OUTPUT
intr_classb_o Yes Yes Yes OUTPUT
intr_classc_o Yes Yes Yes OUTPUT
intr_classd_o Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[0][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[1][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[2][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[3][9:0] Yes Yes Yes OUTPUT
Other bits of crashdump_o.class_esc_cnt[3:0][31:0] No No No OUTPUT
crashdump_o.class_accum_cnt[3:0][15:0] Yes Yes Yes OUTPUT
crashdump_o.loc_alert_cause[3:0] Yes Yes Yes OUTPUT
crashdump_o.alert_cause[3:0] Yes Yes Yes OUTPUT
entropy_i Yes Yes Yes INPUT
alert_tx_i[0].alert_n Yes Yes Yes INPUT
alert_tx_i[0].alert_p Yes Yes Yes INPUT
alert_tx_i[1].alert_n Yes Yes Yes INPUT
alert_tx_i[1].alert_p Yes Yes Yes INPUT
alert_tx_i[2].alert_n Yes Yes Yes INPUT
alert_tx_i[2].alert_p Yes Yes Yes INPUT
alert_tx_i[3].alert_n Yes Yes Yes INPUT
alert_tx_i[3].alert_p Yes Yes Yes INPUT
alert_rx_o[0].ack_n Yes Yes Yes OUTPUT
alert_rx_o[0].ack_p Yes Yes Yes OUTPUT
alert_rx_o[0].ping_n Yes Yes Yes OUTPUT
alert_rx_o[0].ping_p Yes Yes Yes OUTPUT
alert_rx_o[1].ack_n Yes Yes Yes OUTPUT
alert_rx_o[1].ack_p Yes Yes Yes OUTPUT
alert_rx_o[1].ping_n Yes Yes Yes OUTPUT
alert_rx_o[1].ping_p Yes Yes Yes OUTPUT
alert_rx_o[2].ack_n Yes Yes Yes OUTPUT
alert_rx_o[2].ack_p Yes Yes Yes OUTPUT
alert_rx_o[2].ping_n Yes Yes Yes OUTPUT
alert_rx_o[2].ping_p Yes Yes Yes OUTPUT
alert_rx_o[3].ack_n Yes Yes Yes OUTPUT
alert_rx_o[3].ack_p Yes Yes Yes OUTPUT
alert_rx_o[3].ping_n Yes Yes Yes OUTPUT
alert_rx_o[3].ping_p Yes Yes Yes OUTPUT
esc_rx_i[0].resp_n Yes Yes Yes INPUT
esc_rx_i[0].resp_p Yes Yes Yes INPUT
esc_rx_i[1].resp_n Yes Yes Yes INPUT
esc_rx_i[1].resp_p Yes Yes Yes INPUT
esc_rx_i[2].resp_n Yes Yes Yes INPUT
esc_rx_i[2].resp_p Yes Yes Yes INPUT
esc_rx_i[3].resp_n Yes Yes Yes INPUT
esc_rx_i[3].resp_p Yes Yes Yes INPUT
esc_tx_o[0].esc_n Yes Yes Yes OUTPUT
esc_tx_o[0].esc_p Yes Yes Yes OUTPUT
esc_tx_o[1].esc_n Yes Yes Yes OUTPUT
esc_tx_o[1].esc_p Yes Yes Yes OUTPUT
esc_tx_o[2].esc_n Yes Yes Yes OUTPUT
esc_tx_o[2].esc_p Yes Yes Yes OUTPUT
esc_tx_o[3].esc_n Yes Yes Yes OUTPUT
esc_tx_o[3].esc_p Yes Yes Yes OUTPUT


Assert Coverage for Module : alert_handler
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckPKnownO_A 2147483647 2147483647 0 0
CheckAccuCntDw 919 919 0 0
CheckEscCntDw 919 919 0 0
CheckNAlerts 919 919 0 0
CheckNClasses 919 919 0 0
CheckNEscSev 919 919 0 0
CrashdumpKnownO_A 2147483647 2147483647 0 0
EscPKnownO_A 2147483647 2147483647 0 0
IrqAKnownO_A 2147483647 2147483647 0 0
IrqBKnownO_A 2147483647 2147483647 0 0
IrqCKnownO_A 2147483647 2147483647 0 0
IrqDKnownO_A 2147483647 2147483647 0 0
TlAReadyKnownO_A 2147483647 2147483647 0 0
TlDValidKnownO_A 2147483647 2147483647 0 0

Line Coverage for Instance : tb.dut
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN20311100.00

48 // TODO: make this fully parametric at some point 49 1/1 assign {intr_classd_o, 50 intr_classc_o, 51 intr_classb_o, 52 intr_classa_o} = irq; 53 54 alert_handler_reg_wrap i_reg_wrap ( 55 .clk_i, 56 .rst_ni, 57 .tl_i, 58 .tl_o, 59 .irq_o ( irq ), 60 .crashdump_o, 61 .hw2reg_wrap, 62 .reg2hw_wrap 63 ); 64 65 //////////////// 66 // Ping Timer // 67 //////////////// 68 69 logic [N_LOC_ALERT-1:0] loc_alert_trig; 70 71 logic [NAlerts-1:0] alert_ping_en; 72 logic [NAlerts-1:0] alert_ping_ok; 73 logic [N_ESC_SEV-1:0] esc_ping_en; 74 logic [N_ESC_SEV-1:0] esc_ping_ok; 75 76 alert_handler_ping_timer i_ping_timer ( 77 .clk_i, 78 .rst_ni, 79 .entropy_i, 80 // we enable ping testing as soon as the config 81 // regs have been locked 82 .en_i ( reg2hw_wrap.config_locked ), 83 .alert_en_i ( reg2hw_wrap.alert_en ), 84 .ping_timeout_cyc_i ( reg2hw_wrap.ping_timeout_cyc ), 85 // this determines the range of the randomly generated 86 // wait period between ping. maximum mask width is PING_CNT_DW. 87 .wait_cyc_mask_i ( PING_CNT_DW'(24'hFFFFFF) ), 88 .alert_ping_en_o ( alert_ping_en ), 89 .esc_ping_en_o ( esc_ping_en ), 90 .alert_ping_ok_i ( alert_ping_ok ), 91 .esc_ping_ok_i ( esc_ping_ok ), 92 .alert_ping_fail_o ( loc_alert_trig[0] ), 93 .esc_ping_fail_o ( loc_alert_trig[1] ) 94 ); 95 96 ///////////////////// 97 // Alert Receivers // 98 ///////////////////// 99 100 logic [NAlerts-1:0] alert_integfail; 101 logic [NAlerts-1:0] alert_trig; 102 103 // Target interrupt notification 104 for (genvar k = 0 ; k < NAlerts ; k++) begin : gen_alerts 105 prim_alert_receiver #( 106 .AsyncOn(AsyncOn[k]) 107 ) i_alert_receiver ( 108 .clk_i , 109 .rst_ni , 110 .ping_en_i ( alert_ping_en[k] ), 111 .ping_ok_o ( alert_ping_ok[k] ), 112 .integ_fail_o ( alert_integfail[k] ), 113 .alert_o ( alert_trig[k] ), 114 .alert_rx_o ( alert_rx_o[k] ), 115 .alert_tx_i ( alert_tx_i[k] ) 116 ); 117 end 118 119 1/1 assign loc_alert_trig[2] = |(reg2hw_wrap.alert_en & alert_integfail); 120 121 /////////////////////////////////////// 122 // Set alert cause bits and classify // 123 /////////////////////////////////////// 124 125 alert_handler_class i_class ( 126 .alert_trig_i ( alert_trig ), 127 .loc_alert_trig_i ( loc_alert_trig ), 128 .alert_en_i ( reg2hw_wrap.alert_en ), 129 .loc_alert_en_i ( reg2hw_wrap.loc_alert_en ), 130 .alert_class_i ( reg2hw_wrap.alert_class ), 131 .loc_alert_class_i ( reg2hw_wrap.loc_alert_class ), 132 .alert_cause_o ( hw2reg_wrap.alert_cause ), 133 .loc_alert_cause_o ( hw2reg_wrap.loc_alert_cause ), 134 .class_trig_o ( hw2reg_wrap.class_trig ) 135 ); 136 137 //////////////////////////////////// 138 // Escalation Handling of Classes // 139 //////////////////////////////////// 140 141 logic [N_CLASSES-1:0] class_accum_trig; 142 logic [N_CLASSES-1:0][N_ESC_SEV-1:0] class_esc_sig_en; 143 144 for (genvar k = 0; k < N_CLASSES; k++) begin : gen_classes 145 alert_handler_accu i_accu ( 146 .clk_i, 147 .rst_ni, 148 .class_en_i ( reg2hw_wrap.class_en[k] ), 149 .clr_i ( reg2hw_wrap.class_clr[k] ), 150 .class_trig_i ( hw2reg_wrap.class_trig[k] ), 151 .thresh_i ( reg2hw_wrap.class_accum_thresh[k] ), 152 .accu_cnt_o ( hw2reg_wrap.class_accum_cnt[k] ), 153 .accu_trig_o ( class_accum_trig[k] ) 154 ); 155 156 alert_handler_esc_timer i_esc_timer ( 157 .clk_i, 158 .rst_ni, 159 .en_i ( reg2hw_wrap.class_en[k] ), 160 // this clear does not apply to interrupts 161 .clr_i ( reg2hw_wrap.class_clr[k] ), 162 // an interrupt enables the timeout 163 .timeout_en_i ( irq[k] ), 164 .accum_trig_i ( class_accum_trig[k] ), 165 .timeout_cyc_i ( reg2hw_wrap.class_timeout_cyc[k] ), 166 .esc_en_i ( reg2hw_wrap.class_esc_en[k] ), 167 .esc_map_i ( reg2hw_wrap.class_esc_map[k] ), 168 .phase_cyc_i ( reg2hw_wrap.class_phase_cyc[k] ), 169 .esc_trig_o ( hw2reg_wrap.class_esc_trig[k] ), 170 .esc_cnt_o ( hw2reg_wrap.class_esc_cnt[k] ), 171 .esc_state_o ( hw2reg_wrap.class_esc_state[k] ), 172 .esc_sig_en_o ( class_esc_sig_en[k] ) 173 ); 174 end 175 176 //////////////////////// 177 // Escalation Senders // 178 //////////////////////// 179 180 logic [N_ESC_SEV-1:0] esc_sig_en; 181 logic [N_ESC_SEV-1:0] esc_integfail; 182 logic [N_ESC_SEV-1:0][N_CLASSES-1:0] esc_sig_en_trsp; 183 184 for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_esc_sev 185 for (genvar j = 0; j < N_CLASSES; j++) begin : gen_transp 186 16/16 assign esc_sig_en_trsp[k][j] = class_esc_sig_en[j][k]; 187 end 188 189 4/4 assign esc_sig_en[k] = |esc_sig_en_trsp[k]; 190 191 prim_esc_sender i_esc_sender ( 192 .clk_i, 193 .rst_ni, 194 .ping_en_i ( esc_ping_en[k] ), 195 .ping_ok_o ( esc_ping_ok[k] ), 196 .integ_fail_o ( esc_integfail[k] ), 197 .esc_en_i ( esc_sig_en[k] ), 198 .esc_rx_i ( esc_rx_i[k] ), 199 .esc_tx_o ( esc_tx_o[k] ) 200 ); 201 end 202 203 1/1 assign loc_alert_trig[3] = |esc_integfail;

Toggle Coverage for Instance : tb.dut
TotalCoveredPercent
Totals 66 65 98.48
Total Bits 752 576 76.60
Total Bits 0->1 376 288 76.60
Total Bits 1->0 376 288 76.60

Ports 66 65 98.48
Port Bits 752 576 76.60
Port Bits 0->1 376 288 76.60
Port Bits 1->0 376 288 76.60

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
clk_i Yes Yes Yes INPUT
rst_ni Yes Yes Yes INPUT
tl_i.d_ready Yes Yes Yes INPUT
tl_i.a_user.parity[7:0] Excluded Excluded Excluded INPUT
tl_i.a_user.parity_en Excluded Excluded Excluded INPUT
tl_i.a_user.rsvd1[6:0] Excluded Excluded Excluded INPUT
tl_i.a_data[31:0] Yes Yes Yes INPUT
tl_i.a_mask[3:0] Yes Yes Yes INPUT
tl_i.a_address[31:0] Yes Yes Yes INPUT
tl_i.a_source[7:0] Yes Yes Yes INPUT
tl_i.a_size[1:0] Yes Yes Yes INPUT
tl_i.a_param[2:0] Excluded Excluded Excluded INPUT
tl_i.a_opcode[2:0] Yes Yes Yes INPUT
tl_i.a_valid Yes Yes Yes INPUT
tl_o.a_ready Yes Yes Yes OUTPUT
tl_o.d_error Yes Yes Yes OUTPUT
tl_o.d_user[15:0] Excluded Excluded Excluded OUTPUT
tl_o.d_data[31:0] Yes Yes Yes OUTPUT
tl_o.d_sink Excluded Excluded Excluded OUTPUT
tl_o.d_source[7:0] Yes Yes Yes OUTPUT
tl_o.d_size[1:0] Yes Yes Yes OUTPUT
tl_o.d_param[2:0] Excluded Excluded Excluded OUTPUT
tl_o.d_opcode[0] Yes Yes Yes OUTPUT
tl_o.d_opcode[2:1] Excluded Excluded Excluded OUTPUT
tl_o.d_valid Yes Yes Yes OUTPUT
intr_classa_o Yes Yes Yes OUTPUT
intr_classb_o Yes Yes Yes OUTPUT
intr_classc_o Yes Yes Yes OUTPUT
intr_classd_o Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[0][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[1][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[2][9:0] Yes Yes Yes OUTPUT
crashdump_o.class_esc_cnt[3][9:0] Yes Yes Yes OUTPUT
Other bits of crashdump_o.class_esc_cnt[3:0][31:0] No No No OUTPUT
crashdump_o.class_accum_cnt[3:0][15:0] Yes Yes Yes OUTPUT
crashdump_o.loc_alert_cause[3:0] Yes Yes Yes OUTPUT
crashdump_o.alert_cause[3:0] Yes Yes Yes OUTPUT
entropy_i Yes Yes Yes INPUT
alert_tx_i[0].alert_n Yes Yes Yes INPUT
alert_tx_i[0].alert_p Yes Yes Yes INPUT
alert_tx_i[1].alert_n Yes Yes Yes INPUT
alert_tx_i[1].alert_p Yes Yes Yes INPUT
alert_tx_i[2].alert_n Yes Yes Yes INPUT
alert_tx_i[2].alert_p Yes Yes Yes INPUT
alert_tx_i[3].alert_n Yes Yes Yes INPUT
alert_tx_i[3].alert_p Yes Yes Yes INPUT
alert_rx_o[0].ack_n Yes Yes Yes OUTPUT
alert_rx_o[0].ack_p Yes Yes Yes OUTPUT
alert_rx_o[0].ping_n Yes Yes Yes OUTPUT
alert_rx_o[0].ping_p Yes Yes Yes OUTPUT
alert_rx_o[1].ack_n Yes Yes Yes OUTPUT
alert_rx_o[1].ack_p Yes Yes Yes OUTPUT
alert_rx_o[1].ping_n Yes Yes Yes OUTPUT
alert_rx_o[1].ping_p Yes Yes Yes OUTPUT
alert_rx_o[2].ack_n Yes Yes Yes OUTPUT
alert_rx_o[2].ack_p Yes Yes Yes OUTPUT
alert_rx_o[2].ping_n Yes Yes Yes OUTPUT
alert_rx_o[2].ping_p Yes Yes Yes OUTPUT
alert_rx_o[3].ack_n Yes Yes Yes OUTPUT
alert_rx_o[3].ack_p Yes Yes Yes OUTPUT
alert_rx_o[3].ping_n Yes Yes Yes OUTPUT
alert_rx_o[3].ping_p Yes Yes Yes OUTPUT
esc_rx_i[0].resp_n Yes Yes Yes INPUT
esc_rx_i[0].resp_p Yes Yes Yes INPUT
esc_rx_i[1].resp_n Yes Yes Yes INPUT
esc_rx_i[1].resp_p Yes Yes Yes INPUT
esc_rx_i[2].resp_n Yes Yes Yes INPUT
esc_rx_i[2].resp_p Yes Yes Yes INPUT
esc_rx_i[3].resp_n Yes Yes Yes INPUT
esc_rx_i[3].resp_p Yes Yes Yes INPUT
esc_tx_o[0].esc_n Yes Yes Yes OUTPUT
esc_tx_o[0].esc_p Yes Yes Yes OUTPUT
esc_tx_o[1].esc_n Yes Yes Yes OUTPUT
esc_tx_o[1].esc_p Yes Yes Yes OUTPUT
esc_tx_o[2].esc_n Yes Yes Yes OUTPUT
esc_tx_o[2].esc_p Yes Yes Yes OUTPUT
esc_tx_o[3].esc_n Yes Yes Yes OUTPUT
esc_tx_o[3].esc_p Yes Yes Yes OUTPUT


Assert Coverage for Instance : tb.dut
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckPKnownO_A 2147483647 2147483647 0 0
CheckAccuCntDw 919 919 0 0
CheckEscCntDw 919 919 0 0
CheckNAlerts 919 919 0 0
CheckNClasses 919 919 0 0
CheckNEscSev 919 919 0 0
CrashdumpKnownO_A 2147483647 2147483647 0 0
EscPKnownO_A 2147483647 2147483647 0 0
IrqAKnownO_A 2147483647 2147483647 0 0
IrqBKnownO_A 2147483647 2147483647 0 0
IrqCKnownO_A 2147483647 2147483647 0 0
IrqDKnownO_A 2147483647 2147483647 0 0
TlAReadyKnownO_A 2147483647 2147483647 0 0
TlDValidKnownO_A 2147483647 2147483647 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%