Module Definition
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Module Instance : tb.dut.i_reg_wrap.u_reg.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN4511100.00
ALWAYS481717100.00
CONT_ASSIGN8711100.00

25 logic op_full, op_partial, op_get; 26 1/1 assign op_full = (tl_i.a_opcode == PutFullData); 27 1/1 assign op_partial = (tl_i.a_opcode == PutPartialData); 28 1/1 assign op_get = (tl_i.a_opcode == Get); 29 30 // Anything that doesn't fall into the permitted category, it raises an error 31 1/1 assign err_o = ~(opcode_allowed & a_config_allowed); 32 33 // opcode check 34 1/1 assign opcode_allowed = (tl_i.a_opcode == PutFullData) 35 | (tl_i.a_opcode == PutPartialData) 36 | (tl_i.a_opcode == Get); 37 38 // a channel configuration check 39 logic addr_sz_chk; // address and size alignment check 40 logic mask_chk; // inactive lane a_mask check 41 logic fulldata_chk; // PutFullData should have size match to mask 42 43 logic [MW-1:0] mask; 44 45 1/1 assign mask = (1 << tl_i.a_address[SubAW-1:0]); 46 47 always_comb begin 48 1/1 addr_sz_chk = 1'b0; 49 1/1 mask_chk = 1'b0; 50 1/1 fulldata_chk = 1'b0; // Only valid when opcode is PutFullData 51 52 1/1 if (tl_i.a_valid) begin 53 1/1 unique case (tl_i.a_size) 54 'h0: begin // 1 Byte 55 1/1 addr_sz_chk = 1'b1; 56 1/1 mask_chk = ~|(tl_i.a_mask & ~mask); 57 1/1 fulldata_chk = |(tl_i.a_mask & mask); 58 end 59 60 'h1: begin // 2 Byte 61 1/1 addr_sz_chk = ~tl_i.a_address[0]; 62 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 63 1/1 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) 64 : ~|(tl_i.a_mask & 4'b1100); 65 1/1 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; 66 end 67 68 'h2: begin // 4 Byte 69 1/1 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; 70 1/1 mask_chk = 1'b1; 71 1/1 fulldata_chk = &tl_i.a_mask[3:0]; 72 end 73 74 default: begin // else 75 addr_sz_chk = 1'b0; 76 mask_chk = 1'b0; 77 fulldata_chk = 1'b0; 78 end 79 endcase 80 end else begin 81 1/1 addr_sz_chk = 1'b0; 82 1/1 mask_chk = 1'b0; 83 1/1 fulldata_chk = 1'b0; 84 end 85 end 86 87 1/1 assign a_config_allowed = addr_sz_chk

Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       63
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-Status
0Covered
1Covered

 LINE       65
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-Status
0Covered
1Covered

Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 52 8 8 100.00


52 if (tl_i.a_valid) begin -1- 53 unique case (tl_i.a_size) -2- 54 'h0: begin // 1 Byte 55 addr_sz_chk = 1'b1; ==> 56 mask_chk = ~|(tl_i.a_mask & ~mask); 57 fulldata_chk = |(tl_i.a_mask & mask); 58 end 59 60 'h1: begin // 2 Byte 61 addr_sz_chk = ~tl_i.a_address[0]; 62 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0] 63 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011) -3- ==> ==> 64 : ~|(tl_i.a_mask & 4'b1100); 65 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ; -4- ==> ==> 66 end 67 68 'h2: begin // 4 Byte 69 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0]; ==> 70 mask_chk = 1'b1; 71 fulldata_chk = &tl_i.a_mask[3:0]; 72 end 73 74 default: begin // else 75 addr_sz_chk = 1'b0; ==> 76 mask_chk = 1'b0; 77 fulldata_chk = 1'b0; 78 end 79 endcase 80 end else begin 81 addr_sz_chk = 1'b0; ==>

Branches:
-1--2--3--4-Status
1 'h0 - - Covered
1 'h1 1 - Covered
1 'h1 0 - Covered
1 'h1 - 1 Covered
1 'h1 - 0 Covered
1 'h00000002 - - Covered
1 default - - Covered
0 - - - Covered


Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 919 919 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%