Module Definition
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Module Instance : tb.dut.gen_classes[0].i_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[1].i_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[2].i_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[3].i_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.20 100.00 76.60 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : alert_handler_accu
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3711100.00
ALWAYS4033100.00

28 29 1/1 assign trig_gated = class_trig_i & class_en_i; 30 31 1/1 assign accu_d = (clr_i) ? '0 : // clear 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum 33 accu_q; 34 35 1/1 assign accu_trig_o = (accu_q >= thresh_i) & trig_gated; 36 37 1/1 assign accu_cnt_o = accu_q; 38 39 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 40 1/1 if (!rst_ni) begin 41 1/1 accu_q <= '0; 42 end else begin 43 1/1 accu_q <= accu_d;

Cond Coverage for Module : alert_handler_accu
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (clr_i ? '0 : ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q))
             --1--
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q)
                 ---------------1--------------
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION (trig_gated && ((!(&accu_q))))
                 -----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

Branch Coverage for Module : alert_handler_accu
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 31 3 3 100.00
IF 40 2 2 100.00


31 assign accu_d = (clr_i) ? '0 : // clear -1- ==> 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum -2- ==> ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


40 if (!rst_ni) begin -1- 41 accu_q <= '0; ==> 42 end else begin 43 accu_q <= accu_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Module : alert_handler_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisabledNoTrigBkwd_A 2147483647 14392640 0 0
DisabledNoTrigFwd_A 2147483647 2147483647 0 0

Line Coverage for Instance : tb.dut.gen_classes[0].i_accu
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3711100.00
ALWAYS4033100.00

28 29 1/1 assign trig_gated = class_trig_i & class_en_i; 30 31 1/1 assign accu_d = (clr_i) ? '0 : // clear 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum 33 accu_q; 34 35 1/1 assign accu_trig_o = (accu_q >= thresh_i) & trig_gated; 36 37 1/1 assign accu_cnt_o = accu_q; 38 39 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 40 1/1 if (!rst_ni) begin 41 1/1 accu_q <= '0; 42 end else begin 43 1/1 accu_q <= accu_d;

Cond Coverage for Instance : tb.dut.gen_classes[0].i_accu
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (clr_i ? '0 : ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q))
             --1--
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q)
                 ---------------1--------------
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION (trig_gated && ((!(&accu_q))))
                 -----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

Branch Coverage for Instance : tb.dut.gen_classes[0].i_accu
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 31 3 3 100.00
IF 40 2 2 100.00


31 assign accu_d = (clr_i) ? '0 : // clear -1- ==> 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum -2- ==> ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


40 if (!rst_ni) begin -1- 41 accu_q <= '0; ==> 42 end else begin 43 accu_q <= accu_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_classes[0].i_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisabledNoTrigBkwd_A 2147483647 2893405 0 0
DisabledNoTrigFwd_A 2147483647 2147483647 0 0

Line Coverage for Instance : tb.dut.gen_classes[1].i_accu
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3711100.00
ALWAYS4033100.00

28 29 1/1 assign trig_gated = class_trig_i & class_en_i; 30 31 1/1 assign accu_d = (clr_i) ? '0 : // clear 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum 33 accu_q; 34 35 1/1 assign accu_trig_o = (accu_q >= thresh_i) & trig_gated; 36 37 1/1 assign accu_cnt_o = accu_q; 38 39 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 40 1/1 if (!rst_ni) begin 41 1/1 accu_q <= '0; 42 end else begin 43 1/1 accu_q <= accu_d;

Cond Coverage for Instance : tb.dut.gen_classes[1].i_accu
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (clr_i ? '0 : ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q))
             --1--
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q)
                 ---------------1--------------
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION (trig_gated && ((!(&accu_q))))
                 -----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

Branch Coverage for Instance : tb.dut.gen_classes[1].i_accu
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 31 3 3 100.00
IF 40 2 2 100.00


31 assign accu_d = (clr_i) ? '0 : // clear -1- ==> 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum -2- ==> ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


40 if (!rst_ni) begin -1- 41 accu_q <= '0; ==> 42 end else begin 43 accu_q <= accu_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_classes[1].i_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisabledNoTrigBkwd_A 2147483647 9038763 0 0
DisabledNoTrigFwd_A 2147483647 2147483647 0 0

Line Coverage for Instance : tb.dut.gen_classes[2].i_accu
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3711100.00
ALWAYS4033100.00

28 29 1/1 assign trig_gated = class_trig_i & class_en_i; 30 31 1/1 assign accu_d = (clr_i) ? '0 : // clear 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum 33 accu_q; 34 35 1/1 assign accu_trig_o = (accu_q >= thresh_i) & trig_gated; 36 37 1/1 assign accu_cnt_o = accu_q; 38 39 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 40 1/1 if (!rst_ni) begin 41 1/1 accu_q <= '0; 42 end else begin 43 1/1 accu_q <= accu_d;

Cond Coverage for Instance : tb.dut.gen_classes[2].i_accu
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (clr_i ? '0 : ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q))
             --1--
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q)
                 ---------------1--------------
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION (trig_gated && ((!(&accu_q))))
                 -----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

Branch Coverage for Instance : tb.dut.gen_classes[2].i_accu
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 31 3 3 100.00
IF 40 2 2 100.00


31 assign accu_d = (clr_i) ? '0 : // clear -1- ==> 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum -2- ==> ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


40 if (!rst_ni) begin -1- 41 accu_q <= '0; ==> 42 end else begin 43 accu_q <= accu_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_classes[2].i_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisabledNoTrigBkwd_A 2147483647 945515 0 0
DisabledNoTrigFwd_A 2147483647 2147483647 0 0

Line Coverage for Instance : tb.dut.gen_classes[3].i_accu
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3711100.00
ALWAYS4033100.00

28 29 1/1 assign trig_gated = class_trig_i & class_en_i; 30 31 1/1 assign accu_d = (clr_i) ? '0 : // clear 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum 33 accu_q; 34 35 1/1 assign accu_trig_o = (accu_q >= thresh_i) & trig_gated; 36 37 1/1 assign accu_cnt_o = accu_q; 38 39 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 40 1/1 if (!rst_ni) begin 41 1/1 accu_q <= '0; 42 end else begin 43 1/1 accu_q <= accu_d;

Cond Coverage for Instance : tb.dut.gen_classes[3].i_accu
TotalCoveredPercent
Conditions77100.00
Logical77100.00
Non-Logical00
Event00

 LINE       31
 EXPRESSION (clr_i ? '0 : ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q))
             --1--
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION ((trig_gated && ((!(&accu_q)))) ? ((accu_q + 1'b1)) : accu_q)
                 ---------------1--------------
-1-Status
0Covered
1Covered

 LINE       31
 SUB-EXPRESSION (trig_gated && ((!(&accu_q))))
                 -----1----    -------2------
-1--2-Status
01Covered
10Covered
11Covered

Branch Coverage for Instance : tb.dut.gen_classes[3].i_accu
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 31 3 3 100.00
IF 40 2 2 100.00


31 assign accu_d = (clr_i) ? '0 : // clear -1- ==> 32 (trig_gated && !(&accu_q)) ? accu_q + 1'b1 : // saturate counter at maximum -2- ==> ==>

Branches:
-1--2-Status
1 - Covered
0 1 Covered
0 0 Covered


40 if (!rst_ni) begin -1- 41 accu_q <= '0; ==> 42 end else begin 43 accu_q <= accu_d; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_classes[3].i_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisabledNoTrigBkwd_A 2147483647 1514957 0 0
DisabledNoTrigFwd_A 2147483647 2147483647 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%