Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_alerts[0].i_alert_receiver.i_decode_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 100.00 66.67 92.86 100.00 gen_alerts[0].i_alert_receiver


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].i_alert_receiver.i_decode_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 100.00 66.67 92.86 100.00 gen_alerts[1].i_alert_receiver


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].i_alert_receiver.i_decode_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 100.00 66.67 92.86 100.00 gen_alerts[2].i_alert_receiver


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].i_alert_receiver.i_decode_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.90 100.00 100.00 66.67 92.86 100.00 gen_alerts[3].i_alert_receiver


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[0].i_esc_sender.i_decode_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.01 100.00 92.31 76.47 100.00 81.25 gen_esc_sev[0].i_esc_sender


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[1].i_esc_sender.i_decode_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.01 100.00 92.31 76.47 100.00 81.25 gen_esc_sev[1].i_esc_sender


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[2].i_esc_sender.i_decode_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.01 100.00 92.31 76.47 100.00 81.25 gen_esc_sev[2].i_esc_sender


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_esc_sev[3].i_esc_sender.i_decode_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.54 100.00 100.00 76.47 100.00 81.25 gen_esc_sev[3].i_esc_sender


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_diff_decode
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Module : prim_diff_decode
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Module : prim_diff_decode
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Module : prim_diff_decode
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 91431794 0 0
SigintFallCheck_A 2147483647 91431794 0 0
SigintLevelCheck_A 2147483647 91431792 0 7352
SigintRiseCheck_A 2147483647 91431794 0 0
gen_sync_assert.EventCheck_A 2147483647 141338181 0 7352
gen_sync_assert.FallCheck_A 2147483647 74243244 0 7352
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 67094937 0 7352
gen_sync_assert.SigintCheck_A 2147483647 91431794 0 0

Line Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver.i_decode_alert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[0].i_alert_receiver.i_decode_alert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 8045902 0 0
SigintFallCheck_A 2147483647 8045902 0 0
SigintLevelCheck_A 2147483647 8045901 0 919
SigintRiseCheck_A 2147483647 8045902 0 0
gen_sync_assert.EventCheck_A 2147483647 5771616 0 919
gen_sync_assert.FallCheck_A 2147483647 3461426 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 2310190 0 919
gen_sync_assert.SigintCheck_A 2147483647 8045902 0 0

Line Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver.i_decode_alert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[1].i_alert_receiver.i_decode_alert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 8050629 0 0
SigintFallCheck_A 2147483647 8050629 0 0
SigintLevelCheck_A 2147483647 8050629 0 919
SigintRiseCheck_A 2147483647 8050629 0 0
gen_sync_assert.EventCheck_A 2147483647 5765907 0 919
gen_sync_assert.FallCheck_A 2147483647 3458333 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 2307574 0 919
gen_sync_assert.SigintCheck_A 2147483647 8050629 0 0

Line Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver.i_decode_alert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[2].i_alert_receiver.i_decode_alert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 8055266 0 0
SigintFallCheck_A 2147483647 8055266 0 0
SigintLevelCheck_A 2147483647 8055266 0 919
SigintRiseCheck_A 2147483647 8055266 0 0
gen_sync_assert.EventCheck_A 2147483647 5766936 0 919
gen_sync_assert.FallCheck_A 2147483647 3458943 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 2307993 0 919
gen_sync_assert.SigintCheck_A 2147483647 8055266 0 0

Line Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver.i_decode_alert
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver.i_decode_alert
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_alerts[3].i_alert_receiver.i_decode_alert
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 8049010 0 0
SigintFallCheck_A 2147483647 8049010 0 0
SigintLevelCheck_A 2147483647 8049010 0 919
SigintRiseCheck_A 2147483647 8049010 0 0
gen_sync_assert.EventCheck_A 2147483647 5766838 0 919
gen_sync_assert.FallCheck_A 2147483647 3457679 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 2309159 0 919
gen_sync_assert.SigintCheck_A 2147483647 8049010 0 0

Line Coverage for Instance : tb.dut.gen_esc_sev[0].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_esc_sev[0].i_esc_sender.i_decode_resp
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_esc_sev[0].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_esc_sev[0].i_esc_sender.i_decode_resp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 17878575 0 0
SigintFallCheck_A 2147483647 17878575 0 0
SigintLevelCheck_A 2147483647 17878575 0 919
SigintRiseCheck_A 2147483647 17878575 0 0
gen_sync_assert.EventCheck_A 2147483647 37368258 0 919
gen_sync_assert.FallCheck_A 2147483647 19000975 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 18367283 0 919
gen_sync_assert.SigintCheck_A 2147483647 17878575 0 0

Line Coverage for Instance : tb.dut.gen_esc_sev[1].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_esc_sev[1].i_esc_sender.i_decode_resp
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_esc_sev[1].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_esc_sev[1].i_esc_sender.i_decode_resp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 14987541 0 0
SigintFallCheck_A 2147483647 14987541 0 0
SigintLevelCheck_A 2147483647 14987541 0 919
SigintRiseCheck_A 2147483647 14987541 0 0
gen_sync_assert.EventCheck_A 2147483647 29889911 0 919
gen_sync_assert.FallCheck_A 2147483647 15265240 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 14624671 0 919
gen_sync_assert.SigintCheck_A 2147483647 14987541 0 0

Line Coverage for Instance : tb.dut.gen_esc_sev[2].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_esc_sev[2].i_esc_sender.i_decode_resp
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_esc_sev[2].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_esc_sev[2].i_esc_sender.i_decode_resp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 10277588 0 0
SigintFallCheck_A 2147483647 10277588 0 0
SigintLevelCheck_A 2147483647 10277588 0 919
SigintRiseCheck_A 2147483647 10277588 0 0
gen_sync_assert.EventCheck_A 2147483647 18457106 0 919
gen_sync_assert.FallCheck_A 2147483647 9544597 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 8912509 0 919
gen_sync_assert.SigintCheck_A 2147483647 10277588 0 0

Line Coverage for Instance : tb.dut.gen_esc_sev[3].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19411100.00
ALWAYS19755100.00

182 // one reg for edge detection 183 1/1 assign diff_pd = diff_pi; 184 185 // incorrect encoding -> signal integrity issue 186 1/1 assign sigint_o = ~(diff_pi ^ diff_ni); 187 188 1/1 assign level_o = (sigint_o) ? level_q : diff_pi; 189 1/1 assign level_d = level_o; 190 191 // detect level transitions 192 1/1 assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; 193 1/1 assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; 194 1/1 assign event_o = rise_o | fall_o; 195 196 always_ff @(posedge clk_i or negedge rst_ni) begin : p_edge_reg 197 1/1 if (!rst_ni) begin 198 1/1 diff_pq <= 1'b0; 199 1/1 level_q <= 1'b0; 200 end else begin 201 1/1 diff_pq <= diff_pd; 202 1/1 level_q <= level_d;

Cond Coverage for Instance : tb.dut.gen_esc_sev[3].i_esc_sender.i_decode_resp
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       188
 EXPRESSION (sigint_o ? level_q : diff_pi)
             ----1---
-1-Status
0Covered
1Covered

Branch Coverage for Instance : tb.dut.gen_esc_sev[3].i_esc_sender.i_decode_resp
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 188 2 2 100.00
IF 197 2 2 100.00


188 assign level_o = (sigint_o) ? level_q : diff_pi; -1- ==> ==>

Branches:
-1-Status
1 Covered
0 Covered


197 if (!rst_ni) begin -1- 198 diff_pq <= 1'b0; ==> 199 level_q <= 1'b0; 200 end else begin 201 diff_pq <= diff_pd; ==>

Branches:
-1-Status
1 Covered
0 Covered


Assert Coverage for Instance : tb.dut.gen_esc_sev[3].i_esc_sender.i_decode_resp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 9 9 100.00 9 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 9 9 100.00 9 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SigintEventCheck_A 2147483647 16087283 0 0
SigintFallCheck_A 2147483647 16087283 0 0
SigintLevelCheck_A 2147483647 16087282 0 919
SigintRiseCheck_A 2147483647 16087283 0 0
gen_sync_assert.EventCheck_A 2147483647 32551609 0 919
gen_sync_assert.FallCheck_A 2147483647 16596051 0 919
gen_sync_assert.LevelCheck_A 2147483647 2147483647 0 0
gen_sync_assert.RiseCheck_A 2147483647 15955558 0 919
gen_sync_assert.SigintCheck_A 2147483647 16087283 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%