Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.76 99.90 96.45 69.06 82.93 97.84 98.37


Total modules in report: 19
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
uvm_pkg 33.33 33.33
prim_lfsr 77.54 95.65 55.00 66.67 92.86
alert_handler 89.69 100.00 69.06 100.00
prim_esc_sender 91.54 100.00 100.00 76.47 100.00 81.25
prim_alert_receiver 91.90 100.00 100.00 66.67 92.86 100.00
alert_handler_ping_timer 94.57 100.00 100.00 80.00 92.86 100.00
alert_handler_esc_timer 95.42 100.00 80.95 100.00 96.15 100.00
alert_handler_reg_wrap 100.00 100.00
alert_handler_accu 100.00 100.00 100.00 100.00 100.00
prim_diff_decode 100.00 100.00 100.00 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_subreg 100.00 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SWACCESS,RESVAL ) 100.00 100.00
prim_subreg ( parameter DW=1,SWACCESS,RESVAL + DW=24,SWACCESS="RW",RESVAL=32 + DW=2,SWACCESS="RW",RESVAL + DW=16,SWACCESS="RW",RESVAL=0 + DW=32,SWACCESS="RW",RESVAL=0 ) 100.00 100.00 100.00
prim_subreg ( parameter DW=1,SWACCESS="W1C",RESVAL ) 100.00 100.00 100.00
prim_subreg ( parameter DW=16,SWACCESS="RW",RESVAL=0 ) 100.00 100.00
prim_subreg ( parameter DW=2,SWACCESS="RW",RESVAL ) 100.00 100.00
prim_subreg ( parameter DW=24,SWACCESS="RW",RESVAL=32 ) 100.00 100.00
prim_subreg ( parameter DW=32,SWACCESS="RW",RESVAL=0 ) 100.00 100.00
prim_intr_hw 100.00 100.00
alert_handler_reg_top 100.00 100.00 100.00 100.00 100.00
tlul_adapter_reg 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
alert_handler_class 100.00 100.00
tb
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