AON_TIMER Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.510s	577.545us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.670s	821.121us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	486.848us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.130s	6.045ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.230s	483.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	532.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	486.848us	20	20	100.00
		aon_timer_csr_aliasing	1.230s	483.152us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.200s	454.085us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.110s	428.296us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.681m	58.283ms	50	50	100.00
V2	jump	aon_timer_jump	1.690s	595.767us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.383m	526.516ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.350s	511.072us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.890s	431.573us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.890s	431.573us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.670s	821.121us	5	5	100.00
		aon_timer_csr_rw	1.300s	486.848us	20	20	100.00
		aon_timer_csr_aliasing	1.230s	483.152us	5	5	100.00
		aon_timer_same_csr_outstanding	5.920s	2.559ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.670s	821.121us	5	5	100.00
		aon_timer_csr_rw	1.300s	486.848us	20	20	100.00
		aon_timer_csr_aliasing	1.230s	483.152us	5	5	100.00
		aon_timer_same_csr_outstanding	5.920s	2.559ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	tl_intg_err	aon_timer_sec_cm	12.630s	7.620ms	5	5	100.00
		aon_timer_tl_intg_err	14.850s	8.536ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.850s	8.536ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.250m	265.070ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			428	430	99.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*])

has 2 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

26.aon_timer_stress_all_with_rand_reset.566447655
Line 700, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25132099583 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 25132099583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.aon_timer_stress_all_with_rand_reset.2933792535
Line 441, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/31.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31133455396 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 31133455396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---