AON_TIMER Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.400s	515.509us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.650s	774.157us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.310s	493.956us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.920s	5.883ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.190s	619.784us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.420s	456.354us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.310s	493.956us	20	20	100.00
		aon_timer_csr_aliasing	1.190s	619.784us	4	5	80.00
V1	mem_walk	aon_timer_mem_walk	1.240s	493.177us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.130s	391.217us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	prescaler	aon_timer_prescaler	58.660s	40.660ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	622.363us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.628m	390.060ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.330s	518.111us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.720s	424.040us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.720s	424.040us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.650s	774.157us	5	5	100.00
		aon_timer_csr_rw	1.310s	493.956us	20	20	100.00
		aon_timer_csr_aliasing	1.190s	619.784us	4	5	80.00
		aon_timer_same_csr_outstanding	3.980s	2.293ms	19	20	95.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.650s	774.157us	5	5	100.00
		aon_timer_csr_rw	1.310s	493.956us	20	20	100.00
		aon_timer_csr_aliasing	1.190s	619.784us	4	5	80.00
		aon_timer_same_csr_outstanding	3.980s	2.293ms	19	20	95.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	11.510s	7.584ms	5	5	100.00
		aon_timer_tl_intg_err	14.490s	9.503ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.490s	9.503ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.125m	866.991ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.50	99.82	94.68	100.00	--	99.35	100.00	97.16

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 2 failures:

Test aon_timer_csr_aliasing has 1 failures.

2.aon_timer_csr_aliasing.1012662721
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 551863198 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 551863198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_same_csr_outstanding has 1 failures.

9.aon_timer_same_csr_outstanding.1900470179
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 833508482 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 833508482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 2 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

13.aon_timer_stress_all_with_rand_reset.3046582587
Line 553, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20159172241 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 20159172241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.aon_timer_stress_all_with_rand_reset.1470565935
Line 350, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6561387652 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 6561387652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---