AON_TIMER Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.500s	608.656us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.850s	1.353ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	553.759us	19	20	95.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	15.460s	11.892ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.310s	469.672us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.420s	533.250us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	553.759us	19	20	95.00
		aon_timer_csr_aliasing	1.310s	469.672us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.070s	399.816us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.130s	392.261us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	prescaler	aon_timer_prescaler	1.395m	50.755ms	50	50	100.00
V2	jump	aon_timer_jump	1.350s	493.126us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.370m	402.459ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.390s	513.260us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.700s	572.196us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.700s	572.196us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.850s	1.353ms	5	5	100.00
		aon_timer_csr_rw	1.350s	553.759us	19	20	95.00
		aon_timer_csr_aliasing	1.310s	469.672us	5	5	100.00
		aon_timer_same_csr_outstanding	6.670s	2.649ms	18	20	90.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.850s	1.353ms	5	5	100.00
		aon_timer_csr_rw	1.350s	553.759us	19	20	95.00
		aon_timer_csr_aliasing	1.310s	469.672us	5	5	100.00
		aon_timer_same_csr_outstanding	6.670s	2.649ms	18	20	90.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	14.010s	7.944ms	5	5	100.00
		aon_timer_tl_intg_err	13.010s	7.981ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.010s	7.981ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.601m	132.556ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 3 failures:

Test aon_timer_csr_rw has 1 failures.

5.aon_timer_csr_rw.3154328855
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_csr_rw/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 347360817 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 347360817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_same_csr_outstanding has 2 failures.

6.aon_timer_same_csr_outstanding.4288586187
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 919181084 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 919181084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_same_csr_outstanding.2545318134
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 1158720794 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 1158720794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 3.aon_timer_stress_all.938002810
    Line 236, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 19063565775 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 19063565775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```