AON_TIMER Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	523.266us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.430s	1.197ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.320s	477.473us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	31.460s	10.383ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.630s	540.148us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.540s	572.035us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.320s	477.473us	20	20	100.00
		aon_timer_csr_aliasing	1.630s	540.148us	4	5	80.00
V1	mem_walk	aon_timer_mem_walk	1.070s	356.758us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.760s	426.067us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	prescaler	aon_timer_prescaler	1.578m	56.625ms	50	50	100.00
V2	jump	aon_timer_jump	1.500s	563.800us	50	50	100.00
V2	stress_all	aon_timer_stress_all	27.992m	996.594ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.320s	483.938us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.960s	506.146us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.960s	506.146us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.430s	1.197ms	5	5	100.00
		aon_timer_csr_rw	1.320s	477.473us	20	20	100.00
		aon_timer_csr_aliasing	1.630s	540.148us	4	5	80.00
		aon_timer_same_csr_outstanding	6.250s	2.314ms	19	20	95.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.430s	1.197ms	5	5	100.00
		aon_timer_csr_rw	1.320s	477.473us	20	20	100.00
		aon_timer_csr_aliasing	1.630s	540.148us	4	5	80.00
		aon_timer_same_csr_outstanding	6.250s	2.314ms	19	20	95.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	8.060s	4.424ms	5	5	100.00
		aon_timer_tl_intg_err	13.550s	8.819ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.550s	8.819ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.876m	233.023ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

UVM_ERROR (aon_timer_scoreboard.sv:310) [scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (* [*] vs * [*]) has 3 failures:

Test aon_timer_stress_all has 1 failures.

6.aon_timer_stress_all.2196542452
Line 224, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1760422352 ps: (aon_timer_scoreboard.sv:310) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 1760422352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 2 failures.

29.aon_timer_stress_all_with_rand_reset.1255703900
Line 483, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/29.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11434251686 ps: (aon_timer_scoreboard.sv:310) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 11434251686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.aon_timer_stress_all_with_rand_reset.4245433545
Line 527, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 18275554044 ps: (aon_timer_scoreboard.sv:310) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WDOG] === cfg.intr_vif.sample_pin(.idx(WDOG)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 18275554044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 2 failures:

Test aon_timer_csr_aliasing has 1 failures.

2.aon_timer_csr_aliasing.3970719273
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_csr_aliasing/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 558269652 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 558269652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_same_csr_outstanding has 1 failures.

19.aon_timer_same_csr_outstanding.2147898493
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 911964251 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 911964251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 33.aon_timer_stress_all_with_rand_reset.543329419
    Line 437, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9837376778 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 9837376778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```