AON_TIMER Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.400s	519.136us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.170s	1.091ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.510s	554.080us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.980s	5.917ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.500s	550.061us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.420s	503.597us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.510s	554.080us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	550.061us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.310s	458.538us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	505.622us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.341m	49.680ms	50	50	100.00
V2	jump	aon_timer_jump	1.430s	550.074us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.798m	421.612ms	50	50	100.00
V2	intr_test	aon_timer_intr_test	1.300s	498.810us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.880s	549.684us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.880s	549.684us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.170s	1.091ms	5	5	100.00
		aon_timer_csr_rw	1.510s	554.080us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	550.061us	5	5	100.00
		aon_timer_same_csr_outstanding	4.550s	1.895ms	17	20	85.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.170s	1.091ms	5	5	100.00
		aon_timer_csr_rw	1.510s	554.080us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	550.061us	5	5	100.00
		aon_timer_same_csr_outstanding	4.550s	1.895ms	17	20	85.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	11.260s	7.463ms	5	5	100.00
		aon_timer_tl_intg_err	14.000s	8.627ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.000s	8.627ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.640m	113.730ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.46	99.82	94.68	100.00	--	99.35	100.00	96.90

Failure Buckets

Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))' has 3 failures:

Test aon_timer_same_csr_outstanding has 3 failures.

4.aon_timer_same_csr_outstanding.3216516740
Line 218, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 2008784616 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 2008784616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_same_csr_outstanding.1964273857
Line 217, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_same_csr_outstanding/latest/run.log

      Offending '(wkup_req_o || ($fell(reg2hw.wkup_cause.q) && (!aon_sleep_mode)))'
  UVM_ERROR @ 702296025 ps: (aon_timer.sv:171) [ASSERT FAILED] WkupStable_A
  UVM_INFO @ 702296025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:269) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*])

has 2 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

17.aon_timer_stress_all_with_rand_reset.3872740355
Line 1246, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 59472600949 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 59472600949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.aon_timer_stress_all_with_rand_reset.3670565394
Line 221, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 657761060 ps: (aon_timer_scoreboard.sv:269) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 657761060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---