AON_TIMER Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.530s 557.908us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 2.450s 1.207ms 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.320s 521.270us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 16.600s 6.005ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.550s 515.386us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.550s 524.388us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.320s 521.270us 20 20 100.00
aon_timer_csr_aliasing 1.550s 515.386us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.190s 458.879us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.120s 506.860us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.338m 56.265ms 50 50 100.00
V2 jump aon_timer_jump 1.440s 599.130us 50 50 100.00
V2 stress_all aon_timer_stress_all 8.205m 356.119ms 50 50 100.00
V2 intr_test aon_timer_intr_test 1.340s 464.730us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 3.190s 660.443us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 3.190s 660.443us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 2.450s 1.207ms 5 5 100.00
aon_timer_csr_rw 1.320s 521.270us 20 20 100.00
aon_timer_csr_aliasing 1.550s 515.386us 5 5 100.00
aon_timer_same_csr_outstanding 5.100s 2.232ms 19 20 95.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 2.450s 1.207ms 5 5 100.00
aon_timer_csr_rw 1.320s 521.270us 20 20 100.00
aon_timer_csr_aliasing 1.550s 515.386us 5 5 100.00
aon_timer_same_csr_outstanding 5.100s 2.232ms 19 20 95.00
V2 TOTAL 239 240 99.58
V2S tl_intg_err aon_timer_sec_cm 7.410s 8.170ms 5 5 100.00
aon_timer_tl_intg_err 14.430s 8.483ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 14.430s 8.483ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 14.358m 895.673ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 429 430 99.77

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.46 99.82 94.68 100.00 -- 99.35 100.00 96.90

Failure Buckets

Past Results