Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
35.46	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	141	91	50	35.46

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	23	11	32.35	100	1	1	0
bite_thold_cp	34	24	10	29.41	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	23	11	32.35	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	34	20	14	41.18	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	23	11	32.35

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[23]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	20650	1		T20	237		T21	237		T22	10
bark[1]	4100	1		T20	82		T21	82		T27	82
bark[9]	300	1		T20	6		T21	6		T27	6
bark[10]	850	1		T28	17		T29	17		T35	17
bark[11]	600	1		T19	12		T24	12		T26	12
bark[22]	850	1		T20	17		T21	17		T27	17
bark[24]	600	1		T28	12		T29	12		T35	12
bark[25]	800	1		T28	16		T29	16		T35	16
bark[26]	850	1		T28	17		T29	17		T35	17
bark[30]	800	1		T28	16		T29	16		T35	16
bark_0	2200	1		T8	6		T34	6		T16	6

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	24	10	29.41

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[2]	0	1	1
bite[4]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	20400	1		T20	234		T21	234		T22	9
bite[1]	4100	1		T20	82		T21	82		T27	82
bite[3]	250	1		T20	5		T21	5		T27	5
bite[5]	850	1		T20	17		T21	17		T27	17
bite[8]	550	1		T28	11		T29	11		T35	11
bite[14]	1650	1		T28	33		T29	33		T35	33
bite[17]	800	1		T28	16		T29	16		T35	16
bite[27]	550	1		T19	11		T24	11		T26	11
bite[31]	850	1		T28	17		T29	17		T35	17
bite_0	2600	1		T8	6		T34	6		T16	6

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32600	1		T8	6		T34	6		T16	6

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	23	11	32.35

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1
prescale[0]	0	1	1
prescale[1]	0	1	1
prescale[3]	0	1	1
prescale[4]	0	1	1
prescale[5]	0	1	1
prescale[7]	0	1	1
prescale[8]	0	1	1
prescale[9]	0	1	1
prescale[10]	0	1	1
prescale[12]	0	1	1
prescale[16]	0	1	1
prescale[17]	0	1	1
prescale[20]	0	1	1
prescale[21]	0	1	1
prescale[22]	0	1	1
prescale[23]	0	1	1
prescale[24]	0	1	1
prescale[25]	0	1	1
prescale[26]	0	1	1
prescale[28]	0	1	1
prescale[29]	0	1	1
prescale[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[2]	750	1		T20	15		T21	15		T27	15
prescale[6]	1750	1		T20	35		T21	35		T27	35
prescale[11]	900	1		T20	18		T21	18		T27	18
prescale[13]	3150	1		T20	63		T21	63		T27	63
prescale[14]	2050	1		T20	20		T21	20		T27	20
prescale[15]	2450	1		T28	49		T29	49		T35	49
prescale[18]	750	1		T28	15		T29	15		T35	15
prescale[19]	100	1		T20	2		T21	2		T27	2
prescale[27]	400	1		T25	8		T50	8		T51	8
prescale[30]	1700	1		T28	34		T29	34		T35	34
prescale_0	18600	1		T8	6		T34	6		T16	6

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24350	1		T8	6		T34	6		T16	6
auto[1]	8250	1		T20	59		T21	59		T27	59

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	32600	1		T8	6		T34	6		T16	6

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	20	14	41.18

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[10]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[17]	0	1	1
wkup[20]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	18350	1		T20	205		T21	205		T22	11
wkup[2]	1100	1		T20	22		T21	22		T27	22
wkup[3]	2100	1		T20	42		T21	42		T27	42
wkup[6]	800	1		T20	16		T21	16		T27	16
wkup[9]	350	1		T20	7		T21	7		T27	7
wkup[11]	850	1		T28	17		T29	17		T35	17
wkup[16]	850	1		T20	17		T21	17		T27	17
wkup[18]	1000	1		T20	7		T21	7		T27	7
wkup[19]	800	1		T28	16		T29	16		T35	16
wkup[21]	850	1		T28	17		T29	17		T35	17
wkup[24]	1350	1		T20	27		T21	27		T27	27
wkup[25]	650	1		T19	13		T24	13		T26	13
wkup[28]	1600	1		T28	32		T29	32		T35	32
wkup_0	1950	1		T8	6		T34	6		T16	6