Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.43 99.82 95.32 100.00 99.35 98.45 73.64


Total test records in report: 430
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T266 /workspace/coverage/default/31.aon_timer_prescaler.13058070474129239908439650170988418946129026775770357551198510004946911698627 Nov 22 01:17:27 PM PST 23 Nov 22 01:18:19 PM PST 23 53247692830 ps
T267 /workspace/coverage/default/19.aon_timer_jump.7770475196018201192191808840935243783264019266516905582563267886523239709630 Nov 22 01:17:13 PM PST 23 Nov 22 01:17:20 PM PST 23 474704303 ps
T268 /workspace/coverage/default/25.aon_timer_stress_all.68999583578487148433371314340754815422302548736601937056649519807979373285596 Nov 22 01:17:30 PM PST 23 Nov 22 01:22:35 PM PST 23 332628779192 ps
T269 /workspace/coverage/default/9.aon_timer_jump.92258487129047278879630029154359982173342289162124685083915717633502794745622 Nov 22 01:16:53 PM PST 23 Nov 22 01:17:09 PM PST 23 474704303 ps
T270 /workspace/coverage/default/17.aon_timer_smoke.95153414251285841897071263203347095899231361725879508678878103258745243257408 Nov 22 01:17:13 PM PST 23 Nov 22 01:17:21 PM PST 23 491168457 ps
T271 /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.65559223824756094810557034170374657897549886775749867096037725949552302315546 Nov 22 01:17:28 PM PST 23 Nov 22 01:24:29 PM PST 23 96759987586 ps
T272 /workspace/coverage/default/12.aon_timer_stress_all.84434433383571091268003825750657654735369496877648461358484982647658955199181 Nov 22 01:16:51 PM PST 23 Nov 22 01:22:04 PM PST 23 332628779192 ps
T273 /workspace/coverage/default/23.aon_timer_stress_all.89335898811188440918656118400979734022876199221160070086737752466391044744124 Nov 22 01:17:15 PM PST 23 Nov 22 01:22:23 PM PST 23 332628779192 ps
T274 /workspace/coverage/default/47.aon_timer_prescaler.1022610253470561821857571145932572078622059722482086385137956768343049607164 Nov 22 01:18:55 PM PST 23 Nov 22 01:19:47 PM PST 23 53247692830 ps
T275 /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.21564873790499596846312635770481608194528849420156120249453642458552749793996 Nov 22 01:17:25 PM PST 23 Nov 22 01:24:37 PM PST 23 96759987586 ps
T276 /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.7517279845581310492992445827614039227330000572246512942875424892843024267547 Nov 22 01:16:58 PM PST 23 Nov 22 01:24:16 PM PST 23 96759987586 ps
T277 /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.23590752602295693889812715336602659189438652817156152661053723961465086281739 Nov 22 01:16:53 PM PST 23 Nov 22 01:24:17 PM PST 23 96759987586 ps
T278 /workspace/coverage/default/8.aon_timer_smoke.68093771347246435280635929157554172978851932388219703471218392542761596651375 Nov 22 01:17:32 PM PST 23 Nov 22 01:17:35 PM PST 23 491168457 ps
T41 /workspace/coverage/default/4.aon_timer_sec_cm.7890403646989185168893556682386266700232481589849582652139179647680690158964 Nov 22 01:16:47 PM PST 23 Nov 22 01:16:56 PM PST 23 4270477508 ps
T279 /workspace/coverage/default/40.aon_timer_jump.29873219444838514130431758985193076502492254154060214351465927572389289559736 Nov 22 01:17:34 PM PST 23 Nov 22 01:17:37 PM PST 23 474704303 ps
T280 /workspace/coverage/default/8.aon_timer_stress_all.94734134100895204189717337172894298799740158939973422465731393701393885876432 Nov 22 01:17:23 PM PST 23 Nov 22 01:22:29 PM PST 23 332628779192 ps
T281 /workspace/coverage/default/20.aon_timer_prescaler.15078401755451426744715799559652318980854358806556917043415483643616656670391 Nov 22 01:17:25 PM PST 23 Nov 22 01:18:17 PM PST 23 53247692830 ps
T282 /workspace/coverage/default/23.aon_timer_smoke.71936556776465218007425497903767809256100865919105932630101605879394744483960 Nov 22 01:17:22 PM PST 23 Nov 22 01:17:28 PM PST 23 491168457 ps
T283 /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.47332512763341726232898396897999699316981384009312114649469169316002922743599 Nov 22 01:17:54 PM PST 23 Nov 22 01:25:09 PM PST 23 96759987586 ps
T284 /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.74393635893933642095572393840533706262946995815470576650178858666975438894203 Nov 22 01:17:38 PM PST 23 Nov 22 01:24:46 PM PST 23 96759987586 ps
T285 /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.108452259973189212925608546782432180740436204510181592923197179527462257270123 Nov 22 01:17:40 PM PST 23 Nov 22 01:24:30 PM PST 23 96759987586 ps
T286 /workspace/coverage/default/14.aon_timer_prescaler.56552888611508558107005554355246189736526670702411529637213328158875274274600 Nov 22 01:16:53 PM PST 23 Nov 22 01:17:56 PM PST 23 53247692830 ps
T287 /workspace/coverage/default/4.aon_timer_stress_all.45654744808717834693554111791150962123299126437969903118400695597860137026679 Nov 22 01:16:49 PM PST 23 Nov 22 01:21:56 PM PST 23 332628779192 ps
T288 /workspace/coverage/default/27.aon_timer_jump.105029790104986778234400337229588387592820124007391643683448598560064381623988 Nov 22 01:17:27 PM PST 23 Nov 22 01:17:31 PM PST 23 474704303 ps
T289 /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.103790884294613523008220317654848759486231870492713438929999230219493496364133 Nov 22 01:17:01 PM PST 23 Nov 22 01:24:15 PM PST 23 96759987586 ps
T290 /workspace/coverage/default/10.aon_timer_stress_all.57643359520597880165607104692575282926935005602204234964567019614153251072978 Nov 22 01:17:11 PM PST 23 Nov 22 01:22:18 PM PST 23 332628779192 ps
T291 /workspace/coverage/default/32.aon_timer_smoke.28933214235733067136711048384983175925076060482335260068073831054401236611272 Nov 22 01:17:38 PM PST 23 Nov 22 01:17:40 PM PST 23 491168457 ps
T292 /workspace/coverage/default/4.aon_timer_jump.11120286399127619027522341109908196984887510489047233803454272358954915746827 Nov 22 01:18:50 PM PST 23 Nov 22 01:18:53 PM PST 23 474704303 ps
T293 /workspace/coverage/default/24.aon_timer_smoke.95254400270995615609672982301364390342791641639045273095690397727393149112738 Nov 22 01:17:23 PM PST 23 Nov 22 01:17:28 PM PST 23 491168457 ps
T294 /workspace/coverage/default/25.aon_timer_prescaler.103806407430891496756968621177497269381905511188640674818160995672790220462185 Nov 22 01:17:22 PM PST 23 Nov 22 01:18:15 PM PST 23 53247692830 ps
T295 /workspace/coverage/default/0.aon_timer_jump.17105640281159017758315746211903978924695758148830282615814371954767926074124 Nov 22 01:16:52 PM PST 23 Nov 22 01:17:07 PM PST 23 474704303 ps
T296 /workspace/coverage/default/37.aon_timer_stress_all.9094563128729237362403447458608718221019289704865833577697968219247470890627 Nov 22 01:17:41 PM PST 23 Nov 22 01:22:45 PM PST 23 332628779192 ps
T297 /workspace/coverage/default/33.aon_timer_jump.10936463550399516638360721448148772638785818803185752443579094178349670845293 Nov 22 01:17:27 PM PST 23 Nov 22 01:17:31 PM PST 23 474704303 ps
T298 /workspace/coverage/default/22.aon_timer_prescaler.30642404470560384130246631174865146242632450519632019325365190456012392951213 Nov 22 01:17:17 PM PST 23 Nov 22 01:18:10 PM PST 23 53247692830 ps
T299 /workspace/coverage/default/46.aon_timer_prescaler.30202090440315097650506354258742763417923111077801974705950836595714253859013 Nov 22 01:18:01 PM PST 23 Nov 22 01:18:58 PM PST 23 53247692830 ps
T72 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.27422830389043093532568695509928502064037362690871518586727212478484146332908 Nov 22 01:48:53 PM PST 23 Nov 22 01:49:00 PM PST 23 4648795910 ps
T300 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.97297014806326322437463825871948277673435232593940286998950339562972452091715 Nov 22 01:48:52 PM PST 23 Nov 22 01:48:55 PM PST 23 418151184 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.89791175592154538015519619059775548130763006782342935158702555451712143369556 Nov 22 01:49:09 PM PST 23 Nov 22 01:49:11 PM PST 23 418151184 ps
T302 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.81921307739432370423429954980305758244984498961802386803267359366192088736080 Nov 22 01:49:21 PM PST 23 Nov 22 01:49:23 PM PST 23 397008496 ps
T303 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.29568011980265450690143105922071165100533374622112117020018043288211126869420 Nov 22 01:49:07 PM PST 23 Nov 22 01:49:18 PM PST 23 6157569554 ps
T304 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.59931366326015291273001380673956126277522633460607418733176240432094240653044 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:25 PM PST 23 396151360 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.84268247806151475175967146257625892891153683239292721853002018296957729400898 Nov 22 01:49:15 PM PST 23 Nov 22 01:49:18 PM PST 23 462972254 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.14683200218998368645441588918319869327902753702843268672803916764195710486987 Nov 22 01:48:51 PM PST 23 Nov 22 01:48:55 PM PST 23 396151360 ps
T59 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.50161986399009624401008263183320184119460152469865554227956399596850678505556 Nov 22 01:49:12 PM PST 23 Nov 22 01:49:15 PM PST 23 1000664381 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.7727978431689823241106396789907939718784526915153021454169318816425183989642 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:44 PM PST 23 6157569554 ps
T61 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.70469978158128591092503725100149023724153164636571254110196218351881976262183 Nov 22 01:49:24 PM PST 23 Nov 22 01:49:27 PM PST 23 453115190 ps
T62 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.64616569675474535332473453874221527701184721718434001088474349432775935859514 Nov 22 01:48:57 PM PST 23 Nov 22 01:49:01 PM PST 23 453115190 ps
T63 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.105007583137182000980450423973575403906186559457817558415320244668552529468973 Nov 22 01:49:26 PM PST 23 Nov 22 01:49:29 PM PST 23 775862608 ps
T64 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.51595804720899669366248653668609841195754026639474782863407598740442662666521 Nov 22 01:49:15 PM PST 23 Nov 22 01:49:17 PM PST 23 418151184 ps
T65 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.115224709986572957454748725356554921086096010278574528171562840801957485016850 Nov 22 01:48:53 PM PST 23 Nov 22 01:48:57 PM PST 23 1000664381 ps
T307 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.94761724240290880857816782256989982904983374656811507469911414243797468126255 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:24 PM PST 23 396151360 ps
T308 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.114047220630548068531382670986548319243666415350894410584783606086678865305412 Nov 22 01:50:01 PM PST 23 Nov 22 01:50:05 PM PST 23 396151360 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.110876203810559906265955436678673544046945882676259761980150774286641062363013 Nov 22 01:49:06 PM PST 23 Nov 22 01:49:08 PM PST 23 775862608 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.36063052371362698665050944731904149511034905422534300584159798689819474338043 Nov 22 01:48:54 PM PST 23 Nov 22 01:49:07 PM PST 23 6157569554 ps
T311 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.61017452826598335753093731997746032380900940464488115496055449609943931077739 Nov 22 01:48:56 PM PST 23 Nov 22 01:49:04 PM PST 23 4648795910 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.58824775169054581157990582512779981902108573105939640480772499885525530338630 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:19 PM PST 23 462972254 ps
T313 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.49613999082852690115865399925381668772832406270040056425942328624755527855106 Nov 22 01:49:28 PM PST 23 Nov 22 01:49:32 PM PST 23 396151360 ps
T314 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.21977632584835355905801580949632017820960882381816964559345931778112197467634 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:33 PM PST 23 453115190 ps
T315 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.10026808340460205299506190695888802774117780790816739450394774428472171652879 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:24 PM PST 23 418151184 ps
T316 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.75938927371463525836865491289839611583254121487058889887845639710524001269519 Nov 22 01:49:10 PM PST 23 Nov 22 01:49:12 PM PST 23 397008496 ps
T317 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.96183036540452427131887980772452459323755517219042043163116672323141218207464 Nov 22 01:49:04 PM PST 23 Nov 22 01:49:06 PM PST 23 397008496 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.56051393293553127480790518466310224289763170520649702273252030312589980291141 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:36 PM PST 23 462972254 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.103874723627839074502770761274203258665575361786695251459736890078273293746957 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:06 PM PST 23 502489795 ps
T320 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.5997071267118510544571794352085099616109081738371871873618321307264826227219 Nov 22 01:49:49 PM PST 23 Nov 22 01:49:51 PM PST 23 396151360 ps
T321 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.63862218423207986648692425540134647263673590198535677628733665026765520597068 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:22 PM PST 23 453115190 ps
T66 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.70628698705027883670809098831028768433624400658962957416702814905516007541197 Nov 22 01:49:02 PM PST 23 Nov 22 01:49:05 PM PST 23 1000664381 ps
T322 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.99502776440658068974537668870906613370081624552802926217651270975573227341200 Nov 22 01:49:34 PM PST 23 Nov 22 01:49:40 PM PST 23 396151360 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.103847509653198070190269689611489693189862267892420526957827745848202566025902 Nov 22 01:49:06 PM PST 23 Nov 22 01:49:08 PM PST 23 462972254 ps
T324 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.99710359533312616984482110811709927072623224980090754159907831075506719713838 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:18 PM PST 23 396151360 ps
T325 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.28163342913343273262310063841639732526908246736683527337802324320579335871863 Nov 22 01:49:10 PM PST 23 Nov 22 01:49:12 PM PST 23 453115190 ps
T67 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.58488213484375889349182228693302650963496711951856967031470219598605957621069 Nov 22 01:48:49 PM PST 23 Nov 22 01:48:55 PM PST 23 1000664381 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.93797409785839481166516207123229402548220569234505933988785933949718137169420 Nov 22 01:49:04 PM PST 23 Nov 22 01:49:06 PM PST 23 453115190 ps
T327 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.92315201213120077793794436126332251646670170226654506329769390806709268950403 Nov 22 01:49:01 PM PST 23 Nov 22 01:49:03 PM PST 23 418151184 ps
T328 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.45264517946301246979428158365810322134335700298398494970800764703148240443555 Nov 22 01:49:01 PM PST 23 Nov 22 01:49:02 PM PST 23 396151360 ps
T329 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.34886266919255307576378639968667455439081424549316954215292089570073881576218 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:21 PM PST 23 418151184 ps
T330 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.93464522361212713727140724067380096983904738195620036897427865591080501939476 Nov 22 01:49:11 PM PST 23 Nov 22 01:49:13 PM PST 23 453115190 ps
T331 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.59261103154645005119360152050756117802315307835340133285545705794775518644221 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:25 PM PST 23 4648795910 ps
T332 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.91308762849854939877242679872533743551729541367110165042424649649611906739593 Nov 22 01:49:39 PM PST 23 Nov 22 01:49:42 PM PST 23 396151360 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.113898201334695078021056499558242032255176768921272382699215636195123281213744 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:22 PM PST 23 1000664381 ps
T333 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.88054946529852458849845538118933327031732817142149546931918644343067356904211 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:41 PM PST 23 4648795910 ps
T334 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.33457787167704378489459997573536996887135325153157413218396595117432083796119 Nov 22 01:49:32 PM PST 23 Nov 22 01:49:38 PM PST 23 396151360 ps
T335 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.35265274390245943637231713813469812180368608963215308124185798544620524714308 Nov 22 01:49:50 PM PST 23 Nov 22 01:49:52 PM PST 23 396151360 ps
T336 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.23294162712654768744428362384692156713277124744405999857275446789717850204719 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:19 PM PST 23 418151184 ps
T337 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.102514165502126610893309881657607088433798747474623941482790801322657648380808 Nov 22 01:49:46 PM PST 23 Nov 22 01:49:48 PM PST 23 396151360 ps
T338 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.30287758514514096922688205499002901145112410442314185902680985466758111815919 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:25 PM PST 23 462972254 ps
T69 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.5688041713472323143265058739785714904946204591191514788165485629511135598083 Nov 22 01:49:24 PM PST 23 Nov 22 01:49:28 PM PST 23 1000664381 ps
T339 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.109797236872638663518618522852814024341858245216917961443156074229931704217393 Nov 22 01:49:07 PM PST 23 Nov 22 01:49:09 PM PST 23 418151184 ps
T340 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.6689405185028908206273019971902277393897065207430671086151856792946650695288 Nov 22 01:48:50 PM PST 23 Nov 22 01:48:59 PM PST 23 4648795910 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.34311024491535683075570091857166127757663063637740034952876156280883949072561 Nov 22 01:49:06 PM PST 23 Nov 22 01:49:08 PM PST 23 396151360 ps
T342 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.91846449660945632085968992515356144914754148593719233392090769530025261725287 Nov 22 01:48:55 PM PST 23 Nov 22 01:48:59 PM PST 23 462972254 ps
T70 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.24777907262176621520148877801985050710309271052852455137488371069692428766302 Nov 22 01:49:05 PM PST 23 Nov 22 01:49:08 PM PST 23 1000664381 ps
T71 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2079084467054935189893610987034574813363261075626617704599452373738659451441 Nov 22 01:49:12 PM PST 23 Nov 22 01:49:14 PM PST 23 1000664381 ps
T343 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.67226991203463134414065354605985093029699294732060019972311892635728800061805 Nov 22 01:49:15 PM PST 23 Nov 22 01:49:18 PM PST 23 1000664381 ps
T344 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.72239723784583840453510715868352643435046003879609391074949904261534705751185 Nov 22 01:49:21 PM PST 23 Nov 22 01:49:23 PM PST 23 396151360 ps
T345 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.107813406495578944114557041471326834238538772951684723125838465754227857052020 Nov 22 01:49:26 PM PST 23 Nov 22 01:49:29 PM PST 23 462972254 ps
T346 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.78775026210735120254593899728355962524404042791805624105472113033739572530403 Nov 22 01:49:13 PM PST 23 Nov 22 01:49:18 PM PST 23 4648795910 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.17223814838384659136061174905150188083330755077905569885883641634989372989458 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:15 PM PST 23 6157569554 ps
T348 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.98483615862967400219526311314914163463014840238182806938414412808194018397055 Nov 22 01:49:48 PM PST 23 Nov 22 01:49:50 PM PST 23 396151360 ps
T349 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.15708932880314142087492870187781518784052667315416788919616631152076539343666 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:06 PM PST 23 1000664381 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.109961510554548162183673928239121129185965365140404997982701478708301986987753 Nov 22 01:49:11 PM PST 23 Nov 22 01:49:13 PM PST 23 462972254 ps
T351 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.17488993522802112057729956149943061222132924145553503741366889427581661763084 Nov 22 01:49:09 PM PST 23 Nov 22 01:49:10 PM PST 23 396151360 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.30342369075648193768700798494257973342057491676142327892167711574359693001965 Nov 22 01:49:40 PM PST 23 Nov 22 01:49:43 PM PST 23 418151184 ps
T353 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.64551133285298601841455477521091744195546547337228019777162053840316557697906 Nov 22 01:49:23 PM PST 23 Nov 22 01:49:31 PM PST 23 4648795910 ps
T354 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.113938957910885261216449629079243476397536818028989406152544294348095675982137 Nov 22 01:49:12 PM PST 23 Nov 22 01:49:14 PM PST 23 418151184 ps
T355 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.108550883187736922583420048520670494007894854177520903768049399492595629821453 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:35 PM PST 23 396151360 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.46195552721810129425985014871593159596765668799868554900748134042798512206035 Nov 22 01:49:34 PM PST 23 Nov 22 01:49:41 PM PST 23 775862608 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.49088110197384246090633744257238369620753268303479575912722629078315481689787 Nov 22 01:48:56 PM PST 23 Nov 22 01:48:59 PM PST 23 397008496 ps
T358 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.27719165991133778644182470967637757757951218407759261921856975624663661372621 Nov 22 01:49:14 PM PST 23 Nov 22 01:49:21 PM PST 23 4648795910 ps
T359 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.112208277258685208368646204005097602458158014912086242901185835220625943792340 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:25 PM PST 23 462972254 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.53491627684732434486087125155102943575438089253515500629581881785879569213052 Nov 22 01:48:53 PM PST 23 Nov 22 01:49:01 PM PST 23 4648795910 ps
T361 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.94054442670241144400064417191725360212714419134420099845401362054519668500271 Nov 22 01:49:13 PM PST 23 Nov 22 01:49:19 PM PST 23 4648795910 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.27978451494461103806861213225910214759598904222935033270888302151786500908373 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:26 PM PST 23 4648795910 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.6899693301775275456546575722602216422488242944802416342440104208984571240667 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:25 PM PST 23 4648795910 ps
T364 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.104592907682204482014480163176083219991616533416921768601392383092083238410819 Nov 22 01:49:05 PM PST 23 Nov 22 01:49:11 PM PST 23 4648795910 ps
T365 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.111856711837936922152993589092120326827787410919677741792105651234995843387716 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:21 PM PST 23 396151360 ps
T366 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.93194073473750509715954945290193636399195985070589257505232011590623547782797 Nov 22 01:49:04 PM PST 23 Nov 22 01:49:06 PM PST 23 453115190 ps
T367 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.111696367357056701617014634835144131458141914239619174878997330781215317597184 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:21 PM PST 23 396151360 ps
T368 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.64197786554545906145186482314815922902110071567750743214415628354286951000102 Nov 22 01:49:27 PM PST 23 Nov 22 01:49:30 PM PST 23 396151360 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.11951113608574796193535404862960959966972433634807784365981507243187879512798 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:05 PM PST 23 453115190 ps
T370 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.68493990827746079280558645472173463109896353701944786881050537397409373546492 Nov 22 01:49:02 PM PST 23 Nov 22 01:49:04 PM PST 23 396151360 ps
T371 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.42313630183893599475358794874950867083091975368468308611738242601954972678363 Nov 22 01:48:48 PM PST 23 Nov 22 01:48:53 PM PST 23 397008496 ps
T372 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.82990457855938286735085588843821122741121547619006363575225354071405191563790 Nov 22 01:49:31 PM PST 23 Nov 22 01:49:36 PM PST 23 502489795 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.64355400777162968055935447573172629705608424574638183518224557893304905871473 Nov 22 01:48:46 PM PST 23 Nov 22 01:49:01 PM PST 23 6157569554 ps
T374 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.46407446135081343743393755538418598922242336311868235946157578390183260493290 Nov 22 01:49:01 PM PST 23 Nov 22 01:49:03 PM PST 23 396151360 ps
T375 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.75488390099141957980993864407242073010912697339841770251772361907284510915736 Nov 22 01:48:47 PM PST 23 Nov 22 01:48:53 PM PST 23 775862608 ps
T376 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.60253598816071097543265672576243519298232927672177181817152866197781332099340 Nov 22 01:49:25 PM PST 23 Nov 22 01:49:28 PM PST 23 418151184 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.70808766632310738203684542320459709068847825618745351610740126322983599502805 Nov 22 01:48:54 PM PST 23 Nov 22 01:48:57 PM PST 23 418151184 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.15568805746107645616813598049360534731039055751241942990525387351365011807795 Nov 22 01:48:50 PM PST 23 Nov 22 01:48:55 PM PST 23 462972254 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.5773899498128275579107425141716193324556754502025605041545695556796292188738 Nov 22 01:48:53 PM PST 23 Nov 22 01:48:57 PM PST 23 396151360 ps
T380 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.57960656128780044415294962509174470966451683569425589931475466355701044670710 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:25 PM PST 23 396151360 ps
T381 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.18648179848871524417030340166427331792860022198728095754633253016927687853779 Nov 22 01:49:01 PM PST 23 Nov 22 01:49:04 PM PST 23 1000664381 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4031559345092818110022066029265540855391621026190161452448163617350792951525 Nov 22 01:49:24 PM PST 23 Nov 22 01:49:28 PM PST 23 1000664381 ps
T383 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.78893710084334202009074589397470607093076048641614240301618586611785318683436 Nov 22 01:49:00 PM PST 23 Nov 22 01:49:02 PM PST 23 453115190 ps
T384 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.108720234132905240284049016874335243049494077918882761897229249928439221499364 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:24 PM PST 23 396151360 ps
T385 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.36640966685540493192552834374965849803225585694182355592041050219140607500796 Nov 22 01:48:55 PM PST 23 Nov 22 01:48:59 PM PST 23 462972254 ps
T386 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.64062308665145246497145265891638802829296305391564351713079835765272536701605 Nov 22 01:48:54 PM PST 23 Nov 22 01:48:57 PM PST 23 396151360 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.110100344142049890300571627748422922431393307556644553324704195733297240335906 Nov 22 01:49:30 PM PST 23 Nov 22 01:49:40 PM PST 23 453115190 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.115213801144322772904869089631023790253632784540138838262920936535735767615794 Nov 22 01:49:10 PM PST 23 Nov 22 01:49:12 PM PST 23 396151360 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.5675794120902945764273026577973371747796768829251388178309754905758582695292 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:19 PM PST 23 1000664381 ps
T390 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.31517645465938291186367274176593061083900858330458209728129412803146159494808 Nov 22 01:49:21 PM PST 23 Nov 22 01:49:24 PM PST 23 462972254 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.105535466682497685180503876122999361430304082746569700594933811024317662543879 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:18 PM PST 23 397008496 ps
T392 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.91134547219112690547506908854218337908807130493160061177498004559451378933764 Nov 22 01:49:42 PM PST 23 Nov 22 01:49:45 PM PST 23 396151360 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2386067024874762366215686369877774533291514627603878766515410958232915072432 Nov 22 01:48:45 PM PST 23 Nov 22 01:48:54 PM PST 23 4648795910 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1741496401199131586586602660801560186702219796583709944242858843625623747405 Nov 22 01:49:37 PM PST 23 Nov 22 01:49:42 PM PST 23 418151184 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.13917416995142681531168678930212845669877054284467458088777563954024649183606 Nov 22 01:48:55 PM PST 23 Nov 22 01:48:59 PM PST 23 462972254 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.15009741142821829504278756470056815915557227685128205767738306037472399261667 Nov 22 01:48:54 PM PST 23 Nov 22 01:48:58 PM PST 23 1000664381 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.97939156597322261969992732094688694249149033319811986263952884976146093344463 Nov 22 01:49:17 PM PST 23 Nov 22 01:49:20 PM PST 23 397008496 ps
T398 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.52806468312548818997675056928583524183969871472212132730265247059819943019381 Nov 22 01:49:28 PM PST 23 Nov 22 01:49:32 PM PST 23 453115190 ps
T399 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.113348638106908255739774643323131551673597914018654112645588584954925292631669 Nov 22 01:48:51 PM PST 23 Nov 22 01:48:55 PM PST 23 418151184 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.67210754401241476814797761191394720950894062852088842491229354207290178586923 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:10 PM PST 23 4648795910 ps
T401 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.65249054802602127039608413914042582539128928802825568781170448732921781664161 Nov 22 01:49:33 PM PST 23 Nov 22 01:49:39 PM PST 23 396151360 ps
T402 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.34317732162495294608803960777081646156817545887840790960245532765187714867525 Nov 22 01:49:01 PM PST 23 Nov 22 01:49:03 PM PST 23 396151360 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.90822001026287033473609409201441079189186486506518121401244250635745348175063 Nov 22 01:49:27 PM PST 23 Nov 22 01:49:29 PM PST 23 396151360 ps
T404 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.112642993344423826135733669312195519781307006001570756084123454976155950734635 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:33 PM PST 23 396151360 ps
T405 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.9771519548080341051660464039140384739176808078939549579541190903638100616220 Nov 22 01:49:13 PM PST 23 Nov 22 01:49:15 PM PST 23 1000664381 ps
T406 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.94741558619849844123944068444425602589598250685167046197088460175058172215108 Nov 22 01:49:21 PM PST 23 Nov 22 01:49:23 PM PST 23 396151360 ps
T407 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.94995338699396052545634998018218671594166505171340000969633302736349746439979 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:20 PM PST 23 396151360 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.95844804612565269270308359987358881223122639035213539592739895701819542237223 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:10 PM PST 23 4648795910 ps
T409 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.86030381663905804553391000475081642499071144901462565846040393899785819278031 Nov 22 01:49:25 PM PST 23 Nov 22 01:49:28 PM PST 23 396151360 ps
T410 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.8023283328215965498462920947002634993936530970898939205013104380328344887815 Nov 22 01:49:43 PM PST 23 Nov 22 01:49:50 PM PST 23 4648795910 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.102023602604390142072966764241520474091451371153156984489571672655086307974479 Nov 22 01:49:23 PM PST 23 Nov 22 01:49:27 PM PST 23 1000664381 ps
T412 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.92210823991182656593211503644133831276743551032347840691883662116707549358154 Nov 22 01:49:26 PM PST 23 Nov 22 01:49:29 PM PST 23 396151360 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.68260306044195041851068914915235531549283812783889872299815127068992953730581 Nov 22 01:49:15 PM PST 23 Nov 22 01:49:17 PM PST 23 396151360 ps
T414 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.62089736257762734536058119244367510344875294142702620095901388341975788365694 Nov 22 01:49:29 PM PST 23 Nov 22 01:49:33 PM PST 23 396151360 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.36114416800620753679464045856773786397397850670438138093455001339202278238392 Nov 22 01:49:18 PM PST 23 Nov 22 01:49:20 PM PST 23 396151360 ps
T416 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.5116456328547466769789915148521439098275169276690702448633518122482795840964 Nov 22 01:49:19 PM PST 23 Nov 22 01:49:22 PM PST 23 453115190 ps
T417 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.30367226026760696366887023103431316085143321387941894978405294187211401000547 Nov 22 01:49:22 PM PST 23 Nov 22 01:49:25 PM PST 23 396151360 ps
T418 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.64513840724233176638273939876323516856205383601253505925995393502137355079636 Nov 22 01:49:09 PM PST 23 Nov 22 01:49:15 PM PST 23 4648795910 ps
T419 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.88621904073259742298382008535080767281080519291295940820909973440914445728398 Nov 22 01:49:03 PM PST 23 Nov 22 01:49:06 PM PST 23 462972254 ps
T420 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.76887770467321572225744214823984954974833527627717830239797556707824643225105 Nov 22 01:49:24 PM PST 23 Nov 22 01:49:27 PM PST 23 396151360 ps
T421 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.38007053856797866189276009363256436735494154701591179192475878720023601436949 Nov 22 01:49:12 PM PST 23 Nov 22 01:49:15 PM PST 23 1000664381 ps
T422 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.46003444780102554503959928567622852740974840871999664413838733786961369869667 Nov 22 01:49:17 PM PST 23 Nov 22 01:49:19 PM PST 23 396151360 ps
T423 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.67793703551618224886242379074299917222397713225063862943254841648051560204233 Nov 22 01:48:58 PM PST 23 Nov 22 01:49:01 PM PST 23 462972254 ps
T424 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.90550688410093316140928652347436416898183567175062045282939254981977884940635 Nov 22 01:48:43 PM PST 23 Nov 22 01:48:49 PM PST 23 462972254 ps
T425 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3402923803911653736553664577946981422788927140971844139193569642310171125624 Nov 22 01:49:26 PM PST 23 Nov 22 01:49:28 PM PST 23 418151184 ps
T426 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.101198082755837835085092891136328938997983701444850587181557662388505324401720 Nov 22 01:49:00 PM PST 23 Nov 22 01:49:02 PM PST 23 775862608 ps
T427 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.74298075566634521986817226454243398484206367243579010154766405686371671417286 Nov 22 01:49:04 PM PST 23 Nov 22 01:49:07 PM PST 23 1000664381 ps
T428 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.79736094775337901128270540651088379920187595792501182011341093827183898466734 Nov 22 01:48:51 PM PST 23 Nov 22 01:48:55 PM PST 23 502489795 ps
T429 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.9161094169873022506325933181868178514765813054500682803586432781064374227406 Nov 22 01:48:56 PM PST 23 Nov 22 01:48:59 PM PST 23 453115190 ps
T430 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.45775909677696705519590115627865318934904388426623702755140747856712810857674 Nov 22 01:49:16 PM PST 23 Nov 22 01:49:18 PM PST 23 396151360 ps

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.85305923808320780546048466972249708986566983404635057769692865944349966427550
Short name T1
Test name
Test status
Simulation time 502489795 ps
CPU time 1.15 seconds
Started Nov 22 01:49:20 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 183924 kb
Host smart-37d8675a-c657-46a3-9fc5-4e02ef4f1d6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85305923808320780546048466972249708986566983404635057769692865944349966427550 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_aliasing.85305923808320780546048466972249708986566983404635057769692865944349966427550
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.51555950670422322732848543979432022963650277296171296739396897857047467325971
Short name T20
Test name
Test status
Simulation time 96759987586 ps
CPU time 424.42 seconds
Started Nov 22 01:16:40 PM PST 23
Finished Nov 22 01:23:46 PM PST 23
Peak memory 198092 kb
Host smart-a26b261f-fbd9-4901-b03e-a5f9f7b8e5ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515559506704223227328
48543979432022963650277296171296739396897857047467325971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_
reset.51555950670422322732848543979432022963650277296171296739396897857047467325971
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.110292252585137431644963351493363566137912951056362861124371244150982825995016
Short name T110
Test name
Test status
Simulation time 332628779192 ps
CPU time 304.04 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:22:09 PM PST 23
Peak memory 193292 kb
Host smart-daba1080-c406-4ec4-8a8f-e452ace6b7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110292252585137431644963351493363566137912951056362861124371244150982825995016 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all.110292252585137431644963351493363566137912951056362861124371244150982825995016
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.7089869217247436604712461669597214049448456681570587290111066415074077599864
Short name T9
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.21 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:32 PM PST 23
Peak memory 197504 kb
Host smart-b79ba3e7-cde2-4306-8e0c-96d7b42b0d97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7089869217247436604712461669597214049448456681570587290111066415074077599864 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_intg_err.7089869217247436604712461669597214049448456681570587290111066415074077599864
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.60129308568769191982319901636169020040033495855651578588418469216492209798077
Short name T54
Test name
Test status
Simulation time 462972254 ps
CPU time 1.48 seconds
Started Nov 22 01:49:45 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 198660 kb
Host smart-54acf816-869e-4b47-98fd-08e36295438b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60129308568769191982319901636169020040033495855651578588418469216492209798077 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.60129308568769191982319901636169020040033495855651578588418469216492209798077
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.33060626375355432679572264388914076738781294030774253845074820045322888341707
Short name T38
Test name
Test status
Simulation time 4270477508 ps
CPU time 4.63 seconds
Started Nov 22 01:16:55 PM PST 23
Finished Nov 22 01:17:13 PM PST 23
Peak memory 214888 kb
Host smart-45013766-7e79-48c6-ad49-dae4c37120f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33060626375355432679572264388914076738781294030774253845074820045322888341707 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.33060626375355432679572264388914076738781294030774253845074820045322888341707
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/14.aon_timer_jump.923463657142426822081938760895711626649095405414845513952207937077933148626
Short name T19
Test name
Test status
Simulation time 474704303 ps
CPU time 0.95 seconds
Started Nov 22 01:16:57 PM PST 23
Finished Nov 22 01:17:10 PM PST 23
Peak memory 183156 kb
Host smart-3a2487e2-7e9f-49ce-bfcb-071ae5369cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923463657142426822081938760895711626649095405414845513952207937077933148626 -assert nopostproc +UVM_TESTNAME=aon_timer_b
ase_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.aon_timer_jump.923463657142426822081938760895711626649095405414845513952207937077933148626
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.87159622581896784064301160068185726747823917178631894248423155807411257435785
Short name T10
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.9 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 193456 kb
Host smart-55057b23-c26d-489d-8efa-a3d3a4cee006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87159622581896784064301160068185726747823917178631894248423155807411257435785
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_same_csr_outstanding.871596225818967840643011600681857267478239171786318
94248423155807411257435785
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.14164209857551555452707103977430276630602702903095691495163997023635512276547
Short name T25
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.98 seconds
Started Nov 22 01:17:07 PM PST 23
Finished Nov 22 01:18:05 PM PST 23
Peak memory 183336 kb
Host smart-fb7e5182-9da4-4190-97b2-1b62a3f878e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14164209857551555452707103977430276630602702903095691495163997023635512276547 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.aon_timer_prescaler.14164209857551555452707103977430276630602702903095691495163997023635512276547
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.103874723627839074502770761274203258665575361786695251459736890078273293746957
Short name T319
Test name
Test status
Simulation time 502489795 ps
CPU time 1.15 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 183996 kb
Host smart-61440022-2e7f-4ab3-acc9-89543c4f0de4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103874723627839074502770761274203258665575361786695251459736890078273293746957 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_aliasing.103874723627839074502770761274203258665575361786695251459736890078273293746957
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.64355400777162968055935447573172629705608424574638183518224557893304905871473
Short name T373
Test name
Test status
Simulation time 6157569554 ps
CPU time 10.57 seconds
Started Nov 22 01:48:46 PM PST 23
Finished Nov 22 01:49:01 PM PST 23
Peak memory 194456 kb
Host smart-2d500850-d770-4e75-88d6-3f398ceb6ec2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64355400777162968055935447573172629705608424574638183518224557893304905871473 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bit_bash.64355400777162968055935447573172629705608424574638183518224557893304905871473
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.110876203810559906265955436678673544046945882676259761980150774286641062363013
Short name T309
Test name
Test status
Simulation time 775862608 ps
CPU time 1.29 seconds
Started Nov 22 01:49:06 PM PST 23
Finished Nov 22 01:49:08 PM PST 23
Peak memory 183804 kb
Host smart-99633bad-53ae-429a-bdac-d8e05ed60226
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110876203810559906265955436678673544046945882676259761980150774286641062363013 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw_reset.110876203810559906265955436678673544046945882676259761980150774286641062363013
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.11951113608574796193535404862960959966972433634807784365981507243187879512798
Short name T369
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 194848 kb
Host smart-150597f3-46df-4aa9-b9dd-ca5bde5ed0a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195111360857479619353540486296095996697243
3634807784365981507243187879512798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1195111360
8574796193535404862960959966972433634807784365981507243187879512798
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.113348638106908255739774643323131551673597914018654112645588584954925292631669
Short name T399
Test name
Test status
Simulation time 418151184 ps
CPU time 0.94 seconds
Started Nov 22 01:48:51 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 183924 kb
Host smart-5d8e28a9-d202-4e7b-8fa2-c13b7119f783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113348638106908255739774643323131551673597914018654112645588584954925292631669 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.113348638106908255739774643323131551673597914018654112645588584954925292631669
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.14683200218998368645441588918319869327902753702843268672803916764195710486987
Short name T306
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:48:51 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 183920 kb
Host smart-af3c9a4a-214e-4f62-bf5d-b5f535887455
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14683200218998368645441588918319869327902753702843268672803916764195710486987 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.14683200218998368645441588918319869327902753702843268672803916764195710486987
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.49088110197384246090633744257238369620753268303479575912722629078315481689787
Short name T357
Test name
Test status
Simulation time 397008496 ps
CPU time 0.87 seconds
Started Nov 22 01:48:56 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 183892 kb
Host smart-3bb616dc-4555-4345-81f4-f9b6b9e9a06e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49088110197384246090633744257238369620753268303479575912722629078315481689787 -a
ssert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_partial_access.4908811019738424609063374425723836962075326830347957591
2722629078315481689787
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.51240458756001558746989528888011162004033386303530644182386535498022311060177
Short name T7
Test name
Test status
Simulation time 397008496 ps
CPU time 0.87 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 183912 kb
Host smart-efd4b6f7-c94b-4abb-8159-aa7037fd2e36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51240458756001558746989528888011162004033386303530644182386535498022311060177 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_walk.51240458756001558746989528888011162004033386303530644182386535498022311060177
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.15009741142821829504278756470056815915557227685128205767738306037472399261667
Short name T396
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.94 seconds
Started Nov 22 01:48:54 PM PST 23
Finished Nov 22 01:48:58 PM PST 23
Peak memory 193352 kb
Host smart-7d9b56b2-8370-4e16-b372-7837f25163fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009741142821829504278756470056815915557227685128205767738306037472399261667
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_same_csr_outstanding.150097411428218295042787564700568159155572276851282
05767738306037472399261667
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.90550688410093316140928652347436416898183567175062045282939254981977884940635
Short name T424
Test name
Test status
Simulation time 462972254 ps
CPU time 1.48 seconds
Started Nov 22 01:48:43 PM PST 23
Finished Nov 22 01:48:49 PM PST 23
Peak memory 198560 kb
Host smart-62ac1b5a-7614-4c9d-8b75-94fc9832e884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90550688410093316140928652347436416898183567175062045282939254981977884940635 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.90550688410093316140928652347436416898183567175062045282939254981977884940635
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.6689405185028908206273019971902277393897065207430671086151856792946650695288
Short name T340
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.26 seconds
Started Nov 22 01:48:50 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 197476 kb
Host smart-21e534b2-e04a-4a47-842b-1dff9e233016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6689405185028908206273019971902277393897065207430671086151856792946650695288 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_intg_err.6689405185028908206273019971902277393897065207430671086151856792946650695288
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.78935940595135206461994777809375011219379399799742124392543939197170994049875
Short name T4
Test name
Test status
Simulation time 502489795 ps
CPU time 1.15 seconds
Started Nov 22 01:49:04 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 183916 kb
Host smart-be97d882-a893-402e-a1d5-1e63681f0a10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78935940595135206461994777809375011219379399799742124392543939197170994049875 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_aliasing.78935940595135206461994777809375011219379399799742124392543939197170994049875
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.17223814838384659136061174905150188083330755077905569885883641634989372989458
Short name T347
Test name
Test status
Simulation time 6157569554 ps
CPU time 10.61 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 194356 kb
Host smart-56290dcc-51ed-4647-a292-b86a0a7442b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223814838384659136061174905150188083330755077905569885883641634989372989458 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bit_bash.17223814838384659136061174905150188083330755077905569885883641634989372989458
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.101198082755837835085092891136328938997983701444850587181557662388505324401720
Short name T426
Test name
Test status
Simulation time 775862608 ps
CPU time 1.26 seconds
Started Nov 22 01:49:00 PM PST 23
Finished Nov 22 01:49:02 PM PST 23
Peak memory 183916 kb
Host smart-488182c8-c245-43f1-8803-4cfb9dde505e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101198082755837835085092891136328938997983701444850587181557662388505324401720 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw_reset.101198082755837835085092891136328938997983701444850587181557662388505324401720
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.93194073473750509715954945290193636399195985070589257505232011590623547782797
Short name T366
Test name
Test status
Simulation time 453115190 ps
CPU time 0.98 seconds
Started Nov 22 01:49:04 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 194868 kb
Host smart-13d283bc-099c-462d-adfe-bfd05ba25edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9319407347375050971595494529019363639919598
5070589257505232011590623547782797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.9319407347
3750509715954945290193636399195985070589257505232011590623547782797
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.89647737500690344775424426116459163551258809625472105672152024637907223083208
Short name T2
Test name
Test status
Simulation time 418151184 ps
CPU time 0.94 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 183848 kb
Host smart-d06c0aac-5b82-414d-8e89-da923fa16f02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89647737500690344775424426116459163551258809625472105672152024637907223083208 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.89647737500690344775424426116459163551258809625472105672152024637907223083208
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.34317732162495294608803960777081646156817545887840790960245532765187714867525
Short name T402
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:03 PM PST 23
Peak memory 183832 kb
Host smart-b1edd274-baa3-48bb-9da5-87629e3b180c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34317732162495294608803960777081646156817545887840790960245532765187714867525 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.34317732162495294608803960777081646156817545887840790960245532765187714867525
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.75938927371463525836865491289839611583254121487058889887845639710524001269519
Short name T316
Test name
Test status
Simulation time 397008496 ps
CPU time 0.87 seconds
Started Nov 22 01:49:10 PM PST 23
Finished Nov 22 01:49:12 PM PST 23
Peak memory 183808 kb
Host smart-2da345eb-e878-4c97-968e-d52e5f016afd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75938927371463525836865491289839611583254121487058889887845639710524001269519 -a
ssert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_partial_access.7593892737146352583686549128983961158325412148705888988
7845639710524001269519
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.96183036540452427131887980772452459323755517219042043163116672323141218207464
Short name T317
Test name
Test status
Simulation time 397008496 ps
CPU time 0.85 seconds
Started Nov 22 01:49:04 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 183908 kb
Host smart-ea79db44-0f50-4bb0-9057-ce5d2ee6bca7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96183036540452427131887980772452459323755517219042043163116672323141218207464 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_walk.96183036540452427131887980772452459323755517219042043163116672323141218207464
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.103847509653198070190269689611489693189862267892420526957827745848202566025902
Short name T323
Test name
Test status
Simulation time 462972254 ps
CPU time 1.52 seconds
Started Nov 22 01:49:06 PM PST 23
Finished Nov 22 01:49:08 PM PST 23
Peak memory 198684 kb
Host smart-e316cdd3-7ae1-4be8-9bc6-743044f37dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103847509653198070190269689611489693189862267892420526957827745848202566025902 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.103847509653198070190269689611489693189862267892420526957827745848202566025902
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2386067024874762366215686369877774533291514627603878766515410958232915072432
Short name T393
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.43 seconds
Started Nov 22 01:48:45 PM PST 23
Finished Nov 22 01:48:54 PM PST 23
Peak memory 197396 kb
Host smart-4be1f890-5cc0-4a99-8ec2-6d70ac78a90a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386067024874762366215686369877774533291514627603878766515410958232915072432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_intg_err.2386067024874762366215686369877774533291514627603878766515410958232915072432
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.89526829562808604108783797120431907760949210431511446814167892237053358948115
Short name T33
Test name
Test status
Simulation time 453115190 ps
CPU time 0.97 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 194836 kb
Host smart-1518cfc5-4d54-4fbf-b4c3-d5f12184b573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8952682956280860410878379712043190776094921
0431511446814167892237053358948115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.895268295
62808604108783797120431907760949210431511446814167892237053358948115
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.110283818401242192024559307069619133165520823164422591480609165517738412567916
Short name T13
Test name
Test status
Simulation time 418151184 ps
CPU time 0.94 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 183856 kb
Host smart-91edbfd7-058f-4876-94da-eb4c9c0a7a5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110283818401242192024559307069619133165520823164422591480609165517738412567916 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.110283818401242192024559307069619133165520823164422591480609165517738412567916
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.68260306044195041851068914915235531549283812783889872299815127068992953730581
Short name T413
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:15 PM PST 23
Finished Nov 22 01:49:17 PM PST 23
Peak memory 183824 kb
Host smart-43bf7dbe-21e0-4697-92bd-e9c9540452c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68260306044195041851068914915235531549283812783889872299815127068992953730581 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.68260306044195041851068914915235531549283812783889872299815127068992953730581
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.9771519548080341051660464039140384739176808078939549579541190903638100616220
Short name T405
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.92 seconds
Started Nov 22 01:49:13 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 193400 kb
Host smart-6a8132ce-4f96-41d4-b37c-2f4f9397da7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9771519548080341051660464039140384739176808078939549579541190903638100616220 -
assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_same_csr_outstanding.977151954808034105166046403914038473917680807893954
9579541190903638100616220
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.30287758514514096922688205499002901145112410442314185902680985466758111815919
Short name T338
Test name
Test status
Simulation time 462972254 ps
CPU time 1.52 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 198548 kb
Host smart-2530a2c7-adf2-47bd-88e7-420d7417c43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287758514514096922688205499002901145112410442314185902680985466758111815919 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.30287758514514096922688205499002901145112410442314185902680985466758111815919
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.64513840724233176638273939876323516856205383601253505925995393502137355079636
Short name T418
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.26 seconds
Started Nov 22 01:49:09 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 197504 kb
Host smart-32db8672-da23-4e25-814d-382265560ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64513840724233176638273939876323516856205383601253505925995393502137355079636 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_intg_err.64513840724233176638273939876323516856205383601253505925995393502137355079636
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.21547386974275130138990966569385639265798145496737392927277937961188511530130
Short name T75
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 194808 kb
Host smart-4bc7cb7b-dc47-473a-b06e-954d8cf488d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154738697427513013899096656938563926579814
5496737392927277937961188511530130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.215473869
74275130138990966569385639265798145496737392927277937961188511530130
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.60253598816071097543265672576243519298232927672177181817152866197781332099340
Short name T376
Test name
Test status
Simulation time 418151184 ps
CPU time 0.93 seconds
Started Nov 22 01:49:25 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 183884 kb
Host smart-1c5258a0-30be-4b2c-94e8-fe3b028d372c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60253598816071097543265672576243519298232927672177181817152866197781332099340 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.60253598816071097543265672576243519298232927672177181817152866197781332099340
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.30367226026760696366887023103431316085143321387941894978405294187211401000547
Short name T417
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 183880 kb
Host smart-ce0fdc6e-1f22-418b-9194-768cd2492981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30367226026760696366887023103431316085143321387941894978405294187211401000547 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.30367226026760696366887023103431316085143321387941894978405294187211401000547
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.50161986399009624401008263183320184119460152469865554227956399596850678505556
Short name T59
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.95 seconds
Started Nov 22 01:49:12 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 193452 kb
Host smart-05c5a454-d120-4c9a-aead-e3ac447bb795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50161986399009624401008263183320184119460152469865554227956399596850678505556
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_same_csr_outstanding.50161986399009624401008263183320184119460152469865
554227956399596850678505556
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.112208277258685208368646204005097602458158014912086242901185835220625943792340
Short name T359
Test name
Test status
Simulation time 462972254 ps
CPU time 1.53 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 198516 kb
Host smart-936c9f94-d736-4669-961f-2db4a6ac332e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112208277258685208368646204005097602458158014912086242901185835220625943792340 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.112208277258685208368646204005097602458158014912086242901185835220625943792340
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.64551133285298601841455477521091744195546547337228019777162053840316557697906
Short name T353
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.23 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:31 PM PST 23
Peak memory 197508 kb
Host smart-0e2b9ea2-8ff2-4f1c-8ff7-5f8b9fdf596b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64551133285298601841455477521091744195546547337228019777162053840316557697906 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_intg_err.64551133285298601841455477521091744195546547337228019777162053840316557697906
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.110100344142049890300571627748422922431393307556644553324704195733297240335906
Short name T387
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 194824 kb
Host smart-cc5f0355-93bb-47fe-ad1b-67fe09329eca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101003441420498903005716277484229224313933
07556644553324704195733297240335906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.11010034
4142049890300571627748422922431393307556644553324704195733297240335906
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.34886266919255307576378639968667455439081424549316954215292089570073881576218
Short name T329
Test name
Test status
Simulation time 418151184 ps
CPU time 0.98 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:21 PM PST 23
Peak memory 183836 kb
Host smart-39ddb5a7-89d4-49e0-824e-aa62be273b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34886266919255307576378639968667455439081424549316954215292089570073881576218 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.34886266919255307576378639968667455439081424549316954215292089570073881576218
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.62089736257762734536058119244367510344875294142702620095901388341975788365694
Short name T414
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 183968 kb
Host smart-56922c1a-ab4c-4d77-a541-9fdd119d80d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62089736257762734536058119244367510344875294142702620095901388341975788365694 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.62089736257762734536058119244367510344875294142702620095901388341975788365694
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.5688041713472323143265058739785714904946204591191514788165485629511135598083
Short name T69
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.9 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 193396 kb
Host smart-69048bda-a705-471c-b687-e8cc60d57395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5688041713472323143265058739785714904946204591191514788165485629511135598083 -
assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_same_csr_outstanding.568804171347232314326505873978571490494620459119151
4788165485629511135598083
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.56051393293553127480790518466310224289763170520649702273252030312589980291141
Short name T318
Test name
Test status
Simulation time 462972254 ps
CPU time 1.47 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 198492 kb
Host smart-485b19ac-2672-4347-a2ff-8d5f43eda33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56051393293553127480790518466310224289763170520649702273252030312589980291141 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.56051393293553127480790518466310224289763170520649702273252030312589980291141
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.58671572630352778557788896095619530200892919427090444109059693635310063137480
Short name T15
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:49:09 PM PST 23
Finished Nov 22 01:49:11 PM PST 23
Peak memory 194864 kb
Host smart-6ff6f50e-d11a-49d3-a50a-b71ccdac0370
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5867157263035277855778889609561953020089291
9427090444109059693635310063137480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.586715726
30352778557788896095619530200892919427090444109059693635310063137480
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.30342369075648193768700798494257973342057491676142327892167711574359693001965
Short name T352
Test name
Test status
Simulation time 418151184 ps
CPU time 0.97 seconds
Started Nov 22 01:49:40 PM PST 23
Finished Nov 22 01:49:43 PM PST 23
Peak memory 183844 kb
Host smart-1b49048f-b6cb-44dd-96b0-b41c5d61b6b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342369075648193768700798494257973342057491676142327892167711574359693001965 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.30342369075648193768700798494257973342057491676142327892167711574359693001965
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.99502776440658068974537668870906613370081624552802926217651270975573227341200
Short name T322
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:40 PM PST 23
Peak memory 183900 kb
Host smart-2a782d8a-b597-4cad-97e0-f7b549582aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99502776440658068974537668870906613370081624552802926217651270975573227341200 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.99502776440658068974537668870906613370081624552802926217651270975573227341200
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2079084467054935189893610987034574813363261075626617704599452373738659451441
Short name T71
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.89 seconds
Started Nov 22 01:49:12 PM PST 23
Finished Nov 22 01:49:14 PM PST 23
Peak memory 193444 kb
Host smart-10858118-a982-4db0-b790-b25d22c19e7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079084467054935189893610987034574813363261075626617704599452373738659451441 -
assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_same_csr_outstanding.207908446705493518989361098703457481336326107562661
7704599452373738659451441
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.8023283328215965498462920947002634993936530970898939205013104380328344887815
Short name T410
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.18 seconds
Started Nov 22 01:49:43 PM PST 23
Finished Nov 22 01:49:50 PM PST 23
Peak memory 197352 kb
Host smart-eca9c553-7862-4ff2-9b98-cc6b7c3e1f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8023283328215965498462920947002634993936530970898939205013104380328344887815 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_intg_err.8023283328215965498462920947002634993936530970898939205013104380328344887815
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.86593932558693372989533758883569126363036963718105088097879005641994982215665
Short name T18
Test name
Test status
Simulation time 453115190 ps
CPU time 0.99 seconds
Started Nov 22 01:49:27 PM PST 23
Finished Nov 22 01:49:30 PM PST 23
Peak memory 194864 kb
Host smart-781c7d85-41ba-47f9-b476-ee371a67174d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8659393255869337298953375888356912636303696
3718105088097879005641994982215665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.865939325
58693372989533758883569126363036963718105088097879005641994982215665
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.109797236872638663518618522852814024341858245216917961443156074229931704217393
Short name T339
Test name
Test status
Simulation time 418151184 ps
CPU time 0.95 seconds
Started Nov 22 01:49:07 PM PST 23
Finished Nov 22 01:49:09 PM PST 23
Peak memory 183880 kb
Host smart-e57ad59e-906c-46c3-a5c6-6e0af24eb3ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109797236872638663518618522852814024341858245216917961443156074229931704217393 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.109797236872638663518618522852814024341858245216917961443156074229931704217393
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.36114416800620753679464045856773786397397850670438138093455001339202278238392
Short name T415
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:20 PM PST 23
Peak memory 183888 kb
Host smart-7355ec38-4555-42ee-81ee-d0615e3168c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36114416800620753679464045856773786397397850670438138093455001339202278238392 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.36114416800620753679464045856773786397397850670438138093455001339202278238392
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.113898201334695078021056499558242032255176768921272382699215636195123281213744
Short name T68
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.94 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 193412 kb
Host smart-c97e1df2-7b3e-49a7-b8b0-049aa9143c77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113898201334695078021056499558242032255176768921272382699215636195123281213744
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_same_csr_outstanding.1138982013346950780210564995582420322551767689212
72382699215636195123281213744
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.109961510554548162183673928239121129185965365140404997982701478708301986987753
Short name T350
Test name
Test status
Simulation time 462972254 ps
CPU time 1.51 seconds
Started Nov 22 01:49:11 PM PST 23
Finished Nov 22 01:49:13 PM PST 23
Peak memory 198532 kb
Host smart-30bd290e-207b-4e1c-a577-c0bab57041f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109961510554548162183673928239121129185965365140404997982701478708301986987753 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.109961510554548162183673928239121129185965365140404997982701478708301986987753
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.59261103154645005119360152050756117802315307835340133285545705794775518644221
Short name T331
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.33 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 197496 kb
Host smart-13dfcad1-0cec-43a3-a6ff-0a16f0df7b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59261103154645005119360152050756117802315307835340133285545705794775518644221 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_intg_err.59261103154645005119360152050756117802315307835340133285545705794775518644221
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.28163342913343273262310063841639732526908246736683527337802324320579335871863
Short name T325
Test name
Test status
Simulation time 453115190 ps
CPU time 0.98 seconds
Started Nov 22 01:49:10 PM PST 23
Finished Nov 22 01:49:12 PM PST 23
Peak memory 194840 kb
Host smart-6c572d10-4c2d-4c00-9692-8d6abbf1713d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816334291334327326231006384163973252690824
6736683527337802324320579335871863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.281633429
13343273262310063841639732526908246736683527337802324320579335871863
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.23294162712654768744428362384692156713277124744405999857275446789717850204719
Short name T336
Test name
Test status
Simulation time 418151184 ps
CPU time 0.93 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:19 PM PST 23
Peak memory 183896 kb
Host smart-7ef1ea53-175d-41dc-a6f8-05b1f1cf20a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23294162712654768744428362384692156713277124744405999857275446789717850204719 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.23294162712654768744428362384692156713277124744405999857275446789717850204719
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.94995338699396052545634998018218671594166505171340000969633302736349746439979
Short name T407
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:20 PM PST 23
Peak memory 183824 kb
Host smart-d8bb6377-0c2f-4b9e-8cb5-0c88bdc350eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94995338699396052545634998018218671594166505171340000969633302736349746439979 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.94995338699396052545634998018218671594166505171340000969633302736349746439979
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.102023602604390142072966764241520474091451371153156984489571672655086307974479
Short name T411
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.91 seconds
Started Nov 22 01:49:23 PM PST 23
Finished Nov 22 01:49:27 PM PST 23
Peak memory 193392 kb
Host smart-a5828d1d-e91c-4cc3-a7e6-052a7d78bf1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102023602604390142072966764241520474091451371153156984489571672655086307974479
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_same_csr_outstanding.1020236026043901420729667642415204740914513711531
56984489571672655086307974479
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.58824775169054581157990582512779981902108573105939640480772499885525530338630
Short name T312
Test name
Test status
Simulation time 462972254 ps
CPU time 1.52 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:19 PM PST 23
Peak memory 198572 kb
Host smart-f9343206-41cd-4b34-a5a6-6ba0877241e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58824775169054581157990582512779981902108573105939640480772499885525530338630 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.58824775169054581157990582512779981902108573105939640480772499885525530338630
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.27978451494461103806861213225910214759598904222935033270888302151786500908373
Short name T362
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.21 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:26 PM PST 23
Peak memory 197528 kb
Host smart-4f748f6c-394b-4791-a93d-7ad2689df5a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978451494461103806861213225910214759598904222935033270888302151786500908373 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_intg_err.27978451494461103806861213225910214759598904222935033270888302151786500908373
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.70469978158128591092503725100149023724153164636571254110196218351881976262183
Short name T61
Test name
Test status
Simulation time 453115190 ps
CPU time 0.99 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:27 PM PST 23
Peak memory 194800 kb
Host smart-250189cf-fa8e-4239-9086-ff5bbe896ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7046997815812859109250372510014902372415316
4636571254110196218351881976262183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.704699781
58128591092503725100149023724153164636571254110196218351881976262183
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.3402923803911653736553664577946981422788927140971844139193569642310171125624
Short name T425
Test name
Test status
Simulation time 418151184 ps
CPU time 0.94 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 183984 kb
Host smart-60b983ec-0431-4c57-be7b-b11e6c33189b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402923803911653736553664577946981422788927140971844139193569642310171125624 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.3402923803911653736553664577946981422788927140971844139193569642310171125624
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.17488993522802112057729956149943061222132924145553503741366889427581661763084
Short name T351
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:09 PM PST 23
Finished Nov 22 01:49:10 PM PST 23
Peak memory 183848 kb
Host smart-1a656163-d9e6-41f7-aa6a-bca971f12e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17488993522802112057729956149943061222132924145553503741366889427581661763084 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.17488993522802112057729956149943061222132924145553503741366889427581661763084
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.67226991203463134414065354605985093029699294732060019972311892635728800061805
Short name T343
Test name
Test status
Simulation time 1000664381 ps
CPU time 2.01 seconds
Started Nov 22 01:49:15 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 193332 kb
Host smart-5d68f762-8ed4-4cae-8c16-2451355df1db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67226991203463134414065354605985093029699294732060019972311892635728800061805
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_same_csr_outstanding.67226991203463134414065354605985093029699294732060
019972311892635728800061805
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.45357512882722656160541408099466666916897660217889204175309149460699999848147
Short name T55
Test name
Test status
Simulation time 462972254 ps
CPU time 1.51 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 198540 kb
Host smart-50103a5f-145f-48cf-a403-c2852a55f640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45357512882722656160541408099466666916897660217889204175309149460699999848147 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.45357512882722656160541408099466666916897660217889204175309149460699999848147
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.88054946529852458849845538118933327031732817142149546931918644343067356904211
Short name T333
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.23 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 197504 kb
Host smart-c1dfe591-e0a6-4217-940b-f18843f4553f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88054946529852458849845538118933327031732817142149546931918644343067356904211 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_intg_err.88054946529852458849845538118933327031732817142149546931918644343067356904211
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.5116456328547466769789915148521439098275169276690702448633518122482795840964
Short name T416
Test name
Test status
Simulation time 453115190 ps
CPU time 0.97 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 194848 kb
Host smart-391d8466-1080-497b-94bb-6e6dd938c8f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5116456328547466769789915148521439098275169
276690702448633518122482795840964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.5116456328
547466769789915148521439098275169276690702448633518122482795840964
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.10026808340460205299506190695888802774117780790816739450394774428472171652879
Short name T315
Test name
Test status
Simulation time 418151184 ps
CPU time 0.96 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:24 PM PST 23
Peak memory 183904 kb
Host smart-3e432616-bb36-4776-a88f-430160d21caa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026808340460205299506190695888802774117780790816739450394774428472171652879 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.10026808340460205299506190695888802774117780790816739450394774428472171652879
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.99710359533312616984482110811709927072623224980090754159907831075506719713838
Short name T324
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 183920 kb
Host smart-11a61084-0e41-4faa-97f3-b30255814b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99710359533312616984482110811709927072623224980090754159907831075506719713838 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.99710359533312616984482110811709927072623224980090754159907831075506719713838
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4031559345092818110022066029265540855391621026190161452448163617350792951525
Short name T382
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.95 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 193400 kb
Host smart-ec345377-6228-41f0-a016-cdd848832eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031559345092818110022066029265540855391621026190161452448163617350792951525 -
assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_same_csr_outstanding.403155934509281811002206602926554085539162102619016
1452448163617350792951525
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.31517645465938291186367274176593061083900858330458209728129412803146159494808
Short name T390
Test name
Test status
Simulation time 462972254 ps
CPU time 1.47 seconds
Started Nov 22 01:49:21 PM PST 23
Finished Nov 22 01:49:24 PM PST 23
Peak memory 198512 kb
Host smart-8825ef4f-a57d-498a-a6b2-b773966f9fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517645465938291186367274176593061083900858330458209728129412803146159494808 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.31517645465938291186367274176593061083900858330458209728129412803146159494808
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.27719165991133778644182470967637757757951218407759261921856975624663661372621
Short name T358
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.2 seconds
Started Nov 22 01:49:14 PM PST 23
Finished Nov 22 01:49:21 PM PST 23
Peak memory 197504 kb
Host smart-b84814ac-0833-4e69-983a-95d52d6c7e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719165991133778644182470967637757757951218407759261921856975624663661372621 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_intg_err.27719165991133778644182470967637757757951218407759261921856975624663661372621
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.21977632584835355905801580949632017820960882381816964559345931778112197467634
Short name T314
Test name
Test status
Simulation time 453115190 ps
CPU time 0.97 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 194808 kb
Host smart-872a2859-6329-4db3-a1d2-686dfbd5067f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197763258483535590580158094963201782096088
2381816964559345931778112197467634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.219776325
84835355905801580949632017820960882381816964559345931778112197467634
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.113938957910885261216449629079243476397536818028989406152544294348095675982137
Short name T354
Test name
Test status
Simulation time 418151184 ps
CPU time 0.99 seconds
Started Nov 22 01:49:12 PM PST 23
Finished Nov 22 01:49:14 PM PST 23
Peak memory 183900 kb
Host smart-ca661329-0f6f-4df5-9525-08c9cf538b17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113938957910885261216449629079243476397536818028989406152544294348095675982137 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.113938957910885261216449629079243476397536818028989406152544294348095675982137
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.56039516727339160544788855610751708619490335697758665102141275000090311540459
Short name T31
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:14 PM PST 23
Finished Nov 22 01:49:17 PM PST 23
Peak memory 183928 kb
Host smart-3566f76b-75c7-44cb-8fe7-fada9cb8b2ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56039516727339160544788855610751708619490335697758665102141275000090311540459 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.56039516727339160544788855610751708619490335697758665102141275000090311540459
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.90683217458905051829865213824971133765371607183914008150510823426931699390903
Short name T5
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.94 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 193452 kb
Host smart-fd14c337-0256-4906-9126-03bbd8600181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90683217458905051829865213824971133765371607183914008150510823426931699390903
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_same_csr_outstanding.90683217458905051829865213824971133765371607183914
008150510823426931699390903
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.42042789872845633471306033787218235840306101386231047108107816296262659136767
Short name T53
Test name
Test status
Simulation time 462972254 ps
CPU time 1.48 seconds
Started Nov 22 01:49:13 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 198552 kb
Host smart-72bc2f32-4b1c-4e5f-bad8-43672066d333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42042789872845633471306033787218235840306101386231047108107816296262659136767 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.42042789872845633471306033787218235840306101386231047108107816296262659136767
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.94054442670241144400064417191725360212714419134420099845401362054519668500271
Short name T361
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.2 seconds
Started Nov 22 01:49:13 PM PST 23
Finished Nov 22 01:49:19 PM PST 23
Peak memory 197476 kb
Host smart-4dd4b324-16da-4e1d-bdfe-8e8ef0c5a100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94054442670241144400064417191725360212714419134420099845401362054519668500271 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_intg_err.94054442670241144400064417191725360212714419134420099845401362054519668500271
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.63862218423207986648692425540134647263673590198535677628733665026765520597068
Short name T321
Test name
Test status
Simulation time 453115190 ps
CPU time 1.01 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:22 PM PST 23
Peak memory 194924 kb
Host smart-21c3c0d6-984b-4818-907b-9e2d54f01dd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6386221842320798664869242554013464726367359
0198535677628733665026765520597068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.638622184
23207986648692425540134647263673590198535677628733665026765520597068
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.51595804720899669366248653668609841195754026639474782863407598740442662666521
Short name T64
Test name
Test status
Simulation time 418151184 ps
CPU time 0.95 seconds
Started Nov 22 01:49:15 PM PST 23
Finished Nov 22 01:49:17 PM PST 23
Peak memory 183952 kb
Host smart-a7ca7843-d6e1-4bc8-9bc4-f4740cf1b41c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51595804720899669366248653668609841195754026639474782863407598740442662666521 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.51595804720899669366248653668609841195754026639474782863407598740442662666521
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.46003444780102554503959928567622852740974840871999664413838733786961369869667
Short name T422
Test name
Test status
Simulation time 396151360 ps
CPU time 0.98 seconds
Started Nov 22 01:49:17 PM PST 23
Finished Nov 22 01:49:19 PM PST 23
Peak memory 183860 kb
Host smart-378c9066-e2c4-40d3-a12c-7070c4e3ac5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46003444780102554503959928567622852740974840871999664413838733786961369869667 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.46003444780102554503959928567622852740974840871999664413838733786961369869667
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.38007053856797866189276009363256436735494154701591179192475878720023601436949
Short name T421
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.91 seconds
Started Nov 22 01:49:12 PM PST 23
Finished Nov 22 01:49:15 PM PST 23
Peak memory 193388 kb
Host smart-c7d33279-d9a2-4369-a3db-8f3ba36073f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007053856797866189276009363256436735494154701591179192475878720023601436949
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_same_csr_outstanding.38007053856797866189276009363256436735494154701591
179192475878720023601436949
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.107813406495578944114557041471326834238538772951684723125838465754227857052020
Short name T345
Test name
Test status
Simulation time 462972254 ps
CPU time 1.48 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 198568 kb
Host smart-a224419d-2a1e-462d-974c-22be4b2f595e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107813406495578944114557041471326834238538772951684723125838465754227857052020 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.107813406495578944114557041471326834238538772951684723125838465754227857052020
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.78775026210735120254593899728355962524404042791805624105472113033739572530403
Short name T346
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.22 seconds
Started Nov 22 01:49:13 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 197376 kb
Host smart-edcde1a4-2712-49fc-a291-cbd9e84ee582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78775026210735120254593899728355962524404042791805624105472113033739572530403 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_intg_err.78775026210735120254593899728355962524404042791805624105472113033739572530403
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.82990457855938286735085588843821122741121547619006363575225354071405191563790
Short name T372
Test name
Test status
Simulation time 502489795 ps
CPU time 1.12 seconds
Started Nov 22 01:49:31 PM PST 23
Finished Nov 22 01:49:36 PM PST 23
Peak memory 183924 kb
Host smart-683a7fc6-e913-4d9b-aa09-952f8ac3e472
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82990457855938286735085588843821122741121547619006363575225354071405191563790 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_aliasing.82990457855938286735085588843821122741121547619006363575225354071405191563790
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.29568011980265450690143105922071165100533374622112117020018043288211126869420
Short name T303
Test name
Test status
Simulation time 6157569554 ps
CPU time 10.32 seconds
Started Nov 22 01:49:07 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 194460 kb
Host smart-09666d3c-f3b6-4457-914b-4bd4bfdd2075
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29568011980265450690143105922071165100533374622112117020018043288211126869420 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bit_bash.29568011980265450690143105922071165100533374622112117020018043288211126869420
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.46195552721810129425985014871593159596765668799868554900748134042798512206035
Short name T356
Test name
Test status
Simulation time 775862608 ps
CPU time 1.23 seconds
Started Nov 22 01:49:34 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 183908 kb
Host smart-047c2a2a-329c-4d94-a96b-2effcbd62112
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46195552721810129425985014871593159596765668799868554900748134042798512206035 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw_reset.46195552721810129425985014871593159596765668799868554900748134042798512206035
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.52806468312548818997675056928583524183969871472212132730265247059819943019381
Short name T398
Test name
Test status
Simulation time 453115190 ps
CPU time 1.01 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:32 PM PST 23
Peak memory 194900 kb
Host smart-707bccba-ca33-4789-a051-ce505df66ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5280646831254881899767505692858352418396987
1472212132730265247059819943019381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.5280646831
2548818997675056928583524183969871472212132730265247059819943019381
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.89791175592154538015519619059775548130763006782342935158702555451712143369556
Short name T301
Test name
Test status
Simulation time 418151184 ps
CPU time 0.98 seconds
Started Nov 22 01:49:09 PM PST 23
Finished Nov 22 01:49:11 PM PST 23
Peak memory 183920 kb
Host smart-11e677ef-c89b-4f2c-ade1-e2fbe0fda1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89791175592154538015519619059775548130763006782342935158702555451712143369556 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.89791175592154538015519619059775548130763006782342935158702555451712143369556
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.115213801144322772904869089631023790253632784540138838262920936535735767615794
Short name T388
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:10 PM PST 23
Finished Nov 22 01:49:12 PM PST 23
Peak memory 184036 kb
Host smart-6d5e039d-b38f-4b08-9acc-095ce2522bcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115213801144322772904869089631023790253632784540138838262920936535735767615794 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.115213801144322772904869089631023790253632784540138838262920936535735767615794
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.97939156597322261969992732094688694249149033319811986263952884976146093344463
Short name T397
Test name
Test status
Simulation time 397008496 ps
CPU time 0.88 seconds
Started Nov 22 01:49:17 PM PST 23
Finished Nov 22 01:49:20 PM PST 23
Peak memory 183868 kb
Host smart-6bb9229c-6a42-40cc-8c8b-32a01212fcf9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97939156597322261969992732094688694249149033319811986263952884976146093344463 -a
ssert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_partial_access.9793915659732226196999273209468869424914903331981198626
3952884976146093344463
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.105535466682497685180503876122999361430304082746569700594933811024317662543879
Short name T391
Test name
Test status
Simulation time 397008496 ps
CPU time 0.86 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 183888 kb
Host smart-2446ed71-9ef8-4752-a121-05b2dcd6c06e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105535466682497685180503876122999361430304082746569700594933811024317662543879 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_walk.105535466682497685180503876122999361430304082746569700594933811024317662543879
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.5675794120902945764273026577973371747796768829251388178309754905758582695292
Short name T389
Test name
Test status
Simulation time 1000664381 ps
CPU time 2.03 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:19 PM PST 23
Peak memory 193364 kb
Host smart-53407ae2-11f8-472f-8a9a-16c676d19eb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5675794120902945764273026577973371747796768829251388178309754905758582695292 -
assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_same_csr_outstanding.5675794120902945764273026577973371747796768829251388
178309754905758582695292
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.84268247806151475175967146257625892891153683239292721853002018296957729400898
Short name T305
Test name
Test status
Simulation time 462972254 ps
CPU time 1.49 seconds
Started Nov 22 01:49:15 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 198480 kb
Host smart-ccf11437-a0fe-44bb-bf8f-fc0ebfcc6ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84268247806151475175967146257625892891153683239292721853002018296957729400898 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.84268247806151475175967146257625892891153683239292721853002018296957729400898
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.27422830389043093532568695509928502064037362690871518586727212478484146332908
Short name T72
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.2 seconds
Started Nov 22 01:48:53 PM PST 23
Finished Nov 22 01:49:00 PM PST 23
Peak memory 197444 kb
Host smart-a8f11cbc-cb38-4e69-8ce8-8e63ad5f54c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422830389043093532568695509928502064037362690871518586727212478484146332908 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_intg_err.27422830389043093532568695509928502064037362690871518586727212478484146332908
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.31918480565984474156460997095293033970115869172541961831854119950092598936966
Short name T32
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:10 PM PST 23
Finished Nov 22 01:49:11 PM PST 23
Peak memory 183900 kb
Host smart-61eb9bef-b16a-44e7-b922-0dfb297d84a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918480565984474156460997095293033970115869172541961831854119950092598936966 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.31918480565984474156460997095293033970115869172541961831854119950092598936966
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.65249054802602127039608413914042582539128928802825568781170448732921781664161
Short name T401
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:33 PM PST 23
Finished Nov 22 01:49:39 PM PST 23
Peak memory 183880 kb
Host smart-70e623f0-3f51-4288-87f3-c22486e59e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65249054802602127039608413914042582539128928802825568781170448732921781664161 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.65249054802602127039608413914042582539128928802825568781170448732921781664161
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.108550883187736922583420048520670494007894854177520903768049399492595629821453
Short name T355
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 183904 kb
Host smart-1f44b4df-c85d-433d-bc9f-19a6dac48eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108550883187736922583420048520670494007894854177520903768049399492595629821453 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.108550883187736922583420048520670494007894854177520903768049399492595629821453
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.72239723784583840453510715868352643435046003879609391074949904261534705751185
Short name T344
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:21 PM PST 23
Finished Nov 22 01:49:23 PM PST 23
Peak memory 183892 kb
Host smart-3929b712-041a-4f0b-84ba-290591201288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72239723784583840453510715868352643435046003879609391074949904261534705751185 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.72239723784583840453510715868352643435046003879609391074949904261534705751185
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.94741558619849844123944068444425602589598250685167046197088460175058172215108
Short name T406
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:21 PM PST 23
Finished Nov 22 01:49:23 PM PST 23
Peak memory 183864 kb
Host smart-d6e65cfa-25ae-49f0-b5c4-9c992701283b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94741558619849844123944068444425602589598250685167046197088460175058172215108 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.94741558619849844123944068444425602589598250685167046197088460175058172215108
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.45775909677696705519590115627865318934904388426623702755140747856712810857674
Short name T430
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:16 PM PST 23
Finished Nov 22 01:49:18 PM PST 23
Peak memory 183856 kb
Host smart-52d61d7d-aaf4-465f-a26a-a704cfdd7c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45775909677696705519590115627865318934904388426623702755140747856712810857674 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.45775909677696705519590115627865318934904388426623702755140747856712810857674
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.57960656128780044415294962509174470966451683569425589931475466355701044670710
Short name T380
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 183888 kb
Host smart-2e5c8351-2d2a-4d24-83f2-edf4f945e311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57960656128780044415294962509174470966451683569425589931475466355701044670710 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.57960656128780044415294962509174470966451683569425589931475466355701044670710
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.86030381663905804553391000475081642499071144901462565846040393899785819278031
Short name T409
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:25 PM PST 23
Finished Nov 22 01:49:28 PM PST 23
Peak memory 183844 kb
Host smart-db838f8b-ec8b-471e-93c1-cb0ccd77e4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86030381663905804553391000475081642499071144901462565846040393899785819278031 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.86030381663905804553391000475081642499071144901462565846040393899785819278031
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.92210823991182656593211503644133831276743551032347840691883662116707549358154
Short name T412
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 183884 kb
Host smart-a281008b-e382-4052-9ae2-288725c7cb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92210823991182656593211503644133831276743551032347840691883662116707549358154 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.92210823991182656593211503644133831276743551032347840691883662116707549358154
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.76887770467321572225744214823984954974833527627717830239797556707824643225105
Short name T420
Test name
Test status
Simulation time 396151360 ps
CPU time 0.92 seconds
Started Nov 22 01:49:24 PM PST 23
Finished Nov 22 01:49:27 PM PST 23
Peak memory 183908 kb
Host smart-0b4fa98c-c9e3-4ed5-82d0-8902e79dd5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76887770467321572225744214823984954974833527627717830239797556707824643225105 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.76887770467321572225744214823984954974833527627717830239797556707824643225105
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.7727978431689823241106396789907939718784526915153021454169318816425183989642
Short name T60
Test name
Test status
Simulation time 6157569554 ps
CPU time 10.46 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:44 PM PST 23
Peak memory 194428 kb
Host smart-e0dffca8-b45a-4898-9618-5da41b53f0db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7727978431689823241106396789907939718784526915153021454169318816425183989642 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bit_bash.7727978431689823241106396789907939718784526915153021454169318816425183989642
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.105007583137182000980450423973575403906186559457817558415320244668552529468973
Short name T63
Test name
Test status
Simulation time 775862608 ps
CPU time 1.25 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 183932 kb
Host smart-f58d7c0f-9df1-4f78-813b-11f6cfa369c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105007583137182000980450423973575403906186559457817558415320244668552529468973 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw_reset.105007583137182000980450423973575403906186559457817558415320244668552529468973
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.9161094169873022506325933181868178514765813054500682803586432781064374227406
Short name T429
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:48:56 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 194860 kb
Host smart-07d6bc70-df57-4521-9a18-68166cd95770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9161094169873022506325933181868178514765813
054500682803586432781064374227406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.91610941698
73022506325933181868178514765813054500682803586432781064374227406
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.1741496401199131586586602660801560186702219796583709944242858843625623747405
Short name T394
Test name
Test status
Simulation time 418151184 ps
CPU time 0.93 seconds
Started Nov 22 01:49:37 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 183812 kb
Host smart-6dc9b0b2-ecff-4d9c-9b17-8695b30c0991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741496401199131586586602660801560186702219796583709944242858843625623747405 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.1741496401199131586586602660801560186702219796583709944242858843625623747405
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.90822001026287033473609409201441079189186486506518121401244250635745348175063
Short name T403
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:27 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 183900 kb
Host smart-b0a9fafe-a03d-47fb-b2a6-a4b142847cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90822001026287033473609409201441079189186486506518121401244250635745348175063 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.90822001026287033473609409201441079189186486506518121401244250635745348175063
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.90729876814958073569866156706662871061989294362713060302309660507559835351633
Short name T14
Test name
Test status
Simulation time 397008496 ps
CPU time 0.87 seconds
Started Nov 22 01:49:26 PM PST 23
Finished Nov 22 01:49:29 PM PST 23
Peak memory 183940 kb
Host smart-9bab8ef3-9cb9-4c9b-b577-50fca0e0f7d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90729876814958073569866156706662871061989294362713060302309660507559835351633 -a
ssert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_partial_access.9072987681495807356986615670666287106198929436271306030
2309660507559835351633
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.81921307739432370423429954980305758244984498961802386803267359366192088736080
Short name T302
Test name
Test status
Simulation time 397008496 ps
CPU time 0.86 seconds
Started Nov 22 01:49:21 PM PST 23
Finished Nov 22 01:49:23 PM PST 23
Peak memory 183940 kb
Host smart-6875ebc8-845a-40a6-bb2c-551323ff52e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81921307739432370423429954980305758244984498961802386803267359366192088736080 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_walk.81921307739432370423429954980305758244984498961802386803267359366192088736080
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.18648179848871524417030340166427331792860022198728095754633253016927687853779
Short name T381
Test name
Test status
Simulation time 1000664381 ps
CPU time 2.02 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 193396 kb
Host smart-d72577d8-782b-4c2a-a77f-d416ccd88a49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648179848871524417030340166427331792860022198728095754633253016927687853779
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_same_csr_outstanding.186481798488715244170303401664273317928600221987280
95754633253016927687853779
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.8038215378574797077693384252403882603953176446988433505320577327317684109092
Short name T6
Test name
Test status
Simulation time 462972254 ps
CPU time 1.53 seconds
Started Nov 22 01:49:20 PM PST 23
Finished Nov 22 01:49:23 PM PST 23
Peak memory 198564 kb
Host smart-4899b4fe-b512-49d7-a2a6-17c9a70ca05f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8038215378574797077693384252403882603953176446988433505320577327317684109092 -assert nopostproc +UV
M_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.8038215378574797077693384252403882603953176446988433505320577327317684109092
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.6899693301775275456546575722602216422488242944802416342440104208984571240667
Short name T363
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.2 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 197476 kb
Host smart-9d545b11-cd9d-4e88-8247-f7101397226c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6899693301775275456546575722602216422488242944802416342440104208984571240667 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_intg_err.6899693301775275456546575722602216422488242944802416342440104208984571240667
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.94761724240290880857816782256989982904983374656811507469911414243797468126255
Short name T307
Test name
Test status
Simulation time 396151360 ps
CPU time 0.96 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:24 PM PST 23
Peak memory 183892 kb
Host smart-51b03bf6-a74a-46e1-939c-b0a994c9d7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94761724240290880857816782256989982904983374656811507469911414243797468126255 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.94761724240290880857816782256989982904983374656811507469911414243797468126255
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.108720234132905240284049016874335243049494077918882761897229249928439221499364
Short name T384
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:24 PM PST 23
Peak memory 183868 kb
Host smart-4f0b0493-1119-469a-a3a3-ae7c5771e007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108720234132905240284049016874335243049494077918882761897229249928439221499364 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.108720234132905240284049016874335243049494077918882761897229249928439221499364
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.64197786554545906145186482314815922902110071567750743214415628354286951000102
Short name T368
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:27 PM PST 23
Finished Nov 22 01:49:30 PM PST 23
Peak memory 183844 kb
Host smart-40e40c2a-9ef2-4f13-a7a3-5f548a4012ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64197786554545906145186482314815922902110071567750743214415628354286951000102 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.64197786554545906145186482314815922902110071567750743214415628354286951000102
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.49613999082852690115865399925381668772832406270040056425942328624755527855106
Short name T313
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:28 PM PST 23
Finished Nov 22 01:49:32 PM PST 23
Peak memory 183968 kb
Host smart-6eae8906-672b-4aa4-8022-82280cea2097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49613999082852690115865399925381668772832406270040056425942328624755527855106 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.49613999082852690115865399925381668772832406270040056425942328624755527855106
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.111696367357056701617014634835144131458141914239619174878997330781215317597184
Short name T367
Test name
Test status
Simulation time 396151360 ps
CPU time 0.93 seconds
Started Nov 22 01:49:18 PM PST 23
Finished Nov 22 01:49:21 PM PST 23
Peak memory 183896 kb
Host smart-7fb40593-1bbc-4179-b08e-0b96dfb862ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111696367357056701617014634835144131458141914239619174878997330781215317597184 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.111696367357056701617014634835144131458141914239619174878997330781215317597184
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.112642993344423826135733669312195519781307006001570756084123454976155950734635
Short name T404
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:29 PM PST 23
Finished Nov 22 01:49:33 PM PST 23
Peak memory 183860 kb
Host smart-484ef6b9-0216-45ba-b922-9c2f6f03ae43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112642993344423826135733669312195519781307006001570756084123454976155950734635 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.112642993344423826135733669312195519781307006001570756084123454976155950734635
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.33457787167704378489459997573536996887135325153157413218396595117432083796119
Short name T334
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:32 PM PST 23
Finished Nov 22 01:49:38 PM PST 23
Peak memory 183836 kb
Host smart-23a3fef5-d492-4de1-be70-40b854f6908a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457787167704378489459997573536996887135325153157413218396595117432083796119 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.33457787167704378489459997573536996887135325153157413218396595117432083796119
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.91134547219112690547506908854218337908807130493160061177498004559451378933764
Short name T392
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:42 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 184012 kb
Host smart-7ae4ab19-fa50-4bc4-aaaf-2023cabdef89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91134547219112690547506908854218337908807130493160061177498004559451378933764 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.91134547219112690547506908854218337908807130493160061177498004559451378933764
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.114047220630548068531382670986548319243666415350894410584783606086678865305412
Short name T308
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:50:01 PM PST 23
Finished Nov 22 01:50:05 PM PST 23
Peak memory 183868 kb
Host smart-77a19594-f780-4471-9e18-65be66d07093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114047220630548068531382670986548319243666415350894410584783606086678865305412 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.114047220630548068531382670986548319243666415350894410584783606086678865305412
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.33051104875534902229671646739094992776847583388143627851620733924238146531399
Short name T8
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:43 PM PST 23
Finished Nov 22 01:49:45 PM PST 23
Peak memory 183888 kb
Host smart-f56ff498-a2bc-4e57-b99b-c01d4e982d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33051104875534902229671646739094992776847583388143627851620733924238146531399 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.33051104875534902229671646739094992776847583388143627851620733924238146531399
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.79736094775337901128270540651088379920187595792501182011341093827183898466734
Short name T428
Test name
Test status
Simulation time 502489795 ps
CPU time 1.12 seconds
Started Nov 22 01:48:51 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 183896 kb
Host smart-25ab4c51-bfc9-444a-939b-851163bce610
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79736094775337901128270540651088379920187595792501182011341093827183898466734 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_aliasing.79736094775337901128270540651088379920187595792501182011341093827183898466734
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.36063052371362698665050944731904149511034905422534300584159798689819474338043
Short name T310
Test name
Test status
Simulation time 6157569554 ps
CPU time 10.39 seconds
Started Nov 22 01:48:54 PM PST 23
Finished Nov 22 01:49:07 PM PST 23
Peak memory 194544 kb
Host smart-3f195a41-fe1d-49da-a21b-2869ad6ca97e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063052371362698665050944731904149511034905422534300584159798689819474338043 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bit_bash.36063052371362698665050944731904149511034905422534300584159798689819474338043
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.75488390099141957980993864407242073010912697339841770251772361907284510915736
Short name T375
Test name
Test status
Simulation time 775862608 ps
CPU time 1.32 seconds
Started Nov 22 01:48:47 PM PST 23
Finished Nov 22 01:48:53 PM PST 23
Peak memory 183916 kb
Host smart-8a313678-cadc-45e3-85c9-2865873c2aba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75488390099141957980993864407242073010912697339841770251772361907284510915736 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_reset.75488390099141957980993864407242073010912697339841770251772361907284510915736
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.93797409785839481166516207123229402548220569234505933988785933949718137169420
Short name T326
Test name
Test status
Simulation time 453115190 ps
CPU time 0.99 seconds
Started Nov 22 01:49:04 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 194804 kb
Host smart-79a03707-c0e9-473e-9d4a-92b0ed258fa6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9379740978583948116651620712322940254822056
9234505933988785933949718137169420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.9379740978
5839481166516207123229402548220569234505933988785933949718137169420
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.64430433439397129297426206581887414836450768279738378631193114078233017992840
Short name T11
Test name
Test status
Simulation time 418151184 ps
CPU time 0.95 seconds
Started Nov 22 01:48:57 PM PST 23
Finished Nov 22 01:49:00 PM PST 23
Peak memory 183872 kb
Host smart-a8653639-c04d-46c5-8de7-df2875fed66d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64430433439397129297426206581887414836450768279738378631193114078233017992840 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.64430433439397129297426206581887414836450768279738378631193114078233017992840
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.5773899498128275579107425141716193324556754502025605041545695556796292188738
Short name T379
Test name
Test status
Simulation time 396151360 ps
CPU time 0.91 seconds
Started Nov 22 01:48:53 PM PST 23
Finished Nov 22 01:48:57 PM PST 23
Peak memory 183904 kb
Host smart-d04443b0-c6c5-4e22-bcb7-8607c3f8dc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5773899498128275579107425141716193324556754502025605041545695556796292188738 -assert nopostproc +UV
M_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.5773899498128275579107425141716193324556754502025605041545695556796292188738
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.466568630016592848582734719433830622138793424895424272510563242246568854843
Short name T17
Test name
Test status
Simulation time 397008496 ps
CPU time 0.88 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:03 PM PST 23
Peak memory 183908 kb
Host smart-7c4b7925-1b5e-4384-9191-ea8f55365725
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466568630016592848582734719433830622138793424895424272510563242246568854843 -ass
ert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_partial_access.466568630016592848582734719433830622138793424895424272510
563242246568854843
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.42313630183893599475358794874950867083091975368468308611738242601954972678363
Short name T371
Test name
Test status
Simulation time 397008496 ps
CPU time 0.88 seconds
Started Nov 22 01:48:48 PM PST 23
Finished Nov 22 01:48:53 PM PST 23
Peak memory 183788 kb
Host smart-74176d9c-0b10-4949-b2bb-e9f517086f9b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42313630183893599475358794874950867083091975368468308611738242601954972678363 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_walk.42313630183893599475358794874950867083091975368468308611738242601954972678363
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.58488213484375889349182228693302650963496711951856967031470219598605957621069
Short name T67
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.91 seconds
Started Nov 22 01:48:49 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 193428 kb
Host smart-79748797-dd75-4d53-91bc-27a6e1795ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58488213484375889349182228693302650963496711951856967031470219598605957621069
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_same_csr_outstanding.584882134843758893491822286933026509634967119518569
67031470219598605957621069
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.15568805746107645616813598049360534731039055751241942990525387351365011807795
Short name T378
Test name
Test status
Simulation time 462972254 ps
CPU time 1.51 seconds
Started Nov 22 01:48:50 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 198696 kb
Host smart-869caf54-45c5-4b8e-a76b-761cb62ec10e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15568805746107645616813598049360534731039055751241942990525387351365011807795 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.15568805746107645616813598049360534731039055751241942990525387351365011807795
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.67210754401241476814797761191394720950894062852088842491229354207290178586923
Short name T400
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.18 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:10 PM PST 23
Peak memory 197464 kb
Host smart-afa5a53e-1be6-4e83-9b63-859945e294cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67210754401241476814797761191394720950894062852088842491229354207290178586923 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_intg_err.67210754401241476814797761191394720950894062852088842491229354207290178586923
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3351127717139328837096965367571945590949184033862245169010294688519147552580
Short name T74
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:35 PM PST 23
Finished Nov 22 01:49:41 PM PST 23
Peak memory 183884 kb
Host smart-9a7fff3e-5f65-4ed7-995a-5484ea9c3e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351127717139328837096965367571945590949184033862245169010294688519147552580 -assert nopostproc +UV
M_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3351127717139328837096965367571945590949184033862245169010294688519147552580
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.111856711837936922152993589092120326827787410919677741792105651234995843387716
Short name T365
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:19 PM PST 23
Finished Nov 22 01:49:21 PM PST 23
Peak memory 183920 kb
Host smart-87ca3c85-85fc-4368-99e5-57d66b61e014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111856711837936922152993589092120326827787410919677741792105651234995843387716 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.111856711837936922152993589092120326827787410919677741792105651234995843387716
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1605014247241943600566607390199780244973847114639617711059214786763369988224
Short name T34
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:08 PM PST 23
Finished Nov 22 01:49:10 PM PST 23
Peak memory 183864 kb
Host smart-1c507534-8dca-44f7-ba9c-3a7ab5399738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605014247241943600566607390199780244973847114639617711059214786763369988224 -assert nopostproc +UV
M_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1605014247241943600566607390199780244973847114639617711059214786763369988224
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.59931366326015291273001380673956126277522633460607418733176240432094240653044
Short name T304
Test name
Test status
Simulation time 396151360 ps
CPU time 0.85 seconds
Started Nov 22 01:49:22 PM PST 23
Finished Nov 22 01:49:25 PM PST 23
Peak memory 184000 kb
Host smart-4fa328ce-8932-49ea-a080-45bc04632a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59931366326015291273001380673956126277522633460607418733176240432094240653044 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.59931366326015291273001380673956126277522633460607418733176240432094240653044
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.102514165502126610893309881657607088433798747474623941482790801322657648380808
Short name T337
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:46 PM PST 23
Finished Nov 22 01:49:48 PM PST 23
Peak memory 183912 kb
Host smart-6ead20f7-5f66-477e-badf-92553ee2dcaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102514165502126610893309881657607088433798747474623941482790801322657648380808 -assert nopostproc +
UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.102514165502126610893309881657607088433798747474623941482790801322657648380808
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.98483615862967400219526311314914163463014840238182806938414412808194018397055
Short name T348
Test name
Test status
Simulation time 396151360 ps
CPU time 0.91 seconds
Started Nov 22 01:49:48 PM PST 23
Finished Nov 22 01:49:50 PM PST 23
Peak memory 183924 kb
Host smart-84027413-f440-4c92-8681-62cce5400c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98483615862967400219526311314914163463014840238182806938414412808194018397055 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.98483615862967400219526311314914163463014840238182806938414412808194018397055
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.91308762849854939877242679872533743551729541367110165042424649649611906739593
Short name T332
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:39 PM PST 23
Finished Nov 22 01:49:42 PM PST 23
Peak memory 183932 kb
Host smart-62326ba1-f34e-4a67-9a14-6db71df7d4bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91308762849854939877242679872533743551729541367110165042424649649611906739593 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.91308762849854939877242679872533743551729541367110165042424649649611906739593
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.35265274390245943637231713813469812180368608963215308124185798544620524714308
Short name T335
Test name
Test status
Simulation time 396151360 ps
CPU time 0.92 seconds
Started Nov 22 01:49:50 PM PST 23
Finished Nov 22 01:49:52 PM PST 23
Peak memory 183980 kb
Host smart-b6d50873-00ce-423c-8cf7-704677b27594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35265274390245943637231713813469812180368608963215308124185798544620524714308 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.35265274390245943637231713813469812180368608963215308124185798544620524714308
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.5997071267118510544571794352085099616109081738371871873618321307264826227219
Short name T320
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:49 PM PST 23
Finished Nov 22 01:49:51 PM PST 23
Peak memory 183980 kb
Host smart-355398d4-f843-4621-a4ec-ea311ac6d4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5997071267118510544571794352085099616109081738371871873618321307264826227219 -assert nopostproc +UV
M_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.5997071267118510544571794352085099616109081738371871873618321307264826227219
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.53906503511148768919142256101282896087277366010128052122872339956428822810042
Short name T16
Test name
Test status
Simulation time 396151360 ps
CPU time 0.87 seconds
Started Nov 22 01:49:30 PM PST 23
Finished Nov 22 01:49:35 PM PST 23
Peak memory 183876 kb
Host smart-2d4d8b67-c875-47d7-8392-0424d0db7bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53906503511148768919142256101282896087277366010128052122872339956428822810042 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.53906503511148768919142256101282896087277366010128052122872339956428822810042
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.64616569675474535332473453874221527701184721718434001088474349432775935859514
Short name T62
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:48:57 PM PST 23
Finished Nov 22 01:49:01 PM PST 23
Peak memory 194840 kb
Host smart-a2f5f1f6-0a2c-4ad8-b51b-49a92eac6818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6461656967547453533247345387422152770118472
1718434001088474349432775935859514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.6461656967
5474535332473453874221527701184721718434001088474349432775935859514
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.70808766632310738203684542320459709068847825618745351610740126322983599502805
Short name T377
Test name
Test status
Simulation time 418151184 ps
CPU time 0.96 seconds
Started Nov 22 01:48:54 PM PST 23
Finished Nov 22 01:48:57 PM PST 23
Peak memory 183780 kb
Host smart-4ba2069d-7d54-45f0-bf5c-cfeb13643307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70808766632310738203684542320459709068847825618745351610740126322983599502805 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.70808766632310738203684542320459709068847825618745351610740126322983599502805
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.46407446135081343743393755538418598922242336311868235946157578390183260493290
Short name T374
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:03 PM PST 23
Peak memory 183892 kb
Host smart-6e9047e3-3780-49c8-8f30-d65a70596d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46407446135081343743393755538418598922242336311868235946157578390183260493290 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.46407446135081343743393755538418598922242336311868235946157578390183260493290
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.115224709986572957454748725356554921086096010278574528171562840801957485016850
Short name T65
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.95 seconds
Started Nov 22 01:48:53 PM PST 23
Finished Nov 22 01:48:57 PM PST 23
Peak memory 193464 kb
Host smart-e6d541cb-148c-4468-8a9e-6b42f5060c21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115224709986572957454748725356554921086096010278574528171562840801957485016850
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_same_csr_outstanding.11522470998657295745474872535655492108609601027857
4528171562840801957485016850
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.36640966685540493192552834374965849803225585694182355592041050219140607500796
Short name T385
Test name
Test status
Simulation time 462972254 ps
CPU time 1.55 seconds
Started Nov 22 01:48:55 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 198548 kb
Host smart-ee920763-5c89-4883-9ec5-cc5ba2bd5b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36640966685540493192552834374965849803225585694182355592041050219140607500796 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.36640966685540493192552834374965849803225585694182355592041050219140607500796
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.61017452826598335753093731997746032380900940464488115496055449609943931077739
Short name T311
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.23 seconds
Started Nov 22 01:48:56 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 197460 kb
Host smart-dac9420f-f7e5-41f2-8c3a-de4e916cf926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61017452826598335753093731997746032380900940464488115496055449609943931077739 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_intg_err.61017452826598335753093731997746032380900940464488115496055449609943931077739
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.78688231432309089076273584670947724797078345810512760387987749010599025522144
Short name T73
Test name
Test status
Simulation time 453115190 ps
CPU time 1 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 194780 kb
Host smart-cda81c87-64cf-4e2d-8b77-2d5b3c464026
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7868823143230908907627358467094772479707834
5810512760387987749010599025522144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.7868823143
2309089076273584670947724797078345810512760387987749010599025522144
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.97297014806326322437463825871948277673435232593940286998950339562972452091715
Short name T300
Test name
Test status
Simulation time 418151184 ps
CPU time 0.96 seconds
Started Nov 22 01:48:52 PM PST 23
Finished Nov 22 01:48:55 PM PST 23
Peak memory 183928 kb
Host smart-7df5d545-7e7f-4270-958c-03a0a6c37f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97297014806326322437463825871948277673435232593940286998950339562972452091715 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.97297014806326322437463825871948277673435232593940286998950339562972452091715
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.45264517946301246979428158365810322134335700298398494970800764703148240443555
Short name T328
Test name
Test status
Simulation time 396151360 ps
CPU time 0.89 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:02 PM PST 23
Peak memory 183836 kb
Host smart-7df92a32-fae9-479a-a670-c926736d8b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45264517946301246979428158365810322134335700298398494970800764703148240443555 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.45264517946301246979428158365810322134335700298398494970800764703148240443555
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.70628698705027883670809098831028768433624400658962957416702814905516007541197
Short name T66
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.92 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:05 PM PST 23
Peak memory 193328 kb
Host smart-a7401698-2c72-40f2-8097-15c76588edd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70628698705027883670809098831028768433624400658962957416702814905516007541197
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_same_csr_outstanding.706286987050278836708090988310287684336244006589629
57416702814905516007541197
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.13917416995142681531168678930212845669877054284467458088777563954024649183606
Short name T395
Test name
Test status
Simulation time 462972254 ps
CPU time 1.59 seconds
Started Nov 22 01:48:55 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 198580 kb
Host smart-937804c6-2323-465b-8674-44f2299695eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13917416995142681531168678930212845669877054284467458088777563954024649183606 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.13917416995142681531168678930212845669877054284467458088777563954024649183606
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.53491627684732434486087125155102943575438089253515500629581881785879569213052
Short name T360
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.27 seconds
Started Nov 22 01:48:53 PM PST 23
Finished Nov 22 01:49:01 PM PST 23
Peak memory 197604 kb
Host smart-c6e9e169-c747-4dfe-b5d5-6602673af678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53491627684732434486087125155102943575438089253515500629581881785879569213052 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_intg_err.53491627684732434486087125155102943575438089253515500629581881785879569213052
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.91692625381871645140599630793220668223342202630349529777079629089870786480086
Short name T52
Test name
Test status
Simulation time 453115190 ps
CPU time 0.99 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 194836 kb
Host smart-12cdc8ee-aad5-4377-8525-70ab55c6a488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9169262538187164514059963079322066822334220
2630349529777079629089870786480086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.9169262538
1871645140599630793220668223342202630349529777079629089870786480086
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.52464078837045369109897234789636925418639829797091820448130659888803184092342
Short name T3
Test name
Test status
Simulation time 418151184 ps
CPU time 0.97 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 183748 kb
Host smart-a2e4ca9d-407a-4046-83d2-9540e77194c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52464078837045369109897234789636925418639829797091820448130659888803184092342 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.52464078837045369109897234789636925418639829797091820448130659888803184092342
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.64062308665145246497145265891638802829296305391564351713079835765272536701605
Short name T386
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:48:54 PM PST 23
Finished Nov 22 01:48:57 PM PST 23
Peak memory 183788 kb
Host smart-c4433c22-2660-450a-850b-736edf8f21b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64062308665145246497145265891638802829296305391564351713079835765272536701605 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.64062308665145246497145265891638802829296305391564351713079835765272536701605
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.74298075566634521986817226454243398484206367243579010154766405686371671417286
Short name T427
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.96 seconds
Started Nov 22 01:49:04 PM PST 23
Finished Nov 22 01:49:07 PM PST 23
Peak memory 193384 kb
Host smart-fc0f5ef0-6e8c-476e-861f-04711dbe32dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74298075566634521986817226454243398484206367243579010154766405686371671417286
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_same_csr_outstanding.742980755666345219868172264542433984842063672435790
10154766405686371671417286
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.91846449660945632085968992515356144914754148593719233392090769530025261725287
Short name T342
Test name
Test status
Simulation time 462972254 ps
CPU time 1.48 seconds
Started Nov 22 01:48:55 PM PST 23
Finished Nov 22 01:48:59 PM PST 23
Peak memory 198548 kb
Host smart-f1ba19a3-bb39-41f9-b07a-908e37b620a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91846449660945632085968992515356144914754148593719233392090769530025261725287 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.91846449660945632085968992515356144914754148593719233392090769530025261725287
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.46438612027330749097951428109027712507933667419053902049858503917664112274976
Short name T12
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.22 seconds
Started Nov 22 01:49:05 PM PST 23
Finished Nov 22 01:49:11 PM PST 23
Peak memory 197456 kb
Host smart-ab4923f9-20e3-4c9d-9232-a404b6c85145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46438612027330749097951428109027712507933667419053902049858503917664112274976 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_intg_err.46438612027330749097951428109027712507933667419053902049858503917664112274976
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.78893710084334202009074589397470607093076048641614240301618586611785318683436
Short name T383
Test name
Test status
Simulation time 453115190 ps
CPU time 1.01 seconds
Started Nov 22 01:49:00 PM PST 23
Finished Nov 22 01:49:02 PM PST 23
Peak memory 194844 kb
Host smart-3e2a5398-204d-44b7-bce8-00a5dd9742fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7889371008433420200907458939747060709307604
8641614240301618586611785318683436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.7889371008
4334202009074589397470607093076048641614240301618586611785318683436
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.83916208707144833357644040677771786093171528093775376458773276262577395683134
Short name T58
Test name
Test status
Simulation time 418151184 ps
CPU time 0.96 seconds
Started Nov 22 01:49:00 PM PST 23
Finished Nov 22 01:49:02 PM PST 23
Peak memory 183908 kb
Host smart-31b7b731-4e78-43bf-824b-f5d3e35643e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83916208707144833357644040677771786093171528093775376458773276262577395683134 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.83916208707144833357644040677771786093171528093775376458773276262577395683134
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.34311024491535683075570091857166127757663063637740034952876156280883949072561
Short name T341
Test name
Test status
Simulation time 396151360 ps
CPU time 0.86 seconds
Started Nov 22 01:49:06 PM PST 23
Finished Nov 22 01:49:08 PM PST 23
Peak memory 183872 kb
Host smart-3251782c-5323-486a-9c4d-d34871dd6098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311024491535683075570091857166127757663063637740034952876156280883949072561 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.34311024491535683075570091857166127757663063637740034952876156280883949072561
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.15708932880314142087492870187781518784052667315416788919616631152076539343666
Short name T349
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.9 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 193424 kb
Host smart-20aa949a-d114-45f2-ac98-f7bcaea6a7a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15708932880314142087492870187781518784052667315416788919616631152076539343666
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_same_csr_outstanding.157089328803141420874928701877815187840526673154167
88919616631152076539343666
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.88621904073259742298382008535080767281080519291295940820909973440914445728398
Short name T419
Test name
Test status
Simulation time 462972254 ps
CPU time 1.49 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:06 PM PST 23
Peak memory 198480 kb
Host smart-2c2d6cb8-a6b9-486f-b9ce-8712e00d6755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88621904073259742298382008535080767281080519291295940820909973440914445728398 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.88621904073259742298382008535080767281080519291295940820909973440914445728398
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.95844804612565269270308359987358881223122639035213539592739895701819542237223
Short name T408
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.29 seconds
Started Nov 22 01:49:03 PM PST 23
Finished Nov 22 01:49:10 PM PST 23
Peak memory 197468 kb
Host smart-be74c495-c75b-46b4-92c7-682fd1da6376
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95844804612565269270308359987358881223122639035213539592739895701819542237223 -assert n
opostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_intg_err.95844804612565269270308359987358881223122639035213539592739895701819542237223
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.93464522361212713727140724067380096983904738195620036897427865591080501939476
Short name T330
Test name
Test status
Simulation time 453115190 ps
CPU time 1.1 seconds
Started Nov 22 01:49:11 PM PST 23
Finished Nov 22 01:49:13 PM PST 23
Peak memory 194832 kb
Host smart-cd8148f6-32f6-4da2-b05f-4c7573fdd34e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9346452236121271372714072406738009698390473
8195620036897427865591080501939476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.9346452236
1212713727140724067380096983904738195620036897427865591080501939476
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.92315201213120077793794436126332251646670170226654506329769390806709268950403
Short name T327
Test name
Test status
Simulation time 418151184 ps
CPU time 0.96 seconds
Started Nov 22 01:49:01 PM PST 23
Finished Nov 22 01:49:03 PM PST 23
Peak memory 183884 kb
Host smart-453c9614-1176-4225-94cd-d944567da027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92315201213120077793794436126332251646670170226654506329769390806709268950403 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.92315201213120077793794436126332251646670170226654506329769390806709268950403
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.68493990827746079280558645472173463109896353701944786881050537397409373546492
Short name T370
Test name
Test status
Simulation time 396151360 ps
CPU time 0.88 seconds
Started Nov 22 01:49:02 PM PST 23
Finished Nov 22 01:49:04 PM PST 23
Peak memory 183984 kb
Host smart-2d183e86-386a-4540-bb2a-9a48e68aaace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68493990827746079280558645472173463109896353701944786881050537397409373546492 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.68493990827746079280558645472173463109896353701944786881050537397409373546492
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.24777907262176621520148877801985050710309271052852455137488371069692428766302
Short name T70
Test name
Test status
Simulation time 1000664381 ps
CPU time 1.91 seconds
Started Nov 22 01:49:05 PM PST 23
Finished Nov 22 01:49:08 PM PST 23
Peak memory 193432 kb
Host smart-f81c33d7-bb2f-4148-845b-2c3d9cdab42f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24777907262176621520148877801985050710309271052852455137488371069692428766302
-assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_same_csr_outstanding.247779072621766215201488778019850507103092710528524
55137488371069692428766302
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.67793703551618224886242379074299917222397713225063862943254841648051560204233
Short name T423
Test name
Test status
Simulation time 462972254 ps
CPU time 1.51 seconds
Started Nov 22 01:48:58 PM PST 23
Finished Nov 22 01:49:01 PM PST 23
Peak memory 198548 kb
Host smart-dacda1c5-7bd1-4d0c-8acb-0af4e2c65c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67793703551618224886242379074299917222397713225063862943254841648051560204233 -assert nopostproc +U
VM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.67793703551618224886242379074299917222397713225063862943254841648051560204233
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.104592907682204482014480163176083219991616533416921768601392383092083238410819
Short name T364
Test name
Test status
Simulation time 4648795910 ps
CPU time 5.19 seconds
Started Nov 22 01:49:05 PM PST 23
Finished Nov 22 01:49:11 PM PST 23
Peak memory 197460 kb
Host smart-a004dc85-85da-4a0d-89cd-ec747cd56356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104592907682204482014480163176083219991616533416921768601392383092083238410819 -assert
nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_intg_err.104592907682204482014480163176083219991616533416921768601392383092083238410819
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.17105640281159017758315746211903978924695758148830282615814371954767926074124
Short name T295
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:07 PM PST 23
Peak memory 183244 kb
Host smart-0dfa1663-6844-49ea-a13e-1557c10c26f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17105640281159017758315746211903978924695758148830282615814371954767926074124 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.aon_timer_jump.17105640281159017758315746211903978924695758148830282615814371954767926074124
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.60061885038777310291338462981566673755634244428709576654639476098809609788767
Short name T199
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.7 seconds
Started Nov 22 01:16:46 PM PST 23
Finished Nov 22 01:17:38 PM PST 23
Peak memory 183288 kb
Host smart-9fb204f1-b587-4c68-b737-234e85684643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60061885038777310291338462981566673755634244428709576654639476098809609788767 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.aon_timer_prescaler.60061885038777310291338462981566673755634244428709576654639476098809609788767
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.31167234439827980885189988615880276912857060995253605380767515449588428166631
Short name T258
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:16:53 PM PST 23
Peak memory 183264 kb
Host smart-581ee2eb-5ea0-4187-94e5-b03469848859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31167234439827980885189988615880276912857060995253605380767515449588428166631 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.aon_timer_smoke.31167234439827980885189988615880276912857060995253605380767515449588428166631
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.112150691696421410629187800203338296157663500956966744272895470281431204606000
Short name T140
Test name
Test status
Simulation time 96759987586 ps
CPU time 422.35 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:23:40 PM PST 23
Peak memory 198104 kb
Host smart-22a42b3b-4359-4b80-a851-2081e03f2bef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112150691696421410629
187800203338296157663500956966744272895470281431204606000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand
_reset.112150691696421410629187800203338296157663500956966744272895470281431204606000
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2274573696752327550525132474358379064516304984299718889102368812212447707803
Short name T129
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:10 PM PST 23
Peak memory 183220 kb
Host smart-37c821fe-6784-4711-b467-73e9d107bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274573696752327550525132474358379064516304984299718889102368812212447707803 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.aon_timer_jump.2274573696752327550525132474358379064516304984299718889102368812212447707803
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.109521004256772083407496885971321136040948371928372590824689874450857110111805
Short name T142
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.9 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:51 PM PST 23
Peak memory 183272 kb
Host smart-e60740b4-281b-4765-b544-11b45ff3dc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109521004256772083407496885971321136040948371928372590824689874450857110111805 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.aon_timer_prescaler.109521004256772083407496885971321136040948371928372590824689874450857110111805
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.96879467191966787003527074051113308464353585951080702241983985968995882950139
Short name T37
Test name
Test status
Simulation time 4270477508 ps
CPU time 4.54 seconds
Started Nov 22 01:16:39 PM PST 23
Finished Nov 22 01:16:45 PM PST 23
Peak memory 215060 kb
Host smart-183bce6d-fb90-4a0d-bb1e-5da29952f205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96879467191966787003527074051113308464353585951080702241983985968995882950139 -assert nopostpro
c +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.96879467191966787003527074051113308464353585951080702241983985968995882950139
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.83585319960432830621891530405019125395882059428912299960272963212927508276532
Short name T23
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:05 PM PST 23
Finished Nov 22 01:17:16 PM PST 23
Peak memory 183256 kb
Host smart-4f6da816-4c0f-471c-b3cd-bf202826a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83585319960432830621891530405019125395882059428912299960272963212927508276532 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.aon_timer_smoke.83585319960432830621891530405019125395882059428912299960272963212927508276532
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.103733944587116223498872700438300481963622901288775181181307052204924463207773
Short name T261
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.21 seconds
Started Nov 22 01:16:34 PM PST 23
Finished Nov 22 01:21:39 PM PST 23
Peak memory 193616 kb
Host smart-d7be20a1-0459-48ea-ab35-a2b8a3a705ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103733944587116223498872700438300481963622901288775181181307052204924463207773 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all.103733944587116223498872700438300481963622901288775181181307052204924463207773
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.77139880121713456414781020934827424298758724750699964618869386842719887469625
Short name T158
Test name
Test status
Simulation time 96759987586 ps
CPU time 425.57 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 198224 kb
Host smart-8e18b8fe-e0ec-4c14-8ac5-8fd48a897339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771398801217134564147
81020934827424298758724750699964618869386842719887469625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_
reset.77139880121713456414781020934827424298758724750699964618869386842719887469625
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.112601639143412080881617491903529448645583430416343192715818049237215064127804
Short name T164
Test name
Test status
Simulation time 474704303 ps
CPU time 1 seconds
Started Nov 22 01:16:54 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183280 kb
Host smart-5fbe9c31-4ba5-48d5-9875-567df8f1ff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112601639143412080881617491903529448645583430416343192715818049237215064127804 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.aon_timer_jump.112601639143412080881617491903529448645583430416343192715818049237215064127804
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.27900015107956862596658730609619561010414814780822342207086554501416951714895
Short name T176
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.62 seconds
Started Nov 22 01:16:55 PM PST 23
Finished Nov 22 01:17:57 PM PST 23
Peak memory 183332 kb
Host smart-81557962-c8b3-43ad-aac1-a9ada797650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27900015107956862596658730609619561010414814780822342207086554501416951714895 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.aon_timer_prescaler.27900015107956862596658730609619561010414814780822342207086554501416951714895
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.88232163639477943125070709123666835336662558695725622697032420962391907175466
Short name T100
Test name
Test status
Simulation time 491168457 ps
CPU time 0.98 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 183144 kb
Host smart-738a01ea-0b2a-4fa1-a2d6-367b2da1ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88232163639477943125070709123666835336662558695725622697032420962391907175466 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.aon_timer_smoke.88232163639477943125070709123666835336662558695725622697032420962391907175466
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.57643359520597880165607104692575282926935005602204234964567019614153251072978
Short name T290
Test name
Test status
Simulation time 332628779192 ps
CPU time 300.85 seconds
Started Nov 22 01:17:11 PM PST 23
Finished Nov 22 01:22:18 PM PST 23
Peak memory 193632 kb
Host smart-8fd0d33f-098a-4fff-a853-8443ebc4cfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57643359520597880165607104692575282926935005602204234964567019614153251072978 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all.57643359520597880165607104692575282926935005602204234964567019614153251072978
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.90111560379574020131814565629760594070179418309683558204094299767436187774858
Short name T133
Test name
Test status
Simulation time 96759987586 ps
CPU time 432.44 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:24:18 PM PST 23
Peak memory 198024 kb
Host smart-64e88701-0821-43dd-ab48-b2a883107df7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901115603795740201318
14565629760594070179418309683558204094299767436187774858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand
_reset.90111560379574020131814565629760594070179418309683558204094299767436187774858
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.6853486240206571982626866577037140876998912267041412733328432600436652158517
Short name T86
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:21 PM PST 23
Finished Nov 22 01:17:25 PM PST 23
Peak memory 183244 kb
Host smart-2e520b4b-2534-4338-8b1c-db7ac1ca8dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6853486240206571982626866577037140876998912267041412733328432600436652158517 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.aon_timer_jump.6853486240206571982626866577037140876998912267041412733328432600436652158517
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.38281418875988800062560122364060653060037154863737518750639840601605058247404
Short name T254
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.35 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 183288 kb
Host smart-feec4177-e212-4fae-8acb-0f134f5e72b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38281418875988800062560122364060653060037154863737518750639840601605058247404 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.aon_timer_prescaler.38281418875988800062560122364060653060037154863737518750639840601605058247404
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.79705034509845597894607337382887758267005558750998971704473771891281676467077
Short name T82
Test name
Test status
Simulation time 491168457 ps
CPU time 0.99 seconds
Started Nov 22 01:17:10 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 183288 kb
Host smart-3db45a18-3aa9-4b86-9558-7ab61580c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79705034509845597894607337382887758267005558750998971704473771891281676467077 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.aon_timer_smoke.79705034509845597894607337382887758267005558750998971704473771891281676467077
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.67404868457886994982387097803787062820071181615831996605589251187734896912417
Short name T200
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.57 seconds
Started Nov 22 01:16:54 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 193632 kb
Host smart-46445626-096b-4ffc-bc59-0537863e5307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67404868457886994982387097803787062820071181615831996605589251187734896912417 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all.67404868457886994982387097803787062820071181615831996605589251187734896912417
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.28737716133837830154870417596534486356283424626068261136720022864504347952830
Short name T93
Test name
Test status
Simulation time 96759987586 ps
CPU time 423.51 seconds
Started Nov 22 01:17:20 PM PST 23
Finished Nov 22 01:24:28 PM PST 23
Peak memory 198188 kb
Host smart-8f54e5fa-0bf8-47ea-a62b-8f3da693a5f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287377161338378301548
70417596534486356283424626068261136720022864504347952830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand
_reset.28737716133837830154870417596534486356283424626068261136720022864504347952830
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.51165347411091753543404841253866497682351448269587549944977006158402012587507
Short name T139
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183264 kb
Host smart-2a09af8d-be8c-45ba-8584-31325561d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51165347411091753543404841253866497682351448269587549944977006158402012587507 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.aon_timer_jump.51165347411091753543404841253866497682351448269587549944977006158402012587507
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.53949885369180894538120588636557892930211289241996746830827235914479750755271
Short name T183
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.62 seconds
Started Nov 22 01:17:20 PM PST 23
Finished Nov 22 01:18:14 PM PST 23
Peak memory 183268 kb
Host smart-5249fb34-3871-4381-ad1b-81880b6e4770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53949885369180894538120588636557892930211289241996746830827235914479750755271 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.aon_timer_prescaler.53949885369180894538120588636557892930211289241996746830827235914479750755271
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.92264099780273917760580193221546644883568886608111511065002138374636545871792
Short name T214
Test name
Test status
Simulation time 491168457 ps
CPU time 1 seconds
Started Nov 22 01:16:55 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183284 kb
Host smart-c641f8e8-3610-46da-a60b-7c46cf163e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92264099780273917760580193221546644883568886608111511065002138374636545871792 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.aon_timer_smoke.92264099780273917760580193221546644883568886608111511065002138374636545871792
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.84434433383571091268003825750657654735369496877648461358484982647658955199181
Short name T272
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.1 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:22:04 PM PST 23
Peak memory 193644 kb
Host smart-57a33116-53c8-47ee-8b51-7f4315ead02e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84434433383571091268003825750657654735369496877648461358484982647658955199181 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all.84434433383571091268003825750657654735369496877648461358484982647658955199181
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.60017563290893450204595715730347661592813234632459088361803911039476238498447
Short name T236
Test name
Test status
Simulation time 96759987586 ps
CPU time 420.52 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:24:07 PM PST 23
Peak memory 198028 kb
Host smart-b4163928-4aad-40b0-ac0d-0e19ee1c52fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600175632908934502045
95715730347661592813234632459088361803911039476238498447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand
_reset.60017563290893450204595715730347661592813234632459088361803911039476238498447
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.38285580895371448902930951138878668571169103390694436839277564113761920622167
Short name T118
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:53 PM PST 23
Finished Nov 22 01:18:03 PM PST 23
Peak memory 183096 kb
Host smart-ce32f71b-12f2-4f29-8d2b-f44967929a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38285580895371448902930951138878668571169103390694436839277564113761920622167 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.aon_timer_jump.38285580895371448902930951138878668571169103390694436839277564113761920622167
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.37972018174046818078852287806778170653622381047143018488147900227781298235174
Short name T157
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.71 seconds
Started Nov 22 01:17:33 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 183228 kb
Host smart-ea9966a7-4af7-476c-84a1-73509c5b5cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37972018174046818078852287806778170653622381047143018488147900227781298235174 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.aon_timer_prescaler.37972018174046818078852287806778170653622381047143018488147900227781298235174
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.112379006575487175265137232531407294695577196475228086265581825644902610838156
Short name T231
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183148 kb
Host smart-e1c34138-41a9-436c-ad67-b4afcd6db0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112379006575487175265137232531407294695577196475228086265581825644902610838156 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.aon_timer_smoke.112379006575487175265137232531407294695577196475228086265581825644902610838156
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.86478093875259907185859285847848183604470674098190129712756603475272608400740
Short name T165
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.36 seconds
Started Nov 22 01:16:59 PM PST 23
Finished Nov 22 01:22:12 PM PST 23
Peak memory 193464 kb
Host smart-f9022e78-fd5b-496b-9672-c512472f3117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86478093875259907185859285847848183604470674098190129712756603475272608400740 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all.86478093875259907185859285847848183604470674098190129712756603475272608400740
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.23590752602295693889812715336602659189438652817156152661053723961465086281739
Short name T277
Test name
Test status
Simulation time 96759987586 ps
CPU time 429.13 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:24:17 PM PST 23
Peak memory 198216 kb
Host smart-0ce215c0-9284-4573-b36f-ee32d273e480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235907526022956938898
12715336602659189438652817156152661053723961465086281739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand
_reset.23590752602295693889812715336602659189438652817156152661053723961465086281739
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.56552888611508558107005554355246189736526670702411529637213328158875274274600
Short name T286
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.59 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:17:56 PM PST 23
Peak memory 183124 kb
Host smart-3e9ede1e-8156-4ffe-9598-ea975b5d4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56552888611508558107005554355246189736526670702411529637213328158875274274600 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.aon_timer_prescaler.56552888611508558107005554355246189736526670702411529637213328158875274274600
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.16775388053587337319981098678081064761437852751768295097238234994494475757846
Short name T84
Test name
Test status
Simulation time 491168457 ps
CPU time 1.03 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:06 PM PST 23
Peak memory 183276 kb
Host smart-d57f234f-eb99-4b4e-999d-1eed8e4c3b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16775388053587337319981098678081064761437852751768295097238234994494475757846 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.aon_timer_smoke.16775388053587337319981098678081064761437852751768295097238234994494475757846
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.49842618607421822680810427412120887232586176696050597902903611277459183655030
Short name T178
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.94 seconds
Started Nov 22 01:17:21 PM PST 23
Finished Nov 22 01:22:27 PM PST 23
Peak memory 193504 kb
Host smart-c61db4ee-e912-4748-b065-a66781625052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49842618607421822680810427412120887232586176696050597902903611277459183655030 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all.49842618607421822680810427412120887232586176696050597902903611277459183655030
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.63421254281810132711390692336400605000647096767608439153723744703076043395912
Short name T162
Test name
Test status
Simulation time 96759987586 ps
CPU time 430.72 seconds
Started Nov 22 01:17:24 PM PST 23
Finished Nov 22 01:24:39 PM PST 23
Peak memory 198040 kb
Host smart-b20cc361-86da-4b68-8981-d563b11dc594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634212542818101327113
90692336400605000647096767608439153723744703076043395912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand
_reset.63421254281810132711390692336400605000647096767608439153723744703076043395912
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.78490050369924790118181822817078588740861587111401057369422857323914190320638
Short name T159
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:11 PM PST 23
Finished Nov 22 01:17:18 PM PST 23
Peak memory 183160 kb
Host smart-a0b9dec9-f73e-47b0-833d-4806450a34f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78490050369924790118181822817078588740861587111401057369422857323914190320638 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.aon_timer_jump.78490050369924790118181822817078588740861587111401057369422857323914190320638
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.94037785906898583244111899542917024165452037804068015656052063624027283062516
Short name T149
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.14 seconds
Started Nov 22 01:17:56 PM PST 23
Finished Nov 22 01:18:52 PM PST 23
Peak memory 183296 kb
Host smart-db11b8a5-0996-46bb-9160-f18396925d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94037785906898583244111899542917024165452037804068015656052063624027283062516 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.aon_timer_prescaler.94037785906898583244111899542917024165452037804068015656052063624027283062516
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.106835086015789376465355663487332976814828726287544134874375660181935287181239
Short name T189
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:17:26 PM PST 23
Peak memory 183312 kb
Host smart-f9b1d946-cb93-4981-9510-3c17352b35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106835086015789376465355663487332976814828726287544134874375660181935287181239 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.aon_timer_smoke.106835086015789376465355663487332976814828726287544134874375660181935287181239
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2824121976927618858394058891759449981686627954440769386712404626673197478509
Short name T117
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.13 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:22:22 PM PST 23
Peak memory 193496 kb
Host smart-9ab931d8-e20b-441b-8ba0-3ca98540ff42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824121976927618858394058891759449981686627954440769386712404626673197478509 -assert nopost
proc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all.2824121976927618858394058891759449981686627954440769386712404626673197478509
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.97389877647260670354923236450855657915141597233238805236947307321073896608239
Short name T232
Test name
Test status
Simulation time 96759987586 ps
CPU time 428.1 seconds
Started Nov 22 01:17:09 PM PST 23
Finished Nov 22 01:24:25 PM PST 23
Peak memory 198180 kb
Host smart-e9845971-38f6-4e9e-a091-2be9b8d5e09e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973898776472606703549
23236450855657915141597233238805236947307321073896608239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand
_reset.97389877647260670354923236450855657915141597233238805236947307321073896608239
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.72728419319581727429174847276827377641196792121066286989825082715671147640165
Short name T151
Test name
Test status
Simulation time 474704303 ps
CPU time 1 seconds
Started Nov 22 01:17:09 PM PST 23
Finished Nov 22 01:17:17 PM PST 23
Peak memory 183200 kb
Host smart-7e218fb7-3f80-41bf-80a7-e8412c202215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72728419319581727429174847276827377641196792121066286989825082715671147640165 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.aon_timer_jump.72728419319581727429174847276827377641196792121066286989825082715671147640165
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.89917687848631808710625947842791312851072658739673329206527666789895311273153
Short name T146
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:55 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 183244 kb
Host smart-4fbc53e2-73c0-4010-9e3e-25eb4c1ece73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89917687848631808710625947842791312851072658739673329206527666789895311273153 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.aon_timer_smoke.89917687848631808710625947842791312851072658739673329206527666789895311273153
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.11357924150370357050210336207723025060559922837486535519004570176712591304957
Short name T137
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.96 seconds
Started Nov 22 01:17:07 PM PST 23
Finished Nov 22 01:22:19 PM PST 23
Peak memory 193188 kb
Host smart-75802b5a-3802-4183-be93-53a9c55f3297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357924150370357050210336207723025060559922837486535519004570176712591304957 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all.11357924150370357050210336207723025060559922837486535519004570176712591304957
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.47332512763341726232898396897999699316981384009312114649469169316002922743599
Short name T283
Test name
Test status
Simulation time 96759987586 ps
CPU time 427.03 seconds
Started Nov 22 01:17:54 PM PST 23
Finished Nov 22 01:25:09 PM PST 23
Peak memory 198096 kb
Host smart-ebaca7dc-ae86-40da-baea-4a82d89e428b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473325127633417262328
98396897999699316981384009312114649469169316002922743599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand
_reset.47332512763341726232898396897999699316981384009312114649469169316002922743599
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.114854436100989397549109449163159632054184988585633661264747537922537621106306
Short name T76
Test name
Test status
Simulation time 474704303 ps
CPU time 1 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183152 kb
Host smart-c92a3a6a-1e92-4710-a541-ca7d5f8d29c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114854436100989397549109449163159632054184988585633661264747537922537621106306 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.aon_timer_jump.114854436100989397549109449163159632054184988585633661264747537922537621106306
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.35180398024783267280659120659870280350942187475686546573565039351715595951923
Short name T186
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.78 seconds
Started Nov 22 01:17:07 PM PST 23
Finished Nov 22 01:18:04 PM PST 23
Peak memory 182916 kb
Host smart-1793cff0-da7d-4beb-ac74-9b856617e911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35180398024783267280659120659870280350942187475686546573565039351715595951923 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.aon_timer_prescaler.35180398024783267280659120659870280350942187475686546573565039351715595951923
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.95153414251285841897071263203347095899231361725879508678878103258745243257408
Short name T270
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:17:21 PM PST 23
Peak memory 183128 kb
Host smart-53d6beaf-74fd-4c53-9809-37994878a367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95153414251285841897071263203347095899231361725879508678878103258745243257408 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.aon_timer_smoke.95153414251285841897071263203347095899231361725879508678878103258745243257408
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.60099339502008763549258996234932270116495935357878048290416841604641221640152
Short name T202
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.84 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:22:13 PM PST 23
Peak memory 193464 kb
Host smart-acdd2db2-c17a-4d2b-b2e4-6719a99f0935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60099339502008763549258996234932270116495935357878048290416841604641221640152 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all.60099339502008763549258996234932270116495935357878048290416841604641221640152
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.52287595817742893878988102261602744585110456780903548384187774846130553108028
Short name T187
Test name
Test status
Simulation time 96759987586 ps
CPU time 418.05 seconds
Started Nov 22 01:17:11 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 198064 kb
Host smart-6f4f71e0-e54d-4644-b4b1-f143b6dfefb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522875958177428938789
88102261602744585110456780903548384187774846130553108028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand
_reset.52287595817742893878988102261602744585110456780903548384187774846130553108028
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.62573938059493745141505030349035018796359942662098789069745355926220155762411
Short name T114
Test name
Test status
Simulation time 474704303 ps
CPU time 0.99 seconds
Started Nov 22 01:18:44 PM PST 23
Finished Nov 22 01:18:48 PM PST 23
Peak memory 182872 kb
Host smart-b90d3339-e204-4b92-810b-51e76abf06e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62573938059493745141505030349035018796359942662098789069745355926220155762411 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.aon_timer_jump.62573938059493745141505030349035018796359942662098789069745355926220155762411
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.93900358969380953666173306513777793226863586025736437031084915417393903627952
Short name T103
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.85 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 183200 kb
Host smart-f5914786-734b-4a50-bb4f-ab64514d6e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93900358969380953666173306513777793226863586025736437031084915417393903627952 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.aon_timer_prescaler.93900358969380953666173306513777793226863586025736437031084915417393903627952
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.45919728928876768672572066211092401810021365090151803976367940204910259841875
Short name T265
Test name
Test status
Simulation time 491168457 ps
CPU time 1.01 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:10 PM PST 23
Peak memory 183104 kb
Host smart-6676b6aa-fb55-4aaf-bc3e-57d12d937d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45919728928876768672572066211092401810021365090151803976367940204910259841875 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.aon_timer_smoke.45919728928876768672572066211092401810021365090151803976367940204910259841875
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.6208683877094869781999502765349304082752885049707479855632930777014785832174
Short name T90
Test name
Test status
Simulation time 332628779192 ps
CPU time 304.77 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 193496 kb
Host smart-d41c106e-3508-44c2-971c-d8c738348ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6208683877094869781999502765349304082752885049707479855632930777014785832174 -assert nopost
proc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all.6208683877094869781999502765349304082752885049707479855632930777014785832174
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.102246287633012949057696035693560729549861599718878450886070590929575346630196
Short name T47
Test name
Test status
Simulation time 96759987586 ps
CPU time 397.7 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:25:22 PM PST 23
Peak memory 196624 kb
Host smart-0142f299-2ac3-4a62-bd86-2b24efe75c81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102246287633012949057
696035693560729549861599718878450886070590929575346630196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_ran
d_reset.102246287633012949057696035693560729549861599718878450886070590929575346630196
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.7770475196018201192191808840935243783264019266516905582563267886523239709630
Short name T267
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 183128 kb
Host smart-5858be2c-cf38-4c30-b947-4e34712c2689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7770475196018201192191808840935243783264019266516905582563267886523239709630 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.aon_timer_jump.7770475196018201192191808840935243783264019266516905582563267886523239709630
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.13696918539792194145226277674928302355978975530481421645802842306972698342060
Short name T92
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.77 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:58 PM PST 23
Peak memory 183224 kb
Host smart-687298e0-8ee1-4e94-8c1e-72191b6b9c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13696918539792194145226277674928302355978975530481421645802842306972698342060 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.aon_timer_prescaler.13696918539792194145226277674928302355978975530481421645802842306972698342060
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.103472847737419019720686523182991706059016223026120541730055403383852866170156
Short name T95
Test name
Test status
Simulation time 491168457 ps
CPU time 0.99 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:17:20 PM PST 23
Peak memory 183128 kb
Host smart-f7cb923c-2223-4468-8a37-3ad313b8b1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103472847737419019720686523182991706059016223026120541730055403383852866170156 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.aon_timer_smoke.103472847737419019720686523182991706059016223026120541730055403383852866170156
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.77865694907630117703922590975539181864487679591046950007678510624412536836750
Short name T251
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.24 seconds
Started Nov 22 01:17:12 PM PST 23
Finished Nov 22 01:22:21 PM PST 23
Peak memory 193524 kb
Host smart-b46022c9-1865-41ac-a9e2-390a0f2bb1ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77865694907630117703922590975539181864487679591046950007678510624412536836750 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all.77865694907630117703922590975539181864487679591046950007678510624412536836750
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.75884134153785743125517641274405685211025431840317015394552750969956364577712
Short name T27
Test name
Test status
Simulation time 96759987586 ps
CPU time 434.67 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 198160 kb
Host smart-f867e64f-12a5-4fd4-8f65-30194b0ad4eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758841341537857431255
17641274405685211025431840317015394552750969956364577712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand
_reset.75884134153785743125517641274405685211025431840317015394552750969956364577712
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.24672059635998711466154250785523925525334106354424152855645402243846505852160
Short name T182
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:16:43 PM PST 23
Finished Nov 22 01:16:46 PM PST 23
Peak memory 183252 kb
Host smart-f3c155c8-264f-40b8-bbf8-e20f42ff8ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24672059635998711466154250785523925525334106354424152855645402243846505852160 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.aon_timer_jump.24672059635998711466154250785523925525334106354424152855645402243846505852160
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.88590734434609445354025904321280248849052044649155909454636458613513242720429
Short name T198
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.79 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:17:27 PM PST 23
Peak memory 183200 kb
Host smart-eae59dae-f2d0-49f2-ad04-a7cb34b839af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88590734434609445354025904321280248849052044649155909454636458613513242720429 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.aon_timer_prescaler.88590734434609445354025904321280248849052044649155909454636458613513242720429
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.103904283375371784087927370935091306817103521427591877948509447539242126364024
Short name T40
Test name
Test status
Simulation time 4270477508 ps
CPU time 4.49 seconds
Started Nov 22 01:18:29 PM PST 23
Finished Nov 22 01:18:35 PM PST 23
Peak memory 215056 kb
Host smart-95d47b42-084f-4f8b-94cf-882507aaa863
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103904283375371784087927370935091306817103521427591877948509447539242126364024 -assert nopostpr
oc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.103904283375371784087927370935091306817103521427591877948509447539242126364024
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.93195980353726401086915304575320789687439134378816010803570252978575656056533
Short name T226
Test name
Test status
Simulation time 491168457 ps
CPU time 0.98 seconds
Started Nov 22 01:16:36 PM PST 23
Finished Nov 22 01:16:39 PM PST 23
Peak memory 183268 kb
Host smart-9736061b-f33d-4fa2-bbb7-591adcf2c565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93195980353726401086915304575320789687439134378816010803570252978575656056533 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.aon_timer_smoke.93195980353726401086915304575320789687439134378816010803570252978575656056533
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.110226905352946669907597405935534695712528451863041700335685428378206528917469
Short name T156
Test name
Test status
Simulation time 332628779192 ps
CPU time 305.12 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:22:11 PM PST 23
Peak memory 193212 kb
Host smart-67fd30ab-294e-401f-9729-db365321f259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110226905352946669907597405935534695712528451863041700335685428378206528917469 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all.110226905352946669907597405935534695712528451863041700335685428378206528917469
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.87114931835524272719140870726489953478943822471491867640482126564745902038489
Short name T166
Test name
Test status
Simulation time 96759987586 ps
CPU time 421.74 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:23:44 PM PST 23
Peak memory 198192 kb
Host smart-b006d3f4-a809-4e00-b37f-d0422a1b9c00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871149318355242727191
40870726489953478943822471491867640482126564745902038489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_
reset.87114931835524272719140870726489953478943822471491867640482126564745902038489
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.61117203408400629393081014921098477624174304341276839934239057075630807964307
Short name T215
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:39 PM PST 23
Finished Nov 22 01:17:42 PM PST 23
Peak memory 183272 kb
Host smart-27e3c410-e559-4695-94a2-5100a281dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61117203408400629393081014921098477624174304341276839934239057075630807964307 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.aon_timer_jump.61117203408400629393081014921098477624174304341276839934239057075630807964307
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.15078401755451426744715799559652318980854358806556917043415483643616656670391
Short name T281
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.51 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:18:17 PM PST 23
Peak memory 183364 kb
Host smart-503f67a0-9a3f-4bc0-8755-3e0f7202f82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15078401755451426744715799559652318980854358806556917043415483643616656670391 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.aon_timer_prescaler.15078401755451426744715799559652318980854358806556917043415483643616656670391
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.72046955586348002897241449589048573465603509283468230518876786749265590944842
Short name T120
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:20 PM PST 23
Finished Nov 22 01:17:25 PM PST 23
Peak memory 183272 kb
Host smart-883c3086-7a15-4616-943e-8770dfd52c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72046955586348002897241449589048573465603509283468230518876786749265590944842 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.aon_timer_smoke.72046955586348002897241449589048573465603509283468230518876786749265590944842
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.103281725970122649622272615448071161509997556670035421991431917693323537710393
Short name T262
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.85 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:22:30 PM PST 23
Peak memory 193632 kb
Host smart-2b909775-2fcf-4935-95c6-158b181c624b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103281725970122649622272615448071161509997556670035421991431917693323537710393 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all.103281725970122649622272615448071161509997556670035421991431917693323537710393
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.92497931168143023896808754597842679133131525213954626922395006129356411776022
Short name T249
Test name
Test status
Simulation time 96759987586 ps
CPU time 439.6 seconds
Started Nov 22 01:17:14 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 198160 kb
Host smart-52c086a5-4bd4-416a-a050-c2b7e52836d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924979311681430238968
08754597842679133131525213954626922395006129356411776022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand
_reset.92497931168143023896808754597842679133131525213954626922395006129356411776022
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.5515928968592716966465763694252533730555303838170146639371810083433045502966
Short name T80
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:16 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 183268 kb
Host smart-a744ba04-1eb0-4bf5-8a41-c40f6b8534ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5515928968592716966465763694252533730555303838170146639371810083433045502966 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.aon_timer_jump.5515928968592716966465763694252533730555303838170146639371810083433045502966
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.104759486577797345623846982774701668165316534709536879433585517851930636983851
Short name T222
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.48 seconds
Started Nov 22 01:17:29 PM PST 23
Finished Nov 22 01:18:20 PM PST 23
Peak memory 183272 kb
Host smart-2a17c5b0-6996-4c91-8f4a-80328bdee6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104759486577797345623846982774701668165316534709536879433585517851930636983851 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.aon_timer_prescaler.104759486577797345623846982774701668165316534709536879433585517851930636983851
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.27357468967081565530244626651779077334986811509456262973522881199548140512370
Short name T87
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 183156 kb
Host smart-615d794f-40f2-4a94-949c-6d9285de15f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27357468967081565530244626651779077334986811509456262973522881199548140512370 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.aon_timer_smoke.27357468967081565530244626651779077334986811509456262973522881199548140512370
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.56133357523358285597812972248903460899161268346453985466885197320540270710895
Short name T170
Test name
Test status
Simulation time 332628779192 ps
CPU time 300.9 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:22:28 PM PST 23
Peak memory 193660 kb
Host smart-83ae39b4-d71d-4b5a-95c8-eca91b134ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56133357523358285597812972248903460899161268346453985466885197320540270710895 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all.56133357523358285597812972248903460899161268346453985466885197320540270710895
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.32359564314055718492698798053951485038911956323273359496695188750964448910075
Short name T210
Test name
Test status
Simulation time 96759987586 ps
CPU time 429.77 seconds
Started Nov 22 01:17:13 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 198204 kb
Host smart-266ce1c1-9672-48e1-95ac-b7fe72157f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323595643140557184926
98798053951485038911956323273359496695188750964448910075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand
_reset.32359564314055718492698798053951485038911956323273359496695188750964448910075
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.39873492030045326768194912239364403789842316140431562229123079898231347679917
Short name T36
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 183140 kb
Host smart-a796d38b-4372-4da7-99c4-2d53aeab869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39873492030045326768194912239364403789842316140431562229123079898231347679917 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.aon_timer_jump.39873492030045326768194912239364403789842316140431562229123079898231347679917
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.30642404470560384130246631174865146242632450519632019325365190456012392951213
Short name T298
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.46 seconds
Started Nov 22 01:17:17 PM PST 23
Finished Nov 22 01:18:10 PM PST 23
Peak memory 183336 kb
Host smart-154fdcd0-6998-4e9b-8022-9483380e7042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30642404470560384130246631174865146242632450519632019325365190456012392951213 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.aon_timer_prescaler.30642404470560384130246631174865146242632450519632019325365190456012392951213
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.12176788793992896376144674243748187257617762627781666091568162976003302213702
Short name T227
Test name
Test status
Simulation time 491168457 ps
CPU time 0.99 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 183228 kb
Host smart-9c9cd5d5-0971-4e5f-87e1-eb941adfc40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12176788793992896376144674243748187257617762627781666091568162976003302213702 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.aon_timer_smoke.12176788793992896376144674243748187257617762627781666091568162976003302213702
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.110648325531667770914128485003094859182527286863711833969949543725757569384064
Short name T220
Test name
Test status
Simulation time 332628779192 ps
CPU time 300.86 seconds
Started Nov 22 01:17:12 PM PST 23
Finished Nov 22 01:22:19 PM PST 23
Peak memory 193656 kb
Host smart-f2b436cb-c55e-4d57-8dfd-890cb6ac40c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110648325531667770914128485003094859182527286863711833969949543725757569384064 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all.110648325531667770914128485003094859182527286863711833969949543725757569384064
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.69153690937072757288380685358093616895322617720174184215760337896354165934359
Short name T57
Test name
Test status
Simulation time 96759987586 ps
CPU time 430.22 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 198084 kb
Host smart-da79b348-7311-42e5-9b1e-f357ad0bf23b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691536909370727572883
80685358093616895322617720174184215760337896354165934359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand
_reset.69153690937072757288380685358093616895322617720174184215760337896354165934359
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.50904375688226113628993557776179959419486099881450755718904308529430920717940
Short name T109
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:18 PM PST 23
Finished Nov 22 01:17:24 PM PST 23
Peak memory 183292 kb
Host smart-2013fc22-6a89-4a26-9ccc-4da1c0c7084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50904375688226113628993557776179959419486099881450755718904308529430920717940 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.aon_timer_jump.50904375688226113628993557776179959419486099881450755718904308529430920717940
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.100675149276513069752242826870946146592851454900596937926212839756155243474578
Short name T235
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.77 seconds
Started Nov 22 01:17:18 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 183228 kb
Host smart-e905e416-2953-4777-8ea1-971a101472dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100675149276513069752242826870946146592851454900596937926212839756155243474578 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.aon_timer_prescaler.100675149276513069752242826870946146592851454900596937926212839756155243474578
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.71936556776465218007425497903767809256100865919105932630101605879394744483960
Short name T282
Test name
Test status
Simulation time 491168457 ps
CPU time 1 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 183212 kb
Host smart-2467665c-1c58-41e1-8564-c4608e2c1e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71936556776465218007425497903767809256100865919105932630101605879394744483960 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.aon_timer_smoke.71936556776465218007425497903767809256100865919105932630101605879394744483960
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.89335898811188440918656118400979734022876199221160070086737752466391044744124
Short name T273
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.88 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:22:23 PM PST 23
Peak memory 193644 kb
Host smart-5605d66a-1741-40fc-9838-ba8ccc1af225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89335898811188440918656118400979734022876199221160070086737752466391044744124 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all.89335898811188440918656118400979734022876199221160070086737752466391044744124
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.33652015962056295477796239434347637107415778353699490015998006840091798879695
Short name T130
Test name
Test status
Simulation time 96759987586 ps
CPU time 436.77 seconds
Started Nov 22 01:17:18 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 198156 kb
Host smart-9b01ce14-7918-4614-900f-149e5e7d3e96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336520159620562954777
96239434347637107415778353699490015998006840091798879695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand
_reset.33652015962056295477796239434347637107415778353699490015998006840091798879695
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.100971114597498585346450581632660793103192212952371533635115339380564634136095
Short name T213
Test name
Test status
Simulation time 474704303 ps
CPU time 1.04 seconds
Started Nov 22 01:17:17 PM PST 23
Finished Nov 22 01:17:23 PM PST 23
Peak memory 183240 kb
Host smart-66c5d5ee-21b6-4e8b-b4cb-dd6abc98e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100971114597498585346450581632660793103192212952371533635115339380564634136095 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.aon_timer_jump.100971114597498585346450581632660793103192212952371533635115339380564634136095
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.63143497173098632211546328169142539776949885459499069496564403348809938672121
Short name T136
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.26 seconds
Started Nov 22 01:17:24 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 183336 kb
Host smart-67b3848d-6401-4152-80ce-ef173523c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63143497173098632211546328169142539776949885459499069496564403348809938672121 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.aon_timer_prescaler.63143497173098632211546328169142539776949885459499069496564403348809938672121
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.95254400270995615609672982301364390342791641639045273095690397727393149112738
Short name T293
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 183248 kb
Host smart-e6b82b46-401c-4329-b26f-3ae70d74ac5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95254400270995615609672982301364390342791641639045273095690397727393149112738 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 24.aon_timer_smoke.95254400270995615609672982301364390342791641639045273095690397727393149112738
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.64434496701856655610948408968246157587922704528528032163509881659646497645593
Short name T28
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.3 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:22:24 PM PST 23
Peak memory 193532 kb
Host smart-076eacc6-031c-4094-8d81-c8295ef7a517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64434496701856655610948408968246157587922704528528032163509881659646497645593 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all.64434496701856655610948408968246157587922704528528032163509881659646497645593
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.57804940512501588406879577233788034092352432939905518995846945790801944749334
Short name T244
Test name
Test status
Simulation time 96759987586 ps
CPU time 432.65 seconds
Started Nov 22 01:17:17 PM PST 23
Finished Nov 22 01:24:35 PM PST 23
Peak memory 198212 kb
Host smart-99d04f0e-08eb-44c6-8cab-93a2e1472fb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578049405125015884068
79577233788034092352432939905518995846945790801944749334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand
_reset.57804940512501588406879577233788034092352432939905518995846945790801944749334
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.49653107955907181119732416808562994614520156330674329663145101511217457646850
Short name T160
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:30 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 183272 kb
Host smart-318a3819-cff7-4028-a875-7415059c1c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49653107955907181119732416808562994614520156330674329663145101511217457646850 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.aon_timer_jump.49653107955907181119732416808562994614520156330674329663145101511217457646850
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.103806407430891496756968621177497269381905511188640674818160995672790220462185
Short name T294
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.75 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:18:15 PM PST 23
Peak memory 183360 kb
Host smart-132e4f09-c2a8-4dbd-87bf-8de2c2773229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103806407430891496756968621177497269381905511188640674818160995672790220462185 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.aon_timer_prescaler.103806407430891496756968621177497269381905511188640674818160995672790220462185
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.8170753598739440592108198275731031712185834044351224140453477989854491258397
Short name T102
Test name
Test status
Simulation time 491168457 ps
CPU time 1.03 seconds
Started Nov 22 01:17:21 PM PST 23
Finished Nov 22 01:17:25 PM PST 23
Peak memory 183224 kb
Host smart-9940594e-1539-423e-8a0f-cec3973647ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8170753598739440592108198275731031712185834044351224140453477989854491258397 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.aon_timer_smoke.8170753598739440592108198275731031712185834044351224140453477989854491258397
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.68999583578487148433371314340754815422302548736601937056649519807979373285596
Short name T268
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.94 seconds
Started Nov 22 01:17:30 PM PST 23
Finished Nov 22 01:22:35 PM PST 23
Peak memory 193604 kb
Host smart-8e1fc80d-679f-4416-8981-36cb87471f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68999583578487148433371314340754815422302548736601937056649519807979373285596 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all.68999583578487148433371314340754815422302548736601937056649519807979373285596
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.29286025701924802657274484841129879148368447443867407876688610771544957616979
Short name T48
Test name
Test status
Simulation time 96759987586 ps
CPU time 423.9 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:24:30 PM PST 23
Peak memory 198184 kb
Host smart-7863db63-c08d-4fe4-85fb-858d7eb5696d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292860257019248026572
74484841129879148368447443867407876688610771544957616979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand
_reset.29286025701924802657274484841129879148368447443867407876688610771544957616979
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.68350787551265069731046350651871719301266303926729623762271393441296283734871
Short name T223
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:17 PM PST 23
Finished Nov 22 01:17:23 PM PST 23
Peak memory 183276 kb
Host smart-971779a4-c801-4d3e-94af-90ddddfcdf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68350787551265069731046350651871719301266303926729623762271393441296283734871 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.aon_timer_jump.68350787551265069731046350651871719301266303926729623762271393441296283734871
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.714998967627302103927164721470705273029247127710305519479576017580172008903
Short name T119
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.01 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:18:16 PM PST 23
Peak memory 183336 kb
Host smart-a9f21bf8-474b-4bb5-83a2-7c147bf82e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714998967627302103927164721470705273029247127710305519479576017580172008903 -assert nopostproc +UVM_TESTNAME=aon_timer_b
ase_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.aon_timer_prescaler.714998967627302103927164721470705273029247127710305519479576017580172008903
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.108144373499890561628924064199967447012318659795460070659419962309115598812197
Short name T89
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 183264 kb
Host smart-ae8524dd-33cc-4e90-9723-2e82685795d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108144373499890561628924064199967447012318659795460070659419962309115598812197 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.aon_timer_smoke.108144373499890561628924064199967447012318659795460070659419962309115598812197
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.12611317190709686706367120593518826814667765882788973628918291788021209467883
Short name T113
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.44 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:22:43 PM PST 23
Peak memory 193504 kb
Host smart-3c80c46a-d65f-4448-bfbc-aec8de828a08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611317190709686706367120593518826814667765882788973628918291788021209467883 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all.12611317190709686706367120593518826814667765882788973628918291788021209467883
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.90683399150953561901877581894899026703238074242734951892904574339925465035248
Short name T180
Test name
Test status
Simulation time 96759987586 ps
CPU time 419.84 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 198228 kb
Host smart-c074dc14-2e08-434b-8be2-9dc56154cc10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906833991509535619018
77581894899026703238074242734951892904574339925465035248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand
_reset.90683399150953561901877581894899026703238074242734951892904574339925465035248
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.105029790104986778234400337229588387592820124007391643683448598560064381623988
Short name T288
Test name
Test status
Simulation time 474704303 ps
CPU time 0.95 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183124 kb
Host smart-816f6153-d6e8-4565-a4ea-d36b28d96780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105029790104986778234400337229588387592820124007391643683448598560064381623988 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.aon_timer_jump.105029790104986778234400337229588387592820124007391643683448598560064381623988
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.110017435789787074995215322508411863079133936102379294098443473310155350172098
Short name T173
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.9 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:18:17 PM PST 23
Peak memory 183360 kb
Host smart-f73e6773-12d8-4273-a910-e1ddca22e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110017435789787074995215322508411863079133936102379294098443473310155350172098 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.aon_timer_prescaler.110017435789787074995215322508411863079133936102379294098443473310155350172098
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.35925959845245971408444267970082833133067766315562823261555897574531615668850
Short name T127
Test name
Test status
Simulation time 491168457 ps
CPU time 1.02 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:32 PM PST 23
Peak memory 183104 kb
Host smart-7b77e5c1-dd33-4ff6-97b4-c5e2ab9b5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35925959845245971408444267970082833133067766315562823261555897574531615668850 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.aon_timer_smoke.35925959845245971408444267970082833133067766315562823261555897574531615668850
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.51442260490302495866814569454335711439090582498600632586109675102411627065727
Short name T191
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.7 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 193648 kb
Host smart-940d3dd8-6825-4592-af20-546f305d2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51442260490302495866814569454335711439090582498600632586109675102411627065727 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all.51442260490302495866814569454335711439090582498600632586109675102411627065727
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.40641789585307341900231414523685783561210808530002415308613165469851807554942
Short name T208
Test name
Test status
Simulation time 96759987586 ps
CPU time 407.69 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:25:32 PM PST 23
Peak memory 196648 kb
Host smart-c6166bb1-dab0-4a6a-9abc-3428dfdb1b8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406417895853073419002
31414523685783561210808530002415308613165469851807554942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand
_reset.40641789585307341900231414523685783561210808530002415308613165469851807554942
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.58248051900251718147122506648261772864425155363476776038470683926690597155610
Short name T250
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183312 kb
Host smart-51914c19-35d7-4c68-ba5f-d8180982ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58248051900251718147122506648261772864425155363476776038470683926690597155610 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.aon_timer_jump.58248051900251718147122506648261772864425155363476776038470683926690597155610
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.60402939458047487825146289142924091558227325711500221311098264398535567889467
Short name T154
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.52 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 183136 kb
Host smart-a58a42d1-3f73-4dde-9a3c-440ce3edd1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60402939458047487825146289142924091558227325711500221311098264398535567889467 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.aon_timer_prescaler.60402939458047487825146289142924091558227325711500221311098264398535567889467
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.6144631852449434226824766538850132430642697469442339870183165076290659144185
Short name T171
Test name
Test status
Simulation time 491168457 ps
CPU time 0.95 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183152 kb
Host smart-d5d9376e-fe77-4b61-a987-7f1e1c509f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6144631852449434226824766538850132430642697469442339870183165076290659144185 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.aon_timer_smoke.6144631852449434226824766538850132430642697469442339870183165076290659144185
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.110084075816370878158238527022686911283881448152138852344283970792836608022961
Short name T243
Test name
Test status
Simulation time 332628779192 ps
CPU time 300.62 seconds
Started Nov 22 01:17:28 PM PST 23
Finished Nov 22 01:22:32 PM PST 23
Peak memory 193488 kb
Host smart-dfda87fc-ec6b-43f9-a173-6ac1614a26b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110084075816370878158238527022686911283881448152138852344283970792836608022961 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all.110084075816370878158238527022686911283881448152138852344283970792836608022961
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.42722657407129453849176549789827234385748381124825953316968737828802391261414
Short name T190
Test name
Test status
Simulation time 96759987586 ps
CPU time 432.96 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:24:42 PM PST 23
Peak memory 198232 kb
Host smart-d1638e37-f1f5-49fa-956c-8bd9920b5b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427226574071294538491
76549789827234385748381124825953316968737828802391261414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand
_reset.42722657407129453849176549789827234385748381124825953316968737828802391261414
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.37459460151032118435535882227528325725091271408453241080504444470584890532189
Short name T209
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183312 kb
Host smart-401b4fba-5afe-45a0-83c6-bc3bef0867fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37459460151032118435535882227528325725091271408453241080504444470584890532189 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.aon_timer_jump.37459460151032118435535882227528325725091271408453241080504444470584890532189
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.100957214367839632481706107607546377575136994896052200387789810798617833606376
Short name T225
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.2 seconds
Started Nov 22 01:17:26 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 183360 kb
Host smart-f879652a-2677-483c-9f5f-3b7afe5d16d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100957214367839632481706107607546377575136994896052200387789810798617833606376 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.aon_timer_prescaler.100957214367839632481706107607546377575136994896052200387789810798617833606376
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.23183348187859049113784473937879158796314176239724675694267951120586183378232
Short name T239
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 183092 kb
Host smart-76ae973b-9d8e-4b4c-a78b-7f74d893c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23183348187859049113784473937879158796314176239724675694267951120586183378232 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.aon_timer_smoke.23183348187859049113784473937879158796314176239724675694267951120586183378232
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.21882581558837765622531533565216743075993964597535931822288382724085588390405
Short name T194
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.25 seconds
Started Nov 22 01:17:36 PM PST 23
Finished Nov 22 01:22:41 PM PST 23
Peak memory 193608 kb
Host smart-3ecc7e8e-665a-4759-a1fe-4a05fadc1289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882581558837765622531533565216743075993964597535931822288382724085588390405 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all.21882581558837765622531533565216743075993964597535931822288382724085588390405
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.13554656899605257160036470088971156530157969668756610544817563453241978231163
Short name T85
Test name
Test status
Simulation time 96759987586 ps
CPU time 422.92 seconds
Started Nov 22 01:18:01 PM PST 23
Finished Nov 22 01:25:12 PM PST 23
Peak memory 197928 kb
Host smart-d87b4d68-c19e-4e8c-bf31-9d32f19b39bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135546568996052571600
36470088971156530157969668756610544817563453241978231163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand
_reset.13554656899605257160036470088971156530157969668756610544817563453241978231163
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.94447505764700539909310847438016062965794739355539320538747012397322397170262
Short name T101
Test name
Test status
Simulation time 474704303 ps
CPU time 0.94 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:19:00 PM PST 23
Peak memory 183136 kb
Host smart-22b53305-5485-4c8e-9727-25214eac171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94447505764700539909310847438016062965794739355539320538747012397322397170262 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.aon_timer_jump.94447505764700539909310847438016062965794739355539320538747012397322397170262
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.74845718198985244561702586184107312468073336002853716282182501559181768717765
Short name T233
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.43 seconds
Started Nov 22 01:17:02 PM PST 23
Finished Nov 22 01:18:02 PM PST 23
Peak memory 183312 kb
Host smart-70db9e22-6972-4e17-bf1b-f13061e683d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74845718198985244561702586184107312468073336002853716282182501559181768717765 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.aon_timer_prescaler.74845718198985244561702586184107312468073336002853716282182501559181768717765
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1527302975309856984190815697199619760675393659158760108085954953383402592719
Short name T39
Test name
Test status
Simulation time 4270477508 ps
CPU time 4.58 seconds
Started Nov 22 01:18:37 PM PST 23
Finished Nov 22 01:18:45 PM PST 23
Peak memory 215084 kb
Host smart-bab7b594-4dc0-42a6-9164-4514ade2c655
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527302975309856984190815697199619760675393659158760108085954953383402592719 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1527302975309856984190815697199619760675393659158760108085954953383402592719
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.6358401668406338189976171514322219932909601287250928197675624666939424574184
Short name T248
Test name
Test status
Simulation time 491168457 ps
CPU time 0.94 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:17:03 PM PST 23
Peak memory 183240 kb
Host smart-a57ceb76-40b4-4767-bf8b-50a708930cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6358401668406338189976171514322219932909601287250928197675624666939424574184 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.aon_timer_smoke.6358401668406338189976171514322219932909601287250928197675624666939424574184
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.22183802894207428558462692396818449670634091585152184223960111316899120626456
Short name T148
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.53 seconds
Started Nov 22 01:18:27 PM PST 23
Finished Nov 22 01:23:32 PM PST 23
Peak memory 193648 kb
Host smart-8d6ab677-86bb-46ef-b247-8da47d6daa15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22183802894207428558462692396818449670634091585152184223960111316899120626456 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all.22183802894207428558462692396818449670634091585152184223960111316899120626456
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.90477220017729479566822415432587771392916879418401966628587425912134332392664
Short name T216
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:17:30 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 183140 kb
Host smart-bfb0cfe4-1a86-432e-bdcc-8b600e534e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90477220017729479566822415432587771392916879418401966628587425912134332392664 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.aon_timer_jump.90477220017729479566822415432587771392916879418401966628587425912134332392664
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.20328303209986249234926013552585469569872359510595115213196279492705236452155
Short name T259
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.64 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:18:18 PM PST 23
Peak memory 183164 kb
Host smart-161bd730-9c87-45a1-88fc-9e8b5738c8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20328303209986249234926013552585469569872359510595115213196279492705236452155 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.aon_timer_prescaler.20328303209986249234926013552585469569872359510595115213196279492705236452155
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4760641385087764334434764332064622653661706574888617344103322100042328724680
Short name T195
Test name
Test status
Simulation time 491168457 ps
CPU time 0.98 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:17:42 PM PST 23
Peak memory 183136 kb
Host smart-2d81af50-96aa-48e2-b039-d10b65f015bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4760641385087764334434764332064622653661706574888617344103322100042328724680 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.aon_timer_smoke.4760641385087764334434764332064622653661706574888617344103322100042328724680
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.94141428847804989043157283432454198599818507783123193082554118276772587397388
Short name T172
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.12 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 193660 kb
Host smart-c011b8d3-623c-49d7-8c8f-2bf42755b859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94141428847804989043157283432454198599818507783123193082554118276772587397388 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all.94141428847804989043157283432454198599818507783123193082554118276772587397388
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.35182776837451426183297095527027205354461968529724606710240196598867235421956
Short name T221
Test name
Test status
Simulation time 96759987586 ps
CPU time 422.65 seconds
Started Nov 22 01:17:53 PM PST 23
Finished Nov 22 01:25:05 PM PST 23
Peak memory 198208 kb
Host smart-156e496d-6afb-42df-8250-a6d031a9ab1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351827768374514261832
97095527027205354461968529724606710240196598867235421956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand
_reset.35182776837451426183297095527027205354461968529724606710240196598867235421956
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.74343922623940390344458308636162512775642014599943125071377947982214704174744
Short name T43
Test name
Test status
Simulation time 474704303 ps
CPU time 1.02 seconds
Started Nov 22 01:17:30 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 183140 kb
Host smart-eee5b042-21a0-40fc-82e1-d6dc739c7707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74343922623940390344458308636162512775642014599943125071377947982214704174744 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.aon_timer_jump.74343922623940390344458308636162512775642014599943125071377947982214704174744
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.13058070474129239908439650170988418946129026775770357551198510004946911698627
Short name T266
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.27 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:18:19 PM PST 23
Peak memory 183192 kb
Host smart-ad463842-ae1f-4ffb-9c8d-e74700153488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13058070474129239908439650170988418946129026775770357551198510004946911698627 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.aon_timer_prescaler.13058070474129239908439650170988418946129026775770357551198510004946911698627
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.86342262306294114124466539576706853383033932755212650338126697971868896741843
Short name T91
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 183264 kb
Host smart-39367d54-ff3b-4c17-a7a1-1db49e4c3b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86342262306294114124466539576706853383033932755212650338126697971868896741843 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 31.aon_timer_smoke.86342262306294114124466539576706853383033932755212650338126697971868896741843
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.68922312862257246304775302727661374177544721400789558460923931978085397582341
Short name T121
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.48 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 193436 kb
Host smart-c7a960d4-333b-4841-b529-9ee850cf51bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68922312862257246304775302727661374177544721400789558460923931978085397582341 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all.68922312862257246304775302727661374177544721400789558460923931978085397582341
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.21564873790499596846312635770481608194528849420156120249453642458552749793996
Short name T275
Test name
Test status
Simulation time 96759987586 ps
CPU time 428.49 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 198228 kb
Host smart-e5e22fe3-d6f3-473d-baad-14926c8cc871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215648737904995968463
12635770481608194528849420156120249453642458552749793996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand
_reset.21564873790499596846312635770481608194528849420156120249453642458552749793996
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.19568525965448782901788873869376177186674709947348629835735872949704616763517
Short name T49
Test name
Test status
Simulation time 474704303 ps
CPU time 1.01 seconds
Started Nov 22 01:17:28 PM PST 23
Finished Nov 22 01:17:32 PM PST 23
Peak memory 183164 kb
Host smart-ea0ba170-69d6-450e-861c-22a7bc25f98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19568525965448782901788873869376177186674709947348629835735872949704616763517 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.aon_timer_jump.19568525965448782901788873869376177186674709947348629835735872949704616763517
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.79207925320048849101944461369818976115364690176214207511512275182805220758314
Short name T98
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.23 seconds
Started Nov 22 01:17:32 PM PST 23
Finished Nov 22 01:18:22 PM PST 23
Peak memory 183356 kb
Host smart-ba1d8e60-8353-445c-a6e1-805cf9cb5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79207925320048849101944461369818976115364690176214207511512275182805220758314 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.aon_timer_prescaler.79207925320048849101944461369818976115364690176214207511512275182805220758314
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.28933214235733067136711048384983175925076060482335260068073831054401236611272
Short name T291
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:17:40 PM PST 23
Peak memory 183104 kb
Host smart-d56b5d92-88d0-446e-b74c-da54a99988a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28933214235733067136711048384983175925076060482335260068073831054401236611272 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.aon_timer_smoke.28933214235733067136711048384983175925076060482335260068073831054401236611272
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.85565068223599376019623782805698598956140302195144394775435405402465615962622
Short name T126
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.58 seconds
Started Nov 22 01:17:29 PM PST 23
Finished Nov 22 01:22:34 PM PST 23
Peak memory 193632 kb
Host smart-f93fa767-2d43-45fe-93bb-892938b02e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85565068223599376019623782805698598956140302195144394775435405402465615962622 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all.85565068223599376019623782805698598956140302195144394775435405402465615962622
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1462398152681708766342829022206267601632930445404683324846482503035711142127
Short name T99
Test name
Test status
Simulation time 96759987586 ps
CPU time 404.77 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:24:27 PM PST 23
Peak memory 198004 kb
Host smart-b59b57ac-7d84-48ea-be43-8906c1cf843b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146239815268170876634
2829022206267601632930445404683324846482503035711142127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_
reset.1462398152681708766342829022206267601632930445404683324846482503035711142127
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.10936463550399516638360721448148772638785818803185752443579094178349670845293
Short name T297
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183156 kb
Host smart-e36b4240-821b-488f-923d-44adf9016463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10936463550399516638360721448148772638785818803185752443579094178349670845293 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.aon_timer_jump.10936463550399516638360721448148772638785818803185752443579094178349670845293
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.60425906960971271662294366615954080977967747430571850265955735758995028501867
Short name T260
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.03 seconds
Started Nov 22 01:17:52 PM PST 23
Finished Nov 22 01:18:51 PM PST 23
Peak memory 183308 kb
Host smart-2ec82e6c-6d11-47a8-b57d-8b56be2d3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60425906960971271662294366615954080977967747430571850265955735758995028501867 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.aon_timer_prescaler.60425906960971271662294366615954080977967747430571850265955735758995028501867
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.28671235942145324345923377535829730454100462744541800390529428677995750275978
Short name T197
Test name
Test status
Simulation time 491168457 ps
CPU time 0.98 seconds
Started Nov 22 01:17:27 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183308 kb
Host smart-fe6da5f2-5f33-42f1-a345-80ffc0fd01e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28671235942145324345923377535829730454100462744541800390529428677995750275978 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.aon_timer_smoke.28671235942145324345923377535829730454100462744541800390529428677995750275978
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.31349147959187131251069795290798600645400671756864957438362492265734981591586
Short name T163
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.22 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:23:48 PM PST 23
Peak memory 191636 kb
Host smart-2e54602a-6f40-4a65-8bb2-44605894c821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349147959187131251069795290798600645400671756864957438362492265734981591586 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all.31349147959187131251069795290798600645400671756864957438362492265734981591586
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.65559223824756094810557034170374657897549886775749867096037725949552302315546
Short name T271
Test name
Test status
Simulation time 96759987586 ps
CPU time 417.48 seconds
Started Nov 22 01:17:28 PM PST 23
Finished Nov 22 01:24:29 PM PST 23
Peak memory 198056 kb
Host smart-61ea369d-a525-42dc-9e0a-f641066aae16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655592238247560948105
57034170374657897549886775749867096037725949552302315546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand
_reset.65559223824756094810557034170374657897549886775749867096037725949552302315546
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.113777248640091566473345565896779158144031908732771971048716640565971847624933
Short name T78
Test name
Test status
Simulation time 474704303 ps
CPU time 1 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:17:28 PM PST 23
Peak memory 183216 kb
Host smart-63a8be45-6ec9-486a-8cdd-a07b2db674c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113777248640091566473345565896779158144031908732771971048716640565971847624933 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.aon_timer_jump.113777248640091566473345565896779158144031908732771971048716640565971847624933
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.103234862442497064780381940014831987639773812386221056642433601851813915318285
Short name T206
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.79 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 183228 kb
Host smart-f7889320-ecf5-4dad-9ec8-e35d75f7bb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103234862442497064780381940014831987639773812386221056642433601851813915318285 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.aon_timer_prescaler.103234862442497064780381940014831987639773812386221056642433601851813915318285
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.80955555784001207593893897794214342394595943167156668294656675942567980686072
Short name T115
Test name
Test status
Simulation time 491168457 ps
CPU time 1 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 183292 kb
Host smart-9cb8a16c-06ca-4381-afa3-688e9c5c91eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80955555784001207593893897794214342394595943167156668294656675942567980686072 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 34.aon_timer_smoke.80955555784001207593893897794214342394595943167156668294656675942567980686072
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.111272518231590259220907840574676104761659379868284180246428301634772822484188
Short name T35
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.81 seconds
Started Nov 22 01:17:26 PM PST 23
Finished Nov 22 01:22:31 PM PST 23
Peak memory 193460 kb
Host smart-904580ce-d547-47bb-9850-63cc6f0a0bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111272518231590259220907840574676104761659379868284180246428301634772822484188 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all.111272518231590259220907840574676104761659379868284180246428301634772822484188
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.108452259973189212925608546782432180740436204510181592923197179527462257270123
Short name T285
Test name
Test status
Simulation time 96759987586 ps
CPU time 408.55 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:24:30 PM PST 23
Peak memory 197996 kb
Host smart-5d378238-19e2-4b5c-9dfc-804e406b35b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108452259973189212925
608546782432180740436204510181592923197179527462257270123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_ran
d_reset.108452259973189212925608546782432180740436204510181592923197179527462257270123
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.34877295711670111172884570483273242923873280921567784002135141347390397613551
Short name T184
Test name
Test status
Simulation time 474704303 ps
CPU time 0.98 seconds
Started Nov 22 01:18:05 PM PST 23
Finished Nov 22 01:18:12 PM PST 23
Peak memory 183244 kb
Host smart-0c9b7fca-a2cc-4d22-b289-c45b535e8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34877295711670111172884570483273242923873280921567784002135141347390397613551 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.aon_timer_jump.34877295711670111172884570483273242923873280921567784002135141347390397613551
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.32384685515618816463553864895906919420816034963973911797548093279138071213032
Short name T234
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.45 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 183172 kb
Host smart-384f12df-8133-4ac1-961c-ce87c34c0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32384685515618816463553864895906919420816034963973911797548093279138071213032 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.aon_timer_prescaler.32384685515618816463553864895906919420816034963973911797548093279138071213032
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.23565406544497900581893454876510101852350044015398520117595644920126022445798
Short name T211
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:17:43 PM PST 23
Peak memory 183064 kb
Host smart-6aff625a-c2f4-48c6-8039-7d84f358ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23565406544497900581893454876510101852350044015398520117595644920126022445798 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.aon_timer_smoke.23565406544497900581893454876510101852350044015398520117595644920126022445798
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.23979857025367686907531191458934035558370189273933827642549979285938979814922
Short name T29
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.14 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:23:39 PM PST 23
Peak memory 193668 kb
Host smart-282daecd-19da-4605-bf18-c0fa92915c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23979857025367686907531191458934035558370189273933827642549979285938979814922 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all.23979857025367686907531191458934035558370189273933827642549979285938979814922
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.25546006592771786662641246458053518575161926943739404801622904804659322781194
Short name T141
Test name
Test status
Simulation time 96759987586 ps
CPU time 422.32 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:24:31 PM PST 23
Peak memory 198092 kb
Host smart-4df2b344-867d-49e8-a818-2dbeb52e9255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255460065927717866626
41246458053518575161926943739404801622904804659322781194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand
_reset.25546006592771786662641246458053518575161926943739404801622904804659322781194
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.37631185679597342269993549146763556809057308569534952580621291480803365410269
Short name T241
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:54 PM PST 23
Finished Nov 22 01:18:03 PM PST 23
Peak memory 183108 kb
Host smart-55eb9ccb-8b3d-483a-b8f3-6b52244fe801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37631185679597342269993549146763556809057308569534952580621291480803365410269 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.aon_timer_jump.37631185679597342269993549146763556809057308569534952580621291480803365410269
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.74700013328827885501912389339273381270608662613835797787703897942319343258945
Short name T257
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.49 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:18:31 PM PST 23
Peak memory 183140 kb
Host smart-1b22bc16-2fe5-4e0a-83a6-b8882b1cfac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74700013328827885501912389339273381270608662613835797787703897942319343258945 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.aon_timer_prescaler.74700013328827885501912389339273381270608662613835797787703897942319343258945
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.40467010006612388550359072112330023581515033694053532453750310556204385582901
Short name T124
Test name
Test status
Simulation time 491168457 ps
CPU time 0.94 seconds
Started Nov 22 01:17:25 PM PST 23
Finished Nov 22 01:17:30 PM PST 23
Peak memory 183080 kb
Host smart-668613cf-9870-4578-94d7-70e8a1306b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40467010006612388550359072112330023581515033694053532453750310556204385582901 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.aon_timer_smoke.40467010006612388550359072112330023581515033694053532453750310556204385582901
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.12512728729085012789338057413982926211556272398251486685387200802518341984022
Short name T134
Test name
Test status
Simulation time 332628779192 ps
CPU time 304.58 seconds
Started Nov 22 01:17:37 PM PST 23
Finished Nov 22 01:22:43 PM PST 23
Peak memory 193496 kb
Host smart-1dab1d20-d81a-4352-a16e-dc30c21b926e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512728729085012789338057413982926211556272398251486685387200802518341984022 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all.12512728729085012789338057413982926211556272398251486685387200802518341984022
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.14559296662935598007028620806652714009191346188776188983340641402927158227787
Short name T255
Test name
Test status
Simulation time 96759987586 ps
CPU time 427.09 seconds
Started Nov 22 01:17:39 PM PST 23
Finished Nov 22 01:24:48 PM PST 23
Peak memory 198160 kb
Host smart-9f38a21b-1b0f-42dd-a4e7-80486a0063b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145592966629355980070
28620806652714009191346188776188983340641402927158227787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand
_reset.14559296662935598007028620806652714009191346188776188983340641402927158227787
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.11970042003264499001086119484511736654305052846982010885967373643694413850278
Short name T219
Test name
Test status
Simulation time 474704303 ps
CPU time 1.05 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 180656 kb
Host smart-5cf27f48-e0fd-4f2c-9fc3-b3cb67203f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11970042003264499001086119484511736654305052846982010885967373643694413850278 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.aon_timer_jump.11970042003264499001086119484511736654305052846982010885967373643694413850278
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.76281553881884034388630076901125428997745568147866726941171109406310777899102
Short name T256
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.21 seconds
Started Nov 22 01:17:34 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 183356 kb
Host smart-ed44ae9f-534a-44f6-9a55-c04397e3e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76281553881884034388630076901125428997745568147866726941171109406310777899102 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.aon_timer_prescaler.76281553881884034388630076901125428997745568147866726941171109406310777899102
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.97656125765708484489934649741342787879937769205538439218689162424469699396299
Short name T242
Test name
Test status
Simulation time 491168457 ps
CPU time 1.02 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 180644 kb
Host smart-d73f248e-5f2e-4295-954b-7f87218be00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97656125765708484489934649741342787879937769205538439218689162424469699396299 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.aon_timer_smoke.97656125765708484489934649741342787879937769205538439218689162424469699396299
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.9094563128729237362403447458608718221019289704865833577697968219247470890627
Short name T296
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.47 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:22:45 PM PST 23
Peak memory 193496 kb
Host smart-4e73c5c1-814b-4402-9d87-be4c42973c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9094563128729237362403447458608718221019289704865833577697968219247470890627 -assert nopost
proc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all.9094563128729237362403447458608718221019289704865833577697968219247470890627
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.17191468886311183936413611789586546865766454145434194544529242376084203347005
Short name T264
Test name
Test status
Simulation time 96759987586 ps
CPU time 429.55 seconds
Started Nov 22 01:17:33 PM PST 23
Finished Nov 22 01:24:45 PM PST 23
Peak memory 198200 kb
Host smart-99f164f2-fcc6-490f-84dd-4af91790a503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171914688863111839364
13611789586546865766454145434194544529242376084203347005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand
_reset.17191468886311183936413611789586546865766454145434194544529242376084203347005
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.82807143860392611587685245767848459751522944596794554206960973512605441562615
Short name T177
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:42 PM PST 23
Finished Nov 22 01:17:44 PM PST 23
Peak memory 183068 kb
Host smart-2459c71a-094d-461d-a8bd-e08542e632bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82807143860392611587685245767848459751522944596794554206960973512605441562615 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.aon_timer_jump.82807143860392611587685245767848459751522944596794554206960973512605441562615
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.35942596884404132095967798556934235219837063662649905963171743965983945827736
Short name T204
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.96 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:18:31 PM PST 23
Peak memory 183300 kb
Host smart-4866330c-73e1-4096-be95-97181357c4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35942596884404132095967798556934235219837063662649905963171743965983945827736 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.aon_timer_prescaler.35942596884404132095967798556934235219837063662649905963171743965983945827736
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.52522123765708926189493091763813791541400600335234911928592358302682080510247
Short name T252
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:18:46 PM PST 23
Peak memory 181588 kb
Host smart-2a6eefe1-97e2-4ba4-aabb-603802ba764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52522123765708926189493091763813791541400600335234911928592358302682080510247 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.aon_timer_smoke.52522123765708926189493091763813791541400600335234911928592358302682080510247
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.70572563230538709195809148981188917686369846568810581927799457144362207357802
Short name T169
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.93 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:23:46 PM PST 23
Peak memory 191232 kb
Host smart-bc10f6f8-410a-4c2e-93bd-8c45df18baf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70572563230538709195809148981188917686369846568810581927799457144362207357802 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all.70572563230538709195809148981188917686369846568810581927799457144362207357802
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.80066219842968604821158682323935569289427069606030938038802704602294991637219
Short name T161
Test name
Test status
Simulation time 96759987586 ps
CPU time 421.59 seconds
Started Nov 22 01:17:37 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 198104 kb
Host smart-d3205be5-38b5-440a-a3d7-67774a841db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800662198429686048211
58682323935569289427069606030938038802704602294991637219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand
_reset.80066219842968604821158682323935569289427069606030938038802704602294991637219
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.99356785745883866625819810600619279527236871164829829508087903860429551157769
Short name T77
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:18:25 PM PST 23
Finished Nov 22 01:18:30 PM PST 23
Peak memory 183240 kb
Host smart-25f81e25-e499-4368-9641-377b3f9a52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99356785745883866625819810600619279527236871164829829508087903860429551157769 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.aon_timer_jump.99356785745883866625819810600619279527236871164829829508087903860429551157769
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.27832525462388410878458622450273833802726424616074287423332359553749932210371
Short name T185
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.72 seconds
Started Nov 22 01:18:35 PM PST 23
Finished Nov 22 01:19:25 PM PST 23
Peak memory 183360 kb
Host smart-12f61511-f15e-4c03-8a10-4cd78e1f4a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27832525462388410878458622450273833802726424616074287423332359553749932210371 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.aon_timer_prescaler.27832525462388410878458622450273833802726424616074287423332359553749932210371
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.39699852370554891477591301981601181999645256864063455654868701795781301934030
Short name T245
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:35 PM PST 23
Finished Nov 22 01:17:38 PM PST 23
Peak memory 183280 kb
Host smart-65f2d063-6831-4559-927c-1857b8dd9c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39699852370554891477591301981601181999645256864063455654868701795781301934030 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.aon_timer_smoke.39699852370554891477591301981601181999645256864063455654868701795781301934030
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.111343956561188459713163841013033244089496592161098544288040391008278370855053
Short name T143
Test name
Test status
Simulation time 332628779192 ps
CPU time 304.14 seconds
Started Nov 22 01:18:46 PM PST 23
Finished Nov 22 01:23:52 PM PST 23
Peak memory 193648 kb
Host smart-07d904d5-7193-4341-9b91-a9b768702b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111343956561188459713163841013033244089496592161098544288040391008278370855053 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all.111343956561188459713163841013033244089496592161098544288040391008278370855053
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.114718104002842774158352528251600447693420185467629799164399659604123494898184
Short name T21
Test name
Test status
Simulation time 96759987586 ps
CPU time 426.52 seconds
Started Nov 22 01:17:32 PM PST 23
Finished Nov 22 01:24:40 PM PST 23
Peak memory 198216 kb
Host smart-739e2e48-7a13-4875-9672-4591cf0555cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114718104002842774158
352528251600447693420185467629799164399659604123494898184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_ran
d_reset.114718104002842774158352528251600447693420185467629799164399659604123494898184
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.11120286399127619027522341109908196984887510489047233803454272358954915746827
Short name T292
Test name
Test status
Simulation time 474704303 ps
CPU time 0.99 seconds
Started Nov 22 01:18:50 PM PST 23
Finished Nov 22 01:18:53 PM PST 23
Peak memory 183160 kb
Host smart-84abed40-ecf5-4285-bbc5-f34d40fdb8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11120286399127619027522341109908196984887510489047233803454272358954915746827 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.aon_timer_jump.11120286399127619027522341109908196984887510489047233803454272358954915746827
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.104709995629197472249448056743489397166501560756711044206710655544361425009258
Short name T229
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.81 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:17:41 PM PST 23
Peak memory 183344 kb
Host smart-3c73a03e-4a65-4e96-9970-b633da7c4952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104709995629197472249448056743489397166501560756711044206710655544361425009258 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.aon_timer_prescaler.104709995629197472249448056743489397166501560756711044206710655544361425009258
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.7890403646989185168893556682386266700232481589849582652139179647680690158964
Short name T41
Test name
Test status
Simulation time 4270477508 ps
CPU time 4.54 seconds
Started Nov 22 01:16:47 PM PST 23
Finished Nov 22 01:16:56 PM PST 23
Peak memory 214856 kb
Host smart-c6309ddf-dd89-4702-a79e-0d6f35cbd896
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7890403646989185168893556682386266700232481589849582652139179647680690158964 -assert nopostproc
+UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.7890403646989185168893556682386266700232481589849582652139179647680690158964
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.67023682455998300174520773005025751069845924302652730439178277209064903800350
Short name T193
Test name
Test status
Simulation time 491168457 ps
CPU time 0.99 seconds
Started Nov 22 01:16:41 PM PST 23
Finished Nov 22 01:16:43 PM PST 23
Peak memory 183204 kb
Host smart-0c65c2b5-d790-48ec-adb9-cb63b7879f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67023682455998300174520773005025751069845924302652730439178277209064903800350 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.aon_timer_smoke.67023682455998300174520773005025751069845924302652730439178277209064903800350
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.45654744808717834693554111791150962123299126437969903118400695597860137026679
Short name T287
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.12 seconds
Started Nov 22 01:16:49 PM PST 23
Finished Nov 22 01:21:56 PM PST 23
Peak memory 193624 kb
Host smart-a0c7e5f5-f758-4da8-ac99-1e797edf568e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45654744808717834693554111791150962123299126437969903118400695597860137026679 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all.45654744808717834693554111791150962123299126437969903118400695597860137026679
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.87405956690857394866030269975114646805198957799710621046711790763178259482769
Short name T228
Test name
Test status
Simulation time 96759987586 ps
CPU time 425.31 seconds
Started Nov 22 01:18:37 PM PST 23
Finished Nov 22 01:25:46 PM PST 23
Peak memory 198192 kb
Host smart-f23de372-ddfe-45c6-b4b5-b6a795235434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874059566908573948660
30269975114646805198957799710621046711790763178259482769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_
reset.87405956690857394866030269975114646805198957799710621046711790763178259482769
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.29873219444838514130431758985193076502492254154060214351465927572389289559736
Short name T279
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:34 PM PST 23
Finished Nov 22 01:17:37 PM PST 23
Peak memory 183288 kb
Host smart-4f719604-40c3-4e2d-b3e8-bfcc0c6f8e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29873219444838514130431758985193076502492254154060214351465927572389289559736 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.aon_timer_jump.29873219444838514130431758985193076502492254154060214351465927572389289559736
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4325780608012970697672799463219029539434608304853832180575146918879708602692
Short name T196
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.58 seconds
Started Nov 22 01:17:33 PM PST 23
Finished Nov 22 01:18:24 PM PST 23
Peak memory 183240 kb
Host smart-2681cd4c-7b1b-4330-a919-dd6aa6d8036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4325780608012970697672799463219029539434608304853832180575146918879708602692 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.aon_timer_prescaler.4325780608012970697672799463219029539434608304853832180575146918879708602692
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.66727846106534593833509169535881544708313139712050376869850238923174838719468
Short name T22
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:35 PM PST 23
Finished Nov 22 01:17:37 PM PST 23
Peak memory 183228 kb
Host smart-c331bc21-8efc-44ef-94fa-60d50a8d3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66727846106534593833509169535881544708313139712050376869850238923174838719468 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.aon_timer_smoke.66727846106534593833509169535881544708313139712050376869850238923174838719468
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.52205962739035302273894318163558603673971225969992282172348544344242624976501
Short name T106
Test name
Test status
Simulation time 332628779192 ps
CPU time 304.24 seconds
Started Nov 22 01:17:59 PM PST 23
Finished Nov 22 01:23:11 PM PST 23
Peak memory 193364 kb
Host smart-583d8fa5-6eaf-4107-970d-e9d387077274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52205962739035302273894318163558603673971225969992282172348544344242624976501 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all.52205962739035302273894318163558603673971225969992282172348544344242624976501
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.65602313113808214292844110385963631408356298037442785868113179394240148509817
Short name T56
Test name
Test status
Simulation time 96759987586 ps
CPU time 435.05 seconds
Started Nov 22 01:18:59 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 198232 kb
Host smart-5aa8bc52-ee34-44bb-987a-42fcc65b8874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656023131138082142928
44110385963631408356298037442785868113179394240148509817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand
_reset.65602313113808214292844110385963631408356298037442785868113179394240148509817
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.49514437952085202492874103200376429889649510297067578090543964755616714887040
Short name T131
Test name
Test status
Simulation time 474704303 ps
CPU time 0.99 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 183280 kb
Host smart-9b6d6464-66e2-4cf3-9adc-f7778bcd9687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49514437952085202492874103200376429889649510297067578090543964755616714887040 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.aon_timer_jump.49514437952085202492874103200376429889649510297067578090543964755616714887040
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.4276619080685391073187493730360962927094792262739254807273686524076354800372
Short name T218
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.75 seconds
Started Nov 22 01:17:42 PM PST 23
Finished Nov 22 01:18:32 PM PST 23
Peak memory 183292 kb
Host smart-5316ba04-3855-4576-9667-641ef1e365cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276619080685391073187493730360962927094792262739254807273686524076354800372 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.aon_timer_prescaler.4276619080685391073187493730360962927094792262739254807273686524076354800372
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.104068693057924307357678452066016054707561872265163172874511557342694441260873
Short name T112
Test name
Test status
Simulation time 491168457 ps
CPU time 0.95 seconds
Started Nov 22 01:17:35 PM PST 23
Finished Nov 22 01:17:37 PM PST 23
Peak memory 183156 kb
Host smart-a89e04a8-2256-44e8-bec1-e4b8a09e8328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104068693057924307357678452066016054707561872265163172874511557342694441260873 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.aon_timer_smoke.104068693057924307357678452066016054707561872265163172874511557342694441260873
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.98122268352987291670383351101818576202706734187400668379269059808936124408537
Short name T105
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.75 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 193088 kb
Host smart-2165c1a7-ab80-4cb9-803b-699cc44a9196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98122268352987291670383351101818576202706734187400668379269059808936124408537 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all.98122268352987291670383351101818576202706734187400668379269059808936124408537
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.10242745146112901625090331963551465527477907398346568080869514928823030012714
Short name T253
Test name
Test status
Simulation time 96759987586 ps
CPU time 441.13 seconds
Started Nov 22 01:18:56 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 198156 kb
Host smart-1636cadf-7b26-48bd-bc1b-4c9c0c48763e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102427451461129016250
90331963551465527477907398346568080869514928823030012714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand
_reset.10242745146112901625090331963551465527477907398346568080869514928823030012714
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.109975087077469454832235020288591698549618691058731445082453409123219308929221
Short name T26
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:36 PM PST 23
Finished Nov 22 01:17:39 PM PST 23
Peak memory 183296 kb
Host smart-c1f4c199-4a27-42b7-90db-b08092f3bb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109975087077469454832235020288591698549618691058731445082453409123219308929221 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.aon_timer_jump.109975087077469454832235020288591698549618691058731445082453409123219308929221
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.113634254172902682590250335005144385555633901293512604249718699977559226748997
Short name T145
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.21 seconds
Started Nov 22 01:17:35 PM PST 23
Finished Nov 22 01:18:25 PM PST 23
Peak memory 183332 kb
Host smart-5b26a8bd-b0a3-4365-9bbb-9f428d4dac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113634254172902682590250335005144385555633901293512604249718699977559226748997 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.aon_timer_prescaler.113634254172902682590250335005144385555633901293512604249718699977559226748997
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.28887674232688397914136142107685780939511879262374921313268914205010728630413
Short name T42
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:33 PM PST 23
Finished Nov 22 01:17:36 PM PST 23
Peak memory 183248 kb
Host smart-1f55e1df-bdb2-402e-b4fb-52d90bd97772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28887674232688397914136142107685780939511879262374921313268914205010728630413 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.aon_timer_smoke.28887674232688397914136142107685780939511879262374921313268914205010728630413
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.861733545346570512514721872881550627467579256945375555766673778221977318195
Short name T111
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.84 seconds
Started Nov 22 01:17:26 PM PST 23
Finished Nov 22 01:22:33 PM PST 23
Peak memory 193464 kb
Host smart-e8575c92-e688-44d0-b37d-42a6b8371cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861733545346570512514721872881550627467579256945375555766673778221977318195 -assert nopostp
roc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all.861733545346570512514721872881550627467579256945375555766673778221977318195
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.12046521342798683714151977917882177195772470761671242992349225458734733952425
Short name T30
Test name
Test status
Simulation time 96759987586 ps
CPU time 415.21 seconds
Started Nov 22 01:17:37 PM PST 23
Finished Nov 22 01:24:34 PM PST 23
Peak memory 198064 kb
Host smart-ebe06115-4c35-47c7-bce9-a7100d5e0ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120465213427986837141
51977917882177195772470761671242992349225458734733952425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand
_reset.12046521342798683714151977917882177195772470761671242992349225458734733952425
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.25166412035202005871151382677599822188186607507408617432258628854282436680347
Short name T150
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:17:40 PM PST 23
Peak memory 183128 kb
Host smart-6ecbbdce-301b-4c36-9a4a-20949d6b1c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25166412035202005871151382677599822188186607507408617432258628854282436680347 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.aon_timer_jump.25166412035202005871151382677599822188186607507408617432258628854282436680347
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.5008576720955319926672478902486271426807214735448495131627516720401985958270
Short name T179
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.36 seconds
Started Nov 22 01:17:37 PM PST 23
Finished Nov 22 01:18:27 PM PST 23
Peak memory 183336 kb
Host smart-09f16565-300b-403f-ada3-c98e9ac2b14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5008576720955319926672478902486271426807214735448495131627516720401985958270 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.aon_timer_prescaler.5008576720955319926672478902486271426807214735448495131627516720401985958270
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.11209257622914157617302809209824672188100359011905543373891803125251648050310
Short name T246
Test name
Test status
Simulation time 491168457 ps
CPU time 1.03 seconds
Started Nov 22 01:17:59 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 181896 kb
Host smart-547033df-3fd5-4c76-9d16-b621bb2fb4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11209257622914157617302809209824672188100359011905543373891803125251648050310 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.aon_timer_smoke.11209257622914157617302809209824672188100359011905543373891803125251648050310
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.81139155776761385241637505577694696887683363225971116939024171017115361430015
Short name T192
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.6 seconds
Started Nov 22 01:18:47 PM PST 23
Finished Nov 22 01:23:51 PM PST 23
Peak memory 193628 kb
Host smart-929bba4d-4f87-4433-b6bb-a64bbe5f4bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81139155776761385241637505577694696887683363225971116939024171017115361430015 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all.81139155776761385241637505577694696887683363225971116939024171017115361430015
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.82590488399191486007697661540905883735465144793076524887999727193817807098801
Short name T44
Test name
Test status
Simulation time 96759987586 ps
CPU time 408.48 seconds
Started Nov 22 01:18:42 PM PST 23
Finished Nov 22 01:25:33 PM PST 23
Peak memory 195676 kb
Host smart-cc13b8cb-e19c-4af8-ac57-30ec48b57fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825904883991914860076
97661540905883735465144793076524887999727193817807098801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand
_reset.82590488399191486007697661540905883735465144793076524887999727193817807098801
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.86783601759247343799713658367386439176857513644026316483181458191838816298876
Short name T79
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:26 PM PST 23
Finished Nov 22 01:17:31 PM PST 23
Peak memory 183156 kb
Host smart-41e55eee-087d-4215-b813-d69c65638456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86783601759247343799713658367386439176857513644026316483181458191838816298876 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.aon_timer_jump.86783601759247343799713658367386439176857513644026316483181458191838816298876
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.74050905495804227295631589750461225758668030112505909539881337341846031182513
Short name T207
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.56 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:18:28 PM PST 23
Peak memory 183200 kb
Host smart-eb2ba210-cc20-43d8-ab59-1a29ffa42b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74050905495804227295631589750461225758668030112505909539881337341846031182513 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.aon_timer_prescaler.74050905495804227295631589750461225758668030112505909539881337341846031182513
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1523092296330858014098653948764801028646017494363279002530048648373219567957
Short name T247
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:42 PM PST 23
Finished Nov 22 01:17:44 PM PST 23
Peak memory 183064 kb
Host smart-bdba89cb-0469-467c-9d18-d1a34932e849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523092296330858014098653948764801028646017494363279002530048648373219567957 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.aon_timer_smoke.1523092296330858014098653948764801028646017494363279002530048648373219567957
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.86429766751830403990564501983634753925338786825917197302146808188925602476218
Short name T175
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.86 seconds
Started Nov 22 01:17:41 PM PST 23
Finished Nov 22 01:22:44 PM PST 23
Peak memory 193152 kb
Host smart-76c26208-0867-44dc-9f0a-09513f2b37e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86429766751830403990564501983634753925338786825917197302146808188925602476218 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all.86429766751830403990564501983634753925338786825917197302146808188925602476218
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.42751749466299533480141933270640210326321519100791696426790024448034970302276
Short name T108
Test name
Test status
Simulation time 96759987586 ps
CPU time 409.87 seconds
Started Nov 22 01:19:19 PM PST 23
Finished Nov 22 01:26:10 PM PST 23
Peak memory 198028 kb
Host smart-397e24ac-ba1d-4f81-8586-27e46bf2df66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427517494662995334801
41933270640210326321519100791696426790024448034970302276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand
_reset.42751749466299533480141933270640210326321519100791696426790024448034970302276
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.75622793923448268213983971355999598814571541305261039916755044317158983006339
Short name T107
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:17:42 PM PST 23
Peak memory 183064 kb
Host smart-a43c6256-b4d0-4185-9a33-007f49cf4782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75622793923448268213983971355999598814571541305261039916755044317158983006339 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.aon_timer_jump.75622793923448268213983971355999598814571541305261039916755044317158983006339
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.51754517988802230123204383490670959425769598562838279490411639617563502274451
Short name T51
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.59 seconds
Started Nov 22 01:17:44 PM PST 23
Finished Nov 22 01:18:33 PM PST 23
Peak memory 183268 kb
Host smart-6d784f78-1940-44ac-a15a-9274dd48db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51754517988802230123204383490670959425769598562838279490411639617563502274451 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.aon_timer_prescaler.51754517988802230123204383490670959425769598562838279490411639617563502274451
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.105408089462332595238621249434358455312385604274745445313139546579976369579374
Short name T135
Test name
Test status
Simulation time 491168457 ps
CPU time 1 seconds
Started Nov 22 01:17:59 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 182848 kb
Host smart-510e5222-01fd-43aa-996a-1d6b0d57bc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105408089462332595238621249434358455312385604274745445313139546579976369579374 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.aon_timer_smoke.105408089462332595238621249434358455312385604274745445313139546579976369579374
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.75096970312132610664745421854282097560747090233458602780160923268444313700382
Short name T263
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.25 seconds
Started Nov 22 01:17:45 PM PST 23
Finished Nov 22 01:22:48 PM PST 23
Peak memory 193432 kb
Host smart-03875e32-54b9-4c90-a9d4-868682411a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75096970312132610664745421854282097560747090233458602780160923268444313700382 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all.75096970312132610664745421854282097560747090233458602780160923268444313700382
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.80929317578250994263843673656428826221572780428963100052103802550312015343365
Short name T94
Test name
Test status
Simulation time 96759987586 ps
CPU time 419.47 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:25:57 PM PST 23
Peak memory 195936 kb
Host smart-759bf7da-ca0c-4245-b95f-c5396b4e968c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809293175782509942638
43673656428826221572780428963100052103802550312015343365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand
_reset.80929317578250994263843673656428826221572780428963100052103802550312015343365
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.96022903634257077295862555739371810066369401909072565656434692718954389266795
Short name T181
Test name
Test status
Simulation time 474704303 ps
CPU time 0.95 seconds
Started Nov 22 01:18:03 PM PST 23
Finished Nov 22 01:18:11 PM PST 23
Peak memory 183220 kb
Host smart-55261ebf-424a-4ad6-977d-5e29e0f752fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96022903634257077295862555739371810066369401909072565656434692718954389266795 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.aon_timer_jump.96022903634257077295862555739371810066369401909072565656434692718954389266795
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.30202090440315097650506354258742763417923111077801974705950836595714253859013
Short name T299
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.48 seconds
Started Nov 22 01:18:01 PM PST 23
Finished Nov 22 01:18:58 PM PST 23
Peak memory 183072 kb
Host smart-c8de0ee7-1abd-4c2a-9a15-e7eb3659363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30202090440315097650506354258742763417923111077801974705950836595714253859013 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.aon_timer_prescaler.30202090440315097650506354258742763417923111077801974705950836595714253859013
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.25830619642016873837987793453367440815863899464087470327325521842080617643803
Short name T97
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:58 PM PST 23
Finished Nov 22 01:18:05 PM PST 23
Peak memory 183284 kb
Host smart-db770aaa-6f2d-4b90-8cc0-075716a616ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25830619642016873837987793453367440815863899464087470327325521842080617643803 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.aon_timer_smoke.25830619642016873837987793453367440815863899464087470327325521842080617643803
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.102462443873601898136030988732115001941160579781170709362478844338142710096163
Short name T96
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.01 seconds
Started Nov 22 01:18:43 PM PST 23
Finished Nov 22 01:23:48 PM PST 23
Peak memory 193632 kb
Host smart-cd68284b-4759-49c0-ba53-17a57122d6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102462443873601898136030988732115001941160579781170709362478844338142710096163 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.102462443873601898136030988732115001941160579781170709362478844338142710096163
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.33183304584220722747196000627200202961359271050299229592158052220767674106625
Short name T224
Test name
Test status
Simulation time 96759987586 ps
CPU time 420.32 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 196268 kb
Host smart-13011a18-a775-40ba-8cd6-fffd9e5f78fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331833045842207227471
96000627200202961359271050299229592158052220767674106625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand
_reset.33183304584220722747196000627200202961359271050299229592158052220767674106625
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.83695999323632178581780888451961278423973657429866870181744786547728294931215
Short name T81
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:17:41 PM PST 23
Peak memory 183288 kb
Host smart-851b1ff4-a7ab-4751-b8d7-fda2f9fa8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83695999323632178581780888451961278423973657429866870181744786547728294931215 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.aon_timer_jump.83695999323632178581780888451961278423973657429866870181744786547728294931215
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1022610253470561821857571145932572078622059722482086385137956768343049607164
Short name T274
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.89 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 180740 kb
Host smart-b9b81645-ead5-4680-b415-7b4892b1a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022610253470561821857571145932572078622059722482086385137956768343049607164 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 47.aon_timer_prescaler.1022610253470561821857571145932572078622059722482086385137956768343049607164
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4655181390173660631452665185704718153873218267841427329154295809084275349076
Short name T122
Test name
Test status
Simulation time 491168457 ps
CPU time 1 seconds
Started Nov 22 01:17:45 PM PST 23
Finished Nov 22 01:17:47 PM PST 23
Peak memory 183236 kb
Host smart-dccd5378-e40b-4329-9d44-296a1fd6e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4655181390173660631452665185704718153873218267841427329154295809084275349076 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.aon_timer_smoke.4655181390173660631452665185704718153873218267841427329154295809084275349076
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.45864846124623543306526543601784796272396231117193967290067404263715394940454
Short name T132
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.81 seconds
Started Nov 22 01:17:45 PM PST 23
Finished Nov 22 01:22:50 PM PST 23
Peak memory 193608 kb
Host smart-62f4e7e4-20ed-4d5d-8d04-3333cad43e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45864846124623543306526543601784796272396231117193967290067404263715394940454 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all.45864846124623543306526543601784796272396231117193967290067404263715394940454
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.36296789979727103814574508872750390744554669669835524513074417706201063673891
Short name T155
Test name
Test status
Simulation time 96759987586 ps
CPU time 440.36 seconds
Started Nov 22 01:17:40 PM PST 23
Finished Nov 22 01:25:02 PM PST 23
Peak memory 198212 kb
Host smart-c24d0f83-b1e5-4502-ace2-440b2d9a3039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362967899797271038145
74508872750390744554669669835524513074417706201063673891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand
_reset.36296789979727103814574508872750390744554669669835524513074417706201063673891
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.39620088034790953639360339633157670728639855452486396260841819273092320979424
Short name T188
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:17:43 PM PST 23
Finished Nov 22 01:17:45 PM PST 23
Peak memory 183268 kb
Host smart-ae366fa3-2a65-47a2-af19-9d88bab3c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39620088034790953639360339633157670728639855452486396260841819273092320979424 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.aon_timer_jump.39620088034790953639360339633157670728639855452486396260841819273092320979424
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.112368471807511073116716813185426108036630302021893521473811992293862713125261
Short name T46
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.72 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:19:47 PM PST 23
Peak memory 180832 kb
Host smart-4e2842c0-1c44-41f8-b8f5-0a75e06713ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112368471807511073116716813185426108036630302021893521473811992293862713125261 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.aon_timer_prescaler.112368471807511073116716813185426108036630302021893521473811992293862713125261
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.23919068424701038239496473010554190426419948554409373055366803330096445762190
Short name T153
Test name
Test status
Simulation time 491168457 ps
CPU time 0.96 seconds
Started Nov 22 01:17:44 PM PST 23
Finished Nov 22 01:17:46 PM PST 23
Peak memory 183272 kb
Host smart-b4f73f5d-efe7-48ab-8944-07a9f2e85d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23919068424701038239496473010554190426419948554409373055366803330096445762190 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.aon_timer_smoke.23919068424701038239496473010554190426419948554409373055366803330096445762190
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.43467466607300688151464749740222974295944916121051967974243617193990683947281
Short name T168
Test name
Test status
Simulation time 332628779192 ps
CPU time 306.25 seconds
Started Nov 22 01:17:59 PM PST 23
Finished Nov 22 01:23:13 PM PST 23
Peak memory 192280 kb
Host smart-121cd8ee-b157-4694-814c-722ab4bec9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43467466607300688151464749740222974295944916121051967974243617193990683947281 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.43467466607300688151464749740222974295944916121051967974243617193990683947281
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.69690461490096249202072428967903757244271146770321421391149321939516822147115
Short name T238
Test name
Test status
Simulation time 96759987586 ps
CPU time 430.47 seconds
Started Nov 22 01:17:47 PM PST 23
Finished Nov 22 01:24:59 PM PST 23
Peak memory 198220 kb
Host smart-77327ef6-e1f8-490e-9bde-50e0b6b7e640
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696904614900962492020
72428967903757244271146770321421391149321939516822147115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand
_reset.69690461490096249202072428967903757244271146770321421391149321939516822147115
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.15649710656457864000242883676307658840354655260130613021752541695974353487152
Short name T123
Test name
Test status
Simulation time 474704303 ps
CPU time 1 seconds
Started Nov 22 01:17:59 PM PST 23
Finished Nov 22 01:18:08 PM PST 23
Peak memory 182872 kb
Host smart-e0f3e05b-aac5-4f41-bc55-96635fbd0dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15649710656457864000242883676307658840354655260130613021752541695974353487152 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.aon_timer_jump.15649710656457864000242883676307658840354655260130613021752541695974353487152
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.7472711651754188496559301941393230784647309147767986730407893935799321482114
Short name T167
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.36 seconds
Started Nov 22 01:18:30 PM PST 23
Finished Nov 22 01:19:21 PM PST 23
Peak memory 183392 kb
Host smart-92ae271e-725c-4106-b026-28f009c471eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7472711651754188496559301941393230784647309147767986730407893935799321482114 -assert nopostproc +UVM_TESTNAME=aon_timer_
base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.aon_timer_prescaler.7472711651754188496559301941393230784647309147767986730407893935799321482114
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.93685634621029980699553464442188976849707598390370183302943359299509379921704
Short name T125
Test name
Test status
Simulation time 491168457 ps
CPU time 1.22 seconds
Started Nov 22 01:18:55 PM PST 23
Finished Nov 22 01:18:59 PM PST 23
Peak memory 180648 kb
Host smart-6af347c9-ca37-4de4-bf99-dead966e5f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93685634621029980699553464442188976849707598390370183302943359299509379921704 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.aon_timer_smoke.93685634621029980699553464442188976849707598390370183302943359299509379921704
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.57284878090933266027674739259542108585163282190337697034040244547632890867591
Short name T144
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.79 seconds
Started Nov 22 01:17:58 PM PST 23
Finished Nov 22 01:23:08 PM PST 23
Peak memory 193644 kb
Host smart-7df41655-6bff-49d9-b12d-bc16f0ead892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57284878090933266027674739259542108585163282190337697034040244547632890867591 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all.57284878090933266027674739259542108585163282190337697034040244547632890867591
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.74393635893933642095572393840533706262946995815470576650178858666975438894203
Short name T284
Test name
Test status
Simulation time 96759987586 ps
CPU time 426.93 seconds
Started Nov 22 01:17:38 PM PST 23
Finished Nov 22 01:24:46 PM PST 23
Peak memory 198192 kb
Host smart-bd40aa70-7db0-4acd-a379-a7022dbc6d72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743936358939336420955
72393840533706262946995815470576650178858666975438894203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand
_reset.74393635893933642095572393840533706262946995815470576650178858666975438894203
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.106652297700436306942998642347609682480213776046145561141751164060640775435111
Short name T24
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:06 PM PST 23
Peak memory 183264 kb
Host smart-d8277fea-bc22-46a8-992f-f63795bb611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106652297700436306942998642347609682480213776046145561141751164060640775435111 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.aon_timer_jump.106652297700436306942998642347609682480213776046145561141751164060640775435111
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.115463668560179446756461775285999141505730716565797208857206630008416708471300
Short name T50
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.35 seconds
Started Nov 22 01:16:51 PM PST 23
Finished Nov 22 01:17:49 PM PST 23
Peak memory 183328 kb
Host smart-d101f045-940e-4f2b-a5a2-134e75737426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115463668560179446756461775285999141505730716565797208857206630008416708471300 -assert nopostproc +UVM_TESTNAME=aon_time
r_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.aon_timer_prescaler.115463668560179446756461775285999141505730716565797208857206630008416708471300
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.51822313847887190702976123876274000352012714032438064686641920841759086391483
Short name T230
Test name
Test status
Simulation time 491168457 ps
CPU time 0.98 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:16:54 PM PST 23
Peak memory 183272 kb
Host smart-22f55141-22f6-4f81-a536-a5cfcae12e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51822313847887190702976123876274000352012714032438064686641920841759086391483 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.aon_timer_smoke.51822313847887190702976123876274000352012714032438064686641920841759086391483
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.58479270697380768617388111229945920545467881988571120733936856651397479082821
Short name T147
Test name
Test status
Simulation time 332628779192 ps
CPU time 301.66 seconds
Started Nov 22 01:16:50 PM PST 23
Finished Nov 22 01:21:59 PM PST 23
Peak memory 193604 kb
Host smart-e0006c5c-0d81-4541-97bc-3cbcce55307c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58479270697380768617388111229945920545467881988571120733936856651397479082821 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all.58479270697380768617388111229945920545467881988571120733936856651397479082821
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.53358710010191023286509155986872825226336579284672440106616799233543424571052
Short name T205
Test name
Test status
Simulation time 96759987586 ps
CPU time 425.16 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:23:57 PM PST 23
Peak memory 198208 kb
Host smart-f7030136-a650-4d0c-a7f0-ef2172967f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533587100101910232865
09155986872825226336579284672440106616799233543424571052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_
reset.53358710010191023286509155986872825226336579284672440106616799233543424571052
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.92581788399943690769984120447711306889526783735558398568756249692423460724335
Short name T240
Test name
Test status
Simulation time 474704303 ps
CPU time 1.04 seconds
Started Nov 22 01:16:52 PM PST 23
Finished Nov 22 01:17:07 PM PST 23
Peak memory 183224 kb
Host smart-5b5ad0f6-0647-42ab-b98b-4e447f8e30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92581788399943690769984120447711306889526783735558398568756249692423460724335 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.aon_timer_jump.92581788399943690769984120447711306889526783735558398568756249692423460724335
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.91064675492692977690985119477899629139611804626879915180625328699792890162177
Short name T128
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.4 seconds
Started Nov 22 01:16:48 PM PST 23
Finished Nov 22 01:17:40 PM PST 23
Peak memory 183372 kb
Host smart-61e8c019-b30c-47aa-852e-015bd9d5962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91064675492692977690985119477899629139611804626879915180625328699792890162177 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.aon_timer_prescaler.91064675492692977690985119477899629139611804626879915180625328699792890162177
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.41781401423873060751284140322880319604793736330586229842371693225042515456973
Short name T45
Test name
Test status
Simulation time 491168457 ps
CPU time 1.03 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 183136 kb
Host smart-90c62bbe-b4a8-4d2a-9ac3-60006eb916a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41781401423873060751284140322880319604793736330586229842371693225042515456973 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.aon_timer_smoke.41781401423873060751284140322880319604793736330586229842371693225042515456973
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.82982801167898944858563910695459014032889051175169352481033774961192861106127
Short name T174
Test name
Test status
Simulation time 332628779192 ps
CPU time 303.98 seconds
Started Nov 22 01:17:10 PM PST 23
Finished Nov 22 01:22:21 PM PST 23
Peak memory 193496 kb
Host smart-dbb0d968-b3c1-4b73-82dd-50f90b495953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82982801167898944858563910695459014032889051175169352481033774961192861106127 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all.82982801167898944858563910695459014032889051175169352481033774961192861106127
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.15622146952906284263299398176214864500429166691120438378813186473897027826507
Short name T201
Test name
Test status
Simulation time 96759987586 ps
CPU time 437.34 seconds
Started Nov 22 01:17:14 PM PST 23
Finished Nov 22 01:24:37 PM PST 23
Peak memory 198228 kb
Host smart-44d662df-9e49-4c20-b8c8-2273b30f21c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156221469529062842632
99398176214864500429166691120438378813186473897027826507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_
reset.15622146952906284263299398176214864500429166691120438378813186473897027826507
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.84822489414304901831007589577689539677108125868480932470942116335510502272934
Short name T237
Test name
Test status
Simulation time 474704303 ps
CPU time 1.01 seconds
Started Nov 22 01:17:15 PM PST 23
Finished Nov 22 01:17:22 PM PST 23
Peak memory 183128 kb
Host smart-5c3170a0-beed-4a80-a193-d932b0843ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84822489414304901831007589577689539677108125868480932470942116335510502272934 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.aon_timer_jump.84822489414304901831007589577689539677108125868480932470942116335510502272934
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.10140063894787450388725934152162675906015339825566442114059817849483820099389
Short name T104
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.55 seconds
Started Nov 22 01:16:54 PM PST 23
Finished Nov 22 01:17:57 PM PST 23
Peak memory 183236 kb
Host smart-947a4fe3-dd10-4a84-b392-39186cb8d68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10140063894787450388725934152162675906015339825566442114059817849483820099389 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.aon_timer_prescaler.10140063894787450388725934152162675906015339825566442114059817849483820099389
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.98505323894329614202263106839436777575441136627808708851771448653041264784473
Short name T83
Test name
Test status
Simulation time 491168457 ps
CPU time 1.03 seconds
Started Nov 22 01:16:54 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183156 kb
Host smart-7293837b-4cef-4e4c-a177-8e3fb870255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98505323894329614202263106839436777575441136627808708851771448653041264784473 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.aon_timer_smoke.98505323894329614202263106839436777575441136627808708851771448653041264784473
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.38633319270485414073224939540147756899224117965767931138608447740955994402038
Short name T138
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.55 seconds
Started Nov 22 01:17:09 PM PST 23
Finished Nov 22 01:22:19 PM PST 23
Peak memory 193492 kb
Host smart-36ddf5c5-88f5-48ba-88be-1cd79c36a576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38633319270485414073224939540147756899224117965767931138608447740955994402038 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all.38633319270485414073224939540147756899224117965767931138608447740955994402038
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.7517279845581310492992445827614039227330000572246512942875424892843024267547
Short name T276
Test name
Test status
Simulation time 96759987586 ps
CPU time 427.22 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:24:16 PM PST 23
Peak memory 198236 kb
Host smart-8ac4bc5f-3dfd-43e7-a42e-fa2426c88ba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751727984558131049299
2445827614039227330000572246512942875424892843024267547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_r
eset.7517279845581310492992445827614039227330000572246512942875424892843024267547
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.86906849876999428532755572807126660869677009513633394906577346354129189534541
Short name T212
Test name
Test status
Simulation time 474704303 ps
CPU time 0.96 seconds
Started Nov 22 01:17:09 PM PST 23
Finished Nov 22 01:17:17 PM PST 23
Peak memory 183272 kb
Host smart-e45c37c6-b9a7-4498-9f31-cb11e0065dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86906849876999428532755572807126660869677009513633394906577346354129189534541 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.aon_timer_jump.86906849876999428532755572807126660869677009513633394906577346354129189534541
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.32432610364584676301055764014605502549077062900096123617649720358928966822557
Short name T203
Test name
Test status
Simulation time 53247692830 ps
CPU time 48.56 seconds
Started Nov 22 01:17:01 PM PST 23
Finished Nov 22 01:18:01 PM PST 23
Peak memory 183308 kb
Host smart-4acee7ed-e94c-441b-a1fe-f4350eb7b5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32432610364584676301055764014605502549077062900096123617649720358928966822557 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.aon_timer_prescaler.32432610364584676301055764014605502549077062900096123617649720358928966822557
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.68093771347246435280635929157554172978851932388219703471218392542761596651375
Short name T278
Test name
Test status
Simulation time 491168457 ps
CPU time 0.99 seconds
Started Nov 22 01:17:32 PM PST 23
Finished Nov 22 01:17:35 PM PST 23
Peak memory 183256 kb
Host smart-e645b40b-9efb-42bb-831d-a16107793884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68093771347246435280635929157554172978851932388219703471218392542761596651375 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.aon_timer_smoke.68093771347246435280635929157554172978851932388219703471218392542761596651375
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.94734134100895204189717337172894298799740158939973422465731393701393885876432
Short name T280
Test name
Test status
Simulation time 332628779192 ps
CPU time 302.6 seconds
Started Nov 22 01:17:23 PM PST 23
Finished Nov 22 01:22:29 PM PST 23
Peak memory 193628 kb
Host smart-eab0e4d0-efa6-49be-ad4b-a7e32a1c370c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94734134100895204189717337172894298799740158939973422465731393701393885876432 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all.94734134100895204189717337172894298799740158939973422465731393701393885876432
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.52531228523716694998225591440315427053146389135450686533441395344106761508341
Short name T88
Test name
Test status
Simulation time 96759987586 ps
CPU time 439.49 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:24:26 PM PST 23
Peak memory 198224 kb
Host smart-3bd67e66-dc2a-4439-a38a-b0e625e75ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525312285237166949982
25591440315427053146389135450686533441395344106761508341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_
reset.52531228523716694998225591440315427053146389135450686533441395344106761508341
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.92258487129047278879630029154359982173342289162124685083915717633502794745622
Short name T269
Test name
Test status
Simulation time 474704303 ps
CPU time 0.97 seconds
Started Nov 22 01:16:53 PM PST 23
Finished Nov 22 01:17:09 PM PST 23
Peak memory 183288 kb
Host smart-3b19737f-5227-46ba-a1cf-2038141c7c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92258487129047278879630029154359982173342289162124685083915717633502794745622 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.aon_timer_jump.92258487129047278879630029154359982173342289162124685083915717633502794745622
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.32392012992655522041140909373305436163273056067643738842653496506823873825357
Short name T217
Test name
Test status
Simulation time 53247692830 ps
CPU time 49.12 seconds
Started Nov 22 01:16:58 PM PST 23
Finished Nov 22 01:17:58 PM PST 23
Peak memory 183292 kb
Host smart-d6bb5db8-c26a-4884-a613-9ed1210f3271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32392012992655522041140909373305436163273056067643738842653496506823873825357 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.aon_timer_prescaler.32392012992655522041140909373305436163273056067643738842653496506823873825357
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.12560989075002612137533947150984677629947421500200210406815996496332332689140
Short name T116
Test name
Test status
Simulation time 491168457 ps
CPU time 0.97 seconds
Started Nov 22 01:17:31 PM PST 23
Finished Nov 22 01:17:33 PM PST 23
Peak memory 183200 kb
Host smart-d51b17ac-f96b-49ce-9d39-e783516675cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12560989075002612137533947150984677629947421500200210406815996496332332689140 -assert nopostproc +UVM_TESTNAME=aon_timer
_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.aon_timer_smoke.12560989075002612137533947150984677629947421500200210406815996496332332689140
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.98158912835782490152115285934251256399345417510657321375476052589939100334700
Short name T152
Test name
Test status
Simulation time 332628779192 ps
CPU time 300.08 seconds
Started Nov 22 01:17:22 PM PST 23
Finished Nov 22 01:22:27 PM PST 23
Peak memory 193580 kb
Host smart-4488092f-cad9-40fc-a629-ec2337074fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158912835782490152115285934251256399345417510657321375476052589939100334700 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all.98158912835782490152115285934251256399345417510657321375476052589939100334700
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.103790884294613523008220317654848759486231870492713438929999230219493496364133
Short name T289
Test name
Test status
Simulation time 96759987586 ps
CPU time 422.28 seconds
Started Nov 22 01:17:01 PM PST 23
Finished Nov 22 01:24:15 PM PST 23
Peak memory 198148 kb
Host smart-5d785a51-e8b0-4e4d-8478-8309f8010181
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103790884294613523008
220317654848759486231870492713438929999230219493496364133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand
_reset.103790884294613523008220317654848759486231870492713438929999230219493496364133
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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