Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.16 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 4 137 97.16


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 0 34 100.00 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 26159 1 T6 151 T18 11 T19 224
bark[1] 417 1 T19 16 T20 17 T36 12
bark[2] 922 1 T27 142 T97 13 T98 12
bark[3] 499 1 T19 183 T99 16 T100 16
bark[4] 547 1 T27 82 T101 16 T102 16
bark[5] 233 1 T49 21 T103 12 T104 22
bark[6] 418 1 T105 12 T55 17 T106 31
bark[7] 313 1 T101 46 T107 12 T108 31
bark[8] 571 1 T43 16 T47 22 T109 16
bark[9] 519 1 T110 22 T103 47 T87 21
bark[10] 781 1 T50 222 T55 37 T111 17
bark[11] 775 1 T112 45 T113 1 T114 26
bark[12] 1015 1 T19 35 T27 16 T115 13
bark[13] 164 1 T17 12 T42 16 T101 31
bark[14] 345 1 T102 32 T116 16 T88 16
bark[15] 526 1 T101 17 T105 16 T52 16
bark[16] 662 1 T19 52 T20 16 T103 16
bark[17] 359 1 T47 16 T117 17 T52 27
bark[18] 370 1 T22 16 T27 17 T47 16
bark[19] 232 1 T6 30 T105 16 T118 16
bark[20] 218 1 T6 25 T119 17 T116 16
bark[21] 301 1 T120 16 T121 12 T122 22
bark[22] 510 1 T22 16 T103 30 T100 26
bark[23] 646 1 T22 16 T44 12 T101 12
bark[24] 991 1 T101 22 T123 13 T51 65
bark[25] 160 1 T103 31 T124 12 T102 32
bark[26] 387 1 T26 13 T125 12 T50 201
bark[27] 594 1 T101 16 T126 12 T127 12
bark[28] 532 1 T6 16 T50 59 T117 17
bark[29] 785 1 T109 16 T128 131 T129 67
bark[30] 284 1 T19 12 T100 17 T130 16
bark[31] 951 1 T20 22 T42 16 T58 12
bark_0 3422 1 T7 6 T13 5 T14 6


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 26019 1 T6 129 T18 10 T19 219
bite[1] 454 1 T106 16 T121 11 T131 11
bite[2] 291 1 T19 11 T109 16 T132 196
bite[3] 302 1 T115 12 T49 20 T50 106
bite[4] 368 1 T22 16 T99 16 T101 11
bite[5] 463 1 T19 16 T47 47 T106 31
bite[6] 966 1 T22 16 T103 31 T109 84
bite[7] 567 1 T105 11 T50 93 T127 11
bite[8] 382 1 T105 16 T103 16 T88 32
bite[9] 279 1 T17 11 T27 141 T123 12
bite[10] 448 1 T27 33 T52 16 T87 20
bite[11] 795 1 T109 36 T128 147 T116 16
bite[12] 564 1 T19 182 T58 11 T105 16
bite[13] 327 1 T42 16 T50 26 T51 17
bite[14] 1383 1 T111 37 T88 16 T122 412
bite[15] 193 1 T101 16 T105 16 T133 16
bite[16] 161 1 T6 30 T101 16 T119 17
bite[17] 514 1 T6 25 T19 34 T22 16
bite[18] 426 1 T47 16 T117 17 T102 16
bite[19] 662 1 T100 16 T134 11 T122 172
bite[20] 462 1 T6 21 T47 16 T50 58
bite[21] 150 1 T20 22 T125 11 T117 17
bite[22] 141 1 T135 16 T90 3 T136 11
bite[23] 570 1 T20 16 T51 64 T107 11
bite[24] 357 1 T26 12 T119 16 T110 35
bite[25] 843 1 T20 17 T50 221 T128 5
bite[26] 225 1 T42 16 T101 77 T39 11
bite[27] 956 1 T19 51 T27 86 T105 16
bite[28] 702 1 T42 31 T44 11 T103 30
bite[29] 326 1 T111 102 T129 16 T137 12
bite[30] 602 1 T43 16 T101 17 T110 111
bite[31] 762 1 T6 16 T99 22 T47 21
bite_0 3948 1 T7 6 T13 5 T14 6


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 45608 1 T7 6 T13 5 T14 6


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 0 34 100.00


User Defined Bins for prescale_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale_max 31 1 T138 31 - - - -
prescale[0] 888 1 T18 8 T119 18 T51 18
prescale[1] 787 1 T19 76 T43 15 T105 32
prescale[2] 618 1 T6 15 T21 8 T27 8
prescale[3] 874 1 T6 15 T19 59 T51 2
prescale[4] 450 1 T19 2 T42 31 T139 2
prescale[5] 491 1 T51 15 T87 15 T100 18
prescale[6] 816 1 T49 2 T119 20 T140 8
prescale[7] 898 1 T19 2 T105 60 T106 34
prescale[8] 826 1 T19 2 T101 18 T49 27
prescale[9] 712 1 T27 15 T50 15 T51 2
prescale[10] 615 1 T141 8 T51 45 T118 68
prescale[11] 996 1 T19 2 T22 47 T27 50
prescale[12] 754 1 T27 2 T51 45 T120 45
prescale[13] 417 1 T22 18 T42 15 T47 18
prescale[14] 646 1 T22 15 T27 123 T43 29
prescale[15] 678 1 T27 15 T42 25 T103 18
prescale[16] 853 1 T6 8 T20 49 T27 57
prescale[17] 530 1 T6 15 T47 31 T50 2
prescale[18] 534 1 T6 15 T142 8 T49 2
prescale[19] 500 1 T22 15 T47 59 T50 94
prescale[20] 666 1 T117 15 T55 31 T111 100
prescale[21] 611 1 T42 8 T49 2 T51 45
prescale[22] 568 1 T42 29 T119 15 T52 90
prescale[23] 618 1 T6 31 T47 15 T51 50
prescale[24] 257 1 T103 20 T111 6 T109 2
prescale[25] 894 1 T19 2 T27 2 T50 2
prescale[26] 450 1 T19 2 T50 37 T52 2
prescale[27] 448 1 T27 9 T42 24 T103 32
prescale[28] 688 1 T27 15 T99 34 T50 178
prescale[29] 688 1 T99 8 T49 2 T55 17
prescale[30] 766 1 T42 15 T143 8 T50 2
prescale[31] 968 1 T47 18 T50 2 T51 75
prescale_0 24103 1 T7 6 T13 5 T14 6


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33633 1 T7 6 T13 5 T14 6
auto[1] 11975 1 T6 39 T26 11 T18 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 45608 1 T7 6 T13 5 T14 6


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 26811 1 T6 129 T18 12 T19 281
wkup[1] 630 1 T101 22 T49 16 T50 13
wkup[2] 502 1 T6 16 T42 16 T51 17
wkup[3] 598 1 T43 16 T50 48 T107 13
wkup[4] 649 1 T19 13 T20 39 T50 16
wkup[5] 621 1 T19 16 T27 32 T111 16
wkup[6] 364 1 T101 16 T47 16 T50 16
wkup[7] 637 1 T19 32 T49 16 T110 22
wkup[8] 399 1 T26 14 T101 33 T105 16
wkup[9] 469 1 T19 16 T58 13 T99 22
wkup[10] 509 1 T19 16 T101 16 T50 16
wkup[11] 483 1 T27 16 T43 21 T50 58
wkup[12] 458 1 T27 16 T43 16 T101 13
wkup[13] 368 1 T22 16 T27 16 T51 16
wkup[14] 334 1 T19 48 T87 16 T118 23
wkup[15] 498 1 T27 16 T99 16 T50 16
wkup[16] 502 1 T19 13 T101 16 T51 16
wkup[17] 462 1 T103 16 T87 17 T127 13
wkup[18] 557 1 T19 16 T42 16 T50 32
wkup[19] 662 1 T27 17 T99 16 T51 22
wkup[20] 606 1 T6 16 T19 32 T27 16
wkup[21] 365 1 T19 17 T47 16 T103 16
wkup[22] 658 1 T6 16 T19 16 T20 16
wkup[23] 360 1 T6 25 T17 13 T27 16
wkup[24] 566 1 T19 16 T50 21 T106 16
wkup[25] 563 1 T22 16 T51 32 T103 13
wkup[26] 474 1 T6 21 T123 14 T50 48
wkup[27] 463 1 T105 29 T50 40 T111 22
wkup[28] 549 1 T101 16 T47 16 T105 16
wkup[29] 500 1 T22 16 T42 16 T51 17
wkup[30] 550 1 T44 13 T47 23 T51 7
wkup[31] 516 1 T20 33 T125 13 T119 17
wkup_0 2925 1 T7 6 T13 5 T14 6

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