Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.61 99.82 95.32 100.00 99.35 100.00 97.16


Total test records in report: 429
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T283 /workspace/coverage/default/31.aon_timer_smoke.319307983 Dec 20 12:21:34 PM PST 23 Dec 20 12:21:50 PM PST 23 376225077 ps
T284 /workspace/coverage/default/43.aon_timer_prescaler.2939548787 Dec 20 12:21:35 PM PST 23 Dec 20 12:21:58 PM PST 23 21163957396 ps
T285 /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3255862461 Dec 20 12:20:38 PM PST 23 Dec 20 12:31:30 PM PST 23 116451437759 ps
T286 /workspace/coverage/default/42.aon_timer_jump.4160378272 Dec 20 12:20:56 PM PST 23 Dec 20 12:21:03 PM PST 23 464047334 ps
T287 /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3019804934 Dec 20 12:20:35 PM PST 23 Dec 20 12:29:57 PM PST 23 212107658799 ps
T288 /workspace/coverage/default/39.aon_timer_prescaler.2908535893 Dec 20 12:20:37 PM PST 23 Dec 20 12:20:52 PM PST 23 24763249005 ps
T289 /workspace/coverage/default/3.aon_timer_smoke.1866555557 Dec 20 12:21:44 PM PST 23 Dec 20 12:21:59 PM PST 23 502851067 ps
T290 /workspace/coverage/default/33.aon_timer_smoke.156502909 Dec 20 12:20:24 PM PST 23 Dec 20 12:20:29 PM PST 23 576024459 ps
T291 /workspace/coverage/default/2.aon_timer_jump.3928622774 Dec 20 12:20:41 PM PST 23 Dec 20 12:20:47 PM PST 23 416151250 ps
T292 /workspace/coverage/default/27.aon_timer_jump.1662213002 Dec 20 12:20:48 PM PST 23 Dec 20 12:20:55 PM PST 23 455366660 ps
T293 /workspace/coverage/default/46.aon_timer_stress_all.4268420201 Dec 20 12:20:44 PM PST 23 Dec 20 12:21:30 PM PST 23 51997899147 ps
T294 /workspace/coverage/default/6.aon_timer_prescaler.3452345535 Dec 20 12:21:13 PM PST 23 Dec 20 12:21:35 PM PST 23 2180554320 ps
T60 /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3314569117 Dec 20 12:21:08 PM PST 23 Dec 20 12:27:40 PM PST 23 36064798479 ps
T295 /workspace/coverage/default/13.aon_timer_smoke.2238996607 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:17 PM PST 23 513555382 ps
T32 /workspace/coverage/default/3.aon_timer_sec_cm.2969236276 Dec 20 12:21:29 PM PST 23 Dec 20 12:21:49 PM PST 23 8255084193 ps
T296 /workspace/coverage/default/26.aon_timer_prescaler.1274750783 Dec 20 12:20:19 PM PST 23 Dec 20 12:20:22 PM PST 23 5840018137 ps
T297 /workspace/coverage/default/8.aon_timer_jump.3366497875 Dec 20 12:21:18 PM PST 23 Dec 20 12:21:39 PM PST 23 391888920 ps
T298 /workspace/coverage/default/13.aon_timer_jump.4047362936 Dec 20 12:21:09 PM PST 23 Dec 20 12:21:22 PM PST 23 594406657 ps
T299 /workspace/coverage/default/32.aon_timer_smoke.1226481983 Dec 20 12:20:57 PM PST 23 Dec 20 12:21:05 PM PST 23 459747243 ps
T300 /workspace/coverage/default/18.aon_timer_prescaler.2034882194 Dec 20 12:21:13 PM PST 23 Dec 20 12:22:22 PM PST 23 35258766313 ps
T301 /workspace/coverage/default/49.aon_timer_stress_all.3867840653 Dec 20 12:20:36 PM PST 23 Dec 20 12:21:36 PM PST 23 131677762269 ps
T302 /workspace/coverage/default/14.aon_timer_jump.3144013676 Dec 20 12:21:08 PM PST 23 Dec 20 12:21:21 PM PST 23 544880157 ps
T303 /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1620801304 Dec 20 12:21:38 PM PST 23 Dec 20 12:26:33 PM PST 23 367449695692 ps
T304 /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3377392687 Dec 20 12:21:34 PM PST 23 Dec 20 12:31:16 PM PST 23 300461592040 ps
T305 /workspace/coverage/default/38.aon_timer_jump.3137840234 Dec 20 12:20:34 PM PST 23 Dec 20 12:20:39 PM PST 23 525091757 ps
T306 /workspace/coverage/default/46.aon_timer_prescaler.3880130732 Dec 20 12:21:00 PM PST 23 Dec 20 12:22:07 PM PST 23 36006729578 ps
T307 /workspace/coverage/default/17.aon_timer_prescaler.151675543 Dec 20 12:21:32 PM PST 23 Dec 20 12:21:59 PM PST 23 14009265382 ps
T33 /workspace/coverage/default/4.aon_timer_sec_cm.2391872696 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:23 PM PST 23 4387200159 ps
T308 /workspace/coverage/default/37.aon_timer_prescaler.539710474 Dec 20 12:20:33 PM PST 23 Dec 20 12:21:06 PM PST 23 36320673487 ps
T309 /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3082601113 Dec 20 12:21:12 PM PST 23 Dec 20 12:31:47 PM PST 23 65016422275 ps
T310 /workspace/coverage/default/33.aon_timer_prescaler.3455518420 Dec 20 12:20:34 PM PST 23 Dec 20 12:20:57 PM PST 23 22288375917 ps
T311 /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.811445407 Dec 20 12:21:10 PM PST 23 Dec 20 12:29:43 PM PST 23 51890041064 ps
T312 /workspace/coverage/default/25.aon_timer_stress_all.909831122 Dec 20 12:20:20 PM PST 23 Dec 20 12:20:33 PM PST 23 18512172326 ps
T313 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.37021620 Dec 20 12:20:14 PM PST 23 Dec 20 12:20:17 PM PST 23 319244546 ps
T314 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.540233641 Dec 20 12:21:02 PM PST 23 Dec 20 12:21:13 PM PST 23 337152150 ps
T80 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3636001766 Dec 20 12:21:04 PM PST 23 Dec 20 12:21:16 PM PST 23 2291365087 ps
T315 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4134920336 Dec 20 12:19:58 PM PST 23 Dec 20 12:20:02 PM PST 23 490619401 ps
T316 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1759642918 Dec 20 12:20:31 PM PST 23 Dec 20 12:20:38 PM PST 23 681645418 ps
T317 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3983734602 Dec 20 12:21:08 PM PST 23 Dec 20 12:21:22 PM PST 23 386579364 ps
T318 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2103654861 Dec 20 12:21:04 PM PST 23 Dec 20 12:21:13 PM PST 23 470543627 ps
T319 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1713852036 Dec 20 12:19:43 PM PST 23 Dec 20 12:19:45 PM PST 23 737331483 ps
T320 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1134022767 Dec 20 12:20:22 PM PST 23 Dec 20 12:20:26 PM PST 23 521094429 ps
T321 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3885522327 Dec 20 12:20:30 PM PST 23 Dec 20 12:20:35 PM PST 23 339670131 ps
T81 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2448349236 Dec 20 12:21:00 PM PST 23 Dec 20 12:21:10 PM PST 23 1194169689 ps
T322 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2912660820 Dec 20 12:21:12 PM PST 23 Dec 20 12:21:29 PM PST 23 467959899 ps
T95 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2030069890 Dec 20 12:20:33 PM PST 23 Dec 20 12:20:41 PM PST 23 5180045295 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3946612583 Dec 20 12:21:09 PM PST 23 Dec 20 12:21:25 PM PST 23 1040181114 ps
T324 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2624188691 Dec 20 12:20:28 PM PST 23 Dec 20 12:20:34 PM PST 23 276408216 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4258316065 Dec 20 12:19:39 PM PST 23 Dec 20 12:19:41 PM PST 23 463896497 ps
T326 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2900990665 Dec 20 12:21:11 PM PST 23 Dec 20 12:21:29 PM PST 23 314970413 ps
T91 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1127049352 Dec 20 12:20:42 PM PST 23 Dec 20 12:20:54 PM PST 23 4194649040 ps
T92 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.721303941 Dec 20 12:20:19 PM PST 23 Dec 20 12:20:35 PM PST 23 8333556362 ps
T327 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4287556687 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:47 PM PST 23 3983231643 ps
T328 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3942096568 Dec 20 12:21:04 PM PST 23 Dec 20 12:21:14 PM PST 23 418872613 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3092056114 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:46 PM PST 23 335383081 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1550151559 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:46 PM PST 23 432100083 ps
T82 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2241041849 Dec 20 12:20:48 PM PST 23 Dec 20 12:20:56 PM PST 23 948113229 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3871389221 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:18 PM PST 23 548888930 ps
T332 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1403662812 Dec 20 12:19:47 PM PST 23 Dec 20 12:19:48 PM PST 23 291620425 ps
T83 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3151126986 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:51 PM PST 23 1762302825 ps
T333 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3067416542 Dec 20 12:20:42 PM PST 23 Dec 20 12:20:49 PM PST 23 351579748 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.742891858 Dec 20 12:20:33 PM PST 23 Dec 20 12:20:38 PM PST 23 311377615 ps
T335 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1504193475 Dec 20 12:20:28 PM PST 23 Dec 20 12:20:34 PM PST 23 433061636 ps
T84 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2711613507 Dec 20 12:20:25 PM PST 23 Dec 20 12:20:33 PM PST 23 876064189 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2143959324 Dec 20 12:21:02 PM PST 23 Dec 20 12:21:11 PM PST 23 404114622 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4289247729 Dec 20 12:21:00 PM PST 23 Dec 20 12:21:09 PM PST 23 467380102 ps
T96 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2643991111 Dec 20 12:20:21 PM PST 23 Dec 20 12:20:26 PM PST 23 8777734057 ps
T338 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2413988027 Dec 20 12:21:31 PM PST 23 Dec 20 12:21:47 PM PST 23 488964716 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1781918023 Dec 20 12:21:10 PM PST 23 Dec 20 12:21:38 PM PST 23 8341952547 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2574559461 Dec 20 12:21:06 PM PST 23 Dec 20 12:21:28 PM PST 23 8483621544 ps
T341 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1830334566 Dec 20 12:20:42 PM PST 23 Dec 20 12:20:48 PM PST 23 300597944 ps
T342 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1951803275 Dec 20 12:21:14 PM PST 23 Dec 20 12:21:35 PM PST 23 462018342 ps
T343 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3448967238 Dec 20 12:21:11 PM PST 23 Dec 20 12:21:28 PM PST 23 292172544 ps
T344 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2435811563 Dec 20 12:20:33 PM PST 23 Dec 20 12:20:38 PM PST 23 315141600 ps
T345 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4092862443 Dec 20 12:19:41 PM PST 23 Dec 20 12:19:43 PM PST 23 638659620 ps
T346 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3930814454 Dec 20 12:20:46 PM PST 23 Dec 20 12:20:57 PM PST 23 8839169739 ps
T347 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4177303220 Dec 20 12:19:58 PM PST 23 Dec 20 12:20:00 PM PST 23 461001288 ps
T348 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1679837510 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:24 PM PST 23 8319053936 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4150152532 Dec 20 12:21:11 PM PST 23 Dec 20 12:21:27 PM PST 23 402913266 ps
T85 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3455574013 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:43 PM PST 23 2178833761 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4063014721 Dec 20 12:21:13 PM PST 23 Dec 20 12:21:34 PM PST 23 6677851374 ps
T69 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1655989476 Dec 20 12:21:31 PM PST 23 Dec 20 12:21:47 PM PST 23 336140618 ps
T70 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.578802092 Dec 20 12:21:05 PM PST 23 Dec 20 12:21:15 PM PST 23 440736027 ps
T71 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3781257812 Dec 20 12:20:34 PM PST 23 Dec 20 12:20:39 PM PST 23 302681478 ps
T72 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.849781272 Dec 20 12:19:47 PM PST 23 Dec 20 12:19:48 PM PST 23 400018880 ps
T73 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1777595858 Dec 20 12:20:10 PM PST 23 Dec 20 12:20:13 PM PST 23 365298536 ps
T350 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2970142749 Dec 20 12:20:25 PM PST 23 Dec 20 12:20:31 PM PST 23 325472981 ps
T351 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.57232957 Dec 20 12:20:38 PM PST 23 Dec 20 12:20:44 PM PST 23 308740580 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1027064575 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:48 PM PST 23 4152181797 ps
T352 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.410921712 Dec 20 12:20:03 PM PST 23 Dec 20 12:20:05 PM PST 23 361453569 ps
T353 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1494202934 Dec 20 12:20:15 PM PST 23 Dec 20 12:20:17 PM PST 23 549511546 ps
T86 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1455399269 Dec 20 12:20:40 PM PST 23 Dec 20 12:20:47 PM PST 23 1333906540 ps
T354 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1783931836 Dec 20 12:21:31 PM PST 23 Dec 20 12:21:47 PM PST 23 382890111 ps
T355 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1724585934 Dec 20 12:20:15 PM PST 23 Dec 20 12:20:17 PM PST 23 471549038 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.789536999 Dec 20 12:20:42 PM PST 23 Dec 20 12:20:50 PM PST 23 5285101530 ps
T356 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3341359981 Dec 20 12:21:43 PM PST 23 Dec 20 12:21:57 PM PST 23 374343613 ps
T357 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2958212155 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:42 PM PST 23 472286225 ps
T358 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4048697985 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:49 PM PST 23 396267284 ps
T64 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2863908122 Dec 20 12:21:30 PM PST 23 Dec 20 12:21:46 PM PST 23 338718196 ps
T359 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.525945165 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:42 PM PST 23 514311642 ps
T360 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.443252351 Dec 20 12:20:30 PM PST 23 Dec 20 12:20:39 PM PST 23 1206930114 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2527223511 Dec 20 12:21:09 PM PST 23 Dec 20 12:21:26 PM PST 23 2081100477 ps
T65 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.84696023 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:42 PM PST 23 433201271 ps
T362 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.735774009 Dec 20 12:21:17 PM PST 23 Dec 20 12:21:38 PM PST 23 316815697 ps
T363 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4147572006 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:50 PM PST 23 402257900 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1611222388 Dec 20 12:19:50 PM PST 23 Dec 20 12:19:54 PM PST 23 3963878804 ps
T365 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1644719911 Dec 20 12:21:04 PM PST 23 Dec 20 12:21:13 PM PST 23 475934776 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3059991280 Dec 20 12:20:33 PM PST 23 Dec 20 12:20:38 PM PST 23 433044218 ps
T367 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2144011880 Dec 20 12:21:06 PM PST 23 Dec 20 12:21:16 PM PST 23 561664576 ps
T78 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.738130961 Dec 20 12:20:46 PM PST 23 Dec 20 12:20:54 PM PST 23 440768618 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1432679495 Dec 20 12:21:05 PM PST 23 Dec 20 12:21:15 PM PST 23 448630531 ps
T369 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1450272511 Dec 20 12:21:12 PM PST 23 Dec 20 12:21:31 PM PST 23 492800380 ps
T370 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.756273006 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:46 PM PST 23 424901228 ps
T371 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1253167760 Dec 20 12:21:05 PM PST 23 Dec 20 12:21:15 PM PST 23 498772053 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.276901291 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:17 PM PST 23 527788046 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4239681503 Dec 20 12:19:33 PM PST 23 Dec 20 12:19:35 PM PST 23 1063218859 ps
T374 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2809895192 Dec 20 12:21:09 PM PST 23 Dec 20 12:21:23 PM PST 23 271318889 ps
T79 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3398143304 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:17 PM PST 23 399175001 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3508648013 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:45 PM PST 23 275188902 ps
T376 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.634427178 Dec 20 12:20:11 PM PST 23 Dec 20 12:20:15 PM PST 23 505030886 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2524499299 Dec 20 12:20:35 PM PST 23 Dec 20 12:20:42 PM PST 23 1873410621 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1270908780 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:51 PM PST 23 411268272 ps
T379 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3743027249 Dec 20 12:20:40 PM PST 23 Dec 20 12:20:46 PM PST 23 955900429 ps
T380 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1415948825 Dec 20 12:19:41 PM PST 23 Dec 20 12:19:43 PM PST 23 433309995 ps
T381 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1023285061 Dec 20 12:21:03 PM PST 23 Dec 20 12:21:13 PM PST 23 377896879 ps
T382 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2245071588 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:17 PM PST 23 288323025 ps
T383 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.582710912 Dec 20 12:20:13 PM PST 23 Dec 20 12:20:15 PM PST 23 417045714 ps
T384 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3430944745 Dec 20 12:21:39 PM PST 23 Dec 20 12:21:54 PM PST 23 332107486 ps
T385 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3893846255 Dec 20 12:20:12 PM PST 23 Dec 20 12:20:14 PM PST 23 424018905 ps
T386 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2255503284 Dec 20 12:21:44 PM PST 23 Dec 20 12:21:59 PM PST 23 282853470 ps
T387 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.856484445 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:50 PM PST 23 468549574 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1405059279 Dec 20 12:21:03 PM PST 23 Dec 20 12:21:13 PM PST 23 334691213 ps
T389 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2505903541 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:18 PM PST 23 434118728 ps
T390 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1413557196 Dec 20 12:21:14 PM PST 23 Dec 20 12:21:35 PM PST 23 489082730 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1468712766 Dec 20 12:20:48 PM PST 23 Dec 20 12:20:55 PM PST 23 379607343 ps
T392 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.296096231 Dec 20 12:20:48 PM PST 23 Dec 20 12:20:56 PM PST 23 482114226 ps
T74 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.896127475 Dec 20 12:21:02 PM PST 23 Dec 20 12:21:11 PM PST 23 341525232 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1678557920 Dec 20 12:20:26 PM PST 23 Dec 20 12:20:34 PM PST 23 4593508290 ps
T394 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3541546840 Dec 20 12:19:50 PM PST 23 Dec 20 12:19:53 PM PST 23 4360998064 ps
T395 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.857425740 Dec 20 12:20:30 PM PST 23 Dec 20 12:20:35 PM PST 23 299013760 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2706117061 Dec 20 12:20:30 PM PST 23 Dec 20 12:20:36 PM PST 23 456051551 ps
T397 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3885430797 Dec 20 12:21:09 PM PST 23 Dec 20 12:21:25 PM PST 23 2062323799 ps
T398 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.710991567 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:50 PM PST 23 516435152 ps
T399 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3222101905 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:46 PM PST 23 1722184869 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3520828872 Dec 20 12:21:13 PM PST 23 Dec 20 12:21:33 PM PST 23 391999004 ps
T401 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.650980558 Dec 20 12:19:36 PM PST 23 Dec 20 12:19:38 PM PST 23 299942236 ps
T402 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2436053744 Dec 20 12:21:32 PM PST 23 Dec 20 12:21:48 PM PST 23 400008599 ps
T403 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.264189480 Dec 20 12:20:46 PM PST 23 Dec 20 12:20:54 PM PST 23 267344750 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.279611652 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:18 PM PST 23 512193019 ps
T93 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3773086304 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:58 PM PST 23 8578239019 ps
T75 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.742311158 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:50 PM PST 23 492983789 ps
T405 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1702214761 Dec 20 12:19:52 PM PST 23 Dec 20 12:19:55 PM PST 23 1456795403 ps
T406 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.362004792 Dec 20 12:21:07 PM PST 23 Dec 20 12:21:19 PM PST 23 4554991139 ps
T407 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.70698466 Dec 20 12:21:06 PM PST 23 Dec 20 12:21:16 PM PST 23 611165634 ps
T408 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.663610002 Dec 20 12:19:34 PM PST 23 Dec 20 12:19:35 PM PST 23 453338176 ps
T409 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2314766389 Dec 20 12:20:59 PM PST 23 Dec 20 12:21:07 PM PST 23 517132177 ps
T76 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3946884825 Dec 20 12:20:34 PM PST 23 Dec 20 12:20:39 PM PST 23 509733801 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4019190996 Dec 20 12:20:59 PM PST 23 Dec 20 12:21:06 PM PST 23 528773305 ps
T94 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3803331441 Dec 20 12:20:42 PM PST 23 Dec 20 12:20:55 PM PST 23 4344591759 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.104837581 Dec 20 12:19:50 PM PST 23 Dec 20 12:19:57 PM PST 23 393703174 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.424286940 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:49 PM PST 23 1101084262 ps
T413 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2952693904 Dec 20 12:21:11 PM PST 23 Dec 20 12:21:30 PM PST 23 329025700 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2827542772 Dec 20 12:21:36 PM PST 23 Dec 20 12:21:52 PM PST 23 477130831 ps
T415 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2645002050 Dec 20 12:21:02 PM PST 23 Dec 20 12:21:13 PM PST 23 511847871 ps
T416 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.975906292 Dec 20 12:21:08 PM PST 23 Dec 20 12:21:21 PM PST 23 278819863 ps
T417 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1392042045 Dec 20 12:20:39 PM PST 23 Dec 20 12:20:51 PM PST 23 12047562029 ps
T418 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3650846874 Dec 20 12:21:03 PM PST 23 Dec 20 12:21:16 PM PST 23 1461860125 ps
T77 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2342457491 Dec 20 12:21:04 PM PST 23 Dec 20 12:21:22 PM PST 23 11514498671 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1894622024 Dec 20 12:19:34 PM PST 23 Dec 20 12:19:36 PM PST 23 1071630757 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.157249157 Dec 20 12:20:43 PM PST 23 Dec 20 12:20:50 PM PST 23 1131880094 ps
T421 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.424112534 Dec 20 12:21:15 PM PST 23 Dec 20 12:21:42 PM PST 23 4436825913 ps
T422 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2104363774 Dec 20 12:20:04 PM PST 23 Dec 20 12:20:07 PM PST 23 511584623 ps
T423 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3086166253 Dec 20 12:21:40 PM PST 23 Dec 20 12:21:54 PM PST 23 384461364 ps
T424 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.21840223 Dec 20 12:20:40 PM PST 23 Dec 20 12:20:47 PM PST 23 465802102 ps
T425 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3611741690 Dec 20 12:19:41 PM PST 23 Dec 20 12:19:42 PM PST 23 617320716 ps
T426 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1179983564 Dec 20 12:20:35 PM PST 23 Dec 20 12:20:42 PM PST 23 357677026 ps
T427 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1792242225 Dec 20 12:20:25 PM PST 23 Dec 20 12:20:32 PM PST 23 365819453 ps
T428 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2730627804 Dec 20 12:20:56 PM PST 23 Dec 20 12:21:04 PM PST 23 420484312 ps
T429 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2183746689 Dec 20 12:20:36 PM PST 23 Dec 20 12:20:43 PM PST 23 8646087702 ps

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2331938283
Short name T1
Test name
Test status
Simulation time 4617304210 ps
CPU time 4.62 seconds
Started Dec 20 12:19:53 PM PST 23
Finished Dec 20 12:19:59 PM PST 23
Peak memory 197344 kb
Host smart-20d6711b-c18d-4be5-8c1f-9f84d953e3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331938283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2331938283
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3026637183
Short name T19
Test name
Test status
Simulation time 104762611762 ps
CPU time 270.5 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:25:52 PM PST 23
Peak memory 197728 kb
Host smart-5a9bc675-6176-441e-b02b-fead1262db32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026637183 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3026637183
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.618313642
Short name T50
Test name
Test status
Simulation time 58093931203 ps
CPU time 256.21 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:25:05 PM PST 23
Peak memory 197756 kb
Host smart-df710ee7-e087-493c-98e6-f2bfaf001b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618313642 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.618313642
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.143858178
Short name T6
Test name
Test status
Simulation time 241241276346 ps
CPU time 318.68 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:26:37 PM PST 23
Peak memory 182924 kb
Host smart-e6d24d5d-6c30-4830-80cd-1cdb1acf884e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143858178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.143858178
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.424755453
Short name T122
Test name
Test status
Simulation time 87044851422 ps
CPU time 451.8 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:28:48 PM PST 23
Peak memory 197732 kb
Host smart-49e6e245-7e5d-44b6-98f6-0e31a1889703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424755453 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.424755453
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2093507660
Short name T102
Test name
Test status
Simulation time 75356955246 ps
CPU time 62.51 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:22:49 PM PST 23
Peak memory 182940 kb
Host smart-f49374fb-844b-4e42-827c-2343a5c367d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093507660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2093507660
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2158183557
Short name T57
Test name
Test status
Simulation time 1110142406 ps
CPU time 2.34 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:20:56 PM PST 23
Peak memory 183896 kb
Host smart-b316ef7f-42c7-4468-a2e9-56ec0c897038
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158183557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2158183557
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.457022343
Short name T103
Test name
Test status
Simulation time 87099213565 ps
CPU time 123.44 seconds
Started Dec 20 12:21:00 PM PST 23
Finished Dec 20 12:23:11 PM PST 23
Peak memory 182848 kb
Host smart-4cb18822-6ada-4d41-9874-6dee39a24ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457022343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.457022343
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3826197364
Short name T20
Test name
Test status
Simulation time 99009849771 ps
CPU time 34.9 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 182916 kb
Host smart-2c6aba60-5ea7-4405-a7bd-e3e4d67578c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826197364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3826197364
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2639540776
Short name T67
Test name
Test status
Simulation time 481001152 ps
CPU time 0.88 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 183820 kb
Host smart-f2245e55-a84b-4b4d-96b3-c0c34d0d9ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639540776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2639540776
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2068641550
Short name T29
Test name
Test status
Simulation time 4356259944 ps
CPU time 7.17 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 215104 kb
Host smart-3b0dc0a1-6514-4b7c-b45d-f1762bcf7d4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068641550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2068641550
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.597563254
Short name T128
Test name
Test status
Simulation time 439961411400 ps
CPU time 589.5 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 198872 kb
Host smart-eb880bd6-6a3f-494e-ae6e-839d8162a90e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597563254 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.597563254
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4259431099
Short name T101
Test name
Test status
Simulation time 16451758372 ps
CPU time 24.2 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 182808 kb
Host smart-ab51691d-b0fa-4566-b427-f75791af35eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259431099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4259431099
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2718638030
Short name T90
Test name
Test status
Simulation time 163552877615 ps
CPU time 365.96 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:28:04 PM PST 23
Peak memory 197712 kb
Host smart-c1b47cd8-6cc0-4905-bc59-407eb03714f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718638030 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2718638030
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2643991111
Short name T96
Test name
Test status
Simulation time 8777734057 ps
CPU time 3.83 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:26 PM PST 23
Peak memory 197680 kb
Host smart-abb8550d-e78e-460d-8e32-0102d1ef6996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643991111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2643991111
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1211628429
Short name T129
Test name
Test status
Simulation time 30528734798 ps
CPU time 314.27 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:25:54 PM PST 23
Peak memory 197908 kb
Host smart-cef1bba9-a067-420c-a7bc-352d7f21095f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211628429 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1211628429
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3901292801
Short name T270
Test name
Test status
Simulation time 224693552468 ps
CPU time 254.24 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:24:58 PM PST 23
Peak memory 197812 kb
Host smart-6aa4207c-725d-44b6-a526-7c2e794cdedd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901292801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3901292801
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2241041849
Short name T82
Test name
Test status
Simulation time 948113229 ps
CPU time 1.53 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:20:56 PM PST 23
Peak memory 192768 kb
Host smart-6a941d67-713a-42e3-9652-38f803ff9d0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241041849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2241041849
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3803331441
Short name T94
Test name
Test status
Simulation time 4344591759 ps
CPU time 7.42 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:55 PM PST 23
Peak memory 197344 kb
Host smart-b5f8a545-ef9d-4334-8c28-66d14bdf3f10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803331441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3803331441
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.273548215
Short name T138
Test name
Test status
Simulation time 155023758250 ps
CPU time 57.42 seconds
Started Dec 20 12:20:53 PM PST 23
Finished Dec 20 12:21:57 PM PST 23
Peak memory 193092 kb
Host smart-a21f81a0-d6eb-4c26-af70-b2994046282a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273548215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.273548215
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.279611652
Short name T404
Test name
Test status
Simulation time 512193019 ps
CPU time 1.1 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 193968 kb
Host smart-16c782b3-ea18-4d4f-b246-05198ea6e150
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279611652 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.279611652
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1392042045
Short name T417
Test name
Test status
Simulation time 12047562029 ps
CPU time 6.03 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:51 PM PST 23
Peak memory 192364 kb
Host smart-183a6747-6524-499a-82ff-dc7ae48ace03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392042045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1392042045
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.166909042
Short name T25
Test name
Test status
Simulation time 333747018 ps
CPU time 0.8 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 194844 kb
Host smart-e053bae2-b784-47c7-9617-339ffbdd4c5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166909042 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.166909042
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.650980558
Short name T401
Test name
Test status
Simulation time 299942236 ps
CPU time 1.03 seconds
Started Dec 20 12:19:36 PM PST 23
Finished Dec 20 12:19:38 PM PST 23
Peak memory 183936 kb
Host smart-1ddb5475-4f84-4def-9e8b-725b382fd7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650980558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.650980558
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1792242225
Short name T427
Test name
Test status
Simulation time 365819453 ps
CPU time 0.67 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 183644 kb
Host smart-d7613108-32b0-4703-8653-e6ea848c685b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792242225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1792242225
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3396105541
Short name T16
Test name
Test status
Simulation time 437265242 ps
CPU time 0.83 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 183988 kb
Host smart-c8eec473-b9d6-4f7b-b4b5-0c6e713389c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396105541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3396105541
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2970142749
Short name T350
Test name
Test status
Simulation time 325472981 ps
CPU time 0.92 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 183892 kb
Host smart-682db864-32f3-4a16-87dc-80d2fea43e07
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970142749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2970142749
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3946612583
Short name T323
Test name
Test status
Simulation time 1040181114 ps
CPU time 1.53 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:25 PM PST 23
Peak memory 193404 kb
Host smart-603c012d-a879-4c28-89e3-1c52e7c4d4a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946612583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3946612583
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2730627804
Short name T428
Test name
Test status
Simulation time 420484312 ps
CPU time 1.67 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 198640 kb
Host smart-11a60355-f2ba-48a3-b7ab-1ac4c9f70056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730627804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2730627804
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1678557920
Short name T393
Test name
Test status
Simulation time 4593508290 ps
CPU time 2.48 seconds
Started Dec 20 12:20:26 PM PST 23
Finished Dec 20 12:20:34 PM PST 23
Peak memory 197052 kb
Host smart-17ca180a-a741-40fb-aa57-2df8c1f180a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678557920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1678557920
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.738130961
Short name T78
Test name
Test status
Simulation time 440768618 ps
CPU time 1.56 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 183904 kb
Host smart-c3b2b86a-e6b6-48d0-9ed4-bdff6d569bd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738130961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.738130961
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4063014721
Short name T61
Test name
Test status
Simulation time 6677851374 ps
CPU time 3.73 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 192352 kb
Host smart-4d204e46-771b-4675-8d61-cf756de78be8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063014721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4063014721
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1713852036
Short name T319
Test name
Test status
Simulation time 737331483 ps
CPU time 1.27 seconds
Started Dec 20 12:19:43 PM PST 23
Finished Dec 20 12:19:45 PM PST 23
Peak memory 183964 kb
Host smart-b12885f0-229d-46da-8414-218ed09155f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713852036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1713852036
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.769433452
Short name T15
Test name
Test status
Simulation time 323474058 ps
CPU time 1.15 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 195980 kb
Host smart-916fa3d2-b117-4648-b7f1-855a3c4cca50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769433452 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.769433452
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4019190996
Short name T410
Test name
Test status
Simulation time 528773305 ps
CPU time 0.71 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 183908 kb
Host smart-31c6d6c9-2f42-45d4-b325-bcf3be091059
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019190996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4019190996
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4048697985
Short name T358
Test name
Test status
Simulation time 396267284 ps
CPU time 1.11 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 183644 kb
Host smart-c087737d-96f6-4bd4-a393-090a2c7c289d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048697985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4048697985
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1415948825
Short name T380
Test name
Test status
Simulation time 433309995 ps
CPU time 1.22 seconds
Started Dec 20 12:19:41 PM PST 23
Finished Dec 20 12:19:43 PM PST 23
Peak memory 183684 kb
Host smart-1a1c1bff-1893-4634-acfa-a0beea0d296b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415948825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1415948825
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.4258316065
Short name T325
Test name
Test status
Simulation time 463896497 ps
CPU time 1.23 seconds
Started Dec 20 12:19:39 PM PST 23
Finished Dec 20 12:19:41 PM PST 23
Peak memory 183672 kb
Host smart-096a9938-3106-45fe-9ffe-c352def4b515
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258316065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.4258316065
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1468712766
Short name T391
Test name
Test status
Simulation time 379607343 ps
CPU time 0.99 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:20:55 PM PST 23
Peak memory 198316 kb
Host smart-3b7465f1-93d1-419d-9300-f92583263089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468712766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1468712766
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2574559461
Short name T340
Test name
Test status
Simulation time 8483621544 ps
CPU time 13.19 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:28 PM PST 23
Peak memory 197584 kb
Host smart-ed2aa2f0-244f-4aa9-a005-2e8a9869eaac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574559461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2574559461
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3611741690
Short name T425
Test name
Test status
Simulation time 617320716 ps
CPU time 0.82 seconds
Started Dec 20 12:19:41 PM PST 23
Finished Dec 20 12:19:42 PM PST 23
Peak memory 196908 kb
Host smart-d7e89f92-f231-4835-8404-28e3eb82643f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611741690 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3611741690
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.104837581
Short name T411
Test name
Test status
Simulation time 393703174 ps
CPU time 0.59 seconds
Started Dec 20 12:19:50 PM PST 23
Finished Dec 20 12:19:57 PM PST 23
Peak memory 183928 kb
Host smart-770c1f57-b046-418e-ae80-597155c10ec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104837581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.104837581
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2527223511
Short name T361
Test name
Test status
Simulation time 2081100477 ps
CPU time 3.82 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:26 PM PST 23
Peak memory 194008 kb
Host smart-d2590723-2876-48a5-90bd-0fa395f37f4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527223511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2527223511
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2952693904
Short name T413
Test name
Test status
Simulation time 329025700 ps
CPU time 2.29 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 198672 kb
Host smart-2d18b349-c698-41d3-ba86-eb5bc4151b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952693904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2952693904
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1679837510
Short name T348
Test name
Test status
Simulation time 8319053936 ps
CPU time 7.35 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:24 PM PST 23
Peak memory 197668 kb
Host smart-e218dd83-d861-4a5e-9364-245b68503add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679837510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1679837510
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1131750715
Short name T10
Test name
Test status
Simulation time 361228217 ps
CPU time 0.93 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 196076 kb
Host smart-3f2789aa-f52b-477e-9455-8d9455acc6e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131750715 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1131750715
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4147572006
Short name T363
Test name
Test status
Simulation time 402257900 ps
CPU time 0.91 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 183896 kb
Host smart-d1fc6fdf-b906-4b3a-964e-62246853e8d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147572006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4147572006
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1830334566
Short name T341
Test name
Test status
Simulation time 300597944 ps
CPU time 1.02 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 183904 kb
Host smart-be417ec4-d2f4-4438-beaf-d484f1dae0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830334566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1830334566
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3743027249
Short name T379
Test name
Test status
Simulation time 955900429 ps
CPU time 0.95 seconds
Started Dec 20 12:20:40 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 193888 kb
Host smart-427b9d36-42d4-4c6a-bd88-1e0d7c3828a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743027249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3743027249
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3067416542
Short name T333
Test name
Test status
Simulation time 351579748 ps
CPU time 1.56 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 198476 kb
Host smart-6b9ed490-7337-4c71-a113-8a4c6cb51b2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067416542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3067416542
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1781918023
Short name T339
Test name
Test status
Simulation time 8341952547 ps
CPU time 14.29 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 197804 kb
Host smart-386a7292-c6b5-4ead-9d94-cae29de1ed7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781918023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1781918023
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.856484445
Short name T387
Test name
Test status
Simulation time 468549574 ps
CPU time 1.24 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 196640 kb
Host smart-f4c3a7f3-0db7-42b7-b130-f3aac6b47506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856484445 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.856484445
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1405059279
Short name T388
Test name
Test status
Simulation time 334691213 ps
CPU time 0.64 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 183796 kb
Host smart-caefa233-d5a9-425e-bf20-ca037774c14f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405059279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1405059279
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1253167760
Short name T371
Test name
Test status
Simulation time 498772053 ps
CPU time 1.31 seconds
Started Dec 20 12:21:05 PM PST 23
Finished Dec 20 12:21:15 PM PST 23
Peak memory 183576 kb
Host smart-6a6ccdf1-1e6a-4f7d-a1ab-42a0df1dce21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253167760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1253167760
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.157249157
Short name T420
Test name
Test status
Simulation time 1131880094 ps
CPU time 1.76 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 193388 kb
Host smart-6dcea8cd-9c36-4516-b500-9d3a4fcd0135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157249157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.157249157
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1270908780
Short name T378
Test name
Test status
Simulation time 411268272 ps
CPU time 2.25 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:51 PM PST 23
Peak memory 198708 kb
Host smart-827fb14d-a8cd-4a9a-92b6-13ea6abff9a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270908780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1270908780
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1724585934
Short name T355
Test name
Test status
Simulation time 471549038 ps
CPU time 0.77 seconds
Started Dec 20 12:20:15 PM PST 23
Finished Dec 20 12:20:17 PM PST 23
Peak memory 196364 kb
Host smart-4f2094ce-92f3-41f0-af67-3b5fbdb5c6c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724585934 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1724585934
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.84696023
Short name T65
Test name
Test status
Simulation time 433201271 ps
CPU time 0.69 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 183932 kb
Host smart-dd5f3144-b3d1-4f5e-aacd-1096e8c3da7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84696023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.84696023
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1023285061
Short name T381
Test name
Test status
Simulation time 377896879 ps
CPU time 0.66 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 183576 kb
Host smart-1c7c9fdb-aeb8-4a7d-8f44-385beb26bc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023285061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1023285061
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3455574013
Short name T85
Test name
Test status
Simulation time 2178833761 ps
CPU time 1.2 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:43 PM PST 23
Peak memory 194208 kb
Host smart-da1c62eb-e6ff-49ba-aae0-6ef08698d2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455574013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3455574013
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.540233641
Short name T314
Test name
Test status
Simulation time 337152150 ps
CPU time 2.19 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 193624 kb
Host smart-41d0f6d8-9c18-4ddc-a604-5613d2c1d417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540233641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.540233641
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1611222388
Short name T364
Test name
Test status
Simulation time 3963878804 ps
CPU time 3.27 seconds
Started Dec 20 12:19:50 PM PST 23
Finished Dec 20 12:19:54 PM PST 23
Peak memory 197356 kb
Host smart-2130d651-a26f-401b-89bc-fb1401c1b52e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611222388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1611222388
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.37021620
Short name T313
Test name
Test status
Simulation time 319244546 ps
CPU time 1.09 seconds
Started Dec 20 12:20:14 PM PST 23
Finished Dec 20 12:20:17 PM PST 23
Peak memory 195116 kb
Host smart-03bcb912-aa58-449e-9974-abd89228e58d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37021620 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.37021620
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3059991280
Short name T366
Test name
Test status
Simulation time 433044218 ps
CPU time 0.68 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 183884 kb
Host smart-fb3517ac-8110-4834-b0f8-96475f9bda46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059991280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3059991280
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.57232957
Short name T351
Test name
Test status
Simulation time 308740580 ps
CPU time 0.94 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:20:44 PM PST 23
Peak memory 183660 kb
Host smart-6474ab9c-04dc-429f-b735-3cd44617081a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57232957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.57232957
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3540592761
Short name T5
Test name
Test status
Simulation time 1318079092 ps
CPU time 1.54 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:40 PM PST 23
Peak memory 194360 kb
Host smart-4028d485-b78a-4acf-8d3b-0616c8dad519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540592761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3540592761
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1638438167
Short name T23
Test name
Test status
Simulation time 358180483 ps
CPU time 1.21 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 198764 kb
Host smart-6a34e2c9-576e-4191-aef1-eaea3a80c7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638438167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1638438167
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2030069890
Short name T95
Test name
Test status
Simulation time 5180045295 ps
CPU time 4.12 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:41 PM PST 23
Peak memory 196288 kb
Host smart-4679f4b7-c207-4ca8-828b-485bffe91513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030069890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2030069890
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.582710912
Short name T383
Test name
Test status
Simulation time 417045714 ps
CPU time 1.19 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:20:15 PM PST 23
Peak memory 194784 kb
Host smart-12d2fec3-a557-4439-8388-033f6b6af0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582710912 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.582710912
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3946884825
Short name T76
Test name
Test status
Simulation time 509733801 ps
CPU time 0.74 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 183952 kb
Host smart-a0fd6721-4eb9-45ba-a9ce-7ed2fde19c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946884825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3946884825
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.742891858
Short name T334
Test name
Test status
Simulation time 311377615 ps
CPU time 0.98 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 183716 kb
Host smart-7a74a3c0-2abd-410d-9e01-2bb09e9d8331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742891858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.742891858
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2524499299
Short name T377
Test name
Test status
Simulation time 1873410621 ps
CPU time 2.84 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 193444 kb
Host smart-3b1d735f-3ca8-4606-879e-db667777d61d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524499299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2524499299
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.634427178
Short name T376
Test name
Test status
Simulation time 505030886 ps
CPU time 2.11 seconds
Started Dec 20 12:20:11 PM PST 23
Finished Dec 20 12:20:15 PM PST 23
Peak memory 198708 kb
Host smart-a00af217-8d20-4a43-ae34-83464b449218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634427178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.634427178
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4287556687
Short name T327
Test name
Test status
Simulation time 3983231643 ps
CPU time 2.46 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:47 PM PST 23
Peak memory 196076 kb
Host smart-efae750f-5493-4cda-94d0-d97b4c5a59f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287556687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4287556687
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2958212155
Short name T357
Test name
Test status
Simulation time 472286225 ps
CPU time 1.33 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 198924 kb
Host smart-c372582b-c3ee-437a-9b28-696568f37edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958212155 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2958212155
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1969712143
Short name T4
Test name
Test status
Simulation time 418512203 ps
CPU time 0.67 seconds
Started Dec 20 12:20:27 PM PST 23
Finished Dec 20 12:20:34 PM PST 23
Peak memory 183964 kb
Host smart-81cd0f4d-6a6f-482f-98a3-8bee5c6d75f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969712143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1969712143
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2624188691
Short name T324
Test name
Test status
Simulation time 276408216 ps
CPU time 0.9 seconds
Started Dec 20 12:20:28 PM PST 23
Finished Dec 20 12:20:34 PM PST 23
Peak memory 183652 kb
Host smart-fb71ba18-c421-4b36-a6c4-1bfbdbc371fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624188691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2624188691
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.443252351
Short name T360
Test name
Test status
Simulation time 1206930114 ps
CPU time 3.43 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 193608 kb
Host smart-8712a457-0f7b-4caa-b473-64b7f71ae5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443252351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.443252351
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2706117061
Short name T396
Test name
Test status
Simulation time 456051551 ps
CPU time 1.76 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:36 PM PST 23
Peak memory 197564 kb
Host smart-16fa2354-03e9-4735-a13c-0895ef747e11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706117061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2706117061
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1494202934
Short name T353
Test name
Test status
Simulation time 549511546 ps
CPU time 0.67 seconds
Started Dec 20 12:20:15 PM PST 23
Finished Dec 20 12:20:17 PM PST 23
Peak memory 193944 kb
Host smart-017c8beb-fa20-4920-b945-c8369596c9d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494202934 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1494202934
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1800273176
Short name T12
Test name
Test status
Simulation time 333161806 ps
CPU time 1.08 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:21 PM PST 23
Peak memory 183920 kb
Host smart-2183b087-cc5d-496a-8b8d-fe19f4c2199b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800273176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1800273176
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3893846255
Short name T385
Test name
Test status
Simulation time 424018905 ps
CPU time 1.09 seconds
Started Dec 20 12:20:12 PM PST 23
Finished Dec 20 12:20:14 PM PST 23
Peak memory 184016 kb
Host smart-85bb83eb-1ed6-480b-a72a-da89db47351c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893846255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3893846255
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2711613507
Short name T84
Test name
Test status
Simulation time 876064189 ps
CPU time 1.82 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 193360 kb
Host smart-56571b4a-b7c4-4ec0-9ab1-f2a21020af82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711613507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2711613507
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.4230893685
Short name T48
Test name
Test status
Simulation time 641514664 ps
CPU time 1.12 seconds
Started Dec 20 12:20:17 PM PST 23
Finished Dec 20 12:20:20 PM PST 23
Peak memory 198140 kb
Host smart-f25259d4-e708-4df2-9472-51ebab355a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230893685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.4230893685
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.721303941
Short name T92
Test name
Test status
Simulation time 8333556362 ps
CPU time 13.5 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 197592 kb
Host smart-256013d0-c929-428f-bcc6-c390c3fbafb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721303941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.721303941
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1134022767
Short name T320
Test name
Test status
Simulation time 521094429 ps
CPU time 1.39 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:26 PM PST 23
Peak memory 196164 kb
Host smart-d22732f6-66d2-43da-9b81-9e88a94237c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134022767 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1134022767
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.410921712
Short name T352
Test name
Test status
Simulation time 361453569 ps
CPU time 0.79 seconds
Started Dec 20 12:20:03 PM PST 23
Finished Dec 20 12:20:05 PM PST 23
Peak memory 183912 kb
Host smart-c9956bfc-1e27-4321-86c9-7dfbc1d8349f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410921712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.410921712
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4169312848
Short name T13
Test name
Test status
Simulation time 270063446 ps
CPU time 0.82 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:21 PM PST 23
Peak memory 183796 kb
Host smart-35fe7563-747b-4b87-bc34-6f7156e3b656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169312848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4169312848
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3885430797
Short name T397
Test name
Test status
Simulation time 2062323799 ps
CPU time 3.08 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:25 PM PST 23
Peak memory 195256 kb
Host smart-9ccc6303-00fc-4a62-8b84-668ffb56c0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885430797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3885430797
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2144011880
Short name T367
Test name
Test status
Simulation time 561664576 ps
CPU time 1.93 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 198696 kb
Host smart-c5b5fdd5-278a-49c5-8e51-f3b642456f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144011880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2144011880
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.362004792
Short name T406
Test name
Test status
Simulation time 4554991139 ps
CPU time 2.41 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 197304 kb
Host smart-b732128a-d9bb-4bce-87bd-d5155b356378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362004792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.362004792
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2827542772
Short name T414
Test name
Test status
Simulation time 477130831 ps
CPU time 0.94 seconds
Started Dec 20 12:21:36 PM PST 23
Finished Dec 20 12:21:52 PM PST 23
Peak memory 194548 kb
Host smart-581f9a8b-d294-4b88-952b-5dc2d2b30d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827542772 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2827542772
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2863908122
Short name T64
Test name
Test status
Simulation time 338718196 ps
CPU time 0.69 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 183908 kb
Host smart-d2ae32dc-6b7b-4ae0-a143-610268970322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863908122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2863908122
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3983734602
Short name T317
Test name
Test status
Simulation time 386579364 ps
CPU time 1.11 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 183680 kb
Host smart-9a5b7deb-9e57-4784-b296-fca691b979d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983734602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3983734602
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3222101905
Short name T399
Test name
Test status
Simulation time 1722184869 ps
CPU time 1.25 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 195200 kb
Host smart-49811eec-af48-4063-bf9e-fb0946576c76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222101905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3222101905
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3520828872
Short name T400
Test name
Test status
Simulation time 391999004 ps
CPU time 2.24 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:33 PM PST 23
Peak memory 198556 kb
Host smart-1e727385-00bd-4d66-8608-abc9cd003e6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520828872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3520828872
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.424112534
Short name T421
Test name
Test status
Simulation time 4436825913 ps
CPU time 6.73 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:42 PM PST 23
Peak memory 196252 kb
Host smart-9e3442fa-95a2-4db5-b03a-ef9f93007047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424112534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.424112534
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.4289247729
Short name T337
Test name
Test status
Simulation time 467380102 ps
CPU time 1.4 seconds
Started Dec 20 12:21:00 PM PST 23
Finished Dec 20 12:21:09 PM PST 23
Peak memory 183912 kb
Host smart-62327e80-4a61-43aa-9433-56aa18c5b5c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289247729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.4289247729
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.789536999
Short name T63
Test name
Test status
Simulation time 5285101530 ps
CPU time 2.39 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 193632 kb
Host smart-a7008ab4-dbbd-4969-a2e8-9a9d600080a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789536999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_bi
t_bash.789536999
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4092862443
Short name T345
Test name
Test status
Simulation time 638659620 ps
CPU time 0.79 seconds
Started Dec 20 12:19:41 PM PST 23
Finished Dec 20 12:19:43 PM PST 23
Peak memory 183800 kb
Host smart-d6d87159-6916-4585-aa4c-66d15a2c1374
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092862443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4092862443
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1042105456
Short name T144
Test name
Test status
Simulation time 459940633 ps
CPU time 1.37 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 195696 kb
Host smart-15f0ce81-341d-4df2-8af1-85b894046b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042105456 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1042105456
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.296096231
Short name T392
Test name
Test status
Simulation time 482114226 ps
CPU time 0.58 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:20:56 PM PST 23
Peak memory 183884 kb
Host smart-eeefc113-28b6-4d78-98dc-88f959fbcf25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296096231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.296096231
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.4150152532
Short name T349
Test name
Test status
Simulation time 402913266 ps
CPU time 0.66 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:27 PM PST 23
Peak memory 183696 kb
Host smart-f71d1b6b-465a-4b42-98d9-330b074cc6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150152532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.4150152532
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2900990665
Short name T326
Test name
Test status
Simulation time 314970413 ps
CPU time 0.6 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 183680 kb
Host smart-847228f5-3331-4ae4-bb0a-3b266f8beff4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900990665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2900990665
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1403662812
Short name T332
Test name
Test status
Simulation time 291620425 ps
CPU time 0.64 seconds
Started Dec 20 12:19:47 PM PST 23
Finished Dec 20 12:19:48 PM PST 23
Peak memory 183936 kb
Host smart-5bafb4ba-8885-4eb4-8519-48412c6477cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403662812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1403662812
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2448349236
Short name T81
Test name
Test status
Simulation time 1194169689 ps
CPU time 1.41 seconds
Started Dec 20 12:21:00 PM PST 23
Finished Dec 20 12:21:10 PM PST 23
Peak memory 194372 kb
Host smart-e883dd82-8623-4b8a-bb7d-0a5138b6c85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448349236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2448349236
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1759642918
Short name T316
Test name
Test status
Simulation time 681645418 ps
CPU time 2.06 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 198720 kb
Host smart-c221f64e-fa76-483d-bb1a-5a10906738f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759642918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1759642918
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3930814454
Short name T346
Test name
Test status
Simulation time 8839169739 ps
CPU time 3.6 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:57 PM PST 23
Peak memory 197712 kb
Host smart-d39ddd4a-f788-4593-bf22-df652169fdca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930814454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3930814454
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1016860841
Short name T7
Test name
Test status
Simulation time 390114007 ps
CPU time 1.14 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 183680 kb
Host smart-12d95624-5b0d-4239-a25b-b1953a27d745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016860841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1016860841
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.975906292
Short name T416
Test name
Test status
Simulation time 278819863 ps
CPU time 0.88 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:21 PM PST 23
Peak memory 183932 kb
Host smart-bb5344bd-5b6c-4dfa-b797-58adda949217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975906292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.975906292
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2435811563
Short name T344
Test name
Test status
Simulation time 315141600 ps
CPU time 0.63 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 183712 kb
Host smart-f77fbe8f-5909-41ed-a689-c72f75055c8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435811563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2435811563
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1777595858
Short name T73
Test name
Test status
Simulation time 365298536 ps
CPU time 1.2 seconds
Started Dec 20 12:20:10 PM PST 23
Finished Dec 20 12:20:13 PM PST 23
Peak memory 183664 kb
Host smart-ce89e0dd-dc16-46cd-a5d5-fa5a9c4c1a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777595858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1777595858
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2314766389
Short name T409
Test name
Test status
Simulation time 517132177 ps
CPU time 1.1 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:07 PM PST 23
Peak memory 183652 kb
Host smart-a9d1d48b-19f3-4a97-96a7-079c4fc0bb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314766389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2314766389
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1655989476
Short name T69
Test name
Test status
Simulation time 336140618 ps
CPU time 1.07 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183888 kb
Host smart-2629797b-7f04-4b1a-a276-ee6c4b7ba067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655989476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1655989476
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.857425740
Short name T395
Test name
Test status
Simulation time 299013760 ps
CPU time 0.73 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 183956 kb
Host smart-88cfe0ad-f28f-44e9-8e5a-183f3cd4d3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857425740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.857425740
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2436053744
Short name T402
Test name
Test status
Simulation time 400008599 ps
CPU time 0.92 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 183792 kb
Host smart-87f03ce1-7466-4dce-990f-d97d55970a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436053744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2436053744
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2809895192
Short name T374
Test name
Test status
Simulation time 271318889 ps
CPU time 0.95 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 183796 kb
Host smart-b9a21564-8d0a-48c5-95fb-04be8d41ddad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809895192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2809895192
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2104363774
Short name T422
Test name
Test status
Simulation time 511584623 ps
CPU time 1.37 seconds
Started Dec 20 12:20:04 PM PST 23
Finished Dec 20 12:20:07 PM PST 23
Peak memory 183688 kb
Host smart-5b4f7acb-bd2f-4e2f-89ad-0b2d00665efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104363774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2104363774
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.742311158
Short name T75
Test name
Test status
Simulation time 492983789 ps
CPU time 0.88 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 193180 kb
Host smart-4e93eacf-faf7-426c-b2ed-5563b5504419
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742311158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.742311158
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2342457491
Short name T77
Test name
Test status
Simulation time 11514498671 ps
CPU time 9.26 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 192360 kb
Host smart-b3187d96-b0b5-4662-a1b0-7c3dade41eff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342457491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2342457491
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4239681503
Short name T373
Test name
Test status
Simulation time 1063218859 ps
CPU time 0.98 seconds
Started Dec 20 12:19:33 PM PST 23
Finished Dec 20 12:19:35 PM PST 23
Peak memory 183964 kb
Host smart-4518dc71-f4ff-4e3e-b155-e5dafacc4091
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239681503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4239681503
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1550151559
Short name T330
Test name
Test status
Simulation time 432100083 ps
CPU time 1.2 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 195644 kb
Host smart-61113129-ef23-415c-b624-7f55ec3661ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550151559 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1550151559
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.756273006
Short name T370
Test name
Test status
Simulation time 424901228 ps
CPU time 1.12 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 183568 kb
Host smart-1cf7cfbf-b98f-496f-af4e-c4c696e42ca4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756273006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.756273006
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.264189480
Short name T403
Test name
Test status
Simulation time 267344750 ps
CPU time 0.92 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 183888 kb
Host smart-318f77ae-c1db-478f-b105-8b8a81190fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264189480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.264189480
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3508648013
Short name T375
Test name
Test status
Simulation time 275188902 ps
CPU time 0.71 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:45 PM PST 23
Peak memory 183932 kb
Host smart-c231b31e-77d1-4398-9c0c-623e67cbc132
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508648013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3508648013
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.21840223
Short name T424
Test name
Test status
Simulation time 465802102 ps
CPU time 1.22 seconds
Started Dec 20 12:20:40 PM PST 23
Finished Dec 20 12:20:47 PM PST 23
Peak memory 183932 kb
Host smart-d0c6a2fa-cbe0-40ba-a2ea-770e48816790
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21840223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wal
k.21840223
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.424286940
Short name T412
Test name
Test status
Simulation time 1101084262 ps
CPU time 0.97 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 192812 kb
Host smart-1de3b8b8-07b7-4f6e-846d-7558f3c08116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424286940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.424286940
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3871389221
Short name T331
Test name
Test status
Simulation time 548888930 ps
CPU time 1.66 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 198776 kb
Host smart-d4155fe9-2139-45be-90aa-6422eecdca79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871389221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3871389221
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2181587731
Short name T9
Test name
Test status
Simulation time 7930568254 ps
CPU time 3.23 seconds
Started Dec 20 12:19:41 PM PST 23
Finished Dec 20 12:19:45 PM PST 23
Peak memory 197640 kb
Host smart-79cc2941-1a39-4818-bc9c-502a33eede51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181587731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2181587731
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3086166253
Short name T423
Test name
Test status
Simulation time 384461364 ps
CPU time 0.69 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 183764 kb
Host smart-e23f42d7-0227-4185-afa7-4cb5c0c2d639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086166253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3086166253
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2216230319
Short name T14
Test name
Test status
Simulation time 377883842 ps
CPU time 0.61 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 183924 kb
Host smart-8c270080-72bd-4cce-967c-e7d7ebb6450a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216230319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2216230319
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2334310577
Short name T66
Test name
Test status
Simulation time 264326910 ps
CPU time 0.87 seconds
Started Dec 20 12:21:33 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 183552 kb
Host smart-1c13d879-ae55-44c7-a74d-95070f672db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334310577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2334310577
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.735774009
Short name T362
Test name
Test status
Simulation time 316815697 ps
CPU time 0.64 seconds
Started Dec 20 12:21:17 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 183648 kb
Host smart-226d38a2-035c-4cbe-af79-d01bc87ad416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735774009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.735774009
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3448967238
Short name T343
Test name
Test status
Simulation time 292172544 ps
CPU time 0.71 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:28 PM PST 23
Peak memory 183740 kb
Host smart-1c51577d-bc11-433d-821a-82eb20b5eb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448967238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3448967238
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3781257812
Short name T71
Test name
Test status
Simulation time 302681478 ps
CPU time 0.74 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 183904 kb
Host smart-a768a53e-4764-429b-b7c5-bad9247c15cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781257812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3781257812
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2560828996
Short name T46
Test name
Test status
Simulation time 282412732 ps
CPU time 0.93 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:45 PM PST 23
Peak memory 183604 kb
Host smart-79d665bf-37f5-4c6e-a488-933f0597abd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560828996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2560828996
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1783931836
Short name T354
Test name
Test status
Simulation time 382890111 ps
CPU time 1.07 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183980 kb
Host smart-a724db34-18dc-4a9a-8ab7-9928f5296d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783931836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1783931836
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2255503284
Short name T386
Test name
Test status
Simulation time 282853470 ps
CPU time 0.92 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:21:59 PM PST 23
Peak memory 183892 kb
Host smart-6ed3e5af-aece-44fe-b06b-91f39e3044f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255503284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2255503284
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1450272511
Short name T369
Test name
Test status
Simulation time 492800380 ps
CPU time 0.64 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 183652 kb
Host smart-60ea0ed6-345b-4684-bdd5-8977a005fff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450272511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1450272511
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1432679495
Short name T368
Test name
Test status
Simulation time 448630531 ps
CPU time 1.26 seconds
Started Dec 20 12:21:05 PM PST 23
Finished Dec 20 12:21:15 PM PST 23
Peak memory 183808 kb
Host smart-6aacb8e7-e342-4e96-94c8-731d0cecfe2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432679495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1432679495
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1027064575
Short name T62
Test name
Test status
Simulation time 4152181797 ps
CPU time 7.48 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 192248 kb
Host smart-71c1973e-f1eb-4f8f-802c-36f5238f4f97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027064575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1027064575
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.885400796
Short name T56
Test name
Test status
Simulation time 800660312 ps
CPU time 1.72 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 183788 kb
Host smart-7c43caee-1d9d-4794-a486-cdf136ce0d6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885400796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.885400796
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.578802092
Short name T70
Test name
Test status
Simulation time 440736027 ps
CPU time 1.22 seconds
Started Dec 20 12:21:05 PM PST 23
Finished Dec 20 12:21:15 PM PST 23
Peak memory 195280 kb
Host smart-0d03e0a8-b8f3-4bd8-9fc5-3110df0e95a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578802092 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.578802092
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.896127475
Short name T74
Test name
Test status
Simulation time 341525232 ps
CPU time 0.67 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:11 PM PST 23
Peak memory 183816 kb
Host smart-30183188-c556-455e-aca5-2a4e91eb483d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896127475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.896127475
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2245071588
Short name T382
Test name
Test status
Simulation time 288323025 ps
CPU time 0.74 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 183696 kb
Host smart-99f12311-4623-4b52-93d2-77e74a21e02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245071588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2245071588
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2754350376
Short name T24
Test name
Test status
Simulation time 381580077 ps
CPU time 0.7 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 183644 kb
Host smart-a636fd8b-402c-45ea-a7bb-39d66c1e2a0e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754350376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2754350376
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.276901291
Short name T372
Test name
Test status
Simulation time 527788046 ps
CPU time 0.53 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 183572 kb
Host smart-4d884793-8c74-4d87-bcb6-5bc879c06246
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276901291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.276901291
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1894622024
Short name T419
Test name
Test status
Simulation time 1071630757 ps
CPU time 1.42 seconds
Started Dec 20 12:19:34 PM PST 23
Finished Dec 20 12:19:36 PM PST 23
Peak memory 192908 kb
Host smart-61bcef1a-1cfc-4cbf-b1eb-8979766d2112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894622024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1894622024
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.70698466
Short name T407
Test name
Test status
Simulation time 611165634 ps
CPU time 1.68 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 198652 kb
Host smart-72248e34-3d56-4b89-b122-0f97df5c30f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70698466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.70698466
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1127049352
Short name T91
Test name
Test status
Simulation time 4194649040 ps
CPU time 6.37 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 197412 kb
Host smart-925df6fd-0e2a-4916-83a9-8b0d5442db90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127049352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1127049352
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2413988027
Short name T338
Test name
Test status
Simulation time 488964716 ps
CPU time 0.86 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 183968 kb
Host smart-06e92057-2cbf-4fbc-8058-c50cddcba736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413988027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2413988027
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3430944745
Short name T384
Test name
Test status
Simulation time 332107486 ps
CPU time 1.08 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 183884 kb
Host smart-3fbc0f27-ba2c-4e94-9854-266f84bdb26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430944745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3430944745
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1951803275
Short name T342
Test name
Test status
Simulation time 462018342 ps
CPU time 0.74 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 183652 kb
Host smart-0fc35b2a-2d8d-4459-84c3-146740a56d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951803275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1951803275
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2715695366
Short name T53
Test name
Test status
Simulation time 450583262 ps
CPU time 0.69 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 183884 kb
Host smart-d390d85a-b2fe-4dbd-b142-af29468fc381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715695366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2715695366
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3885522327
Short name T321
Test name
Test status
Simulation time 339670131 ps
CPU time 0.73 seconds
Started Dec 20 12:20:30 PM PST 23
Finished Dec 20 12:20:35 PM PST 23
Peak memory 183712 kb
Host smart-f6bc504f-39a2-4317-85b2-d665b10834bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885522327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3885522327
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2912660820
Short name T322
Test name
Test status
Simulation time 467959899 ps
CPU time 0.72 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 183644 kb
Host smart-ad88ec34-0c40-4462-9d6f-7ef579670ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912660820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2912660820
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3341359981
Short name T356
Test name
Test status
Simulation time 374343613 ps
CPU time 0.63 seconds
Started Dec 20 12:21:43 PM PST 23
Finished Dec 20 12:21:57 PM PST 23
Peak memory 183652 kb
Host smart-4a8d450e-fb1f-415d-a0af-05022b28b573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341359981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3341359981
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1179983564
Short name T426
Test name
Test status
Simulation time 357677026 ps
CPU time 1.08 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 183648 kb
Host smart-c6d1c7dd-dfab-4ebb-bac9-229d914b1755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179983564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1179983564
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1504193475
Short name T335
Test name
Test status
Simulation time 433061636 ps
CPU time 1.14 seconds
Started Dec 20 12:20:28 PM PST 23
Finished Dec 20 12:20:34 PM PST 23
Peak memory 183892 kb
Host smart-99501342-0cae-4150-b1a2-4c49f4db10b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504193475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1504193475
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1413557196
Short name T390
Test name
Test status
Simulation time 489082730 ps
CPU time 0.55 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 183892 kb
Host smart-a37a255c-d37d-45a7-bf59-e6a71c68f34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413557196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1413557196
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.525945165
Short name T359
Test name
Test status
Simulation time 514311642 ps
CPU time 1.34 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 195524 kb
Host smart-1e6136cb-759a-49bb-a418-b703e38efc34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525945165 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.525945165
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1854025044
Short name T2
Test name
Test status
Simulation time 507062366 ps
CPU time 1.23 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 183804 kb
Host smart-53d089c5-4f52-4a2b-ab4d-bb4829119f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854025044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1854025044
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3942096568
Short name T328
Test name
Test status
Simulation time 418872613 ps
CPU time 1.11 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:14 PM PST 23
Peak memory 183812 kb
Host smart-3b701df1-b7a9-49fb-9c0e-80385b0d69a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942096568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3942096568
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3151126986
Short name T83
Test name
Test status
Simulation time 1762302825 ps
CPU time 1.75 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:51 PM PST 23
Peak memory 194984 kb
Host smart-76e3ec65-c5b9-4a8a-ba47-0868c5a1af67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151126986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3151126986
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.710991567
Short name T398
Test name
Test status
Simulation time 516435152 ps
CPU time 1.89 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 198752 kb
Host smart-c92d0ffd-a878-429e-9ead-49dbb58f5dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710991567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.710991567
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2183746689
Short name T429
Test name
Test status
Simulation time 8646087702 ps
CPU time 2.07 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:43 PM PST 23
Peak memory 197552 kb
Host smart-b2c0281a-3919-4c43-87f1-0272073afb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183746689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2183746689
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2103654861
Short name T318
Test name
Test status
Simulation time 470543627 ps
CPU time 0.92 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 198448 kb
Host smart-422dd47f-1c61-423c-b3e6-4e6e0290652d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103654861 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2103654861
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.663610002
Short name T408
Test name
Test status
Simulation time 453338176 ps
CPU time 0.72 seconds
Started Dec 20 12:19:34 PM PST 23
Finished Dec 20 12:19:35 PM PST 23
Peak memory 183796 kb
Host smart-3815daa4-2c29-46e5-9e08-62eb565d6272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663610002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.663610002
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2859978800
Short name T68
Test name
Test status
Simulation time 393443466 ps
CPU time 1.14 seconds
Started Dec 20 12:21:05 PM PST 23
Finished Dec 20 12:21:14 PM PST 23
Peak memory 183580 kb
Host smart-123712b9-2d22-4668-8c1a-0dda1c31541c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859978800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2859978800
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1702214761
Short name T405
Test name
Test status
Simulation time 1456795403 ps
CPU time 2.44 seconds
Started Dec 20 12:19:52 PM PST 23
Finished Dec 20 12:19:55 PM PST 23
Peak memory 193460 kb
Host smart-7520ebbd-9d40-47e3-a899-ffe15e0d0be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702214761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1702214761
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4134920336
Short name T315
Test name
Test status
Simulation time 490619401 ps
CPU time 2.62 seconds
Started Dec 20 12:19:58 PM PST 23
Finished Dec 20 12:20:02 PM PST 23
Peak memory 198780 kb
Host smart-e3a43011-161b-44f0-8990-fd5d5fb1b486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134920336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4134920336
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.554987358
Short name T3
Test name
Test status
Simulation time 641969750 ps
CPU time 0.79 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:11 PM PST 23
Peak memory 196184 kb
Host smart-3a1469ed-e14a-4ad4-9c06-1dc14baba507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554987358 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.554987358
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3398143304
Short name T79
Test name
Test status
Simulation time 399175001 ps
CPU time 0.71 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 183804 kb
Host smart-c2f66977-5e89-4c1f-b58b-8f16c84d4828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398143304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3398143304
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4177303220
Short name T347
Test name
Test status
Simulation time 461001288 ps
CPU time 1.22 seconds
Started Dec 20 12:19:58 PM PST 23
Finished Dec 20 12:20:00 PM PST 23
Peak memory 183728 kb
Host smart-7a801929-b95a-43b0-8b65-21584d83ae60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177303220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4177303220
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3650846874
Short name T418
Test name
Test status
Simulation time 1461860125 ps
CPU time 3.43 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 194456 kb
Host smart-a73a190a-3003-4524-81b4-04438a7259b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650846874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3650846874
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3092056114
Short name T329
Test name
Test status
Simulation time 335383081 ps
CPU time 1.47 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 198464 kb
Host smart-a279fbf4-2642-43d0-a3c2-3292abd247da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092056114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3092056114
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3773086304
Short name T93
Test name
Test status
Simulation time 8578239019 ps
CPU time 12.85 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:58 PM PST 23
Peak memory 197636 kb
Host smart-a11e1faf-e619-4671-baf2-9fca1a39fce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773086304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3773086304
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2505903541
Short name T389
Test name
Test status
Simulation time 434118728 ps
CPU time 0.8 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 196212 kb
Host smart-1e080683-43e0-4297-8c82-c7386336d80a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505903541 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2505903541
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2150048858
Short name T8
Test name
Test status
Simulation time 492737540 ps
CPU time 1.2 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 183932 kb
Host smart-46811fdb-12ec-4e77-b4d0-5c8751da4901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150048858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2150048858
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1644719911
Short name T365
Test name
Test status
Simulation time 475934776 ps
CPU time 0.68 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 183756 kb
Host smart-57775dfd-fe79-4607-9ee7-7d3fea3ecd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644719911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1644719911
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3636001766
Short name T80
Test name
Test status
Simulation time 2291365087 ps
CPU time 3 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:16 PM PST 23
Peak memory 192256 kb
Host smart-5ea521e1-680b-47c2-9097-780e7fb291a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636001766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3636001766
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2645002050
Short name T415
Test name
Test status
Simulation time 511847871 ps
CPU time 1.76 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 198508 kb
Host smart-cfa9d678-cc7b-4d34-bb35-ca64412366c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645002050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2645002050
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3541546840
Short name T394
Test name
Test status
Simulation time 4360998064 ps
CPU time 2.35 seconds
Started Dec 20 12:19:50 PM PST 23
Finished Dec 20 12:19:53 PM PST 23
Peak memory 196036 kb
Host smart-ef419ff2-363e-4219-b520-8a276184c217
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541546840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3541546840
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3865196242
Short name T54
Test name
Test status
Simulation time 410177223 ps
CPU time 1.23 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 195124 kb
Host smart-5948b1bf-c888-4742-95fb-095ab3b75a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865196242 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3865196242
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2143959324
Short name T336
Test name
Test status
Simulation time 404114622 ps
CPU time 0.71 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:11 PM PST 23
Peak memory 183900 kb
Host smart-f47a5085-2105-4f3f-87b9-4aa6c0a28356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143959324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2143959324
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.849781272
Short name T72
Test name
Test status
Simulation time 400018880 ps
CPU time 0.65 seconds
Started Dec 20 12:19:47 PM PST 23
Finished Dec 20 12:19:48 PM PST 23
Peak memory 183700 kb
Host smart-ff401934-594d-46f8-892d-d14f2ffef34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849781272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.849781272
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1455399269
Short name T86
Test name
Test status
Simulation time 1333906540 ps
CPU time 1.55 seconds
Started Dec 20 12:20:40 PM PST 23
Finished Dec 20 12:20:47 PM PST 23
Peak memory 192760 kb
Host smart-13592120-bc64-4e8d-96ed-5e63bb3955b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455399269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1455399269
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1341774984
Short name T45
Test name
Test status
Simulation time 583934548 ps
CPU time 1.38 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 198612 kb
Host smart-a57fe81f-f071-4788-9d80-f63e7f779b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341774984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1341774984
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3801521112
Short name T11
Test name
Test status
Simulation time 8551837169 ps
CPU time 3.82 seconds
Started Dec 20 12:19:55 PM PST 23
Finished Dec 20 12:20:00 PM PST 23
Peak memory 197832 kb
Host smart-9414f73f-7f2c-44ac-928c-f6100e2c9f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801521112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3801521112
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3447412881
Short name T127
Test name
Test status
Simulation time 420549713 ps
CPU time 0.82 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 182800 kb
Host smart-f4cf671d-f899-4aec-a082-2c4bcdee8de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447412881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3447412881
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2447661376
Short name T232
Test name
Test status
Simulation time 22242098694 ps
CPU time 8.59 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 182872 kb
Host smart-fbc452de-6045-4ca0-8c08-8a528a71a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447661376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2447661376
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.654218188
Short name T162
Test name
Test status
Simulation time 572211432 ps
CPU time 0.74 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 182708 kb
Host smart-59570309-f3d2-4fef-832c-9233d29ea1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654218188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.654218188
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2299569672
Short name T247
Test name
Test status
Simulation time 42649178089 ps
CPU time 60.07 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 182884 kb
Host smart-5652682f-b3a6-44ab-aa85-c0d798dccd56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299569672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2299569672
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3496724677
Short name T52
Test name
Test status
Simulation time 230713828215 ps
CPU time 338.69 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:27:37 PM PST 23
Peak memory 197772 kb
Host smart-aa4a35a6-f86e-4daa-b379-c3629f49002e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496724677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3496724677
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1831814563
Short name T240
Test name
Test status
Simulation time 439704104 ps
CPU time 1.13 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182812 kb
Host smart-c079abe1-a9d7-4023-8ad8-56be9b9223cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831814563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1831814563
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3542614087
Short name T18
Test name
Test status
Simulation time 843873196 ps
CPU time 0.68 seconds
Started Dec 20 12:21:33 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 182744 kb
Host smart-fc49c2f7-f2dc-4aa8-bd13-60127feabece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542614087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3542614087
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1654531349
Short name T31
Test name
Test status
Simulation time 4461565238 ps
CPU time 1.14 seconds
Started Dec 20 12:22:00 PM PST 23
Finished Dec 20 12:22:05 PM PST 23
Peak memory 214980 kb
Host smart-c1778f6e-f7da-495d-aa55-3d62bf53b580
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654531349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1654531349
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.1364920617
Short name T172
Test name
Test status
Simulation time 586619517 ps
CPU time 0.58 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:21:50 PM PST 23
Peak memory 182904 kb
Host smart-ce7b1bbd-664b-4192-a89c-b2eeaa4ee00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364920617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.1364920617
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1408236638
Short name T112
Test name
Test status
Simulation time 67433187447 ps
CPU time 94.69 seconds
Started Dec 20 12:20:29 PM PST 23
Finished Dec 20 12:22:08 PM PST 23
Peak memory 192984 kb
Host smart-c1268f25-b284-4677-b6a1-c842d36836bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408236638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1408236638
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.462734668
Short name T109
Test name
Test status
Simulation time 326272894676 ps
CPU time 352.33 seconds
Started Dec 20 12:20:18 PM PST 23
Finished Dec 20 12:26:11 PM PST 23
Peak memory 197716 kb
Host smart-d3f1c737-fe43-47e8-b95b-5f26346a016f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462734668 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.462734668
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.964031843
Short name T185
Test name
Test status
Simulation time 567018639 ps
CPU time 1.38 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:24 PM PST 23
Peak memory 182796 kb
Host smart-4c225b31-f52e-45bd-b6ee-5998eccd95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964031843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.964031843
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.968051258
Short name T233
Test name
Test status
Simulation time 3088583559 ps
CPU time 4.83 seconds
Started Dec 20 12:20:17 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 182896 kb
Host smart-bda57b3b-b5ae-4582-9abb-25a77958c1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968051258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.968051258
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2663336898
Short name T212
Test name
Test status
Simulation time 512387636 ps
CPU time 1.27 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:37 PM PST 23
Peak memory 182688 kb
Host smart-63e97313-4052-4d36-9e9d-25203a0b6408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663336898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2663336898
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1303808409
Short name T119
Test name
Test status
Simulation time 206588935052 ps
CPU time 333.9 seconds
Started Dec 20 12:21:43 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 193116 kb
Host smart-f7804c7e-8983-4baa-b880-ea2e1ebd7ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303808409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1303808409
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2435509893
Short name T274
Test name
Test status
Simulation time 21589124884 ps
CPU time 178.36 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:23:30 PM PST 23
Peak memory 197760 kb
Host smart-511f26e1-796c-4497-b3ad-ff4d8f1b602c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435509893 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2435509893
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.828730447
Short name T26
Test name
Test status
Simulation time 490723502 ps
CPU time 1.27 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 182892 kb
Host smart-c1363e39-253d-4c64-84d8-a7759ecb5571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828730447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.828730447
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4098031877
Short name T183
Test name
Test status
Simulation time 5867427309 ps
CPU time 1.46 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 182800 kb
Host smart-c6775e06-baa3-4fe3-8c79-6fa312748fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098031877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4098031877
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1468907699
Short name T216
Test name
Test status
Simulation time 577245109 ps
CPU time 0.94 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 182796 kb
Host smart-714fcd5e-0665-416a-aaed-06eaba257a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468907699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1468907699
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3832529079
Short name T108
Test name
Test status
Simulation time 198979433843 ps
CPU time 81.8 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:22:56 PM PST 23
Peak memory 192932 kb
Host smart-3626e50e-fb9e-4cce-b075-6c8155b7b2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832529079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3832529079
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.324188699
Short name T139
Test name
Test status
Simulation time 97465257799 ps
CPU time 230.68 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:24:35 PM PST 23
Peak memory 197744 kb
Host smart-63a78a37-4449-47ab-b240-a927ac387f4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324188699 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.324188699
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1146673388
Short name T186
Test name
Test status
Simulation time 413503188 ps
CPU time 0.67 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 182824 kb
Host smart-670b0973-83ce-4273-a98f-f11c9189a17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146673388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1146673388
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2487409985
Short name T152
Test name
Test status
Simulation time 33105875561 ps
CPU time 13.07 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 182872 kb
Host smart-d7fa8ca2-9942-42f6-b97f-d31c7c2e4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487409985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2487409985
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2685297648
Short name T146
Test name
Test status
Simulation time 374739684 ps
CPU time 1.18 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 182700 kb
Host smart-c5a8396e-46ac-48db-aca8-fd2ddbfa11ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685297648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2685297648
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.847969406
Short name T250
Test name
Test status
Simulation time 312424369902 ps
CPU time 117.99 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:23:44 PM PST 23
Peak memory 194080 kb
Host smart-36086bc9-763d-4db0-ace9-fc85d77cf7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847969406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.847969406
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1799992047
Short name T271
Test name
Test status
Simulation time 86276028688 ps
CPU time 667.3 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:31:28 PM PST 23
Peak memory 199256 kb
Host smart-9c6c299f-c96e-4a26-b1be-f42ea06d9724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799992047 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1799992047
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.4047362936
Short name T298
Test name
Test status
Simulation time 594406657 ps
CPU time 1.07 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:22 PM PST 23
Peak memory 182820 kb
Host smart-f981e5f6-f300-47f6-b20f-e0dd3b34311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047362936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.4047362936
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3689571457
Short name T260
Test name
Test status
Simulation time 36943428629 ps
CPU time 13.35 seconds
Started Dec 20 12:21:25 PM PST 23
Finished Dec 20 12:21:57 PM PST 23
Peak memory 182836 kb
Host smart-fa444d0f-b5bf-442b-a69d-bbcfdfaabb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689571457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3689571457
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2238996607
Short name T295
Test name
Test status
Simulation time 513555382 ps
CPU time 1.28 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:17 PM PST 23
Peak memory 182696 kb
Host smart-6a513bf1-5d7b-4286-831b-6f83b7c8abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238996607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2238996607
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2080766992
Short name T227
Test name
Test status
Simulation time 88744869622 ps
CPU time 33.99 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:59 PM PST 23
Peak memory 182908 kb
Host smart-b4a0f7fe-ab7a-423e-84fc-f72acb509bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080766992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2080766992
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2093641811
Short name T225
Test name
Test status
Simulation time 190023954274 ps
CPU time 188.93 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:24:31 PM PST 23
Peak memory 197764 kb
Host smart-7c3cba95-1b02-4b1f-a439-ec90eef5bc12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093641811 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2093641811
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3144013676
Short name T302
Test name
Test status
Simulation time 544880157 ps
CPU time 0.9 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:21 PM PST 23
Peak memory 182820 kb
Host smart-9f4badd7-5a63-4e8e-ae4c-35c7f19fd333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144013676 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3144013676
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3406922907
Short name T165
Test name
Test status
Simulation time 27978712894 ps
CPU time 45.26 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:22:31 PM PST 23
Peak memory 182820 kb
Host smart-0b86f06b-4fd2-4c63-b5ac-06cee138e878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406922907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3406922907
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.979178883
Short name T214
Test name
Test status
Simulation time 464836166 ps
CPU time 0.75 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 182668 kb
Host smart-febd1713-2fcb-4a9b-9eeb-af3da07027cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979178883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.979178883
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1889232142
Short name T22
Test name
Test status
Simulation time 96815422114 ps
CPU time 154.41 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:23:06 PM PST 23
Peak memory 182892 kb
Host smart-ba17db00-1116-44b1-b0d6-e40494043f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889232142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1889232142
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1620801304
Short name T303
Test name
Test status
Simulation time 367449695692 ps
CPU time 281.15 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:26:33 PM PST 23
Peak memory 197724 kb
Host smart-72c22cb7-a002-4330-811e-c158a670a8e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620801304 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1620801304
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3925018230
Short name T98
Test name
Test status
Simulation time 593356005 ps
CPU time 1.42 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182824 kb
Host smart-81045dc9-0d55-4d3e-9c30-f1ea72a93301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925018230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3925018230
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.896044421
Short name T202
Test name
Test status
Simulation time 22315533272 ps
CPU time 32.06 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:52 PM PST 23
Peak memory 182868 kb
Host smart-658575bf-fe03-4935-a0b5-1f0673a752b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896044421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.896044421
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3621509558
Short name T276
Test name
Test status
Simulation time 357571884 ps
CPU time 1.07 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182812 kb
Host smart-ec37c0e3-9a19-4c70-923c-50f787d0a796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621509558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3621509558
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3314044099
Short name T228
Test name
Test status
Simulation time 132445024395 ps
CPU time 201.18 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:24:45 PM PST 23
Peak memory 182872 kb
Host smart-2eeb25f8-c90c-4d50-ba90-3a7e2218bc08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314044099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3314044099
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.811445407
Short name T311
Test name
Test status
Simulation time 51890041064 ps
CPU time 497.53 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 197712 kb
Host smart-4981f4f9-b841-4359-9cb2-f710aa9c9ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811445407 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.811445407
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.409848677
Short name T125
Test name
Test status
Simulation time 578101044 ps
CPU time 0.95 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:27 PM PST 23
Peak memory 182824 kb
Host smart-e0a7d348-01ca-4104-8b08-52f0c21b1aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409848677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.409848677
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1035316767
Short name T213
Test name
Test status
Simulation time 19364320480 ps
CPU time 31.32 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:22:01 PM PST 23
Peak memory 182936 kb
Host smart-104d0225-45e3-464e-88f2-83050e2439a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035316767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1035316767
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3879390751
Short name T226
Test name
Test status
Simulation time 515238169 ps
CPU time 0.58 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 182716 kb
Host smart-9915cf43-7fdd-49a6-9b15-e47490ccfce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879390751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3879390751
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2396016849
Short name T178
Test name
Test status
Simulation time 90209632037 ps
CPU time 33.05 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:53 PM PST 23
Peak memory 192960 kb
Host smart-e56ac49e-de03-4e95-b3cd-d63f784a26cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396016849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2396016849
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3102453420
Short name T49
Test name
Test status
Simulation time 47640511843 ps
CPU time 342.59 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:27:13 PM PST 23
Peak memory 197644 kb
Host smart-c8124f49-e87b-4c09-a1b5-f58924be91e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102453420 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3102453420
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2632853745
Short name T170
Test name
Test status
Simulation time 502748511 ps
CPU time 1.41 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 182828 kb
Host smart-d38c04bb-fac2-4924-9c29-def4af804e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632853745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2632853745
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.151675543
Short name T307
Test name
Test status
Simulation time 14009265382 ps
CPU time 12.25 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:21:59 PM PST 23
Peak memory 182836 kb
Host smart-032adac0-2b90-410e-91b4-3d2e0a6d2a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151675543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.151675543
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3736506489
Short name T219
Test name
Test status
Simulation time 480530944 ps
CPU time 1.33 seconds
Started Dec 20 12:21:15 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 182764 kb
Host smart-7b127205-997c-471f-b91d-1481b944aab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736506489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3736506489
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3755687502
Short name T120
Test name
Test status
Simulation time 232987811045 ps
CPU time 570.11 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:31:03 PM PST 23
Peak memory 198924 kb
Host smart-26bda828-7c8b-4c77-846c-e4ba8b778194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755687502 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3755687502
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1002333295
Short name T239
Test name
Test status
Simulation time 534942059 ps
CPU time 0.71 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182784 kb
Host smart-0820a466-bcf1-46e8-aa8f-b0d13ae4490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002333295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1002333295
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2034882194
Short name T300
Test name
Test status
Simulation time 35258766313 ps
CPU time 50.3 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:22:22 PM PST 23
Peak memory 182836 kb
Host smart-41d4a384-a36a-4cea-9d43-9bc99c0052a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034882194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2034882194
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.768431340
Short name T280
Test name
Test status
Simulation time 366650284 ps
CPU time 0.63 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182792 kb
Host smart-638c742b-5f19-48e0-a3f4-df54dd9340d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768431340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.768431340
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3340053394
Short name T241
Test name
Test status
Simulation time 149576849625 ps
CPU time 205.82 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:25:05 PM PST 23
Peak memory 193200 kb
Host smart-87ef0534-2e96-4d0e-9d7c-3a9ab3695c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340053394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3340053394
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2779654579
Short name T121
Test name
Test status
Simulation time 571794000 ps
CPU time 0.77 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182852 kb
Host smart-5a309ac8-1689-4238-914b-de9f392a5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779654579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2779654579
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1381271614
Short name T201
Test name
Test status
Simulation time 1094910420 ps
CPU time 0.95 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182680 kb
Host smart-a5b15028-739f-49d2-83de-75ab75ac4c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381271614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1381271614
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1889672048
Short name T28
Test name
Test status
Simulation time 440855235 ps
CPU time 1.13 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182684 kb
Host smart-9721530c-47da-43ac-b90f-284618403858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889672048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1889672048
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2221379219
Short name T273
Test name
Test status
Simulation time 156748602857 ps
CPU time 217.87 seconds
Started Dec 20 12:21:42 PM PST 23
Finished Dec 20 12:25:33 PM PST 23
Peak memory 182868 kb
Host smart-9da1cb5e-7cb2-4784-b156-297f22daa58d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221379219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2221379219
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3082601113
Short name T309
Test name
Test status
Simulation time 65016422275 ps
CPU time 618.57 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:31:47 PM PST 23
Peak memory 197760 kb
Host smart-3ea8d04e-4dd7-4405-b5d3-f4e03804b223
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082601113 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3082601113
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3928622774
Short name T291
Test name
Test status
Simulation time 416151250 ps
CPU time 0.69 seconds
Started Dec 20 12:20:41 PM PST 23
Finished Dec 20 12:20:47 PM PST 23
Peak memory 182776 kb
Host smart-e5dbab2f-d9ec-4267-9792-13c07efef3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928622774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3928622774
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3361785212
Short name T179
Test name
Test status
Simulation time 29377367342 ps
CPU time 34.63 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:22:09 PM PST 23
Peak memory 182900 kb
Host smart-cd843776-6f66-4a04-b5c0-0b408bdc6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361785212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3361785212
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1742460478
Short name T30
Test name
Test status
Simulation time 4517167044 ps
CPU time 3.54 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 214932 kb
Host smart-a936f1f7-67be-48a3-9d6c-49e27426b34d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742460478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1742460478
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.617980493
Short name T252
Test name
Test status
Simulation time 639196377 ps
CPU time 0.62 seconds
Started Dec 20 12:21:16 PM PST 23
Finished Dec 20 12:21:37 PM PST 23
Peak memory 182700 kb
Host smart-eed6b8b3-7511-4a7a-a6ec-eb9a77a6e56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617980493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.617980493
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.284019398
Short name T114
Test name
Test status
Simulation time 133519833176 ps
CPU time 108.61 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:23:03 PM PST 23
Peak memory 193256 kb
Host smart-e68366c7-07af-4bb6-9572-11f96b5cb743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284019398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.284019398
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1424233809
Short name T131
Test name
Test status
Simulation time 370599227 ps
CPU time 0.81 seconds
Started Dec 20 12:21:45 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 182792 kb
Host smart-66968d7e-8f17-4379-84a6-484e3f3b2d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424233809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1424233809
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3863637434
Short name T243
Test name
Test status
Simulation time 10260479885 ps
CPU time 2.85 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 182884 kb
Host smart-d4f6e1a4-4307-4819-8579-57b6d3b13e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863637434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3863637434
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1490115693
Short name T281
Test name
Test status
Simulation time 544238731 ps
CPU time 0.67 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 182752 kb
Host smart-83365b3e-c4db-493c-b8be-d9e2cd9b67f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490115693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1490115693
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4166392239
Short name T110
Test name
Test status
Simulation time 216306234681 ps
CPU time 174.4 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:24:52 PM PST 23
Peak memory 182856 kb
Host smart-d165047e-2099-4524-beb5-d0135a31234c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166392239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4166392239
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3939204190
Short name T278
Test name
Test status
Simulation time 77870364226 ps
CPU time 293.99 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:26:42 PM PST 23
Peak memory 197868 kb
Host smart-7cb28c14-e573-4e27-b7ed-4a446738686d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939204190 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3939204190
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2724923580
Short name T205
Test name
Test status
Simulation time 372380408 ps
CPU time 0.64 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 182808 kb
Host smart-e158acd0-5316-4c11-9439-a1d824d54c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724923580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2724923580
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.367438582
Short name T140
Test name
Test status
Simulation time 12488411765 ps
CPU time 18.53 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:22:04 PM PST 23
Peak memory 182860 kb
Host smart-4c5ee4be-8f77-48d0-ab5e-89c7bffa3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367438582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.367438582
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.718217036
Short name T151
Test name
Test status
Simulation time 343201744 ps
CPU time 0.98 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 182684 kb
Host smart-d7c6c366-268a-44fb-a96b-bd096291072c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718217036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.718217036
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1653251176
Short name T246
Test name
Test status
Simulation time 35477551807 ps
CPU time 186.79 seconds
Started Dec 20 12:21:45 PM PST 23
Finished Dec 20 12:25:06 PM PST 23
Peak memory 197700 kb
Host smart-ce64d598-dec7-438b-9440-bf1eb9571f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653251176 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1653251176
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3152039369
Short name T97
Test name
Test status
Simulation time 554038658 ps
CPU time 1.4 seconds
Started Dec 20 12:20:15 PM PST 23
Finished Dec 20 12:20:18 PM PST 23
Peak memory 182848 kb
Host smart-567aa1cc-365f-4ca5-9f24-189e683e5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152039369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3152039369
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3452613012
Short name T157
Test name
Test status
Simulation time 6772675592 ps
CPU time 3.1 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 182944 kb
Host smart-f0a8a5b3-7e43-4e1a-bbc4-47c353e71bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452613012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3452613012
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1603097829
Short name T160
Test name
Test status
Simulation time 376886303 ps
CPU time 0.8 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 182876 kb
Host smart-f4a7c08f-796a-446a-a42b-28d839401472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603097829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1603097829
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3318420366
Short name T174
Test name
Test status
Simulation time 167011306939 ps
CPU time 250.66 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:24:55 PM PST 23
Peak memory 182868 kb
Host smart-18f52b19-d510-4881-b096-75e67b86b60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318420366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3318420366
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3201803811
Short name T208
Test name
Test status
Simulation time 434733927 ps
CPU time 0.67 seconds
Started Dec 20 12:20:18 PM PST 23
Finished Dec 20 12:20:20 PM PST 23
Peak memory 182968 kb
Host smart-46ec1c76-35dc-4988-b833-88ac435fc8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201803811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3201803811
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3123052775
Short name T173
Test name
Test status
Simulation time 6948504580 ps
CPU time 2.05 seconds
Started Dec 20 12:20:14 PM PST 23
Finished Dec 20 12:20:18 PM PST 23
Peak memory 182992 kb
Host smart-3d095fdc-2410-4adf-9f58-7083a3c3cdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123052775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3123052775
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2204549823
Short name T206
Test name
Test status
Simulation time 403324507 ps
CPU time 1.15 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 182800 kb
Host smart-26aad594-242b-4dbc-a0b9-6206ebb7c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204549823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2204549823
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.543921282
Short name T47
Test name
Test status
Simulation time 185527868808 ps
CPU time 157.6 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:23:18 PM PST 23
Peak memory 182812 kb
Host smart-337bfdde-af9a-4e3a-a656-5939739454be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543921282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.543921282
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1327316505
Short name T118
Test name
Test status
Simulation time 141260420949 ps
CPU time 581.35 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:30:19 PM PST 23
Peak memory 197772 kb
Host smart-4ad6bc12-b89b-4808-831a-2991787c3ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327316505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1327316505
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1137048560
Short name T169
Test name
Test status
Simulation time 403981575 ps
CPU time 1.24 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182824 kb
Host smart-885e502a-da97-4b17-8a2a-ee9b0190ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137048560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1137048560
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3894191832
Short name T159
Test name
Test status
Simulation time 3508501250 ps
CPU time 3.12 seconds
Started Dec 20 12:20:09 PM PST 23
Finished Dec 20 12:20:14 PM PST 23
Peak memory 182852 kb
Host smart-0a16908b-56cd-47e5-80f8-716118b7f5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894191832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3894191832
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3744409294
Short name T266
Test name
Test status
Simulation time 334627609 ps
CPU time 1.04 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:20:42 PM PST 23
Peak memory 182844 kb
Host smart-2ae4bea7-0f11-4021-b575-88b98fd0e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744409294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3744409294
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1187553776
Short name T105
Test name
Test status
Simulation time 62905222172 ps
CPU time 90.69 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:22:11 PM PST 23
Peak memory 194296 kb
Host smart-288e5480-40ef-452b-84c5-5acc38f5086f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187553776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1187553776
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3255862461
Short name T285
Test name
Test status
Simulation time 116451437759 ps
CPU time 646.44 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:31:30 PM PST 23
Peak memory 199596 kb
Host smart-db8c1f3b-2f11-4f44-8c4d-d40440114a37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255862461 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3255862461
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3687489654
Short name T199
Test name
Test status
Simulation time 484330591 ps
CPU time 1.32 seconds
Started Dec 20 12:20:07 PM PST 23
Finished Dec 20 12:20:09 PM PST 23
Peak memory 182848 kb
Host smart-91f50a90-8554-4186-8e0a-09623d065bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687489654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3687489654
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2404334973
Short name T224
Test name
Test status
Simulation time 35573926670 ps
CPU time 52.37 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 182956 kb
Host smart-842fa1b2-c044-4db1-865d-25f994181326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404334973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2404334973
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3676979253
Short name T154
Test name
Test status
Simulation time 340887919 ps
CPU time 1.04 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:37 PM PST 23
Peak memory 182904 kb
Host smart-7deb7029-78ad-4427-9266-a5458eb31923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676979253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3676979253
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.909831122
Short name T312
Test name
Test status
Simulation time 18512172326 ps
CPU time 11.94 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 182868 kb
Host smart-9f9f00ca-2348-46c7-9ec3-6cf7d0e7f7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909831122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.909831122
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3806634013
Short name T197
Test name
Test status
Simulation time 66927841808 ps
CPU time 549.28 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:29:24 PM PST 23
Peak memory 197756 kb
Host smart-9e9926e5-5411-4053-af49-7417effdb93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806634013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3806634013
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2018858722
Short name T279
Test name
Test status
Simulation time 427617085 ps
CPU time 0.62 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:41 PM PST 23
Peak memory 182924 kb
Host smart-e819d407-6410-44ce-9825-a83d08db23bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018858722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2018858722
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1274750783
Short name T296
Test name
Test status
Simulation time 5840018137 ps
CPU time 1.11 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:22 PM PST 23
Peak memory 182992 kb
Host smart-24df95a6-da32-4abf-a95e-e881e18f879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274750783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1274750783
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.717804246
Short name T187
Test name
Test status
Simulation time 406558306 ps
CPU time 0.71 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 182692 kb
Host smart-b1ae770f-8788-4bde-aeb6-5735fb16dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717804246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.717804246
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3196049154
Short name T130
Test name
Test status
Simulation time 54809660859 ps
CPU time 17.19 seconds
Started Dec 20 12:20:14 PM PST 23
Finished Dec 20 12:20:34 PM PST 23
Peak memory 193096 kb
Host smart-a648b268-67f5-4ecb-b6b2-c2ec7a5d6477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196049154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3196049154
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3050732477
Short name T207
Test name
Test status
Simulation time 14802758531 ps
CPU time 105.59 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:22:26 PM PST 23
Peak memory 197740 kb
Host smart-6858b983-9821-40f7-9f4d-8fc0106481fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050732477 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3050732477
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1662213002
Short name T292
Test name
Test status
Simulation time 455366660 ps
CPU time 1.2 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:20:55 PM PST 23
Peak memory 182884 kb
Host smart-3e18bbdf-c5c9-46d2-bf92-922d2d27b727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662213002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1662213002
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1020176959
Short name T242
Test name
Test status
Simulation time 22260370024 ps
CPU time 34.19 seconds
Started Dec 20 12:20:37 PM PST 23
Finished Dec 20 12:21:21 PM PST 23
Peak memory 182848 kb
Host smart-7ac31e80-c0d8-4bed-9d50-cd9fff2b33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020176959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1020176959
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2879941426
Short name T263
Test name
Test status
Simulation time 425925146 ps
CPU time 1.18 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182724 kb
Host smart-1c57c80a-de01-44c9-8d27-6cdd976c20a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879941426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2879941426
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.889081706
Short name T135
Test name
Test status
Simulation time 148037548317 ps
CPU time 225.85 seconds
Started Dec 20 12:20:16 PM PST 23
Finished Dec 20 12:24:03 PM PST 23
Peak memory 193080 kb
Host smart-bb9c4c5f-666e-48dd-9905-9a50aa3be41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889081706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.889081706
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.525288275
Short name T132
Test name
Test status
Simulation time 321831675563 ps
CPU time 275.53 seconds
Started Dec 20 12:20:13 PM PST 23
Finished Dec 20 12:24:50 PM PST 23
Peak memory 197736 kb
Host smart-1114268b-80d1-4613-a10b-517de2f35cd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525288275 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.525288275
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2545112307
Short name T163
Test name
Test status
Simulation time 579976841 ps
CPU time 1.47 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 182772 kb
Host smart-841508da-a1ca-4d23-b926-f755ac1e0ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545112307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2545112307
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3472574665
Short name T37
Test name
Test status
Simulation time 45059901929 ps
CPU time 17.61 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 182980 kb
Host smart-af967799-52b6-43de-8cae-c705eb86fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472574665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3472574665
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3766795289
Short name T195
Test name
Test status
Simulation time 581854048 ps
CPU time 0.66 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 182436 kb
Host smart-cbe364b4-b86e-4ee7-a6d5-9d34709d892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766795289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3766795289
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3189922385
Short name T116
Test name
Test status
Simulation time 89054566888 ps
CPU time 33.96 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:21:11 PM PST 23
Peak memory 182764 kb
Host smart-d013f9b9-bfe0-4ce8-9f28-c4bfcd628815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189922385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3189922385
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.669811489
Short name T217
Test name
Test status
Simulation time 121199693875 ps
CPU time 255.07 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:26:08 PM PST 23
Peak memory 205924 kb
Host smart-417bf113-eba0-4c45-b302-84a2c7c5a485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669811489 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.669811489
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2229819617
Short name T264
Test name
Test status
Simulation time 485577335 ps
CPU time 0.92 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 182856 kb
Host smart-12e7e4e8-4a0f-4792-a2c1-a33f869e7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229819617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2229819617
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.354107439
Short name T149
Test name
Test status
Simulation time 26888172007 ps
CPU time 22.29 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:45 PM PST 23
Peak memory 182844 kb
Host smart-7ef9f302-9cc2-437d-9415-a8a006f0e9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354107439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.354107439
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2054071127
Short name T167
Test name
Test status
Simulation time 554073276 ps
CPU time 1.31 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 182800 kb
Host smart-bcead5f5-99c2-46d6-b013-31b8d072940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054071127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2054071127
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1182231051
Short name T99
Test name
Test status
Simulation time 114555124363 ps
CPU time 45.26 seconds
Started Dec 20 12:20:51 PM PST 23
Finished Dec 20 12:21:44 PM PST 23
Peak memory 192976 kb
Host smart-bcf1e8bc-2f31-4e09-9f0b-8490035359d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182231051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1182231051
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.102065869
Short name T27
Test name
Test status
Simulation time 78931655284 ps
CPU time 368.58 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 197628 kb
Host smart-f98a1c64-d663-493c-880d-da7be3b42a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102065869 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.102065869
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1228453361
Short name T137
Test name
Test status
Simulation time 521872632 ps
CPU time 0.71 seconds
Started Dec 20 12:20:12 PM PST 23
Finished Dec 20 12:20:14 PM PST 23
Peak memory 182840 kb
Host smart-4739a8d8-8912-44c4-a5ec-4dba5901a77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228453361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1228453361
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.391021752
Short name T164
Test name
Test status
Simulation time 35687574921 ps
CPU time 12.2 seconds
Started Dec 20 12:21:24 PM PST 23
Finished Dec 20 12:21:55 PM PST 23
Peak memory 182836 kb
Host smart-d757f812-b896-4c53-afc5-2d8758cd9aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391021752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.391021752
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2969236276
Short name T32
Test name
Test status
Simulation time 8255084193 ps
CPU time 3.61 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:21:49 PM PST 23
Peak memory 215012 kb
Host smart-8957c902-8c1a-423d-bf8c-250c06374442
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969236276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2969236276
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1866555557
Short name T289
Test name
Test status
Simulation time 502851067 ps
CPU time 1.23 seconds
Started Dec 20 12:21:44 PM PST 23
Finished Dec 20 12:21:59 PM PST 23
Peak memory 182664 kb
Host smart-cb39520e-fee7-4edf-915b-46aed9d2aa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866555557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1866555557
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.494054935
Short name T100
Test name
Test status
Simulation time 123515708306 ps
CPU time 180.53 seconds
Started Dec 20 12:21:28 PM PST 23
Finished Dec 20 12:24:46 PM PST 23
Peak memory 194188 kb
Host smart-c7a116c0-4262-49eb-81f2-0c052459fe88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494054935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.494054935
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4085854645
Short name T161
Test name
Test status
Simulation time 492772202 ps
CPU time 1.34 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182896 kb
Host smart-14852465-0c47-43f3-8177-31ec0a59c8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085854645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4085854645
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4046613188
Short name T204
Test name
Test status
Simulation time 11274248104 ps
CPU time 4.88 seconds
Started Dec 20 12:20:49 PM PST 23
Finished Dec 20 12:21:02 PM PST 23
Peak memory 182852 kb
Host smart-53a62e5f-1ce2-4957-9662-dc3d7ac6e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046613188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4046613188
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.2678371998
Short name T230
Test name
Test status
Simulation time 496224285 ps
CPU time 0.91 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:20:38 PM PST 23
Peak memory 182664 kb
Host smart-22a29806-d19f-4d07-80e0-271cf1d07a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678371998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.2678371998
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3744224347
Short name T211
Test name
Test status
Simulation time 99732470384 ps
CPU time 158 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:23:22 PM PST 23
Peak memory 192980 kb
Host smart-3402ec75-7e26-44be-b56d-dd747c070665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744224347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3744224347
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2029206907
Short name T244
Test name
Test status
Simulation time 14136280051 ps
CPU time 141.32 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 197688 kb
Host smart-6744cfeb-2fb8-4ed7-aff2-46deed66979f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029206907 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2029206907
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2164914158
Short name T17
Test name
Test status
Simulation time 412223538 ps
CPU time 0.72 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182816 kb
Host smart-1badab76-5d5d-4f94-b80d-6079d73ab062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164914158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2164914158
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.281343903
Short name T269
Test name
Test status
Simulation time 23982214351 ps
CPU time 13.24 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 182808 kb
Host smart-c3ae260b-d6df-4b6f-a711-d179f99c77ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281343903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.281343903
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.319307983
Short name T283
Test name
Test status
Simulation time 376225077 ps
CPU time 1.03 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:21:50 PM PST 23
Peak memory 182744 kb
Host smart-25eec847-3863-4077-8774-33b017cf26fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319307983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.319307983
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.983207235
Short name T117
Test name
Test status
Simulation time 60102334868 ps
CPU time 90.11 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:23:19 PM PST 23
Peak memory 192804 kb
Host smart-6f717646-2eb1-43fa-864d-cf70623d763d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983207235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.983207235
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.319898711
Short name T265
Test name
Test status
Simulation time 18626117554 ps
CPU time 196.27 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:23:58 PM PST 23
Peak memory 197712 kb
Host smart-a01fbe72-784e-4f72-b242-a3f9e9ebd0ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319898711 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.319898711
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3587904003
Short name T58
Test name
Test status
Simulation time 534902562 ps
CPU time 1.32 seconds
Started Dec 20 12:20:55 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 182812 kb
Host smart-45fc0c4f-911a-4490-a093-f43001f60972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587904003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3587904003
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3668625850
Short name T191
Test name
Test status
Simulation time 31184480072 ps
CPU time 24.01 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:22:17 PM PST 23
Peak memory 182840 kb
Host smart-64505328-9690-45dc-9d3b-0f5efc76d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668625850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3668625850
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1226481983
Short name T299
Test name
Test status
Simulation time 459747243 ps
CPU time 1.29 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 182684 kb
Host smart-573ae819-e50f-41af-9732-7c0c3de50ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226481983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1226481983
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2521700568
Short name T88
Test name
Test status
Simulation time 199197632500 ps
CPU time 344.79 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:27:05 PM PST 23
Peak memory 197712 kb
Host smart-9318e622-f410-40a5-8832-6aba6ecd2fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521700568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2521700568
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4065068245
Short name T115
Test name
Test status
Simulation time 395433788 ps
CPU time 1.02 seconds
Started Dec 20 12:21:20 PM PST 23
Finished Dec 20 12:21:41 PM PST 23
Peak memory 182768 kb
Host smart-39e8ab32-4e18-491b-8110-3effc33c3ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065068245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4065068245
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3455518420
Short name T310
Test name
Test status
Simulation time 22288375917 ps
CPU time 19.1 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:57 PM PST 23
Peak memory 182844 kb
Host smart-7953b64d-2144-4849-852a-49d5be2b9b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455518420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3455518420
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.156502909
Short name T290
Test name
Test status
Simulation time 576024459 ps
CPU time 0.99 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 182720 kb
Host smart-96b1c5fb-0d11-436c-a598-40951afa0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156502909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.156502909
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2486618509
Short name T215
Test name
Test status
Simulation time 153261245520 ps
CPU time 209.74 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:25:22 PM PST 23
Peak memory 192820 kb
Host smart-f979203d-685b-42a4-8943-75c23c71cf07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486618509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2486618509
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3679604419
Short name T155
Test name
Test status
Simulation time 28030273831 ps
CPU time 139.59 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:24:12 PM PST 23
Peak memory 197720 kb
Host smart-d8dceba0-d205-4345-bd7c-fd8a268fec12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679604419 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3679604419
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3400745000
Short name T39
Test name
Test status
Simulation time 485356865 ps
CPU time 1.34 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 182892 kb
Host smart-f3e5883b-2359-4be6-813c-c9ee83813220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400745000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3400745000
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2589286509
Short name T193
Test name
Test status
Simulation time 3375274533 ps
CPU time 2.76 seconds
Started Dec 20 12:20:44 PM PST 23
Finished Dec 20 12:20:53 PM PST 23
Peak memory 182960 kb
Host smart-78329727-399d-4e7f-87e1-57808731cd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589286509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2589286509
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2607859192
Short name T177
Test name
Test status
Simulation time 528197028 ps
CPU time 1.2 seconds
Started Dec 20 12:20:45 PM PST 23
Finished Dec 20 12:20:53 PM PST 23
Peak memory 182852 kb
Host smart-ef916ea8-0b17-4d0e-b856-d2ab96d21581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607859192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2607859192
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2682538682
Short name T254
Test name
Test status
Simulation time 61180949585 ps
CPU time 119.09 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:23:15 PM PST 23
Peak memory 197844 kb
Host smart-34c511b5-40ed-49a2-b344-9a5df80803a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682538682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2682538682
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.479813190
Short name T36
Test name
Test status
Simulation time 428205251 ps
CPU time 0.59 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:21:52 PM PST 23
Peak memory 182744 kb
Host smart-ae518567-bf07-402c-83c0-6fd5d4bd64ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479813190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.479813190
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1796870418
Short name T40
Test name
Test status
Simulation time 6671174305 ps
CPU time 2.97 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:28 PM PST 23
Peak memory 182876 kb
Host smart-64fa7821-8029-4393-b88e-1c0df71a6e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796870418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1796870418
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3259765238
Short name T210
Test name
Test status
Simulation time 540666771 ps
CPU time 0.67 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:08 PM PST 23
Peak memory 182732 kb
Host smart-20851590-4058-421f-aa5c-ce2f7ad7ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259765238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3259765238
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2996808950
Short name T133
Test name
Test status
Simulation time 58467908042 ps
CPU time 8.11 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:22:00 PM PST 23
Peak memory 192984 kb
Host smart-df7aa372-26fc-42c1-90a8-55688094590f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996808950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2996808950
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.705300673
Short name T87
Test name
Test status
Simulation time 34708970515 ps
CPU time 364.42 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:26:31 PM PST 23
Peak memory 197676 kb
Host smart-493101a2-ec70-4dc1-b477-8e1943b3ffba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705300673 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.705300673
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3243018184
Short name T44
Test name
Test status
Simulation time 349414380 ps
CPU time 0.8 seconds
Started Dec 20 12:21:38 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182720 kb
Host smart-257a5f5f-98e5-4c83-a795-2c34e4d2c74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243018184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3243018184
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2794961608
Short name T21
Test name
Test status
Simulation time 4125999189 ps
CPU time 2.28 seconds
Started Dec 20 12:20:32 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182844 kb
Host smart-e4bd7ed8-7570-434b-b82a-df3df0b2e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794961608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2794961608
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4087065096
Short name T171
Test name
Test status
Simulation time 386036478 ps
CPU time 0.65 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:21:52 PM PST 23
Peak memory 182624 kb
Host smart-dd7bf1d8-213d-446c-a22f-ede08f490b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087065096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4087065096
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2484221247
Short name T248
Test name
Test status
Simulation time 50894898883 ps
CPU time 39.75 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 182968 kb
Host smart-c9a7d061-0a05-4c67-a130-7fa3e428b68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484221247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2484221247
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.510258039
Short name T59
Test name
Test status
Simulation time 36585946443 ps
CPU time 242.27 seconds
Started Dec 20 12:20:54 PM PST 23
Finished Dec 20 12:25:04 PM PST 23
Peak memory 197788 kb
Host smart-d5da6959-dbe6-4e74-8e3c-a60564afa382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510258039 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.510258039
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1262807262
Short name T190
Test name
Test status
Simulation time 487562397 ps
CPU time 1.19 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:18 PM PST 23
Peak memory 182844 kb
Host smart-36d75402-0ff6-4600-93a2-ac7f50e6a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262807262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1262807262
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.539710474
Short name T308
Test name
Test status
Simulation time 36320673487 ps
CPU time 29.38 seconds
Started Dec 20 12:20:33 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 182860 kb
Host smart-d91e0230-f5ad-48d7-9097-f7dec05535c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539710474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.539710474
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3734978852
Short name T150
Test name
Test status
Simulation time 545768480 ps
CPU time 0.83 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 182712 kb
Host smart-09a04a20-71aa-4b50-a1d6-e49806ed9c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734978852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3734978852
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1585458304
Short name T277
Test name
Test status
Simulation time 163919048077 ps
CPU time 116.61 seconds
Started Dec 20 12:20:52 PM PST 23
Finished Dec 20 12:22:56 PM PST 23
Peak memory 193056 kb
Host smart-0eb2cd18-91dc-43c2-bd16-8af6c135b6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585458304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1585458304
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3137840234
Short name T305
Test name
Test status
Simulation time 525091757 ps
CPU time 0.81 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:39 PM PST 23
Peak memory 182944 kb
Host smart-51082c44-cb1a-44e2-8d76-aa8677356bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137840234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3137840234
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3727732218
Short name T223
Test name
Test status
Simulation time 45244244792 ps
CPU time 13.48 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 182860 kb
Host smart-34a21ed3-c755-496f-b478-32511bce10be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727732218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3727732218
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1044992496
Short name T200
Test name
Test status
Simulation time 456719578 ps
CPU time 0.84 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:20:41 PM PST 23
Peak memory 182720 kb
Host smart-4b69904a-6621-4f55-9d18-007030527cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044992496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1044992496
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2819802425
Short name T251
Test name
Test status
Simulation time 34836594653 ps
CPU time 28.6 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 193080 kb
Host smart-76903e58-f1f9-48ed-bce0-c095573a5301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819802425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2819802425
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1390654565
Short name T198
Test name
Test status
Simulation time 57491308113 ps
CPU time 613.34 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:30:41 PM PST 23
Peak memory 197972 kb
Host smart-8139cf57-df64-4669-ae43-2f96af769817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390654565 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1390654565
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2704656537
Short name T123
Test name
Test status
Simulation time 437706801 ps
CPU time 0.7 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:46 PM PST 23
Peak memory 182832 kb
Host smart-6200bfff-ff62-4ade-b562-6c6ae7964a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704656537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2704656537
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.2908535893
Short name T288
Test name
Test status
Simulation time 24763249005 ps
CPU time 10.09 seconds
Started Dec 20 12:20:37 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 182876 kb
Host smart-aa2992ea-3f74-460b-b6c0-942a20c788bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908535893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.2908535893
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1695675215
Short name T194
Test name
Test status
Simulation time 598199716 ps
CPU time 0.76 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 182752 kb
Host smart-fd6e1695-c352-493c-859b-44723ab60fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695675215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1695675215
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1653713951
Short name T42
Test name
Test status
Simulation time 259134741508 ps
CPU time 97.3 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:22:50 PM PST 23
Peak memory 182840 kb
Host smart-7e4b9e2c-a256-4811-ae28-3c423f20778b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653713951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1653713951
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.705026595
Short name T126
Test name
Test status
Simulation time 574692277 ps
CPU time 1.37 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:21:14 PM PST 23
Peak memory 182808 kb
Host smart-36d7d470-9533-4d82-8e3f-0176796b8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705026595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.705026595
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1910216007
Short name T38
Test name
Test status
Simulation time 12020353141 ps
CPU time 4.55 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:21:19 PM PST 23
Peak memory 182832 kb
Host smart-3d777421-80f6-4042-b4a9-b48ada8bc3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910216007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1910216007
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2391872696
Short name T33
Test name
Test status
Simulation time 4387200159 ps
CPU time 6.16 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 214864 kb
Host smart-5ff45569-83d0-40d9-8714-7522f28593dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391872696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2391872696
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4139324958
Short name T236
Test name
Test status
Simulation time 540386540 ps
CPU time 1.34 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 182728 kb
Host smart-58a27fb0-c7d6-48db-990e-b6afa0f70b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139324958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4139324958
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2522356871
Short name T104
Test name
Test status
Simulation time 103707782592 ps
CPU time 160.86 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:24:26 PM PST 23
Peak memory 192880 kb
Host smart-bcf14b64-dbe0-4a9a-8279-46b71104f002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522356871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2522356871
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3637536140
Short name T34
Test name
Test status
Simulation time 17909380873 ps
CPU time 132.96 seconds
Started Dec 20 12:21:25 PM PST 23
Finished Dec 20 12:23:56 PM PST 23
Peak memory 197684 kb
Host smart-a69c4d95-fe92-466b-a5e9-78329bca81fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637536140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3637536140
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.4133199807
Short name T182
Test name
Test status
Simulation time 429337597 ps
CPU time 0.61 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 182804 kb
Host smart-a6016505-fbf4-4c1a-a4ee-1bb2ed214ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133199807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.4133199807
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1643746920
Short name T143
Test name
Test status
Simulation time 39276610564 ps
CPU time 37.13 seconds
Started Dec 20 12:20:31 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 182864 kb
Host smart-aebdacfe-1956-46aa-8b93-3a02c2e1d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643746920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1643746920
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1178002590
Short name T184
Test name
Test status
Simulation time 606905787 ps
CPU time 0.77 seconds
Started Dec 20 12:21:16 PM PST 23
Finished Dec 20 12:21:37 PM PST 23
Peak memory 182868 kb
Host smart-56c35d7c-b0f6-4ef4-9e78-360d3c734a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178002590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1178002590
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3377392687
Short name T304
Test name
Test status
Simulation time 300461592040 ps
CPU time 567.26 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 198296 kb
Host smart-92d81d7f-d9dd-4597-9d92-64ce6c48032a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377392687 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3377392687
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2789330833
Short name T261
Test name
Test status
Simulation time 418288416 ps
CPU time 0.93 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:33 PM PST 23
Peak memory 182792 kb
Host smart-b6fc536a-7f9a-432f-94e2-e252cab9e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789330833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2789330833
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3123116026
Short name T141
Test name
Test status
Simulation time 13361498941 ps
CPU time 19.58 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 182908 kb
Host smart-8ceed904-ae6b-416f-a58d-a0f8e29f72b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123116026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3123116026
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2431940366
Short name T275
Test name
Test status
Simulation time 530996177 ps
CPU time 0.84 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 182728 kb
Host smart-45107dbe-847a-4cbe-aacb-1fc44974ef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431940366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2431940366
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1846250248
Short name T106
Test name
Test status
Simulation time 187669841567 ps
CPU time 80.73 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:23:14 PM PST 23
Peak memory 192944 kb
Host smart-2abbabe5-b8fb-41fc-a17c-cbac30827ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846250248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1846250248
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.409040717
Short name T189
Test name
Test status
Simulation time 37066899960 ps
CPU time 149.53 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:24:18 PM PST 23
Peak memory 197688 kb
Host smart-b0ea4765-996e-4e8f-8800-2091efab16dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409040717 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.409040717
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4160378272
Short name T286
Test name
Test status
Simulation time 464047334 ps
CPU time 1.1 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 182844 kb
Host smart-4d3bfe36-0788-4648-ae31-bf35d62c6171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160378272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4160378272
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1673217288
Short name T245
Test name
Test status
Simulation time 19313221218 ps
CPU time 18.82 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:21:37 PM PST 23
Peak memory 182908 kb
Host smart-22ac9442-43dd-4312-82b5-260a58f33fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673217288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1673217288
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2490415277
Short name T222
Test name
Test status
Simulation time 466920551 ps
CPU time 0.69 seconds
Started Dec 20 12:21:32 PM PST 23
Finished Dec 20 12:21:48 PM PST 23
Peak memory 182636 kb
Host smart-ec3f6b7d-8eb1-4d34-9102-06db66dc9179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490415277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2490415277
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.717285905
Short name T237
Test name
Test status
Simulation time 79888456560 ps
CPU time 29.13 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:51 PM PST 23
Peak memory 194224 kb
Host smart-192bc47e-5462-467a-ab2b-5e448c67bb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717285905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.717285905
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3738812156
Short name T218
Test name
Test status
Simulation time 23207801089 ps
CPU time 242.36 seconds
Started Dec 20 12:21:04 PM PST 23
Finished Dec 20 12:25:15 PM PST 23
Peak memory 197764 kb
Host smart-7d7ea403-d28e-4b9e-b646-c0d4941498d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738812156 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3738812156
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1575501084
Short name T231
Test name
Test status
Simulation time 433981285 ps
CPU time 0.69 seconds
Started Dec 20 12:21:50 PM PST 23
Finished Dec 20 12:22:03 PM PST 23
Peak memory 182768 kb
Host smart-04aa29cd-9d08-40fb-b67e-b0d9e36aaed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575501084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1575501084
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2939548787
Short name T284
Test name
Test status
Simulation time 21163957396 ps
CPU time 8.81 seconds
Started Dec 20 12:21:35 PM PST 23
Finished Dec 20 12:21:58 PM PST 23
Peak memory 182808 kb
Host smart-04fc5e2b-54c5-40d5-b987-d9fdc393b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939548787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2939548787
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3581825940
Short name T166
Test name
Test status
Simulation time 592442575 ps
CPU time 0.62 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:10 PM PST 23
Peak memory 182836 kb
Host smart-6eba3198-bcbd-4a9e-a712-db382200be31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581825940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3581825940
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.308296519
Short name T203
Test name
Test status
Simulation time 15022328226 ps
CPU time 3.29 seconds
Started Dec 20 12:21:00 PM PST 23
Finished Dec 20 12:21:12 PM PST 23
Peak memory 193080 kb
Host smart-c79cde3d-9bcc-4ad3-a3c6-bd587b76e153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308296519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.308296519
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2776469695
Short name T124
Test name
Test status
Simulation time 384720618 ps
CPU time 1.14 seconds
Started Dec 20 12:21:40 PM PST 23
Finished Dec 20 12:21:54 PM PST 23
Peak memory 182768 kb
Host smart-8b659ebe-471b-454d-a985-9789e7f65c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776469695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2776469695
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.783092432
Short name T156
Test name
Test status
Simulation time 19084791799 ps
CPU time 15.27 seconds
Started Dec 20 12:21:42 PM PST 23
Finished Dec 20 12:22:10 PM PST 23
Peak memory 182824 kb
Host smart-95adf200-75dd-4605-bbf3-6a7368dd58e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783092432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.783092432
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.591366823
Short name T255
Test name
Test status
Simulation time 425565517 ps
CPU time 0.66 seconds
Started Dec 20 12:20:34 PM PST 23
Finished Dec 20 12:20:40 PM PST 23
Peak memory 182636 kb
Host smart-7032a79f-ecee-4743-b6e8-07996b119433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591366823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.591366823
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2310914614
Short name T89
Test name
Test status
Simulation time 50462966760 ps
CPU time 184.02 seconds
Started Dec 20 12:21:39 PM PST 23
Finished Dec 20 12:24:57 PM PST 23
Peak memory 197696 kb
Host smart-93254fa5-76ba-4556-8f11-8e6736038c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310914614 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2310914614
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3009122746
Short name T134
Test name
Test status
Simulation time 555194686 ps
CPU time 0.64 seconds
Started Dec 20 12:20:44 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 182896 kb
Host smart-5d6639ed-a755-4eaa-b11b-72cfe92f3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009122746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3009122746
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4267463185
Short name T158
Test name
Test status
Simulation time 37243908686 ps
CPU time 10.54 seconds
Started Dec 20 12:21:36 PM PST 23
Finished Dec 20 12:22:01 PM PST 23
Peak memory 182796 kb
Host smart-2fdcb4cd-594d-431e-aeee-8665fb3a08d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267463185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4267463185
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3559218207
Short name T181
Test name
Test status
Simulation time 394876511 ps
CPU time 1.14 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:26 PM PST 23
Peak memory 182776 kb
Host smart-ed454e2d-efb6-426b-a6fd-c4efbcc994a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559218207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3559218207
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2937028502
Short name T258
Test name
Test status
Simulation time 73279999873 ps
CPU time 29.86 seconds
Started Dec 20 12:21:37 PM PST 23
Finished Dec 20 12:22:21 PM PST 23
Peak memory 182788 kb
Host smart-a0f42343-df70-4337-8b78-157d38de816a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937028502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2937028502
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1217439259
Short name T267
Test name
Test status
Simulation time 65785746794 ps
CPU time 247.81 seconds
Started Dec 20 12:20:41 PM PST 23
Finished Dec 20 12:24:54 PM PST 23
Peak memory 197780 kb
Host smart-db61be29-f532-40e4-96fd-1ff239bc629a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217439259 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1217439259
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3165224620
Short name T176
Test name
Test status
Simulation time 504703997 ps
CPU time 0.96 seconds
Started Dec 20 12:21:19 PM PST 23
Finished Dec 20 12:21:41 PM PST 23
Peak memory 182888 kb
Host smart-a8b33ed2-be78-49f8-bcf6-954442936ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165224620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3165224620
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.3880130732
Short name T306
Test name
Test status
Simulation time 36006729578 ps
CPU time 58.87 seconds
Started Dec 20 12:21:00 PM PST 23
Finished Dec 20 12:22:07 PM PST 23
Peak memory 182932 kb
Host smart-e3c7a57e-7a34-4342-b5c2-70ed68bca9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880130732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.3880130732
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4019811067
Short name T209
Test name
Test status
Simulation time 583546390 ps
CPU time 0.6 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 182816 kb
Host smart-5f461862-166e-4afa-a7ed-dcc3670f2f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019811067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4019811067
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4268420201
Short name T293
Test name
Test status
Simulation time 51997899147 ps
CPU time 39.85 seconds
Started Dec 20 12:20:44 PM PST 23
Finished Dec 20 12:21:30 PM PST 23
Peak memory 182852 kb
Host smart-7a331b7f-3ed4-40da-94b6-ac9689ce2416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268420201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4268420201
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.866593152
Short name T256
Test name
Test status
Simulation time 45235096322 ps
CPU time 494.88 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 197772 kb
Host smart-7f92e6a0-c0c4-4a4d-94cf-eedefe9d69c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866593152 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.866593152
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3156587312
Short name T35
Test name
Test status
Simulation time 503946462 ps
CPU time 1.25 seconds
Started Dec 20 12:21:28 PM PST 23
Finished Dec 20 12:21:46 PM PST 23
Peak memory 182856 kb
Host smart-1347bab5-ca78-44b5-bee7-b535325ab357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156587312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3156587312
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.4024558457
Short name T221
Test name
Test status
Simulation time 44029547107 ps
CPU time 65.1 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:22:30 PM PST 23
Peak memory 182916 kb
Host smart-ec5a5b23-708f-4efe-8367-30436ee6adce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024558457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.4024558457
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.961809206
Short name T257
Test name
Test status
Simulation time 532096126 ps
CPU time 0.73 seconds
Started Dec 20 12:20:45 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 182728 kb
Host smart-36e323cb-5935-48e1-b264-d5bfcf0f87f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961809206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.961809206
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2071779540
Short name T249
Test name
Test status
Simulation time 32844396240 ps
CPU time 35.4 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:21:53 PM PST 23
Peak memory 192976 kb
Host smart-51fac5cd-a353-4144-811c-5492e68d3f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071779540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2071779540
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4044145913
Short name T196
Test name
Test status
Simulation time 39273025779 ps
CPU time 213.35 seconds
Started Dec 20 12:21:06 PM PST 23
Finished Dec 20 12:24:48 PM PST 23
Peak memory 197732 kb
Host smart-f5381f0c-7715-4287-af6c-50d64c1d1656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044145913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4044145913
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1493863013
Short name T107
Test name
Test status
Simulation time 418752586 ps
CPU time 0.7 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 182696 kb
Host smart-3f1b9918-9810-4089-8538-435fa8cc28a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493863013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1493863013
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.80418912
Short name T41
Test name
Test status
Simulation time 14885106431 ps
CPU time 3.14 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 182860 kb
Host smart-7edd2f1d-daa8-4c02-8c6e-3ffd63bb2c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80418912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.80418912
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4018067643
Short name T220
Test name
Test status
Simulation time 506672604 ps
CPU time 1.41 seconds
Started Dec 20 12:21:16 PM PST 23
Finished Dec 20 12:21:38 PM PST 23
Peak memory 182668 kb
Host smart-0112439a-192a-49bd-b9a3-694435c265ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018067643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4018067643
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3019804934
Short name T287
Test name
Test status
Simulation time 212107658799 ps
CPU time 556.85 seconds
Started Dec 20 12:20:35 PM PST 23
Finished Dec 20 12:29:57 PM PST 23
Peak memory 198296 kb
Host smart-ae4c3c17-7860-496d-b203-edad44ad0c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019804934 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3019804934
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4105374912
Short name T188
Test name
Test status
Simulation time 570007658 ps
CPU time 0.75 seconds
Started Dec 20 12:20:55 PM PST 23
Finished Dec 20 12:21:02 PM PST 23
Peak memory 182712 kb
Host smart-e29bbf28-0e60-48c8-bbb0-690fd4d94a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105374912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4105374912
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.4028209807
Short name T268
Test name
Test status
Simulation time 24756111928 ps
CPU time 9.57 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:12 PM PST 23
Peak memory 182868 kb
Host smart-6bd3a32b-e1b3-43c2-8dc4-adb718d57290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028209807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.4028209807
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3561412823
Short name T145
Test name
Test status
Simulation time 600302176 ps
CPU time 0.71 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:08 PM PST 23
Peak memory 182708 kb
Host smart-ffcd601c-318c-4131-b8aa-b32284ebf3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561412823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3561412823
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3867840653
Short name T301
Test name
Test status
Simulation time 131677762269 ps
CPU time 54.45 seconds
Started Dec 20 12:20:36 PM PST 23
Finished Dec 20 12:21:36 PM PST 23
Peak memory 182872 kb
Host smart-204e6a59-8391-48a2-87fd-a4f3ad7db84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867840653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3867840653
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2993543442
Short name T55
Test name
Test status
Simulation time 206576021054 ps
CPU time 295.21 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:25:49 PM PST 23
Peak memory 197744 kb
Host smart-8e96896f-fd1f-4374-9bb9-5732c3d7f0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993543442 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2993543442
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2498245528
Short name T136
Test name
Test status
Simulation time 510567189 ps
CPU time 0.71 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182824 kb
Host smart-b0c1ee0b-0263-43ca-b26d-a216905512b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498245528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2498245528
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.931323707
Short name T153
Test name
Test status
Simulation time 11027744589 ps
CPU time 4.38 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:21:28 PM PST 23
Peak memory 182892 kb
Host smart-646aea3a-83ed-403f-b4db-d1bc8ab7c5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931323707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.931323707
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2025782362
Short name T148
Test name
Test status
Simulation time 420171354 ps
CPU time 0.67 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:24 PM PST 23
Peak memory 182716 kb
Host smart-0eeba7d2-cd17-4b61-be5c-0f6eaafab309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025782362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2025782362
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.318430715
Short name T235
Test name
Test status
Simulation time 136709774897 ps
CPU time 135.55 seconds
Started Dec 20 12:21:10 PM PST 23
Finished Dec 20 12:23:41 PM PST 23
Peak memory 182864 kb
Host smart-ddd559ed-2cae-41af-8d0c-0b385b244460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318430715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.318430715
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3325990578
Short name T51
Test name
Test status
Simulation time 128001152003 ps
CPU time 517.68 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:30:23 PM PST 23
Peak memory 197948 kb
Host smart-1d050510-c316-4af3-9161-1eb4989b2a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325990578 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3325990578
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1938566556
Short name T234
Test name
Test status
Simulation time 389571298 ps
CPU time 1.13 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:34 PM PST 23
Peak memory 182768 kb
Host smart-bf1ed0f3-8a7a-48bc-9653-c39e77bf9357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938566556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1938566556
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3452345535
Short name T294
Test name
Test status
Simulation time 2180554320 ps
CPU time 3.98 seconds
Started Dec 20 12:21:13 PM PST 23
Finished Dec 20 12:21:35 PM PST 23
Peak memory 182664 kb
Host smart-471e62c9-0dbe-4b9f-82bc-21e398c1856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452345535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3452345535
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1997274553
Short name T147
Test name
Test status
Simulation time 437521253 ps
CPU time 0.61 seconds
Started Dec 20 12:21:09 PM PST 23
Finished Dec 20 12:21:23 PM PST 23
Peak memory 182700 kb
Host smart-694f64dd-f6a7-47ee-b512-fbc103458df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997274553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1997274553
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1937860687
Short name T43
Test name
Test status
Simulation time 70655720125 ps
CPU time 28.37 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:58 PM PST 23
Peak memory 193028 kb
Host smart-29924ad0-5942-4bc8-bb11-0e8c3a5bd786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937860687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1937860687
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3961808265
Short name T111
Test name
Test status
Simulation time 65843264211 ps
CPU time 419.06 seconds
Started Dec 20 12:21:14 PM PST 23
Finished Dec 20 12:28:34 PM PST 23
Peak memory 197816 kb
Host smart-3bc83c00-a4b5-4760-b525-5856c0e92820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961808265 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3961808265
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3512603997
Short name T253
Test name
Test status
Simulation time 387754433 ps
CPU time 0.82 seconds
Started Dec 20 12:21:11 PM PST 23
Finished Dec 20 12:21:29 PM PST 23
Peak memory 182872 kb
Host smart-dc25d272-3905-4ae0-936a-1eca936182d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512603997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3512603997
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4114985832
Short name T168
Test name
Test status
Simulation time 18075716040 ps
CPU time 16.53 seconds
Started Dec 20 12:21:29 PM PST 23
Finished Dec 20 12:22:02 PM PST 23
Peak memory 182840 kb
Host smart-694ee741-7c3c-4dea-b333-2994fcb2b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114985832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4114985832
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2172403558
Short name T238
Test name
Test status
Simulation time 444166609 ps
CPU time 0.58 seconds
Started Dec 20 12:21:31 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182596 kb
Host smart-e0b35883-5a4a-4816-abed-8b8095f4180e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172403558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2172403558
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2988822954
Short name T175
Test name
Test status
Simulation time 213654280989 ps
CPU time 361.9 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:26:46 PM PST 23
Peak memory 192992 kb
Host smart-7f1adeab-0c0a-4209-b197-18ce7ecf4d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988822954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2988822954
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.412917119
Short name T113
Test name
Test status
Simulation time 34945783821 ps
CPU time 361.64 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 197724 kb
Host smart-962b8966-f4f1-4c2b-abac-d72dcb16dc4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412917119 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.412917119
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3366497875
Short name T297
Test name
Test status
Simulation time 391888920 ps
CPU time 0.65 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:21:39 PM PST 23
Peak memory 182744 kb
Host smart-bcef3460-7768-4791-ac0a-98f60613b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366497875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3366497875
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3384847503
Short name T180
Test name
Test status
Simulation time 32475519618 ps
CPU time 44.89 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:22:14 PM PST 23
Peak memory 182884 kb
Host smart-9c44bc39-4a11-48de-8cef-2c3c28705d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384847503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3384847503
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4006223626
Short name T229
Test name
Test status
Simulation time 393435599 ps
CPU time 1.08 seconds
Started Dec 20 12:21:18 PM PST 23
Finished Dec 20 12:21:40 PM PST 23
Peak memory 182636 kb
Host smart-92f5df20-4603-4801-adbc-1bc6ebe13850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006223626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4006223626
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3537894693
Short name T272
Test name
Test status
Simulation time 92468122711 ps
CPU time 78.06 seconds
Started Dec 20 12:21:07 PM PST 23
Finished Dec 20 12:22:35 PM PST 23
Peak memory 193212 kb
Host smart-367105f9-6d83-4795-8e7d-cfb90e401492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537894693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3537894693
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3314569117
Short name T60
Test name
Test status
Simulation time 36064798479 ps
CPU time 381.1 seconds
Started Dec 20 12:21:08 PM PST 23
Finished Dec 20 12:27:40 PM PST 23
Peak memory 197832 kb
Host smart-d926591a-49aa-47a7-965e-934cad1c62d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314569117 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3314569117
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1528907100
Short name T192
Test name
Test status
Simulation time 429949727 ps
CPU time 1.26 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:21:31 PM PST 23
Peak memory 182804 kb
Host smart-30861993-b242-40bd-9661-174cec4ac036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528907100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1528907100
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3520639933
Short name T142
Test name
Test status
Simulation time 35688195917 ps
CPU time 51.04 seconds
Started Dec 20 12:21:34 PM PST 23
Finished Dec 20 12:22:40 PM PST 23
Peak memory 182932 kb
Host smart-c3decd32-07ef-4e57-ace9-9e8423a2606a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520639933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3520639933
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3643471528
Short name T259
Test name
Test status
Simulation time 334751092 ps
CPU time 0.98 seconds
Started Dec 20 12:21:30 PM PST 23
Finished Dec 20 12:21:47 PM PST 23
Peak memory 182904 kb
Host smart-9cd7b6d1-5b7f-4002-8779-b948c712edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643471528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3643471528
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.501218158
Short name T282
Test name
Test status
Simulation time 232385051560 ps
CPU time 193.93 seconds
Started Dec 20 12:21:12 PM PST 23
Finished Dec 20 12:24:44 PM PST 23
Peak memory 182848 kb
Host smart-9873ac06-5230-47f1-bbd1-9c1c131fc073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501218158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.501218158
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2368436039
Short name T262
Test name
Test status
Simulation time 85767514838 ps
CPU time 423.96 seconds
Started Dec 20 12:21:27 PM PST 23
Finished Dec 20 12:28:49 PM PST 23
Peak memory 197852 kb
Host smart-ddd42b56-1964-4040-97ea-848c84e7778a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368436039 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2368436039
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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