Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 26864 1 T13 134 T19 11 T20 11
bark[1] 468 1 T35 17 T71 65 T72 106
bark[2] 724 1 T41 16 T68 17 T73 16
bark[3] 553 1 T41 43 T42 47 T74 17
bark[4] 329 1 T42 17 T75 16 T76 12
bark[5] 247 1 T33 21 T77 16 T78 16
bark[6] 477 1 T33 17 T79 16 T77 26
bark[7] 272 1 T33 17 T68 43 T80 16
bark[8] 658 1 T68 21 T81 16 T82 23
bark[9] 328 1 T72 16 T83 138 T84 38
bark[10] 139 1 T85 12 T86 22 T87 16
bark[11] 157 1 T77 16 T75 16 T88 17
bark[12] 763 1 T21 12 T23 13 T41 21
bark[13] 411 1 T13 16 T45 21 T89 16
bark[14] 602 1 T13 12 T90 29 T74 32
bark[15] 374 1 T33 17 T40 1 T71 16
bark[16] 207 1 T91 16 T92 32 T93 16
bark[17] 316 1 T40 43 T80 17 T84 32
bark[18] 623 1 T89 12 T94 16 T95 30
bark[19] 854 1 T68 209 T74 60 T94 18
bark[20] 463 1 T24 22 T68 21 T89 26
bark[21] 221 1 T33 16 T74 38 T81 53
bark[22] 529 1 T48 12 T35 17 T74 17
bark[23] 743 1 T13 51 T91 17 T96 12
bark[24] 410 1 T18 12 T71 22 T82 16
bark[25] 612 1 T41 203 T79 17 T75 32
bark[26] 151 1 T77 26 T97 16 T98 17
bark[27] 491 1 T24 48 T45 169 T99 79
bark[28] 575 1 T72 17 T100 32 T101 27
bark[29] 363 1 T102 79 T94 17 T101 43
bark[30] 535 1 T89 16 T81 30 T75 27
bark[31] 826 1 T33 16 T35 16 T90 42
bark_0 3428 1 T8 6 T31 9 T15 9


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 26553 1 T13 134 T19 10 T20 10
bite[1] 274 1 T24 22 T48 11 T42 17
bite[2] 783 1 T41 20 T45 20 T35 17
bite[3] 363 1 T13 11 T68 17 T74 17
bite[4] 257 1 T33 34 T79 16 T78 16
bite[5] 292 1 T24 16 T80 17 T76 11
bite[6] 765 1 T103 11 T83 138 T104 11
bite[7] 196 1 T71 16 T105 17 T88 17
bite[8] 280 1 T13 16 T75 16 T106 20
bite[9] 395 1 T74 37 T100 16 T93 16
bite[10] 872 1 T74 17 T94 17 T97 16
bite[11] 202 1 T77 26 T91 16 T102 79
bite[12] 621 1 T41 42 T68 43 T107 22
bite[13] 478 1 T40 42 T90 26 T71 64
bite[14] 356 1 T85 11 T94 17 T82 16
bite[15] 751 1 T81 16 T77 16 T91 16
bite[16] 98 1 T21 11 T89 11 T77 16
bite[17] 392 1 T81 30 T77 25 T75 16
bite[18] 400 1 T33 20 T74 32 T78 111
bite[19] 135 1 T73 16 T108 11 T106 16
bite[20] 425 1 T80 16 T75 27 T88 16
bite[21] 545 1 T74 123 T89 16 T95 25
bite[22] 344 1 T33 16 T35 16 T71 188
bite[23] 347 1 T41 16 T90 29 T93 42
bite[24] 459 1 T13 51 T45 168 T68 16
bite[25] 403 1 T89 16 T109 31 T110 102
bite[26] 824 1 T41 198 T49 11 T68 204
bite[27] 249 1 T67 66 T79 17 T111 12
bite[28] 938 1 T18 11 T33 16 T81 53
bite[29] 870 1 T33 17 T74 59 T80 12
bite[30] 571 1 T75 16 T105 56 T112 11
bite[31] 323 1 T24 22 T42 46 T101 42
bite_0 3952 1 T8 6 T31 9 T15 9


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 44713 1 T8 6 T31 9 T15 9


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 788 1 T33 31 T42 60 T45 52
prescale[1] 480 1 T22 8 T33 2 T41 15
prescale[2] 703 1 T40 41 T67 2 T74 34
prescale[3] 694 1 T41 32 T113 8 T45 93
prescale[4] 707 1 T35 31 T68 15 T74 2
prescale[5] 708 1 T13 15 T24 25 T91 45
prescale[6] 765 1 T74 66 T80 15 T114 8
prescale[7] 562 1 T33 15 T40 24 T45 31
prescale[8] 912 1 T33 2 T40 59 T68 32
prescale[9] 561 1 T67 4 T107 2 T115 8
prescale[10] 508 1 T33 138 T40 2 T41 2
prescale[11] 1078 1 T33 59 T40 15 T68 85
prescale[12] 699 1 T33 44 T41 2 T81 38
prescale[13] 295 1 T19 8 T41 2 T42 21
prescale[14] 381 1 T33 15 T41 2 T35 18
prescale[15] 769 1 T24 15 T42 148 T116 8
prescale[16] 419 1 T33 8 T40 2 T41 2
prescale[17] 683 1 T35 15 T67 2 T74 62
prescale[18] 543 1 T24 25 T117 8 T74 36
prescale[19] 808 1 T41 55 T90 29 T94 15
prescale[20] 1023 1 T20 8 T45 34 T68 180
prescale[21] 773 1 T24 15 T42 34 T35 27
prescale[22] 667 1 T41 41 T42 53 T74 2
prescale[23] 1035 1 T33 2 T41 2 T74 31
prescale[24] 328 1 T40 29 T74 2 T118 8
prescale[25] 664 1 T13 37 T33 15 T40 56
prescale[26] 839 1 T42 12 T68 2 T79 44
prescale[27] 439 1 T33 46 T45 31 T90 15
prescale[28] 673 1 T33 29 T42 65 T119 8
prescale[29] 663 1 T41 2 T45 29 T79 43
prescale[30] 552 1 T13 15 T41 38 T42 31
prescale[31] 666 1 T13 31 T40 2 T41 53
prescale_0 23328 1 T8 6 T31 9 T15 9


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33340 1 T8 6 T31 9 T15 9
auto[1] 11373 1 T13 30 T18 10 T20 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 44713 1 T8 6 T31 9 T15 9


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 26323 1 T13 131 T19 12 T20 12
wkup[1] 501 1 T33 16 T40 22 T41 17
wkup[2] 429 1 T41 38 T74 33 T82 16
wkup[3] 414 1 T13 22 T45 48 T68 21
wkup[4] 782 1 T21 13 T42 16 T67 10
wkup[5] 511 1 T40 16 T41 22 T45 19
wkup[6] 572 1 T13 16 T42 16 T45 22
wkup[7] 543 1 T41 16 T42 44 T74 13
wkup[8] 594 1 T33 16 T48 13 T35 17
wkup[9] 314 1 T74 17 T77 16 T120 16
wkup[10] 548 1 T24 26 T41 21 T81 22
wkup[11] 384 1 T40 2 T42 16 T68 17
wkup[12] 474 1 T35 17 T71 16 T105 6
wkup[13] 378 1 T33 16 T41 16 T74 28
wkup[14] 504 1 T33 17 T81 16 T107 22
wkup[15] 474 1 T13 16 T42 17 T68 22
wkup[16] 497 1 T13 13 T23 14 T41 16
wkup[17] 465 1 T33 16 T85 13 T42 32
wkup[18] 555 1 T13 16 T24 16 T33 16
wkup[19] 443 1 T41 38 T45 32 T68 16
wkup[20] 557 1 T33 17 T80 16 T71 58
wkup[21] 735 1 T18 13 T33 16 T45 16
wkup[22] 378 1 T42 13 T45 24 T68 18
wkup[23] 600 1 T67 16 T103 13 T73 22
wkup[24] 396 1 T24 22 T40 26 T41 16
wkup[25] 626 1 T41 16 T68 16 T90 26
wkup[26] 457 1 T49 13 T68 43 T75 16
wkup[27] 498 1 T40 16 T68 16 T111 14
wkup[28] 440 1 T24 22 T33 17 T41 16
wkup[29] 493 1 T33 16 T42 16 T74 28
wkup[30] 365 1 T45 16 T74 17 T73 16
wkup[31] 529 1 T33 35 T68 22 T90 16
wkup_0 2934 1 T8 6 T31 9 T15 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%