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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.32 100.00 99.35 100.00 96.90


Total test records in report: 429
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T272 /workspace/coverage/default/3.aon_timer_smoke.332000048 Dec 24 01:09:39 PM PST 23 Dec 24 01:09:47 PM PST 23 382342008 ps
T273 /workspace/coverage/default/20.aon_timer_jump.1285960768 Dec 24 01:09:39 PM PST 23 Dec 24 01:09:48 PM PST 23 356375200 ps
T274 /workspace/coverage/default/40.aon_timer_prescaler.3196913048 Dec 24 01:09:49 PM PST 23 Dec 24 01:10:00 PM PST 23 21041556545 ps
T38 /workspace/coverage/default/1.aon_timer_sec_cm.3739748410 Dec 24 01:09:35 PM PST 23 Dec 24 01:09:51 PM PST 23 4407768822 ps
T275 /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1051643037 Dec 24 01:09:41 PM PST 23 Dec 24 01:11:51 PM PST 23 128446774666 ps
T276 /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3260031127 Dec 24 01:09:34 PM PST 23 Dec 24 01:22:04 PM PST 23 98313891810 ps
T277 /workspace/coverage/default/5.aon_timer_smoke.1570376322 Dec 24 01:09:31 PM PST 23 Dec 24 01:09:38 PM PST 23 622814623 ps
T278 /workspace/coverage/default/2.aon_timer_stress_all.1802097878 Dec 24 01:09:32 PM PST 23 Dec 24 01:12:13 PM PST 23 561911673493 ps
T279 /workspace/coverage/default/19.aon_timer_stress_all.2138346154 Dec 24 01:09:39 PM PST 23 Dec 24 01:11:02 PM PST 23 193651129518 ps
T280 /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1627538837 Dec 24 01:09:49 PM PST 23 Dec 24 01:17:14 PM PST 23 58543188292 ps
T281 /workspace/coverage/default/49.aon_timer_stress_all.3844508943 Dec 24 01:09:55 PM PST 23 Dec 24 01:12:48 PM PST 23 131762171534 ps
T282 /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1287304973 Dec 24 01:09:38 PM PST 23 Dec 24 01:20:08 PM PST 23 610005304439 ps
T283 /workspace/coverage/default/47.aon_timer_stress_all.2104785793 Dec 24 01:10:06 PM PST 23 Dec 24 01:15:11 PM PST 23 203179756310 ps
T39 /workspace/coverage/default/2.aon_timer_sec_cm.2997510240 Dec 24 01:09:35 PM PST 23 Dec 24 01:09:50 PM PST 23 4019582569 ps
T284 /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1789706500 Dec 24 01:09:40 PM PST 23 Dec 24 01:19:27 PM PST 23 214215715288 ps
T285 /workspace/coverage/default/37.aon_timer_stress_all.4203322813 Dec 24 01:09:43 PM PST 23 Dec 24 01:11:38 PM PST 23 76226791188 ps
T286 /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3255726944 Dec 24 01:09:42 PM PST 23 Dec 24 01:18:44 PM PST 23 94863994167 ps
T287 /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1555389949 Dec 24 01:10:01 PM PST 23 Dec 24 01:11:46 PM PST 23 54561389001 ps
T288 /workspace/coverage/default/21.aon_timer_jump.4006954548 Dec 24 01:09:54 PM PST 23 Dec 24 01:09:59 PM PST 23 470260604 ps
T289 /workspace/coverage/default/17.aon_timer_jump.2713839194 Dec 24 01:09:38 PM PST 23 Dec 24 01:09:46 PM PST 23 413482533 ps
T290 /workspace/coverage/default/44.aon_timer_jump.3589866091 Dec 24 01:09:47 PM PST 23 Dec 24 01:09:54 PM PST 23 385358087 ps
T291 /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1396975333 Dec 24 01:09:57 PM PST 23 Dec 24 01:14:01 PM PST 23 96200452536 ps
T292 /workspace/coverage/default/29.aon_timer_stress_all.529580406 Dec 24 01:09:48 PM PST 23 Dec 24 01:13:10 PM PST 23 487358259325 ps
T293 /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.821837604 Dec 24 01:09:41 PM PST 23 Dec 24 01:11:35 PM PST 23 39913796874 ps
T294 /workspace/coverage/default/2.aon_timer_prescaler.671194164 Dec 24 01:09:38 PM PST 23 Dec 24 01:09:59 PM PST 23 38014633447 ps
T295 /workspace/coverage/default/45.aon_timer_smoke.2156298216 Dec 24 01:10:04 PM PST 23 Dec 24 01:10:09 PM PST 23 495215805 ps
T296 /workspace/coverage/default/13.aon_timer_smoke.3131907860 Dec 24 01:09:40 PM PST 23 Dec 24 01:09:48 PM PST 23 387089576 ps
T297 /workspace/coverage/default/26.aon_timer_smoke.2933766662 Dec 24 01:09:41 PM PST 23 Dec 24 01:09:50 PM PST 23 334996905 ps
T298 /workspace/coverage/default/26.aon_timer_jump.1372056898 Dec 24 01:09:46 PM PST 23 Dec 24 01:09:53 PM PST 23 422584080 ps
T299 /workspace/coverage/default/48.aon_timer_smoke.159012105 Dec 24 01:09:59 PM PST 23 Dec 24 01:10:03 PM PST 23 577054541 ps
T300 /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2540435230 Dec 24 01:09:34 PM PST 23 Dec 24 01:17:52 PM PST 23 1183338973354 ps
T301 /workspace/coverage/default/42.aon_timer_smoke.356768996 Dec 24 01:09:48 PM PST 23 Dec 24 01:09:55 PM PST 23 408494554 ps
T302 /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3575226666 Dec 24 01:09:35 PM PST 23 Dec 24 01:12:00 PM PST 23 36861962733 ps
T303 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2391949067 Dec 24 12:21:22 PM PST 23 Dec 24 12:21:24 PM PST 23 497417216 ps
T304 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1740414164 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:37 PM PST 23 408935630 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1542914530 Dec 24 12:24:40 PM PST 23 Dec 24 12:24:43 PM PST 23 465216697 ps
T121 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1052649945 Dec 24 12:26:49 PM PST 23 Dec 24 12:27:02 PM PST 23 6262646521 ps
T46 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.824923164 Dec 24 12:20:00 PM PST 23 Dec 24 12:20:16 PM PST 23 7875259480 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2635099586 Dec 24 12:23:46 PM PST 23 Dec 24 12:23:50 PM PST 23 4443726872 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1215754709 Dec 24 12:21:20 PM PST 23 Dec 24 12:21:21 PM PST 23 325205597 ps
T308 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2877873053 Dec 24 12:23:57 PM PST 23 Dec 24 12:23:59 PM PST 23 434298162 ps
T309 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.748745142 Dec 24 12:26:13 PM PST 23 Dec 24 12:26:17 PM PST 23 507267835 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3471603965 Dec 24 12:23:46 PM PST 23 Dec 24 12:23:51 PM PST 23 8746232125 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3892300368 Dec 24 12:23:16 PM PST 23 Dec 24 12:23:19 PM PST 23 504044694 ps
T312 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.29967470 Dec 24 12:21:55 PM PST 23 Dec 24 12:21:57 PM PST 23 325855960 ps
T313 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.471169766 Dec 24 12:28:48 PM PST 23 Dec 24 12:28:58 PM PST 23 516214650 ps
T52 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.795266207 Dec 24 12:27:19 PM PST 23 Dec 24 12:27:23 PM PST 23 334879617 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2773897563 Dec 24 12:31:52 PM PST 23 Dec 24 12:32:23 PM PST 23 524153866 ps
T315 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2143362868 Dec 24 12:20:25 PM PST 23 Dec 24 12:20:38 PM PST 23 7995024778 ps
T316 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.639696166 Dec 24 12:28:41 PM PST 23 Dec 24 12:28:57 PM PST 23 462441160 ps
T53 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.910172897 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:39 PM PST 23 470970618 ps
T65 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2127608098 Dec 24 12:26:16 PM PST 23 Dec 24 12:26:22 PM PST 23 1974711545 ps
T317 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3599270991 Dec 24 12:22:15 PM PST 23 Dec 24 12:22:19 PM PST 23 487326445 ps
T66 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1696986620 Dec 24 12:24:21 PM PST 23 Dec 24 12:24:33 PM PST 23 1069232495 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1338942827 Dec 24 12:23:34 PM PST 23 Dec 24 12:23:36 PM PST 23 313310572 ps
T69 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2012294748 Dec 24 12:22:51 PM PST 23 Dec 24 12:22:53 PM PST 23 8565588315 ps
T319 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1670826342 Dec 24 12:26:18 PM PST 23 Dec 24 12:26:21 PM PST 23 489255642 ps
T320 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4025114798 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:40 PM PST 23 363577235 ps
T321 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.507815154 Dec 24 12:20:24 PM PST 23 Dec 24 12:20:26 PM PST 23 463363206 ps
T322 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3260132438 Dec 24 12:22:44 PM PST 23 Dec 24 12:22:46 PM PST 23 458100403 ps
T54 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2609615009 Dec 24 12:28:40 PM PST 23 Dec 24 12:28:47 PM PST 23 448307929 ps
T323 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2941919312 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:00 PM PST 23 374661304 ps
T55 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3051468852 Dec 24 12:28:40 PM PST 23 Dec 24 12:28:48 PM PST 23 351912951 ps
T56 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2072135034 Dec 24 12:26:34 PM PST 23 Dec 24 12:26:36 PM PST 23 295364004 ps
T324 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2908682552 Dec 24 12:26:50 PM PST 23 Dec 24 12:26:53 PM PST 23 556650971 ps
T325 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2033541094 Dec 24 12:26:59 PM PST 23 Dec 24 12:27:05 PM PST 23 412898591 ps
T326 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3072255331 Dec 24 12:22:50 PM PST 23 Dec 24 12:22:53 PM PST 23 941798748 ps
T327 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1810332557 Dec 24 12:25:11 PM PST 23 Dec 24 12:25:13 PM PST 23 1019921963 ps
T328 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3597272909 Dec 24 12:21:43 PM PST 23 Dec 24 12:21:45 PM PST 23 639303589 ps
T329 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1051227756 Dec 24 12:26:34 PM PST 23 Dec 24 12:26:37 PM PST 23 1441221956 ps
T330 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2255366754 Dec 24 12:26:47 PM PST 23 Dec 24 12:26:50 PM PST 23 358493402 ps
T331 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3272599228 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:37 PM PST 23 289261943 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.904409227 Dec 24 12:20:22 PM PST 23 Dec 24 12:20:24 PM PST 23 387422744 ps
T332 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2857291262 Dec 24 12:26:16 PM PST 23 Dec 24 12:26:21 PM PST 23 391977353 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1134241740 Dec 24 12:26:55 PM PST 23 Dec 24 12:26:59 PM PST 23 438875609 ps
T334 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.180891948 Dec 24 12:24:58 PM PST 23 Dec 24 12:25:02 PM PST 23 1576773174 ps
T335 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3987768280 Dec 24 12:23:46 PM PST 23 Dec 24 12:23:48 PM PST 23 2038980361 ps
T58 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.115245818 Dec 24 12:29:19 PM PST 23 Dec 24 12:29:29 PM PST 23 329627930 ps
T336 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2230891967 Dec 24 12:22:07 PM PST 23 Dec 24 12:22:13 PM PST 23 524971473 ps
T337 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2018726551 Dec 24 12:26:49 PM PST 23 Dec 24 12:26:53 PM PST 23 1585669343 ps
T59 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1873191607 Dec 24 12:24:06 PM PST 23 Dec 24 12:24:07 PM PST 23 427360099 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.105782679 Dec 24 12:20:51 PM PST 23 Dec 24 12:20:53 PM PST 23 464238409 ps
T339 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1096524257 Dec 24 12:21:20 PM PST 23 Dec 24 12:21:21 PM PST 23 459481217 ps
T340 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3925957167 Dec 24 12:26:36 PM PST 23 Dec 24 12:26:39 PM PST 23 593798792 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4205586560 Dec 24 12:20:06 PM PST 23 Dec 24 12:20:08 PM PST 23 478363540 ps
T342 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1256834355 Dec 24 12:20:22 PM PST 23 Dec 24 12:20:24 PM PST 23 301449658 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.113127371 Dec 24 12:30:03 PM PST 23 Dec 24 12:30:30 PM PST 23 504257324 ps
T343 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2160778968 Dec 24 12:27:20 PM PST 23 Dec 24 12:27:25 PM PST 23 1340611667 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3579221288 Dec 24 12:26:13 PM PST 23 Dec 24 12:26:17 PM PST 23 454059910 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.843515370 Dec 24 12:24:24 PM PST 23 Dec 24 12:24:32 PM PST 23 684077630 ps
T346 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2268886439 Dec 24 12:21:02 PM PST 23 Dec 24 12:21:04 PM PST 23 304130991 ps
T347 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.65410399 Dec 24 12:28:46 PM PST 23 Dec 24 12:28:55 PM PST 23 499179790 ps
T348 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.168800843 Dec 24 12:26:14 PM PST 23 Dec 24 12:26:18 PM PST 23 1907771404 ps
T61 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2972768923 Dec 24 12:19:54 PM PST 23 Dec 24 12:19:56 PM PST 23 283539212 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2498097196 Dec 24 12:21:16 PM PST 23 Dec 24 12:21:21 PM PST 23 7888212332 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3361140680 Dec 24 12:22:18 PM PST 23 Dec 24 12:22:26 PM PST 23 2648246787 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.239572990 Dec 24 12:24:36 PM PST 23 Dec 24 12:24:39 PM PST 23 341113522 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1004317646 Dec 24 12:22:49 PM PST 23 Dec 24 12:22:51 PM PST 23 355989107 ps
T352 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1871635287 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:43 PM PST 23 8599230618 ps
T353 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2594903000 Dec 24 12:20:00 PM PST 23 Dec 24 12:20:04 PM PST 23 535216877 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3918971045 Dec 24 12:30:04 PM PST 23 Dec 24 12:30:31 PM PST 23 384624428 ps
T355 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3309518751 Dec 24 12:26:54 PM PST 23 Dec 24 12:26:59 PM PST 23 479622884 ps
T356 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.976997944 Dec 24 12:20:24 PM PST 23 Dec 24 12:20:25 PM PST 23 423413311 ps
T357 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2256890226 Dec 24 12:25:06 PM PST 23 Dec 24 12:25:08 PM PST 23 346379939 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1210261559 Dec 24 12:26:28 PM PST 23 Dec 24 12:26:31 PM PST 23 331789707 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2187381669 Dec 24 12:31:18 PM PST 23 Dec 24 12:31:44 PM PST 23 584401684 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2995515354 Dec 24 12:26:49 PM PST 23 Dec 24 12:26:53 PM PST 23 477558593 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1270692292 Dec 24 12:23:18 PM PST 23 Dec 24 12:23:19 PM PST 23 542417040 ps
T361 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.765112093 Dec 24 12:24:00 PM PST 23 Dec 24 12:24:03 PM PST 23 443865495 ps
T362 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1932741607 Dec 24 12:21:02 PM PST 23 Dec 24 12:21:04 PM PST 23 414969211 ps
T363 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1287641203 Dec 24 12:20:23 PM PST 23 Dec 24 12:20:25 PM PST 23 327034649 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2449598602 Dec 24 12:26:36 PM PST 23 Dec 24 12:26:40 PM PST 23 378914137 ps
T365 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3153466801 Dec 24 12:26:13 PM PST 23 Dec 24 12:26:16 PM PST 23 316383113 ps
T366 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2361506445 Dec 24 12:23:45 PM PST 23 Dec 24 12:23:47 PM PST 23 541106895 ps
T367 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.219465212 Dec 24 12:26:30 PM PST 23 Dec 24 12:26:33 PM PST 23 282672170 ps
T368 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1317554595 Dec 24 12:20:43 PM PST 23 Dec 24 12:20:46 PM PST 23 4220807317 ps
T369 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3030931715 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:43 PM PST 23 1080084833 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2700794546 Dec 24 12:24:27 PM PST 23 Dec 24 12:24:33 PM PST 23 582473829 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2932639705 Dec 24 12:26:14 PM PST 23 Dec 24 12:26:18 PM PST 23 463068790 ps
T372 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.745472588 Dec 24 12:28:48 PM PST 23 Dec 24 12:28:58 PM PST 23 683338709 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1469364591 Dec 24 12:28:48 PM PST 23 Dec 24 12:29:07 PM PST 23 11387218982 ps
T374 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4256794214 Dec 24 12:20:31 PM PST 23 Dec 24 12:20:32 PM PST 23 384054887 ps
T375 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1052815841 Dec 24 12:21:18 PM PST 23 Dec 24 12:21:20 PM PST 23 444139268 ps
T376 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2665515979 Dec 24 12:25:21 PM PST 23 Dec 24 12:25:23 PM PST 23 414898035 ps
T377 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2299128053 Dec 24 12:25:39 PM PST 23 Dec 24 12:25:42 PM PST 23 386704279 ps
T378 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.100833082 Dec 24 12:25:38 PM PST 23 Dec 24 12:25:41 PM PST 23 373246776 ps
T379 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3448666349 Dec 24 12:21:17 PM PST 23 Dec 24 12:21:20 PM PST 23 4324346569 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1869834068 Dec 24 12:24:37 PM PST 23 Dec 24 12:24:41 PM PST 23 898292803 ps
T381 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1127047620 Dec 24 12:21:16 PM PST 23 Dec 24 12:21:18 PM PST 23 274588478 ps
T382 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3465067885 Dec 24 12:21:02 PM PST 23 Dec 24 12:21:09 PM PST 23 4454812906 ps
T383 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3162254776 Dec 24 12:21:02 PM PST 23 Dec 24 12:21:04 PM PST 23 502443103 ps
T384 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.947067910 Dec 24 12:25:38 PM PST 23 Dec 24 12:25:41 PM PST 23 334704225 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2518813386 Dec 24 12:24:22 PM PST 23 Dec 24 12:24:32 PM PST 23 1113244579 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1344913597 Dec 24 12:23:59 PM PST 23 Dec 24 12:24:02 PM PST 23 403434551 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3803831322 Dec 24 12:19:50 PM PST 23 Dec 24 12:19:53 PM PST 23 905141210 ps
T388 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3180887645 Dec 24 12:22:41 PM PST 23 Dec 24 12:22:43 PM PST 23 379460743 ps
T389 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2865781564 Dec 24 12:21:39 PM PST 23 Dec 24 12:21:40 PM PST 23 448963702 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2859442002 Dec 24 12:21:19 PM PST 23 Dec 24 12:21:33 PM PST 23 7745424132 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2804971347 Dec 24 12:22:06 PM PST 23 Dec 24 12:22:12 PM PST 23 496042341 ps
T392 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1380390834 Dec 24 12:23:57 PM PST 23 Dec 24 12:24:02 PM PST 23 4592813098 ps
T393 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3173300663 Dec 24 12:20:56 PM PST 23 Dec 24 12:21:00 PM PST 23 8026014024 ps
T394 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2389840132 Dec 24 12:22:54 PM PST 23 Dec 24 12:22:56 PM PST 23 4563192803 ps
T395 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3937067132 Dec 24 12:20:01 PM PST 23 Dec 24 12:20:04 PM PST 23 374779010 ps
T396 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.726912616 Dec 24 12:21:55 PM PST 23 Dec 24 12:21:57 PM PST 23 531542811 ps
T397 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.367074137 Dec 24 12:24:20 PM PST 23 Dec 24 12:24:23 PM PST 23 301991053 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3675888983 Dec 24 12:26:58 PM PST 23 Dec 24 12:27:11 PM PST 23 2728316620 ps
T398 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.549166083 Dec 24 12:21:00 PM PST 23 Dec 24 12:21:01 PM PST 23 422850948 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1510678777 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:40 PM PST 23 337058805 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.857187468 Dec 24 12:26:54 PM PST 23 Dec 24 12:27:02 PM PST 23 4381119844 ps
T401 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.683191681 Dec 24 12:24:05 PM PST 23 Dec 24 12:24:07 PM PST 23 382247140 ps
T402 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3108776446 Dec 24 12:27:19 PM PST 23 Dec 24 12:27:24 PM PST 23 387835020 ps
T403 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1916005353 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:38 PM PST 23 525185842 ps
T404 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3350598053 Dec 24 12:26:58 PM PST 23 Dec 24 12:27:03 PM PST 23 519279526 ps
T405 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3994791088 Dec 24 12:24:37 PM PST 23 Dec 24 12:24:54 PM PST 23 8769539510 ps
T406 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2109296795 Dec 24 12:21:02 PM PST 23 Dec 24 12:21:04 PM PST 23 599319716 ps
T407 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3732689125 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:40 PM PST 23 340868792 ps
T408 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3212539878 Dec 24 12:26:22 PM PST 23 Dec 24 12:26:26 PM PST 23 399632467 ps
T409 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.34863799 Dec 24 12:26:52 PM PST 23 Dec 24 12:27:08 PM PST 23 8387575166 ps
T410 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3154004761 Dec 24 12:26:54 PM PST 23 Dec 24 12:27:01 PM PST 23 1283782829 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3745288042 Dec 24 12:26:59 PM PST 23 Dec 24 12:27:05 PM PST 23 276717931 ps
T412 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3519886966 Dec 24 12:21:27 PM PST 23 Dec 24 12:21:28 PM PST 23 361896349 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3691445874 Dec 24 12:20:14 PM PST 23 Dec 24 12:20:17 PM PST 23 1822968921 ps
T414 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4181097900 Dec 24 12:25:37 PM PST 23 Dec 24 12:25:46 PM PST 23 7668498857 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3835076588 Dec 24 12:20:43 PM PST 23 Dec 24 12:20:45 PM PST 23 587369920 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2776544825 Dec 24 12:26:49 PM PST 23 Dec 24 12:26:52 PM PST 23 297310957 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1876773306 Dec 24 12:24:08 PM PST 23 Dec 24 12:24:16 PM PST 23 6094433220 ps
T418 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2360363635 Dec 24 12:27:06 PM PST 23 Dec 24 12:27:13 PM PST 23 864416690 ps
T419 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1014284670 Dec 24 12:23:16 PM PST 23 Dec 24 12:23:20 PM PST 23 1843044467 ps
T420 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3016790520 Dec 24 12:26:34 PM PST 23 Dec 24 12:26:37 PM PST 23 349882573 ps
T421 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1931054440 Dec 24 12:26:56 PM PST 23 Dec 24 12:27:03 PM PST 23 5970756346 ps
T64 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3019115099 Dec 24 12:26:13 PM PST 23 Dec 24 12:26:17 PM PST 23 371107108 ps
T422 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2280542517 Dec 24 12:24:23 PM PST 23 Dec 24 12:24:32 PM PST 23 453093963 ps
T423 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4011031059 Dec 24 12:20:26 PM PST 23 Dec 24 12:20:28 PM PST 23 363782961 ps
T424 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3206939553 Dec 24 12:21:36 PM PST 23 Dec 24 12:21:39 PM PST 23 427325983 ps
T425 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.285662563 Dec 24 12:24:21 PM PST 23 Dec 24 12:24:30 PM PST 23 519875323 ps
T426 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2603298130 Dec 24 12:20:26 PM PST 23 Dec 24 12:20:28 PM PST 23 440737282 ps
T427 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.682750943 Dec 24 12:26:35 PM PST 23 Dec 24 12:26:39 PM PST 23 329719009 ps
T428 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2406062052 Dec 24 12:26:34 PM PST 23 Dec 24 12:26:36 PM PST 23 676105029 ps
T429 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4000576258 Dec 24 12:23:35 PM PST 23 Dec 24 12:23:37 PM PST 23 497775479 ps

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.366596812
Short name T11
Test name
Test status
Simulation time 7412625246 ps
CPU time 12.28 seconds
Started Dec 24 12:24:23 PM PST 23
Finished Dec 24 12:24:43 PM PST 23
Peak memory 197968 kb
Host smart-a86f39e5-6ab3-4de4-8d51-6f6cec877f38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366596812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.366596812
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3974046214
Short name T24
Test name
Test status
Simulation time 114802027970 ps
CPU time 20.35 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 182696 kb
Host smart-be8b1629-fb5c-4b9b-bf6f-a93939a6c860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974046214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3974046214
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.4075516218
Short name T33
Test name
Test status
Simulation time 18303958885 ps
CPU time 133.77 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:12:04 PM PST 23
Peak memory 197652 kb
Host smart-27b7c30e-033d-4c9f-ad7f-54afb41283cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075516218 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.4075516218
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.839542859
Short name T13
Test name
Test status
Simulation time 381319890519 ps
CPU time 89.1 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 192784 kb
Host smart-ae15e075-d2d5-4b0e-b74e-e14c6a406abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839542859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.839542859
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1252289738
Short name T106
Test name
Test status
Simulation time 468369130371 ps
CPU time 493.02 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:18:19 PM PST 23
Peak memory 197720 kb
Host smart-5970a2ef-a440-404d-98d9-b8a032b7e026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252289738 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1252289738
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3090058486
Short name T74
Test name
Test status
Simulation time 276822851680 ps
CPU time 519.45 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:18:49 PM PST 23
Peak memory 197580 kb
Host smart-0c8da35f-728c-493c-8305-dbac8d1cd39b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090058486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3090058486
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.877259835
Short name T50
Test name
Test status
Simulation time 79229609191 ps
CPU time 691.63 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:21:15 PM PST 23
Peak memory 198748 kb
Host smart-43550ad4-c6eb-453d-8642-bc5bc78c9fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877259835 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.877259835
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.566135057
Short name T88
Test name
Test status
Simulation time 216060501108 ps
CPU time 397.59 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:16:26 PM PST 23
Peak memory 197696 kb
Host smart-d9d2b704-4bda-4d1d-8505-6c136667e521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566135057 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.566135057
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.4139873850
Short name T14
Test name
Test status
Simulation time 579866887 ps
CPU time 1.81 seconds
Started Dec 24 12:20:45 PM PST 23
Finished Dec 24 12:20:48 PM PST 23
Peak memory 198460 kb
Host smart-2621467b-3ea7-4c70-a886-bbd54efe87f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139873850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.4139873850
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1149394402
Short name T37
Test name
Test status
Simulation time 7427069819 ps
CPU time 12.1 seconds
Started Dec 24 01:09:42 PM PST 23
Finished Dec 24 01:10:01 PM PST 23
Peak memory 215004 kb
Host smart-3604e0ec-8504-4675-bc69-14d25b5d3676
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149394402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1149394402
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3533739640
Short name T41
Test name
Test status
Simulation time 86574363861 ps
CPU time 692.84 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:21:30 PM PST 23
Peak memory 198972 kb
Host smart-1a4b393e-75cb-4d08-9015-4a7e445f1067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533739640 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3533739640
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2880283628
Short name T94
Test name
Test status
Simulation time 76058817664 ps
CPU time 122.23 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 182820 kb
Host smart-4c9f21fd-5f2b-4dc3-a710-cb96a25bd747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880283628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2880283628
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1940565463
Short name T87
Test name
Test status
Simulation time 500742723669 ps
CPU time 919.97 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:25:12 PM PST 23
Peak memory 201380 kb
Host smart-a0e69b17-e362-4b51-96bd-40f48da240ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940565463 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1940565463
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1555389949
Short name T287
Test name
Test status
Simulation time 54561389001 ps
CPU time 102.03 seconds
Started Dec 24 01:10:01 PM PST 23
Finished Dec 24 01:11:46 PM PST 23
Peak memory 197716 kb
Host smart-875e5633-57a5-4c60-b3b2-98ba8c24228e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555389949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1555389949
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.564366719
Short name T4
Test name
Test status
Simulation time 1190052745 ps
CPU time 2.19 seconds
Started Dec 24 12:22:52 PM PST 23
Finished Dec 24 12:22:55 PM PST 23
Peak memory 194140 kb
Host smart-4895ab5c-37ca-4b69-8d3f-dd1c23d171b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564366719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.564366719
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2851520895
Short name T91
Test name
Test status
Simulation time 255852072342 ps
CPU time 114.07 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 193216 kb
Host smart-cf53a424-c5fb-4aba-90e1-76cdc8aa85f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851520895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2851520895
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2187381669
Short name T62
Test name
Test status
Simulation time 584401684 ps
CPU time 1.5 seconds
Started Dec 24 12:31:18 PM PST 23
Finished Dec 24 12:31:44 PM PST 23
Peak memory 193348 kb
Host smart-6a735a11-4c9a-42b0-90eb-2b2af5b2c0e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187381669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2187381669
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3213167944
Short name T80
Test name
Test status
Simulation time 281242820820 ps
CPU time 416.03 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:16:39 PM PST 23
Peak memory 182796 kb
Host smart-b258c9d3-982f-408c-a713-7ed8a0cac840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213167944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3213167944
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.280297049
Short name T213
Test name
Test status
Simulation time 418358046 ps
CPU time 0.87 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 182692 kb
Host smart-c8298909-8965-4dd4-9d37-adc7b7bb1a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280297049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.280297049
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3675888983
Short name T63
Test name
Test status
Simulation time 2728316620 ps
CPU time 10.15 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:11 PM PST 23
Peak memory 195228 kb
Host smart-be8cd33a-7f2b-4e97-ad15-9e89653a4434
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675888983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3675888983
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1869834068
Short name T380
Test name
Test status
Simulation time 898292803 ps
CPU time 1.99 seconds
Started Dec 24 12:24:37 PM PST 23
Finished Dec 24 12:24:41 PM PST 23
Peak memory 182044 kb
Host smart-840ff458-d6b0-4904-9761-89fb12581c99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869834068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1869834068
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2280542517
Short name T422
Test name
Test status
Simulation time 453093963 ps
CPU time 1.35 seconds
Started Dec 24 12:24:23 PM PST 23
Finished Dec 24 12:24:32 PM PST 23
Peak memory 194632 kb
Host smart-35b7e800-8006-4db1-be66-e486313c1dae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280542517 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2280542517
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.904409227
Short name T57
Test name
Test status
Simulation time 387422744 ps
CPU time 0.73 seconds
Started Dec 24 12:20:22 PM PST 23
Finished Dec 24 12:20:24 PM PST 23
Peak memory 183280 kb
Host smart-ac17c2f5-db8d-480a-8019-448ab1aa03d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904409227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.904409227
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.471169766
Short name T313
Test name
Test status
Simulation time 516214650 ps
CPU time 1.17 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 183168 kb
Host smart-c931ae96-5c2d-43f5-ae1c-983cbbf3f7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471169766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.471169766
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2804971347
Short name T391
Test name
Test status
Simulation time 496042341 ps
CPU time 1.16 seconds
Started Dec 24 12:22:06 PM PST 23
Finished Dec 24 12:22:12 PM PST 23
Peak memory 183356 kb
Host smart-eca1f480-bb69-40db-ba53-33232493b73c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804971347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2804971347
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2773897563
Short name T314
Test name
Test status
Simulation time 524153866 ps
CPU time 0.67 seconds
Started Dec 24 12:31:52 PM PST 23
Finished Dec 24 12:32:23 PM PST 23
Peak memory 183420 kb
Host smart-25df6c82-d2a8-4552-b053-0597dcd31535
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773897563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2773897563
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1872929008
Short name T6
Test name
Test status
Simulation time 1993286272 ps
CPU time 1.87 seconds
Started Dec 24 12:23:22 PM PST 23
Finished Dec 24 12:23:24 PM PST 23
Peak memory 194452 kb
Host smart-1ebaf680-a64d-473c-a9a9-710efab3510f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872929008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1872929008
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2859442002
Short name T390
Test name
Test status
Simulation time 7745424132 ps
CPU time 12.86 seconds
Started Dec 24 12:21:19 PM PST 23
Finished Dec 24 12:21:33 PM PST 23
Peak memory 197468 kb
Host smart-d5c9de82-cfaa-44d9-8a5b-c21e2ebe1b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859442002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2859442002
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.843515370
Short name T345
Test name
Test status
Simulation time 684077630 ps
CPU time 0.93 seconds
Started Dec 24 12:24:24 PM PST 23
Finished Dec 24 12:24:32 PM PST 23
Peak memory 183212 kb
Host smart-0c55e985-7ad7-4489-9e75-275980096af7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843515370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.843515370
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1931054440
Short name T421
Test name
Test status
Simulation time 5970756346 ps
CPU time 3.15 seconds
Started Dec 24 12:26:56 PM PST 23
Finished Dec 24 12:27:03 PM PST 23
Peak memory 191760 kb
Host smart-50826d79-a5c7-4c9a-a196-7e0c61b88d17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931054440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1931054440
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3154004761
Short name T410
Test name
Test status
Simulation time 1283782829 ps
CPU time 2.33 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:27:01 PM PST 23
Peak memory 181768 kb
Host smart-3a746a4d-ba9f-4515-af97-d84ca8735e48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154004761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3154004761
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3309518751
Short name T355
Test name
Test status
Simulation time 479622884 ps
CPU time 0.96 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 196296 kb
Host smart-2e5a54e3-0491-4c4c-b734-026eb11e05b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309518751 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3309518751
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2361506445
Short name T366
Test name
Test status
Simulation time 541106895 ps
CPU time 1.17 seconds
Started Dec 24 12:23:45 PM PST 23
Finished Dec 24 12:23:47 PM PST 23
Peak memory 192960 kb
Host smart-49c0fd53-e3d9-48bc-b357-d7c0c64b40d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361506445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2361506445
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3745288042
Short name T411
Test name
Test status
Simulation time 276717931 ps
CPU time 0.68 seconds
Started Dec 24 12:26:59 PM PST 23
Finished Dec 24 12:27:05 PM PST 23
Peak memory 183172 kb
Host smart-c2da10e4-4be4-44f8-a3e1-9090aedb7533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745288042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3745288042
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3260132438
Short name T322
Test name
Test status
Simulation time 458100403 ps
CPU time 1.2 seconds
Started Dec 24 12:22:44 PM PST 23
Finished Dec 24 12:22:46 PM PST 23
Peak memory 183432 kb
Host smart-495a326d-2abd-43b8-9942-783282be475c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260132438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3260132438
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2211015609
Short name T122
Test name
Test status
Simulation time 386797108 ps
CPU time 0.53 seconds
Started Dec 24 12:27:00 PM PST 23
Finished Dec 24 12:27:06 PM PST 23
Peak memory 183312 kb
Host smart-42b64edd-819d-42d4-bbac-0f3098d3bbb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211015609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2211015609
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3987768280
Short name T335
Test name
Test status
Simulation time 2038980361 ps
CPU time 1.43 seconds
Started Dec 24 12:23:46 PM PST 23
Finished Dec 24 12:23:48 PM PST 23
Peak memory 194108 kb
Host smart-34e53a66-f506-4420-85a3-2d1dc51e6c03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987768280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3987768280
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1344913597
Short name T386
Test name
Test status
Simulation time 403434551 ps
CPU time 2.39 seconds
Started Dec 24 12:23:59 PM PST 23
Finished Dec 24 12:24:02 PM PST 23
Peak memory 198428 kb
Host smart-92fcef15-0d68-4575-acdd-ae202ee90580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344913597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1344913597
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2498097196
Short name T70
Test name
Test status
Simulation time 7888212332 ps
CPU time 4.14 seconds
Started Dec 24 12:21:16 PM PST 23
Finished Dec 24 12:21:21 PM PST 23
Peak memory 197872 kb
Host smart-b849d044-8c58-4ab5-9208-31589fef972b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498097196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2498097196
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2594903000
Short name T353
Test name
Test status
Simulation time 535216877 ps
CPU time 1.48 seconds
Started Dec 24 12:20:00 PM PST 23
Finished Dec 24 12:20:04 PM PST 23
Peak memory 194560 kb
Host smart-28ea2bf7-0b2b-41e4-817b-de720b64e5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594903000 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2594903000
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2972768923
Short name T61
Test name
Test status
Simulation time 283539212 ps
CPU time 1.07 seconds
Started Dec 24 12:19:54 PM PST 23
Finished Dec 24 12:19:56 PM PST 23
Peak memory 182836 kb
Host smart-b41b13a0-d927-47b2-95c9-f6307389ebbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972768923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2972768923
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2268886439
Short name T346
Test name
Test status
Simulation time 304130991 ps
CPU time 0.98 seconds
Started Dec 24 12:21:02 PM PST 23
Finished Dec 24 12:21:04 PM PST 23
Peak memory 183400 kb
Host smart-2c927ffd-222e-49bd-bd44-025b6db2800b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268886439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2268886439
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1696986620
Short name T66
Test name
Test status
Simulation time 1069232495 ps
CPU time 2.35 seconds
Started Dec 24 12:24:21 PM PST 23
Finished Dec 24 12:24:33 PM PST 23
Peak memory 193112 kb
Host smart-cb7c1dec-c385-45ca-bf67-423106a8a3ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696986620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1696986620
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2449598602
Short name T364
Test name
Test status
Simulation time 378914137 ps
CPU time 1.92 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:40 PM PST 23
Peak memory 198580 kb
Host smart-6f743dc5-08d4-4136-bee4-ac560f0ba146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449598602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2449598602
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1317554595
Short name T368
Test name
Test status
Simulation time 4220807317 ps
CPU time 2.7 seconds
Started Dec 24 12:20:43 PM PST 23
Finished Dec 24 12:20:46 PM PST 23
Peak memory 196972 kb
Host smart-9a9795fb-18b8-4323-876e-76d24bd38093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317554595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1317554595
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3835076588
Short name T415
Test name
Test status
Simulation time 587369920 ps
CPU time 1.47 seconds
Started Dec 24 12:20:43 PM PST 23
Finished Dec 24 12:20:45 PM PST 23
Peak memory 195128 kb
Host smart-29ca8d00-f8fe-49eb-a01f-0cd84e7615d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835076588 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3835076588
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.115245818
Short name T58
Test name
Test status
Simulation time 329627930 ps
CPU time 1.04 seconds
Started Dec 24 12:29:19 PM PST 23
Finished Dec 24 12:29:29 PM PST 23
Peak memory 183224 kb
Host smart-b23ad496-296e-4c36-95c1-5f48a73801c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115245818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.115245818
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.549166083
Short name T398
Test name
Test status
Simulation time 422850948 ps
CPU time 0.58 seconds
Started Dec 24 12:21:00 PM PST 23
Finished Dec 24 12:21:01 PM PST 23
Peak memory 183644 kb
Host smart-935f0701-ddd8-4247-a630-8aa20b34231a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549166083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.549166083
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.367074137
Short name T397
Test name
Test status
Simulation time 301991053 ps
CPU time 1.75 seconds
Started Dec 24 12:24:20 PM PST 23
Finished Dec 24 12:24:23 PM PST 23
Peak memory 198440 kb
Host smart-9bb16694-3dd4-4545-8d0d-cc451c18f07c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367074137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.367074137
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3173300663
Short name T393
Test name
Test status
Simulation time 8026014024 ps
CPU time 3.06 seconds
Started Dec 24 12:20:56 PM PST 23
Finished Dec 24 12:21:00 PM PST 23
Peak memory 197672 kb
Host smart-4318e2dc-32ae-4159-9a3f-a6e2a4caa451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173300663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3173300663
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2908682552
Short name T324
Test name
Test status
Simulation time 556650971 ps
CPU time 0.82 seconds
Started Dec 24 12:26:50 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 194288 kb
Host smart-4acd9a2f-6333-4709-bed3-40dda04f18cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908682552 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2908682552
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2033541094
Short name T325
Test name
Test status
Simulation time 412898591 ps
CPU time 1.13 seconds
Started Dec 24 12:26:59 PM PST 23
Finished Dec 24 12:27:05 PM PST 23
Peak memory 183612 kb
Host smart-252fcbb1-45e3-4985-90d5-23055f8c2006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033541094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2033541094
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.4000576258
Short name T429
Test name
Test status
Simulation time 497775479 ps
CPU time 0.86 seconds
Started Dec 24 12:23:35 PM PST 23
Finished Dec 24 12:23:37 PM PST 23
Peak memory 183652 kb
Host smart-39b68ff8-fab9-4a44-87ef-26d809d7736a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000576258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.4000576258
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3691445874
Short name T413
Test name
Test status
Simulation time 1822968921 ps
CPU time 1.35 seconds
Started Dec 24 12:20:14 PM PST 23
Finished Dec 24 12:20:17 PM PST 23
Peak memory 193624 kb
Host smart-8f9e6023-0637-4d2a-bd3a-a8ebcee04bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691445874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3691445874
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1338942827
Short name T318
Test name
Test status
Simulation time 313310572 ps
CPU time 1.63 seconds
Started Dec 24 12:23:34 PM PST 23
Finished Dec 24 12:23:36 PM PST 23
Peak memory 198536 kb
Host smart-84590a09-dbc2-4a87-9b13-2c7d53cc8925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338942827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1338942827
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.3465067885
Short name T382
Test name
Test status
Simulation time 4454812906 ps
CPU time 6.92 seconds
Started Dec 24 12:21:02 PM PST 23
Finished Dec 24 12:21:09 PM PST 23
Peak memory 197036 kb
Host smart-323b9019-e27c-414d-803c-266425e70b98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465067885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.3465067885
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1270692292
Short name T360
Test name
Test status
Simulation time 542417040 ps
CPU time 0.87 seconds
Started Dec 24 12:23:18 PM PST 23
Finished Dec 24 12:23:19 PM PST 23
Peak memory 196180 kb
Host smart-ce547edd-14dd-4164-8291-653b8ebc6095
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270692292 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1270692292
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2256890226
Short name T357
Test name
Test status
Simulation time 346379939 ps
CPU time 0.64 seconds
Started Dec 24 12:25:06 PM PST 23
Finished Dec 24 12:25:08 PM PST 23
Peak memory 183688 kb
Host smart-418fd5d4-75b0-49b8-a29b-6997bc50693d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256890226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2256890226
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4285152378
Short name T30
Test name
Test status
Simulation time 391069092 ps
CPU time 0.81 seconds
Started Dec 24 12:25:44 PM PST 23
Finished Dec 24 12:25:47 PM PST 23
Peak memory 183432 kb
Host smart-8258ea41-6c7b-4c7c-aa12-524eef08c415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285152378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4285152378
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3030931715
Short name T369
Test name
Test status
Simulation time 1080084833 ps
CPU time 3.07 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 194080 kb
Host smart-9fab0bbe-a7ac-41b1-8c1b-135e4f398d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030931715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3030931715
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2406062052
Short name T428
Test name
Test status
Simulation time 676105029 ps
CPU time 1.32 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 196920 kb
Host smart-e4573d0b-14c8-4737-b166-1cc15defba7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406062052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2406062052
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.824923164
Short name T46
Test name
Test status
Simulation time 7875259480 ps
CPU time 15.39 seconds
Started Dec 24 12:20:00 PM PST 23
Finished Dec 24 12:20:16 PM PST 23
Peak memory 197836 kb
Host smart-17420403-2e71-40e3-8961-feb6fa3aa9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824923164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.824923164
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2109296795
Short name T406
Test name
Test status
Simulation time 599319716 ps
CPU time 0.81 seconds
Started Dec 24 12:21:02 PM PST 23
Finished Dec 24 12:21:04 PM PST 23
Peak memory 196216 kb
Host smart-f9447c31-31e2-4738-95d5-ab53d59b20c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109296795 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2109296795
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1510678777
Short name T399
Test name
Test status
Simulation time 337058805 ps
CPU time 0.66 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:40 PM PST 23
Peak memory 183616 kb
Host smart-8cad77bf-559f-4e64-af12-e5a5f23d9570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510678777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1510678777
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1409123182
Short name T8
Test name
Test status
Simulation time 362567619 ps
CPU time 0.99 seconds
Started Dec 24 12:23:10 PM PST 23
Finished Dec 24 12:23:12 PM PST 23
Peak memory 183400 kb
Host smart-72bceee0-62ab-4b76-bda2-ba814807a2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409123182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1409123182
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2160778968
Short name T343
Test name
Test status
Simulation time 1340611667 ps
CPU time 1.73 seconds
Started Dec 24 12:27:20 PM PST 23
Finished Dec 24 12:27:25 PM PST 23
Peak memory 192324 kb
Host smart-7d25fa27-525c-4ec9-853c-81b1e177aaa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160778968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2160778968
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.239572990
Short name T350
Test name
Test status
Simulation time 341113522 ps
CPU time 1.91 seconds
Started Dec 24 12:24:36 PM PST 23
Finished Dec 24 12:24:39 PM PST 23
Peak memory 197476 kb
Host smart-abce6a0f-bf0e-450c-914e-b9ffed0fe527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239572990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.239572990
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1871635287
Short name T352
Test name
Test status
Simulation time 8599230618 ps
CPU time 3.5 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:43 PM PST 23
Peak memory 197316 kb
Host smart-739f3cba-f810-431e-b472-757da4141fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871635287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1871635287
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2932639705
Short name T371
Test name
Test status
Simulation time 463068790 ps
CPU time 1.44 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 195012 kb
Host smart-b9e7baad-6b09-41c6-a3d9-03b91bccb2c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932639705 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2932639705
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3019115099
Short name T64
Test name
Test status
Simulation time 371107108 ps
CPU time 1.17 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 181456 kb
Host smart-af6452f3-f27f-4738-8d88-b1fbafe1b268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019115099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3019115099
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1740414164
Short name T304
Test name
Test status
Simulation time 408935630 ps
CPU time 0.7 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 183344 kb
Host smart-f44344f2-e64b-42e2-b559-43c12b5f2914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740414164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1740414164
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2360363635
Short name T418
Test name
Test status
Simulation time 864416690 ps
CPU time 2.52 seconds
Started Dec 24 12:27:06 PM PST 23
Finished Dec 24 12:27:13 PM PST 23
Peak memory 192708 kb
Host smart-012293ea-ab19-408e-b36c-a4232c8c50e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360363635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2360363635
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2837378564
Short name T16
Test name
Test status
Simulation time 307055703 ps
CPU time 1.49 seconds
Started Dec 24 12:23:23 PM PST 23
Finished Dec 24 12:23:25 PM PST 23
Peak memory 198456 kb
Host smart-ed14eb81-50a3-4669-b57b-4990034a3cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837378564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2837378564
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3448666349
Short name T379
Test name
Test status
Simulation time 4324346569 ps
CPU time 2.52 seconds
Started Dec 24 12:21:17 PM PST 23
Finished Dec 24 12:21:20 PM PST 23
Peak memory 196136 kb
Host smart-74796e30-cfa7-48ba-ac06-00cc8fb2c274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448666349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3448666349
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4011031059
Short name T423
Test name
Test status
Simulation time 363782961 ps
CPU time 1.34 seconds
Started Dec 24 12:20:26 PM PST 23
Finished Dec 24 12:20:28 PM PST 23
Peak memory 195020 kb
Host smart-5e58cb79-36fd-4f09-907d-65822ea23f53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011031059 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4011031059
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.795266207
Short name T52
Test name
Test status
Simulation time 334879617 ps
CPU time 0.73 seconds
Started Dec 24 12:27:19 PM PST 23
Finished Dec 24 12:27:23 PM PST 23
Peak memory 182352 kb
Host smart-818bcccc-e11c-4eb1-898e-f7e9d611b276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795266207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.795266207
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3272599228
Short name T331
Test name
Test status
Simulation time 289261943 ps
CPU time 0.75 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 183084 kb
Host smart-1cf548d9-3076-4c31-aae2-bae20f110075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272599228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3272599228
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.180891948
Short name T334
Test name
Test status
Simulation time 1576773174 ps
CPU time 1.55 seconds
Started Dec 24 12:24:58 PM PST 23
Finished Dec 24 12:25:02 PM PST 23
Peak memory 193752 kb
Host smart-92ea6e9d-ad5e-4ac0-bf11-408dd347223b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180891948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.180891948
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3223471333
Short name T26
Test name
Test status
Simulation time 566879276 ps
CPU time 2.05 seconds
Started Dec 24 12:22:50 PM PST 23
Finished Dec 24 12:22:53 PM PST 23
Peak memory 198440 kb
Host smart-2e12f831-d522-4e29-b020-2044bd7df2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223471333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3223471333
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2012294748
Short name T69
Test name
Test status
Simulation time 8565588315 ps
CPU time 1.71 seconds
Started Dec 24 12:22:51 PM PST 23
Finished Dec 24 12:22:53 PM PST 23
Peak memory 197488 kb
Host smart-1e628174-1cd5-4a56-ae27-582413655899
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012294748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2012294748
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.285662563
Short name T425
Test name
Test status
Simulation time 519875323 ps
CPU time 1.45 seconds
Started Dec 24 12:24:21 PM PST 23
Finished Dec 24 12:24:30 PM PST 23
Peak memory 194448 kb
Host smart-0e68b3ad-7e2f-4f7b-a1a3-c405388c1c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285662563 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.285662563
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4025114798
Short name T320
Test name
Test status
Simulation time 363577235 ps
CPU time 0.65 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:40 PM PST 23
Peak memory 183588 kb
Host smart-8aad4eda-dabd-40a7-af54-d046da2705fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025114798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4025114798
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1127047620
Short name T381
Test name
Test status
Simulation time 274588478 ps
CPU time 1.05 seconds
Started Dec 24 12:21:16 PM PST 23
Finished Dec 24 12:21:18 PM PST 23
Peak memory 183860 kb
Host smart-40dd5135-4ec9-4ac4-bc72-74ec020c3981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127047620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1127047620
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3072255331
Short name T326
Test name
Test status
Simulation time 941798748 ps
CPU time 1.88 seconds
Started Dec 24 12:22:50 PM PST 23
Finished Dec 24 12:22:53 PM PST 23
Peak memory 192540 kb
Host smart-bfdb84a5-e4b6-49ea-850e-b1f7a16f5ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072255331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3072255331
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1916005353
Short name T403
Test name
Test status
Simulation time 525185842 ps
CPU time 1.52 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:38 PM PST 23
Peak memory 198092 kb
Host smart-d0b32a8e-50af-4e22-b647-37c218a21e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916005353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1916005353
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2389840132
Short name T394
Test name
Test status
Simulation time 4563192803 ps
CPU time 1.91 seconds
Started Dec 24 12:22:54 PM PST 23
Finished Dec 24 12:22:56 PM PST 23
Peak memory 195812 kb
Host smart-af2e28f9-1eb1-43f3-a971-c14ad3f78f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389840132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2389840132
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3579221288
Short name T344
Test name
Test status
Simulation time 454059910 ps
CPU time 1.4 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 193696 kb
Host smart-25b750be-8be9-48e1-8360-f609a0ccb30f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579221288 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3579221288
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3599270991
Short name T317
Test name
Test status
Simulation time 487326445 ps
CPU time 0.92 seconds
Started Dec 24 12:22:15 PM PST 23
Finished Dec 24 12:22:19 PM PST 23
Peak memory 183660 kb
Host smart-13a417e4-dddf-462c-9bca-b675e5767df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599270991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3599270991
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2941919312
Short name T323
Test name
Test status
Simulation time 374661304 ps
CPU time 1.16 seconds
Started Dec 24 12:27:53 PM PST 23
Finished Dec 24 12:28:00 PM PST 23
Peak memory 182536 kb
Host smart-5502f6c8-c936-498f-825f-7820e1c55e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941919312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2941919312
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.168800843
Short name T348
Test name
Test status
Simulation time 1907771404 ps
CPU time 2.57 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 194740 kb
Host smart-09deffa2-862d-4308-9aed-ec0a4878da60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168800843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.168800843
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.682750943
Short name T427
Test name
Test status
Simulation time 329719009 ps
CPU time 1.77 seconds
Started Dec 24 12:26:35 PM PST 23
Finished Dec 24 12:26:39 PM PST 23
Peak memory 198416 kb
Host smart-b785834c-0520-4f33-86e0-043770433518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682750943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.682750943
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.4181097900
Short name T414
Test name
Test status
Simulation time 7668498857 ps
CPU time 7.36 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:46 PM PST 23
Peak memory 197464 kb
Host smart-16595bf8-d520-4bf9-8c9c-5a506c1bd849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181097900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.4181097900
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.1542914530
Short name T305
Test name
Test status
Simulation time 465216697 ps
CPU time 1.32 seconds
Started Dec 24 12:24:40 PM PST 23
Finished Dec 24 12:24:43 PM PST 23
Peak memory 194220 kb
Host smart-5360e4a6-685b-48cb-be51-25228145a4b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542914530 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.1542914530
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.910172897
Short name T53
Test name
Test status
Simulation time 470970618 ps
CPU time 0.7 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:39 PM PST 23
Peak memory 183616 kb
Host smart-7263724b-7f79-4b8d-8feb-517653472cd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910172897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.910172897
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1096524257
Short name T339
Test name
Test status
Simulation time 459481217 ps
CPU time 0.63 seconds
Started Dec 24 12:21:20 PM PST 23
Finished Dec 24 12:21:21 PM PST 23
Peak memory 183400 kb
Host smart-02a6e34f-ea0c-4bb2-9da5-7aa8e7b01b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096524257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1096524257
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1810332557
Short name T327
Test name
Test status
Simulation time 1019921963 ps
CPU time 1.07 seconds
Started Dec 24 12:25:11 PM PST 23
Finished Dec 24 12:25:13 PM PST 23
Peak memory 192308 kb
Host smart-1f1eb9bf-50f8-4991-9e09-413d8ef15a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810332557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1810332557
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4049929908
Short name T27
Test name
Test status
Simulation time 718825211 ps
CPU time 1.66 seconds
Started Dec 24 12:26:14 PM PST 23
Finished Dec 24 12:26:18 PM PST 23
Peak memory 198128 kb
Host smart-03ce7d9c-0309-49de-a2b3-7169bbf64d97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049929908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4049929908
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2143362868
Short name T315
Test name
Test status
Simulation time 7995024778 ps
CPU time 12.8 seconds
Started Dec 24 12:20:25 PM PST 23
Finished Dec 24 12:20:38 PM PST 23
Peak memory 197608 kb
Host smart-b01b41c6-9390-46dc-a0cb-4039685ec6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143362868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2143362868
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1100363055
Short name T3
Test name
Test status
Simulation time 343743267 ps
CPU time 1.08 seconds
Started Dec 24 12:24:37 PM PST 23
Finished Dec 24 12:24:40 PM PST 23
Peak memory 190668 kb
Host smart-c1dce2a7-341e-419c-95ca-603ba95171f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100363055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1100363055
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1876773306
Short name T417
Test name
Test status
Simulation time 6094433220 ps
CPU time 7.61 seconds
Started Dec 24 12:24:08 PM PST 23
Finished Dec 24 12:24:16 PM PST 23
Peak memory 192560 kb
Host smart-c3aff257-d8a3-4be5-aa45-3d25e0884ee9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876773306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1876773306
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4176722985
Short name T17
Test name
Test status
Simulation time 1231506189 ps
CPU time 1.63 seconds
Started Dec 24 12:24:37 PM PST 23
Finished Dec 24 12:24:40 PM PST 23
Peak memory 181628 kb
Host smart-94dc442c-3562-479a-9c06-bfe5daab0975
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176722985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4176722985
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1004317646
Short name T351
Test name
Test status
Simulation time 355989107 ps
CPU time 0.9 seconds
Started Dec 24 12:22:49 PM PST 23
Finished Dec 24 12:22:51 PM PST 23
Peak memory 195204 kb
Host smart-17fef40f-c938-432f-8974-89023b70ec05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004317646 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1004317646
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2371194400
Short name T12
Test name
Test status
Simulation time 375905178 ps
CPU time 0.71 seconds
Started Dec 24 12:21:22 PM PST 23
Finished Dec 24 12:21:23 PM PST 23
Peak memory 192900 kb
Host smart-f79c2175-44fa-497e-80c1-e286169faf2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371194400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2371194400
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1134241740
Short name T333
Test name
Test status
Simulation time 438875609 ps
CPU time 1.18 seconds
Started Dec 24 12:26:55 PM PST 23
Finished Dec 24 12:26:59 PM PST 23
Peak memory 182396 kb
Host smart-cbc2520d-6ea8-4a99-abba-2e8c5c1fafda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134241740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1134241740
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.105782679
Short name T338
Test name
Test status
Simulation time 464238409 ps
CPU time 1.23 seconds
Started Dec 24 12:20:51 PM PST 23
Finished Dec 24 12:20:53 PM PST 23
Peak memory 183668 kb
Host smart-a6f82fa4-86d4-4a5e-8d46-7d2e39d0e258
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105782679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.105782679
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.65410399
Short name T347
Test name
Test status
Simulation time 499179790 ps
CPU time 0.6 seconds
Started Dec 24 12:28:46 PM PST 23
Finished Dec 24 12:28:55 PM PST 23
Peak memory 182516 kb
Host smart-a4d7a23d-6130-4822-9ba8-84522082e7f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65410399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wal
k.65410399
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3361140680
Short name T349
Test name
Test status
Simulation time 2648246787 ps
CPU time 4.31 seconds
Started Dec 24 12:22:18 PM PST 23
Finished Dec 24 12:22:26 PM PST 23
Peak memory 195456 kb
Host smart-c7d1511c-f960-4914-8c86-9ea646616ece
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361140680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3361140680
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3206939553
Short name T424
Test name
Test status
Simulation time 427325983 ps
CPU time 1.8 seconds
Started Dec 24 12:21:36 PM PST 23
Finished Dec 24 12:21:39 PM PST 23
Peak memory 198444 kb
Host smart-b4ac8bd3-8118-4c78-8aa3-1a1246ee33f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206939553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3206939553
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3994791088
Short name T405
Test name
Test status
Simulation time 8769539510 ps
CPU time 15.39 seconds
Started Dec 24 12:24:37 PM PST 23
Finished Dec 24 12:24:54 PM PST 23
Peak memory 195972 kb
Host smart-4f01375f-2a63-4d07-8733-2ae5922a93f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994791088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3994791088
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3016790520
Short name T420
Test name
Test status
Simulation time 349882573 ps
CPU time 1.04 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 183344 kb
Host smart-9c779889-04a4-4384-8c04-c64ac6a1a1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016790520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3016790520
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3732689125
Short name T407
Test name
Test status
Simulation time 340868792 ps
CPU time 0.84 seconds
Started Dec 24 12:25:37 PM PST 23
Finished Dec 24 12:25:40 PM PST 23
Peak memory 183624 kb
Host smart-defdfb50-9cdd-416d-9ce3-cac1b6f62b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732689125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3732689125
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4256794214
Short name T374
Test name
Test status
Simulation time 384054887 ps
CPU time 0.6 seconds
Started Dec 24 12:20:31 PM PST 23
Finished Dec 24 12:20:32 PM PST 23
Peak memory 183396 kb
Host smart-92672c20-e37d-4b77-bf20-7f6ea1660e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256794214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4256794214
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.748745142
Short name T309
Test name
Test status
Simulation time 507267835 ps
CPU time 1.3 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:17 PM PST 23
Peak memory 180984 kb
Host smart-aada0d07-dd1b-4ae7-a6d3-73ff74a59966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748745142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.748745142
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3162254776
Short name T383
Test name
Test status
Simulation time 502443103 ps
CPU time 1.03 seconds
Started Dec 24 12:21:02 PM PST 23
Finished Dec 24 12:21:04 PM PST 23
Peak memory 183440 kb
Host smart-61c2d975-7154-4718-86ad-8464c6006797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162254776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3162254776
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3108776446
Short name T402
Test name
Test status
Simulation time 387835020 ps
CPU time 1.24 seconds
Started Dec 24 12:27:19 PM PST 23
Finished Dec 24 12:27:24 PM PST 23
Peak memory 182052 kb
Host smart-020ba5eb-7e8b-44c5-8702-06e7d8086d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108776446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3108776446
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.947067910
Short name T384
Test name
Test status
Simulation time 334704225 ps
CPU time 0.62 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:41 PM PST 23
Peak memory 182244 kb
Host smart-80bb8bc6-af8b-4b2f-8a3f-610b3bbf096f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947067910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.947067910
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2299128053
Short name T377
Test name
Test status
Simulation time 386704279 ps
CPU time 1.07 seconds
Started Dec 24 12:25:39 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 183148 kb
Host smart-77f0fa14-9eef-44f5-9aa9-e73c1b48a8de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299128053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2299128053
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3153466801
Short name T365
Test name
Test status
Simulation time 316383113 ps
CPU time 0.82 seconds
Started Dec 24 12:26:13 PM PST 23
Finished Dec 24 12:26:16 PM PST 23
Peak memory 181720 kb
Host smart-d75ae1de-af77-4c29-85ee-d7b8274ee490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153466801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3153466801
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.100833082
Short name T378
Test name
Test status
Simulation time 373246776 ps
CPU time 0.73 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:41 PM PST 23
Peak memory 182124 kb
Host smart-a7d79199-dbf1-4981-a3ee-529da58519cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100833082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.100833082
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2995515354
Short name T359
Test name
Test status
Simulation time 477558593 ps
CPU time 1.51 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 183620 kb
Host smart-65decafa-4c36-46d1-86bb-1d2cfe759ec5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995515354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2995515354
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1469364591
Short name T373
Test name
Test status
Simulation time 11387218982 ps
CPU time 9.69 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:29:07 PM PST 23
Peak memory 191836 kb
Host smart-9455882a-b741-4f4b-80ac-91a7c161076a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469364591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1469364591
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.745472588
Short name T372
Test name
Test status
Simulation time 683338709 ps
CPU time 1.25 seconds
Started Dec 24 12:28:48 PM PST 23
Finished Dec 24 12:28:58 PM PST 23
Peak memory 183416 kb
Host smart-395597d1-2616-4c59-8cfb-9959f360ec07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745472588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.745472588
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2255366754
Short name T330
Test name
Test status
Simulation time 358493402 ps
CPU time 0.75 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:50 PM PST 23
Peak memory 194944 kb
Host smart-b982b164-68f7-4d0a-a03b-2a3358821f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255366754 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2255366754
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.113127371
Short name T60
Test name
Test status
Simulation time 504257324 ps
CPU time 1.22 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:30 PM PST 23
Peak memory 183676 kb
Host smart-72f528f0-85ac-4700-9cfa-6360166783fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113127371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.113127371
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3918971045
Short name T354
Test name
Test status
Simulation time 384624428 ps
CPU time 1.04 seconds
Started Dec 24 12:30:04 PM PST 23
Finished Dec 24 12:30:31 PM PST 23
Peak memory 183548 kb
Host smart-84c61691-7a63-4222-a0f9-e870681ff2ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918971045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3918971045
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2224641198
Short name T44
Test name
Test status
Simulation time 425046731 ps
CPU time 0.78 seconds
Started Dec 24 12:27:04 PM PST 23
Finished Dec 24 12:27:10 PM PST 23
Peak memory 183272 kb
Host smart-e6ecbf75-ca8d-4c44-bb7d-486e3f18b235
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224641198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2224641198
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4205586560
Short name T341
Test name
Test status
Simulation time 478363540 ps
CPU time 0.72 seconds
Started Dec 24 12:20:06 PM PST 23
Finished Dec 24 12:20:08 PM PST 23
Peak memory 183264 kb
Host smart-f20b4daa-5fd5-466d-a3df-a7c557200d6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205586560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4205586560
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3803831322
Short name T387
Test name
Test status
Simulation time 905141210 ps
CPU time 1.07 seconds
Started Dec 24 12:19:50 PM PST 23
Finished Dec 24 12:19:53 PM PST 23
Peak memory 192608 kb
Host smart-eaecf80c-06a4-4eb5-bb54-06aefeb0ee28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803831322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3803831322
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4020714907
Short name T47
Test name
Test status
Simulation time 581145521 ps
CPU time 1.92 seconds
Started Dec 24 12:23:00 PM PST 23
Finished Dec 24 12:23:03 PM PST 23
Peak memory 198380 kb
Host smart-fcfaa462-5d7d-4b88-ade6-e43be130b6e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020714907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4020714907
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.857187468
Short name T400
Test name
Test status
Simulation time 4381119844 ps
CPU time 3.82 seconds
Started Dec 24 12:26:54 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 194360 kb
Host smart-3aa62ba2-015d-455c-ae0d-fa9ec7f599b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857187468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.857187468
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1256834355
Short name T342
Test name
Test status
Simulation time 301449658 ps
CPU time 0.73 seconds
Started Dec 24 12:20:22 PM PST 23
Finished Dec 24 12:20:24 PM PST 23
Peak memory 183004 kb
Host smart-574bea7d-4c3c-4eac-bdde-2fe73663e3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256834355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1256834355
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.219465212
Short name T367
Test name
Test status
Simulation time 282672170 ps
CPU time 0.72 seconds
Started Dec 24 12:26:30 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 183352 kb
Host smart-cd366655-5401-4e20-9271-9f827dc033ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219465212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.219465212
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1023979625
Short name T123
Test name
Test status
Simulation time 443248204 ps
CPU time 0.86 seconds
Started Dec 24 12:26:31 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 183432 kb
Host smart-e0470ecf-b035-438d-913e-6f623be13222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023979625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1023979625
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3180887645
Short name T388
Test name
Test status
Simulation time 379460743 ps
CPU time 0.73 seconds
Started Dec 24 12:22:41 PM PST 23
Finished Dec 24 12:22:43 PM PST 23
Peak memory 183444 kb
Host smart-82bd88d4-80c3-41eb-8970-3b0d4d591ebb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180887645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3180887645
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.726912616
Short name T396
Test name
Test status
Simulation time 531542811 ps
CPU time 0.71 seconds
Started Dec 24 12:21:55 PM PST 23
Finished Dec 24 12:21:57 PM PST 23
Peak memory 183404 kb
Host smart-569deda3-abe2-41c3-800e-6d079e29bf9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726912616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.726912616
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.976997944
Short name T356
Test name
Test status
Simulation time 423413311 ps
CPU time 0.71 seconds
Started Dec 24 12:20:24 PM PST 23
Finished Dec 24 12:20:25 PM PST 23
Peak memory 183856 kb
Host smart-2b0e723b-95e1-45cd-b565-cd19c1a9eef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976997944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.976997944
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1883675797
Short name T25
Test name
Test status
Simulation time 448674486 ps
CPU time 0.72 seconds
Started Dec 24 12:25:23 PM PST 23
Finished Dec 24 12:25:24 PM PST 23
Peak memory 183312 kb
Host smart-445d05c8-1398-4aaf-a8fa-505a0d6b0038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883675797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1883675797
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.86047976
Short name T31
Test name
Test status
Simulation time 420969962 ps
CPU time 1.19 seconds
Started Dec 24 12:21:39 PM PST 23
Finished Dec 24 12:21:41 PM PST 23
Peak memory 183396 kb
Host smart-766b1e5a-3eb3-448d-af3d-f3239e050437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86047976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.86047976
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3519886966
Short name T412
Test name
Test status
Simulation time 361896349 ps
CPU time 1.16 seconds
Started Dec 24 12:21:27 PM PST 23
Finished Dec 24 12:21:28 PM PST 23
Peak memory 183412 kb
Host smart-e5587f66-26ba-4267-b128-7b5180a1588b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519886966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3519886966
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1287641203
Short name T363
Test name
Test status
Simulation time 327034649 ps
CPU time 1.04 seconds
Started Dec 24 12:20:23 PM PST 23
Finished Dec 24 12:20:25 PM PST 23
Peak memory 184100 kb
Host smart-63dbd805-3741-4102-ad5b-b6995b889d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287641203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1287641203
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2934645620
Short name T1
Test name
Test status
Simulation time 359430663 ps
CPU time 0.85 seconds
Started Dec 24 12:26:47 PM PST 23
Finished Dec 24 12:26:50 PM PST 23
Peak memory 183612 kb
Host smart-7ce93fb0-635b-4921-9e57-616284647047
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934645620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2934645620
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1052649945
Short name T121
Test name
Test status
Simulation time 6262646521 ps
CPU time 10.89 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:27:02 PM PST 23
Peak memory 192056 kb
Host smart-372af38d-f748-4fb1-b119-45b0af8aef34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052649945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1052649945
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.826901255
Short name T7
Test name
Test status
Simulation time 1214905150 ps
CPU time 2.17 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:27 PM PST 23
Peak memory 181984 kb
Host smart-03917b2c-4889-4b54-9891-c8f4ef52ab45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826901255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.826901255
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2700794546
Short name T370
Test name
Test status
Simulation time 582473829 ps
CPU time 1.15 seconds
Started Dec 24 12:24:27 PM PST 23
Finished Dec 24 12:24:33 PM PST 23
Peak memory 197172 kb
Host smart-d3eabe3c-53e8-45df-97f3-4c4214534c76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700794546 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2700794546
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2857291262
Short name T332
Test name
Test status
Simulation time 391977353 ps
CPU time 1.36 seconds
Started Dec 24 12:26:16 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 181848 kb
Host smart-fde967e5-b2b7-4512-a124-bb7c6bbcad58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857291262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2857291262
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1210261559
Short name T358
Test name
Test status
Simulation time 331789707 ps
CPU time 1.12 seconds
Started Dec 24 12:26:28 PM PST 23
Finished Dec 24 12:26:31 PM PST 23
Peak memory 182408 kb
Host smart-003902bb-706f-40c6-9cd0-747da65f4619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210261559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1210261559
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2776544825
Short name T416
Test name
Test status
Simulation time 297310957 ps
CPU time 0.97 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:52 PM PST 23
Peak memory 183616 kb
Host smart-47e8af25-13c9-4103-ace1-bd616e2337d9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776544825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2776544825
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3212539878
Short name T408
Test name
Test status
Simulation time 399632467 ps
CPU time 1.17 seconds
Started Dec 24 12:26:22 PM PST 23
Finished Dec 24 12:26:26 PM PST 23
Peak memory 181588 kb
Host smart-3b2afad8-73b7-4f87-a8bf-055e367c0f00
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212539878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3212539878
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2018726551
Short name T337
Test name
Test status
Simulation time 1585669343 ps
CPU time 1.35 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:53 PM PST 23
Peak memory 191820 kb
Host smart-cd88228f-22b2-4925-9ba8-4c059df2095b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018726551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2018726551
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2230891967
Short name T336
Test name
Test status
Simulation time 524971473 ps
CPU time 1.8 seconds
Started Dec 24 12:22:07 PM PST 23
Finished Dec 24 12:22:13 PM PST 23
Peak memory 198520 kb
Host smart-cd211941-005b-43a0-aaae-2ecaa4077acd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230891967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2230891967
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3471603965
Short name T310
Test name
Test status
Simulation time 8746232125 ps
CPU time 4.04 seconds
Started Dec 24 12:23:46 PM PST 23
Finished Dec 24 12:23:51 PM PST 23
Peak memory 197472 kb
Host smart-ac5b4a52-7e4a-4f6e-ba7d-01f478a84df5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471603965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3471603965
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2665515979
Short name T376
Test name
Test status
Simulation time 414898035 ps
CPU time 1.22 seconds
Started Dec 24 12:25:21 PM PST 23
Finished Dec 24 12:25:23 PM PST 23
Peak memory 183420 kb
Host smart-3e7b3a8d-3ca5-4163-a902-a7336b83e5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665515979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2665515979
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2182025814
Short name T43
Test name
Test status
Simulation time 547284265 ps
CPU time 0.67 seconds
Started Dec 24 12:26:31 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 183416 kb
Host smart-6d60e3fe-e8ab-4129-99cd-577d733d99e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182025814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2182025814
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.507815154
Short name T321
Test name
Test status
Simulation time 463363206 ps
CPU time 1.23 seconds
Started Dec 24 12:20:24 PM PST 23
Finished Dec 24 12:20:26 PM PST 23
Peak memory 184096 kb
Host smart-181a4236-e354-4519-aa4f-e5f87538bef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507815154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.507815154
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2998901336
Short name T15
Test name
Test status
Simulation time 512157826 ps
CPU time 1.22 seconds
Started Dec 24 12:26:31 PM PST 23
Finished Dec 24 12:26:33 PM PST 23
Peak memory 183416 kb
Host smart-101d9ff8-8763-4f11-9853-1c310c5f67e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998901336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2998901336
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.29967470
Short name T312
Test name
Test status
Simulation time 325855960 ps
CPU time 0.99 seconds
Started Dec 24 12:21:55 PM PST 23
Finished Dec 24 12:21:57 PM PST 23
Peak memory 183644 kb
Host smart-b0834615-d7ab-4515-85a0-1dcc4389d8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29967470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.29967470
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2865781564
Short name T389
Test name
Test status
Simulation time 448963702 ps
CPU time 0.76 seconds
Started Dec 24 12:21:39 PM PST 23
Finished Dec 24 12:21:40 PM PST 23
Peak memory 183396 kb
Host smart-5a83d34e-70c9-4ceb-b93c-78853bc7cd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865781564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2865781564
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1670826342
Short name T319
Test name
Test status
Simulation time 489255642 ps
CPU time 0.87 seconds
Started Dec 24 12:26:18 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 183032 kb
Host smart-0d103b3b-e7f5-46f1-93e7-30bc359a35cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670826342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1670826342
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2603298130
Short name T426
Test name
Test status
Simulation time 440737282 ps
CPU time 0.72 seconds
Started Dec 24 12:20:26 PM PST 23
Finished Dec 24 12:20:28 PM PST 23
Peak memory 183412 kb
Host smart-d998ed9f-875f-4aee-a61c-222ab4df9d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603298130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2603298130
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2391949067
Short name T303
Test name
Test status
Simulation time 497417216 ps
CPU time 1.37 seconds
Started Dec 24 12:21:22 PM PST 23
Finished Dec 24 12:21:24 PM PST 23
Peak memory 183444 kb
Host smart-3e8771c9-310a-42a9-a65f-79b6cedbcff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391949067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2391949067
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1100088230
Short name T28
Test name
Test status
Simulation time 352164718 ps
CPU time 0.81 seconds
Started Dec 24 12:25:38 PM PST 23
Finished Dec 24 12:25:42 PM PST 23
Peak memory 183148 kb
Host smart-5c88a319-ce55-4f61-bcb2-46a9e351a4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100088230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1100088230
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3799715114
Short name T29
Test name
Test status
Simulation time 532733030 ps
CPU time 1.42 seconds
Started Dec 24 12:20:25 PM PST 23
Finished Dec 24 12:20:27 PM PST 23
Peak memory 195568 kb
Host smart-aa320958-d30d-4012-80b6-09e503337b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799715114 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3799715114
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2609615009
Short name T54
Test name
Test status
Simulation time 448307929 ps
CPU time 0.86 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 12:28:47 PM PST 23
Peak memory 183248 kb
Host smart-036d6c0f-e6d3-47e5-a7e2-2a419a7ffb33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609615009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2609615009
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3937067132
Short name T395
Test name
Test status
Simulation time 374779010 ps
CPU time 0.67 seconds
Started Dec 24 12:20:01 PM PST 23
Finished Dec 24 12:20:04 PM PST 23
Peak memory 183404 kb
Host smart-f5fe267f-0bfc-43ee-8730-caf536438e51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937067132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3937067132
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.72590837
Short name T5
Test name
Test status
Simulation time 2100268900 ps
CPU time 3.6 seconds
Started Dec 24 12:22:54 PM PST 23
Finished Dec 24 12:22:58 PM PST 23
Peak memory 191840 kb
Host smart-9b75549d-e5ef-42c2-a0f1-85b66f4a25f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72590837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_t
imer_same_csr_outstanding.72590837
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.760021171
Short name T9
Test name
Test status
Simulation time 592556605 ps
CPU time 2.46 seconds
Started Dec 24 12:26:49 PM PST 23
Finished Dec 24 12:26:54 PM PST 23
Peak memory 198500 kb
Host smart-68114135-7f4a-48e8-9096-7bdf02b7084a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760021171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.760021171
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2635099586
Short name T306
Test name
Test status
Simulation time 4443726872 ps
CPU time 3.44 seconds
Started Dec 24 12:23:46 PM PST 23
Finished Dec 24 12:23:50 PM PST 23
Peak memory 196028 kb
Host smart-cdf64381-a69b-47dc-8a9e-c7281b33c202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635099586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2635099586
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1052815841
Short name T375
Test name
Test status
Simulation time 444139268 ps
CPU time 0.78 seconds
Started Dec 24 12:21:18 PM PST 23
Finished Dec 24 12:21:20 PM PST 23
Peak memory 195256 kb
Host smart-69cec6d5-eb63-4959-b5bd-2526f97c8ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052815841 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1052815841
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1873191607
Short name T59
Test name
Test status
Simulation time 427360099 ps
CPU time 1.13 seconds
Started Dec 24 12:24:06 PM PST 23
Finished Dec 24 12:24:07 PM PST 23
Peak memory 183632 kb
Host smart-9860f776-d2da-4cc3-98e6-6addbe3fa2cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873191607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1873191607
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1215754709
Short name T307
Test name
Test status
Simulation time 325205597 ps
CPU time 1.1 seconds
Started Dec 24 12:21:20 PM PST 23
Finished Dec 24 12:21:21 PM PST 23
Peak memory 183400 kb
Host smart-53e316ef-136e-44e2-96e3-1baf297eaea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215754709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1215754709
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1014284670
Short name T419
Test name
Test status
Simulation time 1843044467 ps
CPU time 3.12 seconds
Started Dec 24 12:23:16 PM PST 23
Finished Dec 24 12:23:20 PM PST 23
Peak memory 194332 kb
Host smart-e92e6644-5a00-466a-b315-a8a5d1de1903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014284670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1014284670
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.765112093
Short name T361
Test name
Test status
Simulation time 443865495 ps
CPU time 2.15 seconds
Started Dec 24 12:24:00 PM PST 23
Finished Dec 24 12:24:03 PM PST 23
Peak memory 198512 kb
Host smart-250cf79d-4c8c-422a-a8d5-c6e26cf87cac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765112093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.765112093
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1380390834
Short name T392
Test name
Test status
Simulation time 4592813098 ps
CPU time 4.31 seconds
Started Dec 24 12:23:57 PM PST 23
Finished Dec 24 12:24:02 PM PST 23
Peak memory 195908 kb
Host smart-573d205a-7c49-4270-8be3-5454c43c574e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380390834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1380390834
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.683191681
Short name T401
Test name
Test status
Simulation time 382247140 ps
CPU time 1.23 seconds
Started Dec 24 12:24:05 PM PST 23
Finished Dec 24 12:24:07 PM PST 23
Peak memory 194528 kb
Host smart-8232f489-7273-4831-b809-e11bf6c87c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683191681 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.683191681
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3051468852
Short name T55
Test name
Test status
Simulation time 351912951 ps
CPU time 1.11 seconds
Started Dec 24 12:28:40 PM PST 23
Finished Dec 24 12:28:48 PM PST 23
Peak memory 183348 kb
Host smart-b72ff294-f22a-46b1-a80f-973036adbf16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051468852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3051468852
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2877873053
Short name T308
Test name
Test status
Simulation time 434298162 ps
CPU time 1.15 seconds
Started Dec 24 12:23:57 PM PST 23
Finished Dec 24 12:23:59 PM PST 23
Peak memory 183432 kb
Host smart-d27b215e-a953-4f90-8faf-976fb6981f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877873053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2877873053
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2127608098
Short name T65
Test name
Test status
Simulation time 1974711545 ps
CPU time 2.19 seconds
Started Dec 24 12:26:16 PM PST 23
Finished Dec 24 12:26:22 PM PST 23
Peak memory 190324 kb
Host smart-685cf1c7-9be3-487e-9b54-140dd1724066
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127608098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2127608098
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.639696166
Short name T316
Test name
Test status
Simulation time 462441160 ps
CPU time 2.44 seconds
Started Dec 24 12:28:41 PM PST 23
Finished Dec 24 12:28:57 PM PST 23
Peak memory 198256 kb
Host smart-03bf897e-7707-49b2-a28d-cbd821b1ac63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639696166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.639696166
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.34863799
Short name T409
Test name
Test status
Simulation time 8387575166 ps
CPU time 13.49 seconds
Started Dec 24 12:26:52 PM PST 23
Finished Dec 24 12:27:08 PM PST 23
Peak memory 197512 kb
Host smart-7757c8b5-6eac-4e46-9b41-fe08d427cd83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34863799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_i
ntg_err.34863799
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3350598053
Short name T404
Test name
Test status
Simulation time 519279526 ps
CPU time 1.52 seconds
Started Dec 24 12:26:58 PM PST 23
Finished Dec 24 12:27:03 PM PST 23
Peak memory 195616 kb
Host smart-f1be951b-c303-4ac5-bd8f-4d4db1cf6879
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350598053 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3350598053
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2072135034
Short name T56
Test name
Test status
Simulation time 295364004 ps
CPU time 0.95 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:36 PM PST 23
Peak memory 183632 kb
Host smart-bccd8d11-77c1-4d7d-a92f-64a3817766d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072135034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2072135034
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1327263249
Short name T124
Test name
Test status
Simulation time 325998833 ps
CPU time 1.39 seconds
Started Dec 24 12:26:16 PM PST 23
Finished Dec 24 12:26:21 PM PST 23
Peak memory 181888 kb
Host smart-c2ee97d2-137d-4d61-b7d8-f7eb2a0891f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327263249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1327263249
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2518813386
Short name T385
Test name
Test status
Simulation time 1113244579 ps
CPU time 1.27 seconds
Started Dec 24 12:24:22 PM PST 23
Finished Dec 24 12:24:32 PM PST 23
Peak memory 193508 kb
Host smart-6725901e-1013-434a-8631-98be2df581a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518813386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2518813386
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3892300368
Short name T311
Test name
Test status
Simulation time 504044694 ps
CPU time 2.83 seconds
Started Dec 24 12:23:16 PM PST 23
Finished Dec 24 12:23:19 PM PST 23
Peak memory 198676 kb
Host smart-4f811dc3-2e23-4ad2-967b-8d058d2df35c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892300368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3892300368
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3925957167
Short name T340
Test name
Test status
Simulation time 593798792 ps
CPU time 0.79 seconds
Started Dec 24 12:26:36 PM PST 23
Finished Dec 24 12:26:39 PM PST 23
Peak memory 196224 kb
Host smart-946ea748-306c-4819-9dc7-315f86441333
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925957167 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3925957167
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2794341612
Short name T10
Test name
Test status
Simulation time 546928445 ps
CPU time 0.75 seconds
Started Dec 24 12:22:23 PM PST 23
Finished Dec 24 12:22:25 PM PST 23
Peak memory 183592 kb
Host smart-a5c19d56-9803-42e5-96b9-738e9581a125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794341612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2794341612
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1932741607
Short name T362
Test name
Test status
Simulation time 414969211 ps
CPU time 1.3 seconds
Started Dec 24 12:21:02 PM PST 23
Finished Dec 24 12:21:04 PM PST 23
Peak memory 183444 kb
Host smart-71b8773c-b4ce-467f-86ca-d1d346121f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932741607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1932741607
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1051227756
Short name T329
Test name
Test status
Simulation time 1441221956 ps
CPU time 1.53 seconds
Started Dec 24 12:26:34 PM PST 23
Finished Dec 24 12:26:37 PM PST 23
Peak memory 191268 kb
Host smart-d4f8455b-f9eb-420b-8e97-56c3db5a4c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051227756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1051227756
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3597272909
Short name T328
Test name
Test status
Simulation time 639303589 ps
CPU time 1.94 seconds
Started Dec 24 12:21:43 PM PST 23
Finished Dec 24 12:21:45 PM PST 23
Peak memory 198672 kb
Host smart-2496c7cd-b5f0-45f7-b1f1-2b7af5350cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597272909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3597272909
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.20368783
Short name T2
Test name
Test status
Simulation time 8356608441 ps
CPU time 13.24 seconds
Started Dec 24 12:20:15 PM PST 23
Finished Dec 24 12:20:30 PM PST 23
Peak memory 197480 kb
Host smart-4b8f7e36-338d-416d-8312-6aabf027745e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20368783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_i
ntg_err.20368783
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.286436972
Short name T112
Test name
Test status
Simulation time 528994859 ps
CPU time 0.67 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182800 kb
Host smart-0e8ffe2f-67c5-4b58-a4b8-8bece95b722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286436972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.286436972
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2876651301
Short name T130
Test name
Test status
Simulation time 14130461821 ps
CPU time 25.74 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 182740 kb
Host smart-6d6fbb7c-76e8-4f89-8b2d-a4e622aafd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876651301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2876651301
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.193385090
Short name T149
Test name
Test status
Simulation time 389332167 ps
CPU time 0.85 seconds
Started Dec 24 01:09:29 PM PST 23
Finished Dec 24 01:09:32 PM PST 23
Peak memory 182672 kb
Host smart-6c90522e-d1ec-4478-97c0-f67913fd1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193385090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.193385090
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1028901581
Short name T159
Test name
Test status
Simulation time 583081802 ps
CPU time 0.78 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182792 kb
Host smart-7b322e28-3deb-4538-9526-6f471a24c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028901581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1028901581
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1221744119
Short name T235
Test name
Test status
Simulation time 26642325130 ps
CPU time 18.83 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:10:02 PM PST 23
Peak memory 182808 kb
Host smart-307d2d84-bcbc-4244-94e7-dfbbb9615bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221744119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1221744119
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3739748410
Short name T38
Test name
Test status
Simulation time 4407768822 ps
CPU time 7.83 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 214980 kb
Host smart-be927aaf-c52e-4fcc-90f7-aef19e2df9b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739748410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3739748410
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3630802832
Short name T34
Test name
Test status
Simulation time 407380839 ps
CPU time 0.67 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 182772 kb
Host smart-6671a7ae-01b2-47ff-9553-b0fc9573434f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630802832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3630802832
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1051643037
Short name T275
Test name
Test status
Simulation time 128446774666 ps
CPU time 123.13 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:11:51 PM PST 23
Peak memory 197612 kb
Host smart-87541763-0e12-4fdb-8c92-8656d90774d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051643037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1051643037
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2132574359
Short name T194
Test name
Test status
Simulation time 518445822 ps
CPU time 1.26 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182748 kb
Host smart-e511db44-2550-4e09-b132-5dab0a5ff8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132574359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2132574359
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2937272399
Short name T19
Test name
Test status
Simulation time 17948471817 ps
CPU time 4.14 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 182744 kb
Host smart-57bf8388-983f-4198-a420-11f3f3e85ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937272399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2937272399
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.468377648
Short name T137
Test name
Test status
Simulation time 385198889 ps
CPU time 1.08 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182672 kb
Host smart-cbb977a0-df08-4a9e-8df6-eeaba6ba8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468377648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.468377648
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2897250090
Short name T200
Test name
Test status
Simulation time 65928994564 ps
CPU time 25.56 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:10:13 PM PST 23
Peak memory 182836 kb
Host smart-326f8dda-e260-4d9f-bd63-2e144a21fa57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897250090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2897250090
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.202113069
Short name T216
Test name
Test status
Simulation time 56465717051 ps
CPU time 449.64 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:17:17 PM PST 23
Peak memory 197732 kb
Host smart-e3c791bb-c6cd-4185-82e8-ca71e3fc7f6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202113069 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.202113069
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4268979203
Short name T103
Test name
Test status
Simulation time 543779281 ps
CPU time 1.39 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182780 kb
Host smart-a23fd746-6893-45f8-88a4-1c7e2baa4b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268979203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4268979203
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2719619474
Short name T204
Test name
Test status
Simulation time 4067605482 ps
CPU time 6.73 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 182744 kb
Host smart-f2e4b8a6-48eb-47be-8b53-53bcb2425d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719619474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2719619474
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4252884841
Short name T157
Test name
Test status
Simulation time 557060587 ps
CPU time 0.64 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 182640 kb
Host smart-5c816454-5e12-4a9c-8d66-2ee9c85f89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252884841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4252884841
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.821837604
Short name T293
Test name
Test status
Simulation time 39913796874 ps
CPU time 106.66 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:11:35 PM PST 23
Peak memory 197692 kb
Host smart-984a9a3c-440d-4e1b-bdeb-ffe2a7357eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821837604 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.821837604
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.215318
Short name T191
Test name
Test status
Simulation time 670645866 ps
CPU time 0.62 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 182772 kb
Host smart-3da71310-78aa-46a1-8f43-0f5a01e65e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.215318
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2208557028
Short name T249
Test name
Test status
Simulation time 26127503102 ps
CPU time 36.89 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 182812 kb
Host smart-c1d6c173-5bb6-4d9b-bd74-463d080d9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208557028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2208557028
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3903881620
Short name T197
Test name
Test status
Simulation time 459399078 ps
CPU time 0.62 seconds
Started Dec 24 01:09:53 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182672 kb
Host smart-cd85b573-f56a-42f2-99d5-534b429bb0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903881620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3903881620
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4243178372
Short name T256
Test name
Test status
Simulation time 273472046092 ps
CPU time 230.7 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:13:44 PM PST 23
Peak memory 193820 kb
Host smart-80d205b1-34fe-489c-98e2-3d769fba6a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243178372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4243178372
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1287304973
Short name T282
Test name
Test status
Simulation time 610005304439 ps
CPU time 621.85 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:20:08 PM PST 23
Peak memory 198636 kb
Host smart-420ba78c-f77b-47b2-8277-945ff927daf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287304973 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1287304973
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2560372232
Short name T175
Test name
Test status
Simulation time 555229991 ps
CPU time 0.96 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182780 kb
Host smart-62c796c2-6754-42ab-9788-9e17e19f4d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560372232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2560372232
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1069694375
Short name T183
Test name
Test status
Simulation time 49537777494 ps
CPU time 71.62 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 182748 kb
Host smart-021c1b97-3545-478f-b612-5c98bedddcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069694375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1069694375
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3131907860
Short name T296
Test name
Test status
Simulation time 387089576 ps
CPU time 0.72 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182780 kb
Host smart-22b4d51e-6226-4bf2-9fad-5ee0127219e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131907860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3131907860
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2376086502
Short name T171
Test name
Test status
Simulation time 141768634461 ps
CPU time 57.32 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:10:38 PM PST 23
Peak memory 182716 kb
Host smart-caf49483-9731-4579-a9f4-ff13f2726d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376086502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2376086502
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1322688191
Short name T73
Test name
Test status
Simulation time 33322665677 ps
CPU time 131.61 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:11:53 PM PST 23
Peak memory 197692 kb
Host smart-978035bb-82cf-4637-9a4d-d4a5d2e66808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322688191 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1322688191
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1600673144
Short name T207
Test name
Test status
Simulation time 496900588 ps
CPU time 1.21 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 182768 kb
Host smart-873fef75-1184-4acd-9ae6-fa4da6ac6509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600673144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1600673144
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1371656569
Short name T143
Test name
Test status
Simulation time 39772853780 ps
CPU time 66.06 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 182824 kb
Host smart-a5d399e7-17f6-42e0-a413-173bf3d99bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371656569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1371656569
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.769865684
Short name T192
Test name
Test status
Simulation time 544295381 ps
CPU time 1.43 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 182660 kb
Host smart-f41e1cdf-ac0d-4f7d-9283-dd9548072b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769865684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.769865684
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2967711365
Short name T109
Test name
Test status
Simulation time 175488271464 ps
CPU time 77.64 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 182784 kb
Host smart-3c131c25-87a9-444f-9c90-ed6a71fc1b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967711365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2967711365
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3575226666
Short name T302
Test name
Test status
Simulation time 36861962733 ps
CPU time 137.2 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:12:00 PM PST 23
Peak memory 197664 kb
Host smart-df04077c-ae8f-47c9-a517-c211b89f7d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575226666 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3575226666
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2086868309
Short name T264
Test name
Test status
Simulation time 401042080 ps
CPU time 0.71 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 182728 kb
Host smart-0cc4efc4-8a38-47de-a8a3-86e2e633e644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086868309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2086868309
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2601250381
Short name T22
Test name
Test status
Simulation time 1881927712 ps
CPU time 3.49 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 182712 kb
Host smart-fe67895d-c91a-4cd5-b8f7-3e7d7cc5d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601250381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2601250381
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2359873736
Short name T155
Test name
Test status
Simulation time 521394619 ps
CPU time 0.58 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:43 PM PST 23
Peak memory 182632 kb
Host smart-51d33231-f63f-411b-89bd-7d1580394049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359873736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2359873736
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.795483671
Short name T100
Test name
Test status
Simulation time 177941745947 ps
CPU time 144.65 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:12:14 PM PST 23
Peak memory 182780 kb
Host smart-c963aa57-7217-4e12-89ec-384ca986282f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795483671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.795483671
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3694235735
Short name T107
Test name
Test status
Simulation time 17756522426 ps
CPU time 193.38 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:12:58 PM PST 23
Peak memory 197628 kb
Host smart-e8d877f1-c1c2-400b-8e21-0671d95932c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694235735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3694235735
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.940558197
Short name T111
Test name
Test status
Simulation time 411754073 ps
CPU time 0.72 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:09:46 PM PST 23
Peak memory 182768 kb
Host smart-85abf6a1-03e0-426a-994d-fb0fc04d1d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940558197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.940558197
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.325878222
Short name T172
Test name
Test status
Simulation time 7674473419 ps
CPU time 6.45 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 182752 kb
Host smart-39245f7f-e68a-43c2-9bca-b4828399f83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325878222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.325878222
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1846731837
Short name T176
Test name
Test status
Simulation time 571354758 ps
CPU time 0.93 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:43 PM PST 23
Peak memory 182720 kb
Host smart-87089a66-78f3-4d4c-9eeb-cacbd53a7304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846731837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1846731837
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.415173380
Short name T84
Test name
Test status
Simulation time 165425323836 ps
CPU time 234.32 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:13:47 PM PST 23
Peak memory 182772 kb
Host smart-0d148a77-b7fb-479d-8885-b713bea0c926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415173380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.415173380
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3944563060
Short name T42
Test name
Test status
Simulation time 30459463311 ps
CPU time 154.79 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:12:21 PM PST 23
Peak memory 197720 kb
Host smart-1235ac54-b23a-48cf-b4f5-fa54914619b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944563060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3944563060
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.2713839194
Short name T289
Test name
Test status
Simulation time 413482533 ps
CPU time 0.67 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:09:46 PM PST 23
Peak memory 182768 kb
Host smart-5849a09d-a3cc-44e6-a8d2-c46ffccbe25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713839194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.2713839194
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2349565738
Short name T271
Test name
Test status
Simulation time 33633827447 ps
CPU time 53.77 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 182808 kb
Host smart-3a734d31-91cd-4ec5-bafb-922305a8d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349565738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2349565738
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3397166130
Short name T262
Test name
Test status
Simulation time 435074890 ps
CPU time 1.14 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182384 kb
Host smart-4e58e615-117f-4d10-ac1d-242684067370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397166130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3397166130
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1013209752
Short name T221
Test name
Test status
Simulation time 114666364118 ps
CPU time 39.91 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 193232 kb
Host smart-a3391772-5a78-4e2e-8530-bd178f097126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013209752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1013209752
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3238962847
Short name T51
Test name
Test status
Simulation time 98583367743 ps
CPU time 967.56 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:25:53 PM PST 23
Peak memory 203268 kb
Host smart-9ff7b1b2-900b-4794-9c4e-0a7b8b9cbc62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238962847 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3238962847
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4036862531
Short name T147
Test name
Test status
Simulation time 512200288 ps
CPU time 0.67 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182708 kb
Host smart-9fb4fcc7-a798-4aed-a670-28e58a8e7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036862531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4036862531
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3624299760
Short name T119
Test name
Test status
Simulation time 36466440233 ps
CPU time 12.91 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 182812 kb
Host smart-41b92cc8-d406-4299-aa2d-30a543c5dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624299760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3624299760
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2703264810
Short name T139
Test name
Test status
Simulation time 494266413 ps
CPU time 1.38 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182380 kb
Host smart-cf51917b-4886-4389-a3e5-84a71c535224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703264810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2703264810
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3260031127
Short name T276
Test name
Test status
Simulation time 98313891810 ps
CPU time 742.9 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:22:04 PM PST 23
Peak memory 199964 kb
Host smart-e255146f-c2da-43ec-8bc9-ba71d958e408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260031127 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3260031127
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1395843360
Short name T255
Test name
Test status
Simulation time 49916185021 ps
CPU time 10.62 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182776 kb
Host smart-3633a326-80cc-4f0d-8e8f-aca3a5b2011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395843360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1395843360
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2007204631
Short name T270
Test name
Test status
Simulation time 569308546 ps
CPU time 0.73 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:09:56 PM PST 23
Peak memory 182636 kb
Host smart-fef3f3fb-8d74-4a33-a047-fec6d9866aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007204631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2007204631
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2138346154
Short name T279
Test name
Test status
Simulation time 193651129518 ps
CPU time 74.51 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 182804 kb
Host smart-fe390057-9948-47ef-907c-3a2d2556eb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138346154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2138346154
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2049987000
Short name T236
Test name
Test status
Simulation time 164395969497 ps
CPU time 232.89 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:13:31 PM PST 23
Peak memory 197704 kb
Host smart-521cada2-db68-439e-a3a8-97611d8c16ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049987000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2049987000
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3232367448
Short name T21
Test name
Test status
Simulation time 550798244 ps
CPU time 1.36 seconds
Started Dec 24 01:09:33 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 182768 kb
Host smart-2174325d-8e3d-4bd4-ac46-b0afcb0dc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232367448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3232367448
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.671194164
Short name T294
Test name
Test status
Simulation time 38014633447 ps
CPU time 14.85 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 182748 kb
Host smart-110d4f54-0fcf-4355-8e5d-e6037807e949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671194164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.671194164
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2997510240
Short name T39
Test name
Test status
Simulation time 4019582569 ps
CPU time 6.45 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 214620 kb
Host smart-f1ffed52-0236-4ec2-89b6-a2b9ec38369b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997510240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2997510240
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3079178063
Short name T126
Test name
Test status
Simulation time 461660774 ps
CPU time 1.25 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:09:47 PM PST 23
Peak memory 182760 kb
Host smart-7ad0002b-4d85-4bd0-8475-f058665b6c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079178063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3079178063
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1802097878
Short name T278
Test name
Test status
Simulation time 561911673493 ps
CPU time 154.6 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:12:13 PM PST 23
Peak memory 194148 kb
Host smart-7bb33059-a3f3-40f9-9caa-46165b88b584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802097878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1802097878
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.4277631858
Short name T78
Test name
Test status
Simulation time 180601849447 ps
CPU time 506.55 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:18:05 PM PST 23
Peak memory 197756 kb
Host smart-c55de3e1-6d0f-47d6-81e3-34de6d3405fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277631858 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.4277631858
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1285960768
Short name T273
Test name
Test status
Simulation time 356375200 ps
CPU time 1.1 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182744 kb
Host smart-2effeda6-9a49-4e12-aca7-06a61d5edd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285960768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1285960768
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3249883383
Short name T146
Test name
Test status
Simulation time 33126749156 ps
CPU time 38.12 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 182784 kb
Host smart-1132c2fd-9213-44ad-a1be-2f53bbb563cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249883383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3249883383
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1662382665
Short name T156
Test name
Test status
Simulation time 519718480 ps
CPU time 0.94 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182740 kb
Host smart-30e467e6-6e33-4316-aa68-0c5e9fe26a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662382665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1662382665
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.545775357
Short name T79
Test name
Test status
Simulation time 202045758766 ps
CPU time 322.3 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:15:11 PM PST 23
Peak memory 182788 kb
Host smart-a97ea224-5e29-47ba-b509-1907a644a233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545775357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.545775357
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3116559560
Short name T180
Test name
Test status
Simulation time 44963912092 ps
CPU time 242.7 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:13:50 PM PST 23
Peak memory 197728 kb
Host smart-a6d184a9-9b0f-4aae-9b56-ecde8006c53b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116559560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3116559560
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4006954548
Short name T288
Test name
Test status
Simulation time 470260604 ps
CPU time 0.73 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 182732 kb
Host smart-93712a56-dbbf-4ed5-ae97-05cbc4d3f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006954548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4006954548
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.2251023272
Short name T162
Test name
Test status
Simulation time 8835978440 ps
CPU time 4.11 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182800 kb
Host smart-547ace42-40f0-4d6e-9320-b088ac09c4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251023272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.2251023272
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.729939147
Short name T238
Test name
Test status
Simulation time 575287561 ps
CPU time 0.72 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:09:45 PM PST 23
Peak memory 182780 kb
Host smart-d9448e31-5102-4578-b2f9-a5d418943155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729939147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.729939147
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1088548270
Short name T102
Test name
Test status
Simulation time 83135171330 ps
CPU time 138.51 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:12:09 PM PST 23
Peak memory 192964 kb
Host smart-df803dc0-f560-4974-86e1-8ca3c7e48b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088548270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1088548270
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1789706500
Short name T284
Test name
Test status
Simulation time 214215715288 ps
CPU time 579.53 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:19:27 PM PST 23
Peak memory 197668 kb
Host smart-92378a4f-916c-4550-8a59-4fcd0511fbe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789706500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1789706500
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2206797414
Short name T178
Test name
Test status
Simulation time 590737412 ps
CPU time 0.74 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182760 kb
Host smart-a259ff11-c92b-48d9-9605-e98caa5639e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206797414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2206797414
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2120612173
Short name T195
Test name
Test status
Simulation time 7254666376 ps
CPU time 3.32 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182788 kb
Host smart-ee85ce08-8082-4418-b467-c209c64b0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120612173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2120612173
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1068464160
Short name T232
Test name
Test status
Simulation time 616183958 ps
CPU time 0.73 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182648 kb
Host smart-1b6505fb-e611-4261-b1de-9de3361dfab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068464160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1068464160
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1813641549
Short name T89
Test name
Test status
Simulation time 289770439818 ps
CPU time 486.8 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:17:51 PM PST 23
Peak memory 194172 kb
Host smart-ec001b45-387e-48f2-b704-a3a4a84b6cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813641549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1813641549
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1583831216
Short name T67
Test name
Test status
Simulation time 26053074434 ps
CPU time 199.69 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:13:11 PM PST 23
Peak memory 197716 kb
Host smart-d54f0e00-64fd-4b2e-8f18-6f768e134cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583831216 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1583831216
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2603417970
Short name T76
Test name
Test status
Simulation time 475642945 ps
CPU time 0.66 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:47 PM PST 23
Peak memory 182724 kb
Host smart-862b0135-60a5-4c55-902a-5e07ecc4fe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603417970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2603417970
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.44654500
Short name T129
Test name
Test status
Simulation time 58960053957 ps
CPU time 6.24 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182784 kb
Host smart-417ded74-6f1e-4329-98b3-77f5791afaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44654500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.44654500
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.259833843
Short name T240
Test name
Test status
Simulation time 488740873 ps
CPU time 0.72 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:09:41 PM PST 23
Peak memory 182676 kb
Host smart-3d61109f-6e70-48ad-844f-9779525570d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259833843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.259833843
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.354464160
Short name T203
Test name
Test status
Simulation time 110983803403 ps
CPU time 63.21 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 182836 kb
Host smart-eb013e63-76a0-4dbc-9675-f3f9811e0f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354464160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.354464160
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1740679385
Short name T174
Test name
Test status
Simulation time 496390218 ps
CPU time 1.08 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:09:52 PM PST 23
Peak memory 182756 kb
Host smart-1dd0add8-65f8-4af7-a2e1-6eaec092d23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740679385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1740679385
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2423292111
Short name T132
Test name
Test status
Simulation time 15800762538 ps
CPU time 24.75 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 182792 kb
Host smart-4b3bb2df-4f13-46d6-b3bd-a94e080bff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423292111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2423292111
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2312260087
Short name T141
Test name
Test status
Simulation time 400440874 ps
CPU time 0.8 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182760 kb
Host smart-60bd200c-6c95-4aac-9f2f-18df2074db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312260087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2312260087
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.292793305
Short name T92
Test name
Test status
Simulation time 91556849512 ps
CPU time 126.76 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:11:55 PM PST 23
Peak memory 182684 kb
Host smart-fa2e0185-c9fd-42da-a868-c0222f47d37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292793305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.292793305
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2877385566
Short name T98
Test name
Test status
Simulation time 57606415960 ps
CPU time 395.81 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:16:28 PM PST 23
Peak memory 197676 kb
Host smart-b958fc9f-3cf1-4e2f-8a0c-bfa0d22aa3f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877385566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2877385566
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3779894288
Short name T96
Test name
Test status
Simulation time 508299523 ps
CPU time 0.92 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:44 PM PST 23
Peak memory 182760 kb
Host smart-342c597e-3ec1-4b84-9b46-492019486e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779894288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3779894288
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3122706204
Short name T135
Test name
Test status
Simulation time 20936338881 ps
CPU time 33.19 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:10:35 PM PST 23
Peak memory 182828 kb
Host smart-fd515df7-a062-4359-acea-56dcf336bdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122706204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3122706204
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3716177029
Short name T253
Test name
Test status
Simulation time 429182437 ps
CPU time 0.77 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 182612 kb
Host smart-d4f81db3-711e-4f4c-9b1a-7bdc53068adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716177029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3716177029
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3034350333
Short name T35
Test name
Test status
Simulation time 81984656112 ps
CPU time 120.03 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 182832 kb
Host smart-47b8a511-36ca-476b-bd67-b71c43295cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034350333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3034350333
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1372056898
Short name T298
Test name
Test status
Simulation time 422584080 ps
CPU time 1.09 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182780 kb
Host smart-f039c8fb-bb03-4829-b3e8-ba1a478e1db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372056898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1372056898
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1151502474
Short name T241
Test name
Test status
Simulation time 40849827756 ps
CPU time 33.13 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 182744 kb
Host smart-875897c5-f5a0-41d7-8c88-8b12f0a7c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151502474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1151502474
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2933766662
Short name T297
Test name
Test status
Simulation time 334996905 ps
CPU time 1.06 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 182572 kb
Host smart-18730b2b-2887-4da9-8245-94a122c1f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933766662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2933766662
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3774104999
Short name T81
Test name
Test status
Simulation time 46130223699 ps
CPU time 7.44 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 192780 kb
Host smart-a9da6dee-1a90-4bfa-866b-c38054befa49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774104999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3774104999
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3620589037
Short name T226
Test name
Test status
Simulation time 120059806448 ps
CPU time 477.55 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:17:49 PM PST 23
Peak memory 197688 kb
Host smart-c5772f18-16e9-4502-90ed-f84ad9b76e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620589037 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3620589037
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3062360819
Short name T49
Test name
Test status
Simulation time 473140865 ps
CPU time 0.86 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 182712 kb
Host smart-c3295526-a76d-4793-82d5-00c867e2501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062360819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3062360819
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3415913996
Short name T251
Test name
Test status
Simulation time 9196623402 ps
CPU time 15.01 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 182748 kb
Host smart-1cf03988-ab24-4278-a512-76bb80d4e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415913996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3415913996
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1343179445
Short name T266
Test name
Test status
Simulation time 525713240 ps
CPU time 0.91 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182520 kb
Host smart-863ea626-2e48-4403-90a6-672b0d3e15a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343179445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1343179445
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1647844082
Short name T228
Test name
Test status
Simulation time 12436332637 ps
CPU time 87.12 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 197760 kb
Host smart-86ae9623-483d-48b3-a4b9-aed4685efd90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647844082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1647844082
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2550844288
Short name T261
Test name
Test status
Simulation time 500008975 ps
CPU time 0.66 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182776 kb
Host smart-e7f6c22d-c5c2-4a41-b8b2-345d53514cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550844288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2550844288
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1905907557
Short name T223
Test name
Test status
Simulation time 51103364607 ps
CPU time 20.78 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 182780 kb
Host smart-528ceb28-a326-4d8b-bb4e-cc41b23fef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905907557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1905907557
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1407320413
Short name T145
Test name
Test status
Simulation time 426314763 ps
CPU time 0.86 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:02 PM PST 23
Peak memory 182780 kb
Host smart-1666c9d2-b182-400b-8589-dcab5cd6f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407320413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1407320413
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3368354708
Short name T166
Test name
Test status
Simulation time 138259217053 ps
CPU time 74.86 seconds
Started Dec 24 01:09:56 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 192796 kb
Host smart-e2f6796c-11aa-4c92-8db4-a9bd8278bbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368354708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3368354708
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.10748041
Short name T95
Test name
Test status
Simulation time 105104150477 ps
CPU time 233.66 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:13:42 PM PST 23
Peak memory 197652 kb
Host smart-4e49b7a4-f15d-4484-9543-de00e8140058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10748041 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.10748041
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3269610227
Short name T227
Test name
Test status
Simulation time 420887539 ps
CPU time 0.74 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:02 PM PST 23
Peak memory 182664 kb
Host smart-41d9e0c4-9420-41a0-82c9-2b9c277b2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269610227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3269610227
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2148765618
Short name T114
Test name
Test status
Simulation time 12056850107 ps
CPU time 20.53 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 182784 kb
Host smart-7a787cc1-39cf-40ba-a7d8-a77ab15b6df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148765618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2148765618
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4260800256
Short name T246
Test name
Test status
Simulation time 507066899 ps
CPU time 1.21 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:09:56 PM PST 23
Peak memory 182380 kb
Host smart-ac70fdf9-dd38-412e-9d88-bce37eebfd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260800256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4260800256
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.529580406
Short name T292
Test name
Test status
Simulation time 487358259325 ps
CPU time 195.61 seconds
Started Dec 24 01:09:48 PM PST 23
Finished Dec 24 01:13:10 PM PST 23
Peak memory 193164 kb
Host smart-f4a9f810-e58f-4003-8ef3-ca8a28a65b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529580406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.529580406
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3290935027
Short name T105
Test name
Test status
Simulation time 39756564207 ps
CPU time 83.94 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:11:26 PM PST 23
Peak memory 197708 kb
Host smart-9b8bec1a-2aae-4d5f-9dfa-dc28aa0a99c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290935027 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3290935027
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1402774415
Short name T257
Test name
Test status
Simulation time 445442638 ps
CPU time 0.67 seconds
Started Dec 24 01:09:35 PM PST 23
Finished Dec 24 01:09:42 PM PST 23
Peak memory 182708 kb
Host smart-e1e8959a-52d9-4eb4-8408-2e74ea7b94b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402774415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1402774415
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.195708075
Short name T164
Test name
Test status
Simulation time 27613811000 ps
CPU time 45.49 seconds
Started Dec 24 01:09:48 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 182784 kb
Host smart-cababefe-c189-4bdb-9b38-3a8015c4400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195708075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.195708075
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1889138431
Short name T36
Test name
Test status
Simulation time 4243706261 ps
CPU time 1.89 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 214728 kb
Host smart-bf1342db-ba7f-422a-8718-d3469b031bd7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889138431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1889138431
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.332000048
Short name T272
Test name
Test status
Simulation time 382342008 ps
CPU time 0.69 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:47 PM PST 23
Peak memory 182632 kb
Host smart-a49627d0-5916-4e1b-95eb-1376292b0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332000048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.332000048
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2775790127
Short name T209
Test name
Test status
Simulation time 170989226893 ps
CPU time 64.19 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:10:41 PM PST 23
Peak memory 193008 kb
Host smart-6486732f-5a41-4922-8b6b-fba615e68d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775790127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2775790127
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1896953759
Short name T86
Test name
Test status
Simulation time 53947964683 ps
CPU time 109.13 seconds
Started Dec 24 01:09:37 PM PST 23
Finished Dec 24 01:11:33 PM PST 23
Peak memory 197688 kb
Host smart-14b25676-2f65-438b-8aad-38fb60b06dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896953759 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1896953759
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2315587590
Short name T185
Test name
Test status
Simulation time 550529702 ps
CPU time 1.33 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:10:14 PM PST 23
Peak memory 182744 kb
Host smart-e2ac67c6-db86-4e6e-99d3-f9e4a2f0c675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315587590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2315587590
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.257244394
Short name T167
Test name
Test status
Simulation time 39445215927 ps
CPU time 53.45 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 182848 kb
Host smart-6a709054-0e2e-4c4e-a4d8-a1f9ede04be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257244394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.257244394
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.333545907
Short name T269
Test name
Test status
Simulation time 494508014 ps
CPU time 0.91 seconds
Started Dec 24 01:09:56 PM PST 23
Finished Dec 24 01:10:01 PM PST 23
Peak memory 182560 kb
Host smart-dd4d63b1-5f23-484c-ae99-bf534f082213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333545907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.333545907
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3910345687
Short name T93
Test name
Test status
Simulation time 174996214082 ps
CPU time 287.28 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:14:49 PM PST 23
Peak memory 182796 kb
Host smart-93c070db-ff06-4e0c-a6f3-71282bc5faa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910345687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3910345687
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2116579396
Short name T82
Test name
Test status
Simulation time 55099424088 ps
CPU time 156.51 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:12:31 PM PST 23
Peak memory 197708 kb
Host smart-20e1de62-c0b9-45e4-b748-27cd26136291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116579396 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2116579396
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.651692612
Short name T23
Test name
Test status
Simulation time 506940632 ps
CPU time 0.72 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182956 kb
Host smart-e0b643ac-fdb9-49a1-83e5-9ecbf28c2cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651692612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.651692612
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3158917109
Short name T20
Test name
Test status
Simulation time 27080504852 ps
CPU time 39.41 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 182760 kb
Host smart-93503367-e0cd-4a90-9d0d-5d26c3b196dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158917109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3158917109
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.542894668
Short name T138
Test name
Test status
Simulation time 456613498 ps
CPU time 0.97 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:10:02 PM PST 23
Peak memory 182552 kb
Host smart-45015e6f-44b9-4b1d-8e8a-0e931c2c605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542894668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.542894668
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3722848898
Short name T259
Test name
Test status
Simulation time 241980050270 ps
CPU time 61.79 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 182724 kb
Host smart-a525f55f-77a4-4c76-bc9b-5cce7f770c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722848898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3722848898
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.2292790445
Short name T208
Test name
Test status
Simulation time 86826895321 ps
CPU time 197.99 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:13:08 PM PST 23
Peak memory 197740 kb
Host smart-d40b7496-35c8-4367-9506-51cea605acd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292790445 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.2292790445
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1863399211
Short name T190
Test name
Test status
Simulation time 359139799 ps
CPU time 1.04 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182780 kb
Host smart-96d7ceed-3e3d-4242-aee1-7acfc63d5236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863399211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1863399211
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.673663440
Short name T136
Test name
Test status
Simulation time 19114048666 ps
CPU time 13.57 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182752 kb
Host smart-97334640-daad-4ac9-95a1-f3653a0e585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673663440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.673663440
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3096966712
Short name T144
Test name
Test status
Simulation time 470085748 ps
CPU time 0.69 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182752 kb
Host smart-03f2d45e-6660-4ded-9867-5d9ca959ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096966712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3096966712
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.71107256
Short name T263
Test name
Test status
Simulation time 57707289419 ps
CPU time 39.74 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:10:31 PM PST 23
Peak memory 182816 kb
Host smart-886cea63-1d69-4126-b45b-bd8370f7d022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71107256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_al
l.71107256
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1777727148
Short name T214
Test name
Test status
Simulation time 50747718857 ps
CPU time 410.76 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:16:38 PM PST 23
Peak memory 197716 kb
Host smart-3ea63307-c259-4059-9624-b6a303e07b8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777727148 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1777727148
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3856271651
Short name T244
Test name
Test status
Simulation time 548371530 ps
CPU time 1.34 seconds
Started Dec 24 01:09:56 PM PST 23
Finished Dec 24 01:10:02 PM PST 23
Peak memory 182728 kb
Host smart-36497cdc-0efe-44f1-9501-eaf129efcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856271651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3856271651
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4199338089
Short name T158
Test name
Test status
Simulation time 15579200821 ps
CPU time 5.81 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:10:01 PM PST 23
Peak memory 182780 kb
Host smart-a900e5b3-f203-4301-abdc-37f92ab67546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199338089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4199338089
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2480327233
Short name T177
Test name
Test status
Simulation time 560293015 ps
CPU time 0.97 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 182756 kb
Host smart-9365f6c5-b610-418b-8d6c-37a20ae4d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480327233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2480327233
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.43818097
Short name T250
Test name
Test status
Simulation time 177815158102 ps
CPU time 230.82 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:13:36 PM PST 23
Peak memory 193000 kb
Host smart-0991048d-8b67-430a-8f23-0e16dbcf021a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43818097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_al
l.43818097
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.374416382
Short name T85
Test name
Test status
Simulation time 436058891 ps
CPU time 1.04 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 182764 kb
Host smart-d93e5780-5859-4584-96e7-f4ccd84151c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374416382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.374416382
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1487824500
Short name T151
Test name
Test status
Simulation time 35780658420 ps
CPU time 58.33 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 182680 kb
Host smart-9ef8e286-f601-44e8-a157-1bb10550336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487824500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1487824500
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.472792712
Short name T127
Test name
Test status
Simulation time 426908338 ps
CPU time 0.69 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182540 kb
Host smart-39d14011-dec5-41a0-8036-4b5d6124f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472792712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.472792712
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.381893289
Short name T83
Test name
Test status
Simulation time 321399872760 ps
CPU time 364.86 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:16:00 PM PST 23
Peak memory 193140 kb
Host smart-c321c568-e7b1-4c53-b565-c107630ce0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381893289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.381893289
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2977508302
Short name T217
Test name
Test status
Simulation time 591439096 ps
CPU time 1.02 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182964 kb
Host smart-716ded18-e05b-4c19-a5df-1388e3ad963b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977508302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2977508302
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3082932848
Short name T116
Test name
Test status
Simulation time 19999273176 ps
CPU time 7.68 seconds
Started Dec 24 01:09:42 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182752 kb
Host smart-2f4c9d63-3b78-4cb3-9db3-7691144e3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082932848 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3082932848
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1706386629
Short name T230
Test name
Test status
Simulation time 392278941 ps
CPU time 1.11 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182960 kb
Host smart-d5276d11-c42d-4d2a-adc2-893454b5157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706386629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1706386629
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3392401058
Short name T75
Test name
Test status
Simulation time 39106935798 ps
CPU time 62.11 seconds
Started Dec 24 01:09:42 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 182784 kb
Host smart-a5defc02-f6dc-4dcd-bcb5-61bd7d55e211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392401058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3392401058
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.50154558
Short name T231
Test name
Test status
Simulation time 468673159 ps
CPU time 0.89 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:09:53 PM PST 23
Peak memory 182620 kb
Host smart-cac06d5f-15b8-47dc-98a3-d0e4fade665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50154558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.50154558
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4235055061
Short name T187
Test name
Test status
Simulation time 51893318288 ps
CPU time 18.38 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 182840 kb
Host smart-893da51a-6954-4a0a-a91f-295822c83f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235055061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4235055061
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1439133642
Short name T181
Test name
Test status
Simulation time 435773718 ps
CPU time 1.19 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:09:52 PM PST 23
Peak memory 182520 kb
Host smart-b13c4045-fb26-4efa-8ae6-318161c0be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439133642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1439133642
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.802391377
Short name T77
Test name
Test status
Simulation time 28717439747 ps
CPU time 11.54 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:10:05 PM PST 23
Peak memory 193324 kb
Host smart-bcd65d30-7db6-49b7-b352-36c31539984e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802391377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.802391377
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3209633067
Short name T99
Test name
Test status
Simulation time 6252252836 ps
CPU time 43.77 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:10:41 PM PST 23
Peak memory 197656 kb
Host smart-1229e923-ec09-4e39-b74a-7d9b812606c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209633067 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3209633067
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1288697724
Short name T242
Test name
Test status
Simulation time 566570991 ps
CPU time 1.29 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182960 kb
Host smart-93e9d2a1-5bb1-4355-8b32-44578cb4a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288697724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1288697724
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2802141411
Short name T179
Test name
Test status
Simulation time 18102814338 ps
CPU time 15.75 seconds
Started Dec 24 01:09:55 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 182772 kb
Host smart-fa35956d-1a61-44a6-bf5e-8addb963e9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802141411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2802141411
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2396997079
Short name T186
Test name
Test status
Simulation time 554239718 ps
CPU time 0.7 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182852 kb
Host smart-3221ddc0-ce40-43a7-b6df-aee8c509a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396997079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2396997079
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4203322813
Short name T285
Test name
Test status
Simulation time 76226791188 ps
CPU time 107.67 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 193236 kb
Host smart-80aea9ef-727f-45ca-a82e-e09c4626b9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203322813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4203322813
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3255726944
Short name T286
Test name
Test status
Simulation time 94863994167 ps
CPU time 534.75 seconds
Started Dec 24 01:09:42 PM PST 23
Finished Dec 24 01:18:44 PM PST 23
Peak memory 198340 kb
Host smart-cf2bb592-eb49-4a35-8f0d-b87442918a21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255726944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3255726944
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1867993836
Short name T134
Test name
Test status
Simulation time 692725289 ps
CPU time 0.58 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 182760 kb
Host smart-022eecb0-21fe-4059-b4bb-6a616c58d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867993836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1867993836
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1096783429
Short name T152
Test name
Test status
Simulation time 32417609181 ps
CPU time 12.53 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:14 PM PST 23
Peak memory 182708 kb
Host smart-0b648ad0-2b84-4389-9cf0-e9e19197118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096783429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1096783429
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1641204484
Short name T260
Test name
Test status
Simulation time 589819968 ps
CPU time 1.34 seconds
Started Dec 24 01:09:48 PM PST 23
Finished Dec 24 01:09:55 PM PST 23
Peak memory 182600 kb
Host smart-52e4bcab-265f-413d-be3d-ace5e8a7e260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641204484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1641204484
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2777838304
Short name T97
Test name
Test status
Simulation time 73678097848 ps
CPU time 111.96 seconds
Started Dec 24 01:09:45 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 182776 kb
Host smart-4e45ee65-0b94-4a52-b129-992486ac95eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777838304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2777838304
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2241241443
Short name T182
Test name
Test status
Simulation time 52549016413 ps
CPU time 544.61 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:19:00 PM PST 23
Peak memory 197340 kb
Host smart-0aad84bd-851b-4936-9ab0-ad3c582cb4af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241241443 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2241241443
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1893471880
Short name T248
Test name
Test status
Simulation time 435034218 ps
CPU time 1.15 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182772 kb
Host smart-f3f06263-941c-402a-9488-4c48c138ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893471880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1893471880
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.6673040
Short name T210
Test name
Test status
Simulation time 7069536049 ps
CPU time 3.56 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:10:05 PM PST 23
Peak memory 182816 kb
Host smart-0cd6c9a7-d45a-4191-8406-439cc4e774e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6673040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.6673040
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.835122745
Short name T148
Test name
Test status
Simulation time 583966525 ps
CPU time 1.31 seconds
Started Dec 24 01:09:53 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 182604 kb
Host smart-9746cf5c-810c-4cb6-8202-117ee28e11ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835122745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.835122745
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3295334641
Short name T168
Test name
Test status
Simulation time 3716638030 ps
CPU time 3.24 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182780 kb
Host smart-0480a429-3e67-481b-b0e4-aa34c4b28838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295334641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3295334641
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3662563553
Short name T142
Test name
Test status
Simulation time 271369379061 ps
CPU time 156.33 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:12:38 PM PST 23
Peak memory 197584 kb
Host smart-1f3c5217-3a3b-49ec-80d1-c7ad33a3389d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662563553 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3662563553
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1966237148
Short name T160
Test name
Test status
Simulation time 389023472 ps
CPU time 1.21 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 182728 kb
Host smart-b5f40ea9-8e70-4b98-a07a-01345bc51ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966237148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1966237148
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4034624661
Short name T169
Test name
Test status
Simulation time 42963012653 ps
CPU time 20.48 seconds
Started Dec 24 01:09:38 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 182748 kb
Host smart-1da0e81c-ebca-4c3e-9827-66dd344073e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034624661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4034624661
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3623492645
Short name T32
Test name
Test status
Simulation time 4253573493 ps
CPU time 2.12 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:09:48 PM PST 23
Peak memory 214652 kb
Host smart-e2c2191c-68e8-46af-bdde-5b527e4edefb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623492645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3623492645
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1413005954
Short name T234
Test name
Test status
Simulation time 477040413 ps
CPU time 1.29 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182620 kb
Host smart-75fad04b-f9e4-40ce-9942-3d6e017cba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413005954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1413005954
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2475042658
Short name T165
Test name
Test status
Simulation time 54671839144 ps
CPU time 66.66 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:11:00 PM PST 23
Peak memory 193020 kb
Host smart-d455359c-4d30-4bad-a7fc-f76c2fd7802e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475042658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2475042658
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2299839682
Short name T184
Test name
Test status
Simulation time 218746331586 ps
CPU time 747.9 seconds
Started Dec 24 01:09:39 PM PST 23
Finished Dec 24 01:22:14 PM PST 23
Peak memory 200480 kb
Host smart-65c37ee8-df5f-4d10-8079-8220ee2dc7af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299839682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2299839682
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3986235104
Short name T201
Test name
Test status
Simulation time 448283255 ps
CPU time 0.61 seconds
Started Dec 24 01:09:46 PM PST 23
Finished Dec 24 01:09:52 PM PST 23
Peak memory 182712 kb
Host smart-7bbd20ce-39e9-4cbe-9dee-b4f392d05e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986235104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3986235104
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3196913048
Short name T274
Test name
Test status
Simulation time 21041556545 ps
CPU time 5.11 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:10:00 PM PST 23
Peak memory 182752 kb
Host smart-359bbfa0-3777-416d-95ef-6f9221e81f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196913048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3196913048
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3287136125
Short name T163
Test name
Test status
Simulation time 490197520 ps
CPU time 0.74 seconds
Started Dec 24 01:09:43 PM PST 23
Finished Dec 24 01:09:50 PM PST 23
Peak memory 182652 kb
Host smart-5da90b58-79b8-4494-ab75-c3dedf0ab803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287136125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3287136125
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2343418543
Short name T220
Test name
Test status
Simulation time 241297825248 ps
CPU time 81.6 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 193028 kb
Host smart-2adba6c3-2a59-4bb6-8cf4-23ec8e2ae950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343418543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2343418543
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.291710852
Short name T68
Test name
Test status
Simulation time 54343931367 ps
CPU time 95.43 seconds
Started Dec 24 01:09:48 PM PST 23
Finished Dec 24 01:11:30 PM PST 23
Peak memory 197736 kb
Host smart-d315f839-6930-4fbc-8408-77e65461f8ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291710852 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.291710852
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2872084124
Short name T218
Test name
Test status
Simulation time 459107966 ps
CPU time 0.71 seconds
Started Dec 24 01:09:59 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182780 kb
Host smart-d78518aa-123e-4589-ada2-8e6872459fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872084124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2872084124
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2604083031
Short name T188
Test name
Test status
Simulation time 35420219258 ps
CPU time 11.06 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 182672 kb
Host smart-0f76c3a4-cd45-4bf5-9d71-b21d0c76aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604083031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2604083031
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2520677021
Short name T258
Test name
Test status
Simulation time 566848166 ps
CPU time 1.38 seconds
Started Dec 24 01:09:59 PM PST 23
Finished Dec 24 01:10:04 PM PST 23
Peak memory 182652 kb
Host smart-9a7665cb-164e-489a-8d8b-6beb38a83c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520677021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2520677021
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2386124706
Short name T229
Test name
Test status
Simulation time 175457019804 ps
CPU time 144.3 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:12:20 PM PST 23
Peak memory 182704 kb
Host smart-627aa99f-2a5b-498f-86ca-f892175c3d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386124706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2386124706
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.54525529
Short name T215
Test name
Test status
Simulation time 14379280986 ps
CPU time 99.08 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:11:33 PM PST 23
Peak memory 195596 kb
Host smart-9ba54fff-b3cc-4e44-b937-5bf8fea99112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54525529 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.54525529
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2331791798
Short name T243
Test name
Test status
Simulation time 551703143 ps
CPU time 0.74 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 182712 kb
Host smart-096933de-a8ac-434d-8f21-e09fda70986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331791798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2331791798
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3796987641
Short name T247
Test name
Test status
Simulation time 14200659815 ps
CPU time 4.39 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182820 kb
Host smart-7a31031a-f48e-493a-b0a1-8cd03bf0c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796987641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3796987641
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.356768996
Short name T301
Test name
Test status
Simulation time 408494554 ps
CPU time 1.22 seconds
Started Dec 24 01:09:48 PM PST 23
Finished Dec 24 01:09:55 PM PST 23
Peak memory 182668 kb
Host smart-4576f6fe-764a-4b6e-a0fa-a572c6e137ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356768996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.356768996
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2011564955
Short name T268
Test name
Test status
Simulation time 162762464606 ps
CPU time 69.38 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:11:10 PM PST 23
Peak memory 182772 kb
Host smart-a5935dad-1a63-4d17-aac1-a691606bf640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011564955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2011564955
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1098591822
Short name T104
Test name
Test status
Simulation time 444902010 ps
CPU time 0.86 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 182780 kb
Host smart-4a9bf357-6de4-45ff-b5d7-bb6a8904175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098591822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1098591822
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3665385048
Short name T115
Test name
Test status
Simulation time 19423945999 ps
CPU time 4.98 seconds
Started Dec 24 01:10:00 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 182812 kb
Host smart-6feab3d7-369c-4a96-914f-2c4923863567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665385048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3665385048
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1221814984
Short name T161
Test name
Test status
Simulation time 439826221 ps
CPU time 0.9 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182480 kb
Host smart-b38d56e8-4bfa-4035-a6ab-2445d96451d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221814984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1221814984
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3765605476
Short name T224
Test name
Test status
Simulation time 140213270767 ps
CPU time 208.16 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:13:25 PM PST 23
Peak memory 193088 kb
Host smart-d1221cd7-7aff-46c8-a681-2ab627f5c40d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765605476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3765605476
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1627538837
Short name T280
Test name
Test status
Simulation time 58543188292 ps
CPU time 439.34 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:17:14 PM PST 23
Peak memory 197744 kb
Host smart-ce39f093-8a0f-4ae8-9ef3-e6e748dfb43f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627538837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1627538837
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3589866091
Short name T290
Test name
Test status
Simulation time 385358087 ps
CPU time 0.84 seconds
Started Dec 24 01:09:47 PM PST 23
Finished Dec 24 01:09:54 PM PST 23
Peak memory 182708 kb
Host smart-1bbcc2f3-e79b-4d37-b9c4-eba038143359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589866091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3589866091
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.878189727
Short name T193
Test name
Test status
Simulation time 19314205402 ps
CPU time 7.17 seconds
Started Dec 24 01:09:59 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 182800 kb
Host smart-07a55cb8-42d9-4aed-8813-118b4eddf6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878189727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.878189727
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2854725933
Short name T170
Test name
Test status
Simulation time 575283424 ps
CPU time 1.43 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:17 PM PST 23
Peak memory 182672 kb
Host smart-5c403b85-7970-417f-9c99-633f678398b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854725933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2854725933
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4230919369
Short name T254
Test name
Test status
Simulation time 415853888959 ps
CPU time 80.11 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:11:34 PM PST 23
Peak memory 193168 kb
Host smart-79fcf399-d0f1-4b7a-b70c-e94256f76b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230919369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4230919369
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1321926031
Short name T245
Test name
Test status
Simulation time 472680931 ps
CPU time 1.21 seconds
Started Dec 24 01:10:08 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 182708 kb
Host smart-39a7059a-28c8-4b2f-8255-4e5fd106a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321926031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1321926031
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4162749818
Short name T128
Test name
Test status
Simulation time 26880246680 ps
CPU time 10.9 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 182792 kb
Host smart-16e9da21-8835-43e4-b20b-8dec4138b4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162749818 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4162749818
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2156298216
Short name T295
Test name
Test status
Simulation time 495215805 ps
CPU time 0.87 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 182768 kb
Host smart-0b33ab41-a1df-4577-ab59-7bdaec400377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156298216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2156298216
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1219574563
Short name T173
Test name
Test status
Simulation time 4007465678 ps
CPU time 7.71 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:14 PM PST 23
Peak memory 182820 kb
Host smart-6cbd1fc2-25fd-4097-9064-7ec43396a243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219574563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1219574563
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1659149845
Short name T189
Test name
Test status
Simulation time 29212864401 ps
CPU time 321.43 seconds
Started Dec 24 01:10:24 PM PST 23
Finished Dec 24 01:15:49 PM PST 23
Peak memory 197724 kb
Host smart-9501bb3d-5e7a-42d1-8eb6-bea40827c9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659149845 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1659149845
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3456994153
Short name T108
Test name
Test status
Simulation time 514910001 ps
CPU time 1.37 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182716 kb
Host smart-b921b72e-6cda-44c7-8eb6-ae2f0a095750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456994153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3456994153
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1905756564
Short name T140
Test name
Test status
Simulation time 4387576254 ps
CPU time 3.95 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 182848 kb
Host smart-4dde6f35-8537-46e9-8f32-f7aa5293ae47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905756564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1905756564
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1443531178
Short name T196
Test name
Test status
Simulation time 405520031 ps
CPU time 1.19 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182668 kb
Host smart-e5148bcf-b970-464f-b999-7ced3aa85c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443531178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1443531178
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3311269860
Short name T110
Test name
Test status
Simulation time 228531625152 ps
CPU time 92.31 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:11:31 PM PST 23
Peak memory 194216 kb
Host smart-dc964751-8cdc-417e-8be2-b2b8c16afe12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311269860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3311269860
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2149230197
Short name T219
Test name
Test status
Simulation time 551293268 ps
CPU time 0.73 seconds
Started Dec 24 01:10:19 PM PST 23
Finished Dec 24 01:10:23 PM PST 23
Peak memory 182776 kb
Host smart-118959ba-587e-4901-81db-05e09a103c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149230197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2149230197
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2421304692
Short name T150
Test name
Test status
Simulation time 19646492834 ps
CPU time 16.65 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 182820 kb
Host smart-cb7ce373-2057-4e4a-8bbe-3f426ee31b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421304692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2421304692
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.2329417290
Short name T252
Test name
Test status
Simulation time 394801950 ps
CPU time 0.84 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 182664 kb
Host smart-2fa98d0c-3a11-4b6e-b09a-814936627aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329417290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.2329417290
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2104785793
Short name T283
Test name
Test status
Simulation time 203179756310 ps
CPU time 299.28 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:15:11 PM PST 23
Peak memory 193052 kb
Host smart-6bb12a5e-123f-4e4d-b10f-2afb763c379a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104785793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2104785793
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.4143250659
Short name T206
Test name
Test status
Simulation time 21918955614 ps
CPU time 225.5 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:14:07 PM PST 23
Peak memory 197648 kb
Host smart-94ab97db-61e8-467d-a0cc-8476b69110b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143250659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.4143250659
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3002128909
Short name T18
Test name
Test status
Simulation time 471273231 ps
CPU time 0.93 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182768 kb
Host smart-226240e2-0cc9-4413-b4ea-48241a641362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002128909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3002128909
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4205403634
Short name T118
Test name
Test status
Simulation time 47220693551 ps
CPU time 19.58 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 182780 kb
Host smart-2faafcfd-5227-46d5-aa12-3fff84691d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205403634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4205403634
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.159012105
Short name T299
Test name
Test status
Simulation time 577054541 ps
CPU time 0.79 seconds
Started Dec 24 01:09:59 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182784 kb
Host smart-ff7acc29-a290-43ab-9c19-ae650c2b826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159012105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.159012105
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2719399720
Short name T101
Test name
Test status
Simulation time 32905788808 ps
CPU time 54.6 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 182724 kb
Host smart-ff5636af-082c-402c-80e7-e2e3790fc25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719399720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2719399720
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1203358786
Short name T199
Test name
Test status
Simulation time 91832645132 ps
CPU time 482.85 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:18:09 PM PST 23
Peak memory 197592 kb
Host smart-5e1b10f2-d547-4d12-94db-17ab63e5f2de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203358786 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1203358786
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.42856413
Short name T48
Test name
Test status
Simulation time 556605599 ps
CPU time 0.78 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:10:13 PM PST 23
Peak memory 182756 kb
Host smart-e1ed1f75-17bf-4188-be20-141d766020c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42856413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.42856413
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2221606612
Short name T117
Test name
Test status
Simulation time 23552307928 ps
CPU time 8.06 seconds
Started Dec 24 01:09:49 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 182792 kb
Host smart-1370bc7d-fdf0-41d3-ac04-b0fcdfaf6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221606612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2221606612
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2004032039
Short name T233
Test name
Test status
Simulation time 525081511 ps
CPU time 1.31 seconds
Started Dec 24 01:09:59 PM PST 23
Finished Dec 24 01:10:04 PM PST 23
Peak memory 182540 kb
Host smart-7b54fb99-4ae9-49e3-84b6-6c4d2d0d2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004032039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2004032039
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3844508943
Short name T281
Test name
Test status
Simulation time 131762171534 ps
CPU time 168.21 seconds
Started Dec 24 01:09:55 PM PST 23
Finished Dec 24 01:12:48 PM PST 23
Peak memory 182744 kb
Host smart-d2a1cfbd-edc8-47b0-8c09-12e09f24c09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844508943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3844508943
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1396975333
Short name T291
Test name
Test status
Simulation time 96200452536 ps
CPU time 239.87 seconds
Started Dec 24 01:09:57 PM PST 23
Finished Dec 24 01:14:01 PM PST 23
Peak memory 197748 kb
Host smart-95bc781b-ac9b-49e3-8811-75bcd112234c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396975333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1396975333
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4092987356
Short name T205
Test name
Test status
Simulation time 376492853 ps
CPU time 0.65 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 182752 kb
Host smart-396db557-32c1-415f-98d8-d1204eaaa69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092987356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4092987356
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4199851028
Short name T202
Test name
Test status
Simulation time 24319456274 ps
CPU time 40.91 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 182784 kb
Host smart-f8b23c4e-aec9-4aa6-8616-45f60f2399a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199851028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4199851028
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.1570376322
Short name T277
Test name
Test status
Simulation time 622814623 ps
CPU time 0.82 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:38 PM PST 23
Peak memory 182620 kb
Host smart-fe3a1741-2fa4-44bc-a05c-09fb7261af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570376322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.1570376322
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.121126475
Short name T198
Test name
Test status
Simulation time 62503037893 ps
CPU time 26.8 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:10:05 PM PST 23
Peak memory 182912 kb
Host smart-b33a5369-687a-496f-931b-f4c34a84a5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121126475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.121126475
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2540435230
Short name T300
Test name
Test status
Simulation time 1183338973354 ps
CPU time 490.02 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:17:52 PM PST 23
Peak memory 197648 kb
Host smart-a398b489-b4e6-4b4c-9039-ad0cf172ab10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540435230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2540435230
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.971903019
Short name T265
Test name
Test status
Simulation time 638767424 ps
CPU time 0.61 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:09:36 PM PST 23
Peak memory 182760 kb
Host smart-3c7c2e15-1cd6-42ef-9295-d0e73c8782c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971903019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.971903019
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.689994889
Short name T267
Test name
Test status
Simulation time 26324808927 ps
CPU time 10.32 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:46 PM PST 23
Peak memory 182812 kb
Host smart-68a9cef2-ca65-4377-a330-f978726ff481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689994889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.689994889
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2173623536
Short name T237
Test name
Test status
Simulation time 514809069 ps
CPU time 0.75 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 182760 kb
Host smart-3c02c21a-1eb5-4f7b-b6fa-91090876c5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173623536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2173623536
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1053529357
Short name T90
Test name
Test status
Simulation time 184129059354 ps
CPU time 140.75 seconds
Started Dec 24 01:09:34 PM PST 23
Finished Dec 24 01:12:01 PM PST 23
Peak memory 193184 kb
Host smart-eddb47e8-0160-49b9-b771-14c439dd5d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053529357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1053529357
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3356513019
Short name T120
Test name
Test status
Simulation time 39581602635 ps
CPU time 315.86 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:14:53 PM PST 23
Peak memory 197652 kb
Host smart-0ebbbc88-efdf-4bdb-a3cb-2e4401d241a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356513019 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3356513019
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3219898225
Short name T225
Test name
Test status
Simulation time 525940122 ps
CPU time 0.76 seconds
Started Dec 24 01:09:44 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 182740 kb
Host smart-afbce067-502b-4697-acb2-17de81824b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219898225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3219898225
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.189279444
Short name T125
Test name
Test status
Simulation time 7303264267 ps
CPU time 7.49 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:55 PM PST 23
Peak memory 182808 kb
Host smart-c7e0dc0c-7c06-4574-a406-d776756bb7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189279444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.189279444
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1147184164
Short name T212
Test name
Test status
Simulation time 441212918 ps
CPU time 0.75 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:09:37 PM PST 23
Peak memory 182644 kb
Host smart-9ca82f66-aaa0-49f9-9933-d53fd8f228ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147184164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1147184164
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.825595056
Short name T222
Test name
Test status
Simulation time 62571065711 ps
CPU time 52.31 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 192940 kb
Host smart-c6e7db91-1519-48a6-b9a8-76c02dec06e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825595056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.825595056
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.138905755
Short name T71
Test name
Test status
Simulation time 21400376784 ps
CPU time 80.43 seconds
Started Dec 24 01:09:36 PM PST 23
Finished Dec 24 01:11:04 PM PST 23
Peak memory 197696 kb
Host smart-702246a4-979e-45d0-b53b-87df4273083f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138905755 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.138905755
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4270282672
Short name T154
Test name
Test status
Simulation time 588455199 ps
CPU time 0.97 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:39 PM PST 23
Peak memory 182792 kb
Host smart-3a3790dc-3a91-45f5-ab29-9e8a0d09284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270282672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4270282672
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3767494762
Short name T133
Test name
Test status
Simulation time 40904703296 ps
CPU time 64.14 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 182808 kb
Host smart-ee8bea5f-1ef7-40c8-8138-6bf3cb35f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767494762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3767494762
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3881552447
Short name T131
Test name
Test status
Simulation time 521879669 ps
CPU time 1.33 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:09:40 PM PST 23
Peak memory 182604 kb
Host smart-a54a6ab0-5957-4e9d-86c9-e44335544d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881552447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3881552447
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2268192670
Short name T239
Test name
Test status
Simulation time 150324437224 ps
CPU time 106.85 seconds
Started Dec 24 01:09:30 PM PST 23
Finished Dec 24 01:11:22 PM PST 23
Peak memory 182836 kb
Host smart-05086776-07f7-4231-a79f-bbc3b3d1a11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268192670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2268192670
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.4193997362
Short name T45
Test name
Test status
Simulation time 182397089891 ps
CPU time 329.69 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:15:06 PM PST 23
Peak memory 197636 kb
Host smart-dd5a53b9-2e3e-482d-8e72-5e6097b17f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193997362 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.4193997362
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2957816566
Short name T153
Test name
Test status
Simulation time 573918561 ps
CPU time 0.75 seconds
Started Dec 24 01:09:41 PM PST 23
Finished Dec 24 01:09:49 PM PST 23
Peak memory 182592 kb
Host smart-04677f2c-02bf-428b-a0bc-eaafd76d5790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957816566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2957816566
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1099332179
Short name T113
Test name
Test status
Simulation time 7886674210 ps
CPU time 3.42 seconds
Started Dec 24 01:09:40 PM PST 23
Finished Dec 24 01:09:51 PM PST 23
Peak memory 182748 kb
Host smart-8672206c-61ce-4d09-8346-9f9bf17500db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099332179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1099332179
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.327228188
Short name T211
Test name
Test status
Simulation time 554403228 ps
CPU time 0.84 seconds
Started Dec 24 01:09:52 PM PST 23
Finished Dec 24 01:09:58 PM PST 23
Peak memory 182716 kb
Host smart-56d7a59f-05eb-4a09-9a56-3a9451fc3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327228188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.327228188
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1929732376
Short name T72
Test name
Test status
Simulation time 380240730799 ps
CPU time 590.82 seconds
Started Dec 24 01:09:31 PM PST 23
Finished Dec 24 01:19:26 PM PST 23
Peak memory 182832 kb
Host smart-cedb7ebc-5000-4417-893a-4a5945f3d03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929732376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1929732376
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.655475536
Short name T40
Test name
Test status
Simulation time 43106924931 ps
CPU time 123.48 seconds
Started Dec 24 01:09:32 PM PST 23
Finished Dec 24 01:11:42 PM PST 23
Peak memory 197724 kb
Host smart-b25d088d-dec4-458f-b97b-a92268769461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655475536 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.655475536
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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