Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.16 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 4 137 97.16


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 0 34 100.00 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 29172 1 T20 11 T21 346 T22 408
bark[1] 680 1 T33 31 T98 126 T103 16
bark[2] 827 1 T24 16 T98 22 T101 38
bark[3] 443 1 T50 16 T43 221 T100 17
bark[4] 509 1 T22 72 T109 16 T102 82
bark[5] 345 1 T50 12 T110 117 T111 22
bark[6] 502 1 T112 17 T113 12 T110 51
bark[7] 425 1 T26 43 T114 16 T102 92
bark[8] 839 1 T100 163 T115 202 T114 17
bark[9] 351 1 T24 16 T50 98 T116 13
bark[10] 440 1 T117 16 T118 16 T119 21
bark[11] 430 1 T21 39 T32 26 T101 17
bark[12] 204 1 T33 27 T43 16 T120 35
bark[13] 239 1 T38 53 T33 17 T110 16
bark[14] 699 1 T115 12 T121 16 T122 12
bark[15] 569 1 T111 37 T123 12 T124 12
bark[16] 500 1 T100 16 T101 51 T121 16
bark[17] 354 1 T21 84 T40 13 T32 41
bark[18] 484 1 T12 12 T33 16 T101 21
bark[19] 854 1 T33 16 T125 17 T111 132
bark[20] 314 1 T26 32 T121 16 T126 32
bark[21] 419 1 T39 13 T100 88 T117 16
bark[22] 441 1 T38 16 T127 12 T112 35
bark[23] 301 1 T24 57 T32 25 T101 69
bark[24] 740 1 T22 16 T115 251 T128 16
bark[25] 333 1 T117 16 T129 16 T130 26
bark[26] 300 1 T22 47 T26 26 T111 16
bark[27] 547 1 T22 16 T100 186 T131 12
bark[28] 776 1 T22 3 T110 6 T132 219
bark[29] 694 1 T38 133 T133 12 T134 16
bark[30] 385 1 T13 12 T21 16 T23 49
bark[31] 631 1 T24 22 T50 21 T135 12
bark_0 3758 1 T7 6 T14 6 T15 6


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28645 1 T20 10 T21 338 T22 402
bite[1] 512 1 T50 21 T120 16 T126 17
bite[2] 347 1 T26 43 T111 125 T117 16
bite[3] 259 1 T22 71 T133 11 T102 77
bite[4] 376 1 T26 26 T100 167 T101 37
bite[5] 870 1 T101 17 T115 201 T136 68
bite[6] 480 1 T112 17 T134 17 T137 163
bite[7] 246 1 T138 16 T109 16 T120 34
bite[8] 364 1 T32 41 T100 185 T113 11
bite[9] 666 1 T22 46 T139 11 T140 11
bite[10] 403 1 T21 99 T24 16 T26 32
bite[11] 224 1 T98 21 T138 16 T103 47
bite[12] 445 1 T43 220 T112 35 T129 16
bite[13] 524 1 T12 11 T134 16 T132 218
bite[14] 507 1 T32 25 T110 5 T128 16
bite[15] 791 1 T23 48 T24 21 T38 52
bite[16] 281 1 T111 22 T141 31 T142 16
bite[17] 594 1 T110 16 T117 16 T134 16
bite[18] 472 1 T22 16 T38 132 T39 12
bite[19] 903 1 T100 87 T109 16 T121 16
bite[20] 1079 1 T21 16 T125 17 T101 116
bite[21] 715 1 T21 23 T43 16 T100 26
bite[22] 310 1 T50 16 T101 21 T103 48
bite[23] 677 1 T22 2 T33 31 T115 250
bite[24] 464 1 T24 56 T33 16 T50 11
bite[25] 322 1 T111 36 T143 11 T130 22
bite[26] 514 1 T22 16 T50 98 T121 20
bite[27] 249 1 T13 11 T24 16 T110 50
bite[28] 584 1 T100 17 T135 11 T101 199
bite[29] 295 1 T38 16 T131 11 T117 16
bite[30] 607 1 T33 17 T111 16 T114 17
bite[31] 485 1 T33 27 T112 17 T98 16
bite_0 4295 1 T7 6 T14 6 T15 6


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 48505 1 T7 6 T14 6 T15 6


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 0 34 100.00


User Defined Bins for prescale_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale_max 56 1 T144 15 T145 41 - -
prescale[0] 1430 1 T26 8 T33 15 T43 21
prescale[1] 920 1 T22 16 T23 15 T38 34
prescale[2] 915 1 T43 72 T100 31 T146 8
prescale[3] 662 1 T43 71 T109 15 T111 46
prescale[4] 1015 1 T111 2 T117 15 T120 88
prescale[5] 802 1 T22 2 T26 47 T38 15
prescale[6] 639 1 T43 31 T111 4 T115 29
prescale[7] 865 1 T20 8 T110 18 T117 18
prescale[8] 603 1 T21 2 T22 37 T23 2
prescale[9] 515 1 T21 16 T100 58 T147 8
prescale[10] 585 1 T21 18 T24 2 T112 8
prescale[11] 1024 1 T21 87 T22 28 T33 15
prescale[12] 829 1 T23 2 T100 24 T110 28
prescale[13] 1054 1 T24 4 T38 2 T148 8
prescale[14] 630 1 T23 16 T24 2 T38 67
prescale[15] 607 1 T21 2 T24 2 T33 77
prescale[16] 657 1 T43 2 T112 15 T110 16
prescale[17] 730 1 T21 2 T24 15 T26 20
prescale[18] 871 1 T21 70 T26 15 T43 15
prescale[19] 624 1 T22 24 T33 18 T111 77
prescale[20] 626 1 T100 2 T149 8 T98 16
prescale[21] 848 1 T21 2 T22 159 T43 2
prescale[22] 443 1 T21 15 T43 63 T111 16
prescale[23] 655 1 T21 2 T23 25 T112 38
prescale[24] 863 1 T24 2 T38 45 T100 46
prescale[25] 576 1 T26 27 T43 15 T110 18
prescale[26] 908 1 T38 12 T43 15 T112 15
prescale[27] 655 1 T110 26 T125 24 T101 136
prescale[28] 532 1 T22 4 T23 30 T24 2
prescale[29] 572 1 T38 15 T43 2 T111 2
prescale[30] 834 1 T50 69 T112 24 T101 17
prescale[31] 1310 1 T138 40 T109 52 T129 48
prescale_0 23706 1 T7 6 T14 6 T15 6


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36532 1 T7 6 T14 6 T15 6
auto[1] 11973 1 T21 173 T22 124 T23 42


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 48505 1 T7 6 T14 6 T15 6


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28935 1 T20 12 T21 285 T22 323
wkup[1] 477 1 T22 25 T50 13 T110 16
wkup[2] 449 1 T21 16 T22 4 T24 22
wkup[3] 536 1 T22 58 T38 7 T33 27
wkup[4] 755 1 T33 16 T50 37 T112 17
wkup[5] 412 1 T50 16 T113 13 T98 7
wkup[6] 569 1 T21 23 T26 16 T38 16
wkup[7] 465 1 T22 16 T43 32 T117 16
wkup[8] 594 1 T23 16 T32 26 T100 16
wkup[9] 650 1 T22 16 T38 16 T100 16
wkup[10] 557 1 T24 16 T33 32 T100 37
wkup[11] 644 1 T13 13 T21 31 T38 32
wkup[12] 503 1 T21 28 T22 16 T38 48
wkup[13] 733 1 T38 16 T100 16 T98 16
wkup[14] 508 1 T38 41 T100 16 T110 16
wkup[15] 400 1 T26 26 T115 7 T139 13
wkup[16] 680 1 T22 7 T112 16 T100 17
wkup[17] 502 1 T22 16 T24 16 T38 16
wkup[18] 769 1 T21 23 T22 16 T38 16
wkup[19] 386 1 T43 26 T101 16 T103 45
wkup[20] 596 1 T38 16 T98 26 T101 16
wkup[21] 460 1 T21 27 T39 14 T100 22
wkup[22] 464 1 T22 13 T33 32 T43 16
wkup[23] 500 1 T110 16 T98 26 T101 16
wkup[24] 394 1 T22 16 T110 16 T101 16
wkup[25] 531 1 T32 16 T43 16 T110 7
wkup[26] 362 1 T22 13 T24 16 T38 16
wkup[27] 517 1 T21 16 T22 16 T110 32
wkup[28] 470 1 T12 13 T21 16 T24 17
wkup[29] 402 1 T21 16 T22 16 T38 22
wkup[30] 457 1 T40 14 T32 25 T115 22
wkup[31] 566 1 T21 16 T26 16 T98 16
wkup_0 3262 1 T7 6 T14 6 T15 6

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