Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.61 99.82 95.32 100.00 99.35 100.00 97.16


Total test records in report: 429
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T282 /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4184233766 Dec 27 12:28:16 PM PST 23 Dec 27 12:31:17 PM PST 23 79334919437 ps
T283 /workspace/coverage/default/28.aon_timer_prescaler.4246021734 Dec 27 12:25:18 PM PST 23 Dec 27 12:26:30 PM PST 23 35423284402 ps
T284 /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3381828330 Dec 27 12:28:49 PM PST 23 Dec 27 12:34:42 PM PST 23 38398293689 ps
T285 /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.207658603 Dec 27 12:25:34 PM PST 23 Dec 27 12:31:44 PM PST 23 130663217717 ps
T286 /workspace/coverage/default/42.aon_timer_prescaler.2194698673 Dec 27 12:26:23 PM PST 23 Dec 27 12:26:43 PM PST 23 12588614304 ps
T287 /workspace/coverage/default/15.aon_timer_prescaler.1840454873 Dec 27 12:26:22 PM PST 23 Dec 27 12:26:58 PM PST 23 31687277173 ps
T288 /workspace/coverage/default/8.aon_timer_prescaler.4174067922 Dec 27 12:24:55 PM PST 23 Dec 27 12:25:09 PM PST 23 31589846764 ps
T289 /workspace/coverage/default/27.aon_timer_stress_all.901968483 Dec 27 12:25:35 PM PST 23 Dec 27 12:30:37 PM PST 23 174070537170 ps
T290 /workspace/coverage/default/10.aon_timer_prescaler.3298614354 Dec 27 12:26:46 PM PST 23 Dec 27 12:27:11 PM PST 23 4621960571 ps
T291 /workspace/coverage/default/8.aon_timer_jump.4192599707 Dec 27 12:24:55 PM PST 23 Dec 27 12:24:58 PM PST 23 369904728 ps
T292 /workspace/coverage/default/49.aon_timer_smoke.2041609388 Dec 27 12:26:00 PM PST 23 Dec 27 12:26:08 PM PST 23 558620817 ps
T293 /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4079028568 Dec 27 12:26:21 PM PST 23 Dec 27 12:34:51 PM PST 23 80811401732 ps
T294 /workspace/coverage/default/9.aon_timer_smoke.3205586945 Dec 27 12:25:23 PM PST 23 Dec 27 12:25:33 PM PST 23 498612181 ps
T295 /workspace/coverage/default/23.aon_timer_prescaler.965456556 Dec 27 12:21:18 PM PST 23 Dec 27 12:21:24 PM PST 23 13400742012 ps
T296 /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3887206117 Dec 27 12:21:53 PM PST 23 Dec 27 12:28:39 PM PST 23 233137863501 ps
T297 /workspace/coverage/default/26.aon_timer_prescaler.2164327709 Dec 27 12:24:08 PM PST 23 Dec 27 12:24:11 PM PST 23 7020298332 ps
T298 /workspace/coverage/default/38.aon_timer_smoke.312704570 Dec 27 12:26:17 PM PST 23 Dec 27 12:26:31 PM PST 23 583553540 ps
T299 /workspace/coverage/default/3.aon_timer_stress_all.3812914568 Dec 27 12:27:03 PM PST 23 Dec 27 12:29:39 PM PST 23 251419341932 ps
T37 /workspace/coverage/default/0.aon_timer_sec_cm.1686242009 Dec 27 12:27:30 PM PST 23 Dec 27 12:28:07 PM PST 23 7081161056 ps
T300 /workspace/coverage/default/33.aon_timer_smoke.1060257096 Dec 27 12:24:33 PM PST 23 Dec 27 12:24:36 PM PST 23 641315496 ps
T301 /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3143010795 Dec 27 12:26:35 PM PST 23 Dec 27 12:29:57 PM PST 23 45894850130 ps
T302 /workspace/coverage/default/28.aon_timer_smoke.1652173402 Dec 27 12:26:08 PM PST 23 Dec 27 12:26:18 PM PST 23 407390552 ps
T303 /workspace/coverage/default/36.aon_timer_jump.516299257 Dec 27 12:28:06 PM PST 23 Dec 27 12:28:42 PM PST 23 456969672 ps
T304 /workspace/coverage/default/19.aon_timer_jump.3051661191 Dec 27 12:26:26 PM PST 23 Dec 27 12:26:41 PM PST 23 438673992 ps
T305 /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1152550969 Dec 27 12:28:41 PM PST 23 Dec 27 12:36:00 PM PST 23 107179478341 ps
T306 /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3148441653 Dec 27 12:27:16 PM PST 23 Dec 27 12:32:16 PM PST 23 35738886699 ps
T307 /workspace/coverage/default/17.aon_timer_stress_all.3965856786 Dec 27 12:27:16 PM PST 23 Dec 27 12:29:15 PM PST 23 184301969628 ps
T308 /workspace/coverage/default/1.aon_timer_jump.2724522565 Dec 27 12:28:27 PM PST 23 Dec 27 12:29:16 PM PST 23 493459895 ps
T309 /workspace/coverage/default/48.aon_timer_smoke.989089685 Dec 27 12:28:43 PM PST 23 Dec 27 12:29:37 PM PST 23 364601574 ps
T310 /workspace/coverage/default/44.aon_timer_jump.752766576 Dec 27 12:27:39 PM PST 23 Dec 27 12:28:11 PM PST 23 544758348 ps
T311 /workspace/coverage/default/12.aon_timer_prescaler.3555250091 Dec 27 12:26:32 PM PST 23 Dec 27 12:27:03 PM PST 23 20398516716 ps
T312 /workspace/coverage/default/1.aon_timer_smoke.3304396294 Dec 27 12:28:44 PM PST 23 Dec 27 12:29:37 PM PST 23 445609009 ps
T313 /workspace/coverage/default/48.aon_timer_prescaler.2943000973 Dec 27 12:22:46 PM PST 23 Dec 27 12:23:03 PM PST 23 36220310108 ps
T314 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.829294337 Dec 27 12:34:24 PM PST 23 Dec 27 12:34:42 PM PST 23 471617720 ps
T315 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.919858061 Dec 27 12:34:49 PM PST 23 Dec 27 12:35:11 PM PST 23 346571926 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1652653567 Dec 27 12:33:38 PM PST 23 Dec 27 12:33:54 PM PST 23 516647314 ps
T91 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.767960288 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:06 PM PST 23 1046873886 ps
T92 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1722389281 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:30 PM PST 23 1026382779 ps
T64 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1734880591 Dec 27 12:34:41 PM PST 23 Dec 27 12:35:00 PM PST 23 479205088 ps
T316 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1796401881 Dec 27 12:33:42 PM PST 23 Dec 27 12:33:58 PM PST 23 380056360 ps
T93 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1861724591 Dec 27 12:33:45 PM PST 23 Dec 27 12:34:03 PM PST 23 1583647510 ps
T317 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.628243004 Dec 27 12:33:55 PM PST 23 Dec 27 12:34:12 PM PST 23 511967883 ps
T94 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1733188858 Dec 27 12:33:30 PM PST 23 Dec 27 12:33:52 PM PST 23 1146863863 ps
T318 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1704637343 Dec 27 12:33:50 PM PST 23 Dec 27 12:34:07 PM PST 23 445667203 ps
T319 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3768509988 Dec 27 12:34:47 PM PST 23 Dec 27 12:35:08 PM PST 23 590158632 ps
T320 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.390996004 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:34 PM PST 23 333027516 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.838878827 Dec 27 12:34:36 PM PST 23 Dec 27 12:34:55 PM PST 23 685844946 ps
T322 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1165971926 Dec 27 12:33:51 PM PST 23 Dec 27 12:34:08 PM PST 23 505341610 ps
T323 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4023966031 Dec 27 12:34:05 PM PST 23 Dec 27 12:34:21 PM PST 23 353112968 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1001198336 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:13 PM PST 23 375947944 ps
T325 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.137032373 Dec 27 12:33:38 PM PST 23 Dec 27 12:33:54 PM PST 23 516615056 ps
T95 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1015046873 Dec 27 12:33:42 PM PST 23 Dec 27 12:34:01 PM PST 23 2288882152 ps
T106 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3940068806 Dec 27 12:34:23 PM PST 23 Dec 27 12:34:52 PM PST 23 8869819914 ps
T65 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2893458936 Dec 27 12:34:09 PM PST 23 Dec 27 12:34:24 PM PST 23 330785163 ps
T71 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2562932858 Dec 27 12:34:09 PM PST 23 Dec 27 12:34:24 PM PST 23 422342285 ps
T66 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1336891744 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:13 PM PST 23 427229699 ps
T72 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1785819487 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:38 PM PST 23 339573238 ps
T73 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4117298903 Dec 27 12:34:02 PM PST 23 Dec 27 12:34:23 PM PST 23 8349002254 ps
T74 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.202984727 Dec 27 12:33:54 PM PST 23 Dec 27 12:34:10 PM PST 23 555225844 ps
T326 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2135052544 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 332634407 ps
T327 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1606216334 Dec 27 12:35:23 PM PST 23 Dec 27 12:35:39 PM PST 23 438824278 ps
T328 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4053495295 Dec 27 12:33:53 PM PST 23 Dec 27 12:34:10 PM PST 23 326237356 ps
T329 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2345326721 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:05 PM PST 23 601725942 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4014737112 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:05 PM PST 23 427044674 ps
T331 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1395637967 Dec 27 12:34:18 PM PST 23 Dec 27 12:34:48 PM PST 23 6119268102 ps
T332 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.5674508 Dec 27 12:34:34 PM PST 23 Dec 27 12:34:52 PM PST 23 319637317 ps
T333 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1662224471 Dec 27 12:34:35 PM PST 23 Dec 27 12:34:54 PM PST 23 704650914 ps
T107 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3993881862 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:24 PM PST 23 4522109859 ps
T334 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.858015468 Dec 27 12:34:46 PM PST 23 Dec 27 12:35:06 PM PST 23 441106681 ps
T335 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3285679708 Dec 27 12:33:44 PM PST 23 Dec 27 12:34:00 PM PST 23 667833549 ps
T336 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3162173221 Dec 27 12:34:35 PM PST 23 Dec 27 12:34:53 PM PST 23 690357005 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1106054733 Dec 27 12:34:50 PM PST 23 Dec 27 12:35:13 PM PST 23 521888519 ps
T338 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3194746876 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:34 PM PST 23 277164233 ps
T67 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3381685448 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:14 PM PST 23 398258072 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2310125859 Dec 27 12:34:45 PM PST 23 Dec 27 12:35:09 PM PST 23 8563817475 ps
T68 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.578029323 Dec 27 12:34:49 PM PST 23 Dec 27 12:35:11 PM PST 23 1102295074 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2609283790 Dec 27 12:34:09 PM PST 23 Dec 27 12:34:25 PM PST 23 266925109 ps
T96 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1063527028 Dec 27 12:33:46 PM PST 23 Dec 27 12:34:06 PM PST 23 1503912331 ps
T69 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.576265145 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 452625121 ps
T341 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1817957725 Dec 27 12:33:37 PM PST 23 Dec 27 12:33:53 PM PST 23 464393775 ps
T342 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1255926628 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:23 PM PST 23 433991175 ps
T343 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1039579625 Dec 27 12:34:09 PM PST 23 Dec 27 12:34:24 PM PST 23 370073627 ps
T344 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1367087718 Dec 27 12:34:22 PM PST 23 Dec 27 12:34:40 PM PST 23 469522289 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.55974197 Dec 27 12:33:43 PM PST 23 Dec 27 12:34:01 PM PST 23 1940024270 ps
T70 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3131143523 Dec 27 12:33:39 PM PST 23 Dec 27 12:33:55 PM PST 23 318913289 ps
T75 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3848687722 Dec 27 12:33:43 PM PST 23 Dec 27 12:34:01 PM PST 23 8198807913 ps
T76 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1012062358 Dec 27 12:34:28 PM PST 23 Dec 27 12:34:45 PM PST 23 267637030 ps
T346 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1633445976 Dec 27 12:34:02 PM PST 23 Dec 27 12:34:17 PM PST 23 1047752858 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.446551790 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:05 PM PST 23 646691114 ps
T348 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3726850593 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:29 PM PST 23 501909942 ps
T349 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.637670023 Dec 27 12:33:59 PM PST 23 Dec 27 12:34:18 PM PST 23 2080549807 ps
T350 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3752658949 Dec 27 12:34:20 PM PST 23 Dec 27 12:34:38 PM PST 23 374129679 ps
T351 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1725632602 Dec 27 12:33:57 PM PST 23 Dec 27 12:34:14 PM PST 23 392326838 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1675505506 Dec 27 12:33:35 PM PST 23 Dec 27 12:33:52 PM PST 23 320958211 ps
T353 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1725229205 Dec 27 12:34:04 PM PST 23 Dec 27 12:34:19 PM PST 23 282952621 ps
T354 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3573676046 Dec 27 12:34:18 PM PST 23 Dec 27 12:34:36 PM PST 23 528294772 ps
T77 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4258965939 Dec 27 12:33:51 PM PST 23 Dec 27 12:34:08 PM PST 23 349304779 ps
T355 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3011205025 Dec 27 12:34:05 PM PST 23 Dec 27 12:34:21 PM PST 23 396423363 ps
T356 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2175958667 Dec 27 12:33:51 PM PST 23 Dec 27 12:34:08 PM PST 23 461736220 ps
T357 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.789929901 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 568910527 ps
T358 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1299524633 Dec 27 12:34:22 PM PST 23 Dec 27 12:34:39 PM PST 23 594678727 ps
T359 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2537352248 Dec 27 12:34:31 PM PST 23 Dec 27 12:34:48 PM PST 23 364587111 ps
T360 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2937746027 Dec 27 12:34:14 PM PST 23 Dec 27 12:34:31 PM PST 23 454920946 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1586367731 Dec 27 12:34:37 PM PST 23 Dec 27 12:35:24 PM PST 23 11482320110 ps
T361 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.504498737 Dec 27 12:34:18 PM PST 23 Dec 27 12:34:35 PM PST 23 417050642 ps
T362 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3358551166 Dec 27 12:33:43 PM PST 23 Dec 27 12:33:59 PM PST 23 485648269 ps
T363 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.587416107 Dec 27 12:34:07 PM PST 23 Dec 27 12:34:24 PM PST 23 639169078 ps
T364 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2994177629 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:05 PM PST 23 553111263 ps
T365 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2350833016 Dec 27 12:34:09 PM PST 23 Dec 27 12:34:25 PM PST 23 433287773 ps
T366 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3351744445 Dec 27 12:34:36 PM PST 23 Dec 27 12:35:00 PM PST 23 4260515551 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1922541884 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:23 PM PST 23 299459936 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1753880505 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:34 PM PST 23 1179418431 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2266503150 Dec 27 12:33:44 PM PST 23 Dec 27 12:34:14 PM PST 23 9619202164 ps
T369 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3927874734 Dec 27 12:34:27 PM PST 23 Dec 27 12:34:44 PM PST 23 529730097 ps
T370 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.451786318 Dec 27 12:33:55 PM PST 23 Dec 27 12:34:11 PM PST 23 565304147 ps
T371 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1612792406 Dec 27 12:33:50 PM PST 23 Dec 27 12:34:08 PM PST 23 447814594 ps
T372 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4020602123 Dec 27 12:33:41 PM PST 23 Dec 27 12:33:58 PM PST 23 519531994 ps
T108 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4284920587 Dec 27 12:34:39 PM PST 23 Dec 27 12:35:01 PM PST 23 7879982227 ps
T373 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1432445612 Dec 27 12:34:04 PM PST 23 Dec 27 12:34:19 PM PST 23 497810030 ps
T374 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3211578976 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:20 PM PST 23 4499633435 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3481602011 Dec 27 12:34:35 PM PST 23 Dec 27 12:34:59 PM PST 23 4374593060 ps
T376 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.135396169 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:18 PM PST 23 8014209817 ps
T80 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2611018486 Dec 27 12:34:19 PM PST 23 Dec 27 12:34:36 PM PST 23 592642107 ps
T377 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.797678042 Dec 27 12:34:36 PM PST 23 Dec 27 12:34:54 PM PST 23 510489831 ps
T378 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1089884281 Dec 27 12:34:47 PM PST 23 Dec 27 12:35:07 PM PST 23 384065280 ps
T379 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4128621240 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:05 PM PST 23 447712725 ps
T380 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1681404792 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:34 PM PST 23 295087594 ps
T81 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1500650750 Dec 27 12:34:23 PM PST 23 Dec 27 12:34:42 PM PST 23 464044387 ps
T381 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3671649925 Dec 27 12:34:47 PM PST 23 Dec 27 12:35:07 PM PST 23 332164166 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1453943384 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:14 PM PST 23 1876814319 ps
T383 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.709243546 Dec 27 12:35:38 PM PST 23 Dec 27 12:35:53 PM PST 23 290536849 ps
T384 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1252864850 Dec 27 12:34:30 PM PST 23 Dec 27 12:34:48 PM PST 23 515023993 ps
T82 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4108613116 Dec 27 12:33:58 PM PST 23 Dec 27 12:34:13 PM PST 23 333610189 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.909328163 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:34 PM PST 23 325631140 ps
T386 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3068914927 Dec 27 12:35:06 PM PST 23 Dec 27 12:35:33 PM PST 23 6139962630 ps
T387 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1862243706 Dec 27 12:33:54 PM PST 23 Dec 27 12:34:10 PM PST 23 467714145 ps
T388 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1582864842 Dec 27 12:34:13 PM PST 23 Dec 27 12:34:30 PM PST 23 388106593 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1911009756 Dec 27 12:33:32 PM PST 23 Dec 27 12:33:52 PM PST 23 397641373 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4243681642 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:04 PM PST 23 490308687 ps
T391 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2331026009 Dec 27 12:34:01 PM PST 23 Dec 27 12:34:16 PM PST 23 404537409 ps
T392 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1769201021 Dec 27 12:34:41 PM PST 23 Dec 27 12:34:59 PM PST 23 343187608 ps
T393 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.407592941 Dec 27 12:33:41 PM PST 23 Dec 27 12:33:58 PM PST 23 1426825440 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4079001699 Dec 27 12:34:07 PM PST 23 Dec 27 12:34:24 PM PST 23 459795731 ps
T395 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.676956611 Dec 27 12:34:16 PM PST 23 Dec 27 12:34:37 PM PST 23 2204116882 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1048251404 Dec 27 12:33:41 PM PST 23 Dec 27 12:33:57 PM PST 23 371322374 ps
T397 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.443208005 Dec 27 12:33:54 PM PST 23 Dec 27 12:34:28 PM PST 23 8403421307 ps
T398 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.847576965 Dec 27 12:33:48 PM PST 23 Dec 27 12:34:04 PM PST 23 495554173 ps
T399 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3417300423 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:19 PM PST 23 8146159566 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1296363955 Dec 27 12:34:44 PM PST 23 Dec 27 12:35:04 PM PST 23 616698515 ps
T401 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.915737787 Dec 27 12:33:42 PM PST 23 Dec 27 12:34:01 PM PST 23 1314321347 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1824509941 Dec 27 12:34:03 PM PST 23 Dec 27 12:34:21 PM PST 23 8851423218 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3984979076 Dec 27 12:34:04 PM PST 23 Dec 27 12:34:21 PM PST 23 853168067 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1003823042 Dec 27 12:34:41 PM PST 23 Dec 27 12:34:59 PM PST 23 305464905 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2643060521 Dec 27 12:33:42 PM PST 23 Dec 27 12:33:59 PM PST 23 455893486 ps
T406 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3549641213 Dec 27 12:34:30 PM PST 23 Dec 27 12:34:48 PM PST 23 264237396 ps
T407 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1814958827 Dec 27 12:35:03 PM PST 23 Dec 27 12:35:22 PM PST 23 987840097 ps
T408 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2672003641 Dec 27 12:34:42 PM PST 23 Dec 27 12:35:02 PM PST 23 1049459254 ps
T409 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2876627340 Dec 27 12:33:49 PM PST 23 Dec 27 12:34:06 PM PST 23 556691855 ps
T410 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.384515664 Dec 27 12:35:33 PM PST 23 Dec 27 12:35:46 PM PST 23 296542696 ps
T411 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.975868067 Dec 27 12:34:01 PM PST 23 Dec 27 12:34:17 PM PST 23 488599126 ps
T412 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1393767719 Dec 27 12:34:13 PM PST 23 Dec 27 12:34:31 PM PST 23 348848293 ps
T413 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.368209213 Dec 27 12:34:30 PM PST 23 Dec 27 12:34:48 PM PST 23 467967154 ps
T105 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2112788979 Dec 27 12:34:44 PM PST 23 Dec 27 12:35:09 PM PST 23 8163282382 ps
T414 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.930700934 Dec 27 12:34:36 PM PST 23 Dec 27 12:34:54 PM PST 23 1322948025 ps
T415 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3180051753 Dec 27 12:34:10 PM PST 23 Dec 27 12:34:28 PM PST 23 385463656 ps
T416 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.83387296 Dec 27 12:34:32 PM PST 23 Dec 27 12:34:49 PM PST 23 353231618 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2126733550 Dec 27 12:34:06 PM PST 23 Dec 27 12:34:23 PM PST 23 490187939 ps
T418 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3189483836 Dec 27 12:34:19 PM PST 23 Dec 27 12:34:37 PM PST 23 342967223 ps
T419 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1392749498 Dec 27 12:34:19 PM PST 23 Dec 27 12:34:42 PM PST 23 4634449713 ps
T420 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3737071136 Dec 27 12:34:02 PM PST 23 Dec 27 12:34:17 PM PST 23 481483382 ps
T421 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1799107069 Dec 27 12:34:12 PM PST 23 Dec 27 12:34:31 PM PST 23 1086864921 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3287040425 Dec 27 12:33:39 PM PST 23 Dec 27 12:33:55 PM PST 23 562497950 ps
T423 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1643803514 Dec 27 12:33:56 PM PST 23 Dec 27 12:34:12 PM PST 23 394635040 ps
T424 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1321319533 Dec 27 12:33:47 PM PST 23 Dec 27 12:34:04 PM PST 23 393013605 ps
T425 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3227600257 Dec 27 12:35:13 PM PST 23 Dec 27 12:35:31 PM PST 23 457447440 ps
T426 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2264026421 Dec 27 12:34:40 PM PST 23 Dec 27 12:34:59 PM PST 23 320600554 ps
T427 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3570565091 Dec 27 12:33:44 PM PST 23 Dec 27 12:33:59 PM PST 23 524377597 ps
T428 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1482219862 Dec 27 12:34:49 PM PST 23 Dec 27 12:35:10 PM PST 23 512052765 ps
T429 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4239816361 Dec 27 12:34:36 PM PST 23 Dec 27 12:34:54 PM PST 23 490183020 ps

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3291669463
Short name T1
Test name
Test status
Simulation time 8221812731 ps
CPU time 2.54 seconds
Started Dec 27 12:33:52 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 197576 kb
Host smart-d6d4ea2d-7892-46df-9fbb-33d428cd392a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291669463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3291669463
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3264047392
Short name T22
Test name
Test status
Simulation time 147187091530 ps
CPU time 210.5 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:31:26 PM PST 23
Peak memory 195828 kb
Host smart-cb88f030-164f-4698-9e30-9bab322766c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264047392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3264047392
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1177509585
Short name T100
Test name
Test status
Simulation time 103221498374 ps
CPU time 173.65 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:32:26 PM PST 23
Peak memory 197296 kb
Host smart-6142d01d-649e-4a44-adc3-dd143b286634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177509585 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1177509585
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.885501039
Short name T111
Test name
Test status
Simulation time 262830414547 ps
CPU time 702.97 seconds
Started Dec 27 12:28:33 PM PST 23
Finished Dec 27 12:41:06 PM PST 23
Peak memory 199764 kb
Host smart-7053ea64-c975-4545-bad6-ec9966ded4c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885501039 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.885501039
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3168828556
Short name T18
Test name
Test status
Simulation time 962311489 ps
CPU time 2.67 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:07 PM PST 23
Peak memory 198644 kb
Host smart-06c3a43f-d9ff-45fd-8f6d-97172f332504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168828556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3168828556
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1633038976
Short name T115
Test name
Test status
Simulation time 2329733705241 ps
CPU time 1248.91 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:50:48 PM PST 23
Peak memory 213632 kb
Host smart-b37f8006-bc49-4dc8-a9f4-29bb9b39e9c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633038976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1633038976
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1396262590
Short name T33
Test name
Test status
Simulation time 323123985051 ps
CPU time 119.44 seconds
Started Dec 27 12:27:18 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 182444 kb
Host smart-66595cf1-12c4-435e-a9f7-ab4a5332bd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396262590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1396262590
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1974226980
Short name T61
Test name
Test status
Simulation time 124963803096 ps
CPU time 626.06 seconds
Started Dec 27 12:24:59 PM PST 23
Finished Dec 27 12:35:28 PM PST 23
Peak memory 199184 kb
Host smart-760ba394-e6eb-44fb-8bcf-b030324dec44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974226980 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1974226980
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3527233569
Short name T13
Test name
Test status
Simulation time 611426807 ps
CPU time 1.45 seconds
Started Dec 27 12:22:04 PM PST 23
Finished Dec 27 12:22:06 PM PST 23
Peak memory 182708 kb
Host smart-898cd173-6395-4a51-83e0-7df427c62f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527233569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3527233569
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2424223008
Short name T103
Test name
Test status
Simulation time 292176589064 ps
CPU time 537.6 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:37:52 PM PST 23
Peak memory 196488 kb
Host smart-7079f543-e1da-4cc4-b91e-ae77226855b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424223008 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2424223008
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1686242009
Short name T37
Test name
Test status
Simulation time 7081161056 ps
CPU time 7.48 seconds
Started Dec 27 12:27:30 PM PST 23
Finished Dec 27 12:28:07 PM PST 23
Peak memory 214368 kb
Host smart-185e02c4-fe06-4c03-ad57-6cc8a9c87d49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686242009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1686242009
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.818671635
Short name T117
Test name
Test status
Simulation time 105959350330 ps
CPU time 41.31 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:30:14 PM PST 23
Peak memory 182392 kb
Host smart-391c6d10-8227-4368-bbec-bef81b0b49df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818671635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_a
ll.818671635
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2092970501
Short name T24
Test name
Test status
Simulation time 27856799948 ps
CPU time 157.63 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:31:54 PM PST 23
Peak memory 197256 kb
Host smart-77360b41-0fad-4f73-8df4-fe19945ef952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092970501 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2092970501
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3648838327
Short name T205
Test name
Test status
Simulation time 329655535948 ps
CPU time 448.22 seconds
Started Dec 27 12:26:38 PM PST 23
Finished Dec 27 12:34:25 PM PST 23
Peak memory 182724 kb
Host smart-d533aef4-b494-4c72-b0c6-94711532da03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648838327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3648838327
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3848687722
Short name T75
Test name
Test status
Simulation time 8198807913 ps
CPU time 2.31 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:34:01 PM PST 23
Peak memory 197492 kb
Host smart-d1570b21-3e3a-47ea-8e00-a109f4472e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848687722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3848687722
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1336891744
Short name T66
Test name
Test status
Simulation time 427229699 ps
CPU time 0.66 seconds
Started Dec 27 12:33:56 PM PST 23
Finished Dec 27 12:34:13 PM PST 23
Peak memory 193040 kb
Host smart-838e28dc-a4b5-4d73-8ef9-cbbaf0b2cabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336891744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1336891744
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1598983864
Short name T236
Test name
Test status
Simulation time 245948472842 ps
CPU time 22.25 seconds
Started Dec 27 12:20:27 PM PST 23
Finished Dec 27 12:20:51 PM PST 23
Peak memory 182368 kb
Host smart-abca3fc3-0b97-40f6-be0c-f106680ed477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598983864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1598983864
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3616333317
Short name T145
Test name
Test status
Simulation time 114081425487 ps
CPU time 170.1 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 197296 kb
Host smart-fc68241d-595b-4602-9cdc-919b0bf5a02d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616333317 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3616333317
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1770546323
Short name T17
Test name
Test status
Simulation time 1292211063 ps
CPU time 2.38 seconds
Started Dec 27 12:34:06 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183732 kb
Host smart-f6c50714-611c-4c97-92f2-1b36390a41f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770546323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1770546323
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1652653567
Short name T63
Test name
Test status
Simulation time 516647314 ps
CPU time 1.07 seconds
Started Dec 27 12:33:38 PM PST 23
Finished Dec 27 12:33:54 PM PST 23
Peak memory 183816 kb
Host smart-1b8ca353-e8a1-497b-b16d-9b36b66098e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652653567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1652653567
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.2266503150
Short name T79
Test name
Test status
Simulation time 9619202164 ps
CPU time 14.93 seconds
Started Dec 27 12:33:44 PM PST 23
Finished Dec 27 12:34:14 PM PST 23
Peak memory 194624 kb
Host smart-77aa106e-0959-48bc-9f26-18e26f9daaa2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266503150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.2266503150
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2331026009
Short name T391
Test name
Test status
Simulation time 404537409 ps
CPU time 0.73 seconds
Started Dec 27 12:34:01 PM PST 23
Finished Dec 27 12:34:16 PM PST 23
Peak memory 194320 kb
Host smart-06c0dd1f-72fa-45a9-9dd0-d64450dd4231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331026009 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2331026009
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3131143523
Short name T70
Test name
Test status
Simulation time 318913289 ps
CPU time 0.76 seconds
Started Dec 27 12:33:39 PM PST 23
Finished Dec 27 12:33:55 PM PST 23
Peak memory 183816 kb
Host smart-a6eefdf5-8d6e-4b81-a17a-66530767babd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131143523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3131143523
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.847576965
Short name T398
Test name
Test status
Simulation time 495554173 ps
CPU time 0.67 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:04 PM PST 23
Peak memory 183552 kb
Host smart-23cfb3f3-215a-4c32-8733-8b4ea6037f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847576965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.847576965
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3358551166
Short name T362
Test name
Test status
Simulation time 485648269 ps
CPU time 0.56 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183416 kb
Host smart-e7e449c6-fe8c-434c-8711-5a588c6be53b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358551166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3358551166
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4023966031
Short name T323
Test name
Test status
Simulation time 353112968 ps
CPU time 0.61 seconds
Started Dec 27 12:34:05 PM PST 23
Finished Dec 27 12:34:21 PM PST 23
Peak memory 183420 kb
Host smart-91aef779-4405-4deb-8baf-48c157b39ec6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023966031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4023966031
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.407592941
Short name T393
Test name
Test status
Simulation time 1426825440 ps
CPU time 1.37 seconds
Started Dec 27 12:33:41 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 193276 kb
Host smart-4972b749-7218-46fe-babe-7c081c30da64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407592941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.407592941
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.765188523
Short name T48
Test name
Test status
Simulation time 307784577 ps
CPU time 1.65 seconds
Started Dec 27 12:33:38 PM PST 23
Finished Dec 27 12:33:55 PM PST 23
Peak memory 198656 kb
Host smart-60c2d06f-24af-4911-9085-4293ce928010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765188523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.765188523
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.446551790
Short name T347
Test name
Test status
Simulation time 646691114 ps
CPU time 1.18 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 193772 kb
Host smart-e967491d-28e1-4eb8-b7f8-b21d791be512
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446551790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.446551790
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2701598014
Short name T45
Test name
Test status
Simulation time 5957592116 ps
CPU time 15.32 seconds
Started Dec 27 12:33:57 PM PST 23
Finished Dec 27 12:34:27 PM PST 23
Peak memory 184004 kb
Host smart-1582ff6d-fce2-4c2d-b9b3-210ba8275fc3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701598014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2701598014
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.587416107
Short name T363
Test name
Test status
Simulation time 639169078 ps
CPU time 1.42 seconds
Started Dec 27 12:34:07 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183580 kb
Host smart-db1b1e83-f38c-4a18-b98e-c999248bb042
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587416107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.587416107
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.975868067
Short name T411
Test name
Test status
Simulation time 488599126 ps
CPU time 1.03 seconds
Started Dec 27 12:34:01 PM PST 23
Finished Dec 27 12:34:17 PM PST 23
Peak memory 198332 kb
Host smart-e6ca7066-f4fa-4043-9bda-66d964debd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975868067 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.975868067
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1048251404
Short name T396
Test name
Test status
Simulation time 371322374 ps
CPU time 0.84 seconds
Started Dec 27 12:33:41 PM PST 23
Finished Dec 27 12:33:57 PM PST 23
Peak memory 193040 kb
Host smart-4ef46c8d-688e-4332-b3b8-08bdecd56d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048251404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1048251404
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2657717459
Short name T14
Test name
Test status
Simulation time 433608249 ps
CPU time 0.68 seconds
Started Dec 27 12:33:54 PM PST 23
Finished Dec 27 12:34:11 PM PST 23
Peak memory 183456 kb
Host smart-03d398ec-7651-4e69-9945-fbcb3bfa98ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657717459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2657717459
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2609283790
Short name T340
Test name
Test status
Simulation time 266925109 ps
CPU time 0.91 seconds
Started Dec 27 12:34:09 PM PST 23
Finished Dec 27 12:34:25 PM PST 23
Peak memory 183476 kb
Host smart-8c811a04-269d-4e74-9226-f74bf8ccacc4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609283790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2609283790
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1675505506
Short name T352
Test name
Test status
Simulation time 320958211 ps
CPU time 0.61 seconds
Started Dec 27 12:33:35 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 183792 kb
Host smart-ad68d3c9-75ba-407c-a87e-16d249ee3bfe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675505506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1675505506
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.55974197
Short name T345
Test name
Test status
Simulation time 1940024270 ps
CPU time 3.3 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:34:01 PM PST 23
Peak memory 194080 kb
Host smart-89d3e016-54cf-4cf0-95b8-1aacd7dfbd76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55974197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_same_csr_outstanding.55974197
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1922541884
Short name T367
Test name
Test status
Simulation time 299459936 ps
CPU time 1.64 seconds
Started Dec 27 12:34:06 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 198544 kb
Host smart-3a2c3072-9cbc-46d4-b1c8-211d50b995bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922541884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1922541884
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3993881862
Short name T107
Test name
Test status
Simulation time 4522109859 ps
CPU time 1.98 seconds
Started Dec 27 12:34:06 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 196096 kb
Host smart-1e68aca6-a070-461e-a9ca-6f3f0e43ce15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993881862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3993881862
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3011205025
Short name T355
Test name
Test status
Simulation time 396423363 ps
CPU time 0.83 seconds
Started Dec 27 12:34:05 PM PST 23
Finished Dec 27 12:34:21 PM PST 23
Peak memory 195704 kb
Host smart-bef2f21b-6d38-4c16-abc9-0b4a5d14903a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011205025 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3011205025
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3671649925
Short name T381
Test name
Test status
Simulation time 332164166 ps
CPU time 0.65 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:35:07 PM PST 23
Peak memory 183724 kb
Host smart-8a00b5e3-d92b-48c1-b32d-bb3f1f8ee411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671649925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3671649925
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1733188858
Short name T94
Test name
Test status
Simulation time 1146863863 ps
CPU time 3.37 seconds
Started Dec 27 12:33:30 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 192712 kb
Host smart-ef11712d-9975-4397-9c32-ed0c9827c8f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733188858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1733188858
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1911009756
Short name T389
Test name
Test status
Simulation time 397641373 ps
CPU time 2.57 seconds
Started Dec 27 12:33:32 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 198524 kb
Host smart-36e6ae79-683c-49a4-a964-e3450d90f001
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911009756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1911009756
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2671705003
Short name T2
Test name
Test status
Simulation time 8078304256 ps
CPU time 6.99 seconds
Started Dec 27 12:33:46 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 197520 kb
Host smart-c1d39437-1c0c-428a-8d54-13ea35580ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671705003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2671705003
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2264026421
Short name T426
Test name
Test status
Simulation time 320600554 ps
CPU time 1.1 seconds
Started Dec 27 12:34:40 PM PST 23
Finished Dec 27 12:34:59 PM PST 23
Peak memory 195556 kb
Host smart-4d1e4f09-d2bf-4c40-b5a2-0ffc33825693
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264026421 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2264026421
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.504498737
Short name T361
Test name
Test status
Simulation time 417050642 ps
CPU time 0.85 seconds
Started Dec 27 12:34:18 PM PST 23
Finished Dec 27 12:34:35 PM PST 23
Peak memory 183768 kb
Host smart-55cdf882-38e4-4111-8c20-b28fb4bfa5cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504498737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.504498737
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.829294337
Short name T314
Test name
Test status
Simulation time 471617720 ps
CPU time 0.7 seconds
Started Dec 27 12:34:24 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 183480 kb
Host smart-3437d2ef-adf4-48f4-b4e0-ea6c540f3a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829294337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.829294337
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1453943384
Short name T382
Test name
Test status
Simulation time 1876814319 ps
CPU time 1.15 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:14 PM PST 23
Peak memory 194828 kb
Host smart-d9558922-d9f4-452c-84ff-baaee3079de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453943384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1453943384
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1725632602
Short name T351
Test name
Test status
Simulation time 392326838 ps
CPU time 1.61 seconds
Started Dec 27 12:33:57 PM PST 23
Finished Dec 27 12:34:14 PM PST 23
Peak memory 198556 kb
Host smart-a1956bc7-395f-403a-bf19-b5467e40ebd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725632602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1725632602
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4117298903
Short name T73
Test name
Test status
Simulation time 8349002254 ps
CPU time 7.54 seconds
Started Dec 27 12:34:02 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 197652 kb
Host smart-113c56f8-b04a-4ec2-8f2d-76013b8058e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117298903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4117298903
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3285679708
Short name T335
Test name
Test status
Simulation time 667833549 ps
CPU time 0.96 seconds
Started Dec 27 12:33:44 PM PST 23
Finished Dec 27 12:34:00 PM PST 23
Peak memory 197156 kb
Host smart-b9a073a5-a4ad-4daa-aa38-6e2edd0ba23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285679708 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3285679708
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.576265145
Short name T69
Test name
Test status
Simulation time 452625121 ps
CPU time 0.99 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183740 kb
Host smart-00da3320-76c3-4e14-ab60-f234a7e02154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576265145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.576265145
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.5674508
Short name T332
Test name
Test status
Simulation time 319637317 ps
CPU time 0.66 seconds
Started Dec 27 12:34:34 PM PST 23
Finished Dec 27 12:34:52 PM PST 23
Peak memory 183596 kb
Host smart-d4d9c316-ee16-4fec-a018-9a6d88fc3d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5674508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.5674508
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.676956611
Short name T395
Test name
Test status
Simulation time 2204116882 ps
CPU time 3.99 seconds
Started Dec 27 12:34:16 PM PST 23
Finished Dec 27 12:34:37 PM PST 23
Peak memory 194856 kb
Host smart-c6913447-5bd2-45e0-9842-6deb991bae55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676956611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.676956611
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1299524633
Short name T358
Test name
Test status
Simulation time 594678727 ps
CPU time 1.59 seconds
Started Dec 27 12:34:22 PM PST 23
Finished Dec 27 12:34:39 PM PST 23
Peak memory 198516 kb
Host smart-bf88adfb-3081-40f5-a7a6-0aa0dd4e3253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299524633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1299524633
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.43134646
Short name T11
Test name
Test status
Simulation time 8820703264 ps
CPU time 13.15 seconds
Started Dec 27 12:33:54 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 197664 kb
Host smart-6870d007-38d4-4e95-931f-d5a3f9465e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43134646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_
intg_err.43134646
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1862243706
Short name T387
Test name
Test status
Simulation time 467714145 ps
CPU time 0.82 seconds
Started Dec 27 12:33:54 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 196216 kb
Host smart-8bac1e14-33a1-412d-9f14-2d34c3cd0bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862243706 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1862243706
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1500650750
Short name T81
Test name
Test status
Simulation time 464044387 ps
CPU time 0.94 seconds
Started Dec 27 12:34:23 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 183708 kb
Host smart-938801bb-6e29-4290-ae36-b123c290596b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500650750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1500650750
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4079001699
Short name T394
Test name
Test status
Simulation time 459795731 ps
CPU time 1.17 seconds
Started Dec 27 12:34:07 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183700 kb
Host smart-3c162877-784f-46f0-b864-25a14b2ddc4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079001699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4079001699
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1753880505
Short name T368
Test name
Test status
Simulation time 1179418431 ps
CPU time 1.52 seconds
Started Dec 27 12:34:16 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 194304 kb
Host smart-34882a5e-5aa3-437b-bbdd-5957930e61b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753880505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1753880505
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3768509988
Short name T319
Test name
Test status
Simulation time 590158632 ps
CPU time 1.74 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:35:08 PM PST 23
Peak memory 198648 kb
Host smart-c9e8d052-5057-478c-a7ea-5f2bfed80cca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768509988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3768509988
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3417300423
Short name T399
Test name
Test status
Simulation time 8146159566 ps
CPU time 13.76 seconds
Started Dec 27 12:33:49 PM PST 23
Finished Dec 27 12:34:19 PM PST 23
Peak memory 197580 kb
Host smart-5faed252-fe01-41cc-8f49-e85a3d607753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417300423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3417300423
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.797678042
Short name T377
Test name
Test status
Simulation time 510489831 ps
CPU time 0.7 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:34:54 PM PST 23
Peak memory 196648 kb
Host smart-8bea958b-66c8-4763-987e-b70db0a901f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797678042 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.797678042
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.789929901
Short name T357
Test name
Test status
Simulation time 568910527 ps
CPU time 0.77 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183752 kb
Host smart-ce8b0feb-6b13-413d-aee0-4d99f4fabc6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789929901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.789929901
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1001198336
Short name T324
Test name
Test status
Simulation time 375947944 ps
CPU time 0.65 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:13 PM PST 23
Peak memory 183748 kb
Host smart-eb6a4a83-78e2-4bd3-a68c-b679693d1d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001198336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1001198336
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2672003641
Short name T408
Test name
Test status
Simulation time 1049459254 ps
CPU time 2.64 seconds
Started Dec 27 12:34:42 PM PST 23
Finished Dec 27 12:35:02 PM PST 23
Peak memory 193576 kb
Host smart-349d624c-6a9c-44cd-ba17-fb1c215f38f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672003641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2672003641
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.1704637343
Short name T318
Test name
Test status
Simulation time 445667203 ps
CPU time 1.13 seconds
Started Dec 27 12:33:50 PM PST 23
Finished Dec 27 12:34:07 PM PST 23
Peak memory 198440 kb
Host smart-c79a578e-1bc2-43e0-99dd-2af6c4f0f0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704637343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.1704637343
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.668964289
Short name T3
Test name
Test status
Simulation time 4537474271 ps
CPU time 4.47 seconds
Started Dec 27 12:34:42 PM PST 23
Finished Dec 27 12:35:04 PM PST 23
Peak memory 195888 kb
Host smart-4bed73e8-e473-4952-acaa-8ddbff1bcfe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668964289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.668964289
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.137032373
Short name T325
Test name
Test status
Simulation time 516615056 ps
CPU time 0.88 seconds
Started Dec 27 12:33:38 PM PST 23
Finished Dec 27 12:33:54 PM PST 23
Peak memory 196364 kb
Host smart-a1a2c9a1-0866-4800-befc-1ea036a73b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137032373 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.137032373
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2611018486
Short name T80
Test name
Test status
Simulation time 592642107 ps
CPU time 0.62 seconds
Started Dec 27 12:34:19 PM PST 23
Finished Dec 27 12:34:36 PM PST 23
Peak memory 193060 kb
Host smart-8c0758a0-74c1-4d16-886e-3f910c3660b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611018486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2611018486
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.615239328
Short name T29
Test name
Test status
Simulation time 339551832 ps
CPU time 0.59 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:35:02 PM PST 23
Peak memory 183724 kb
Host smart-4598bfba-c6d7-4426-a4ca-d8cde5a23128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615239328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.615239328
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1633445976
Short name T346
Test name
Test status
Simulation time 1047752858 ps
CPU time 0.66 seconds
Started Dec 27 12:34:02 PM PST 23
Finished Dec 27 12:34:17 PM PST 23
Peak memory 193204 kb
Host smart-6cce4870-3c58-4b0d-9275-57fac14de058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633445976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1633445976
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3984979076
Short name T403
Test name
Test status
Simulation time 853168067 ps
CPU time 2.43 seconds
Started Dec 27 12:34:04 PM PST 23
Finished Dec 27 12:34:21 PM PST 23
Peak memory 198516 kb
Host smart-1906f2e2-47fe-432b-9e41-f1aeef65edd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984979076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3984979076
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2112788979
Short name T105
Test name
Test status
Simulation time 8163282382 ps
CPU time 7.15 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:35:09 PM PST 23
Peak memory 197696 kb
Host smart-fd570ada-b312-4add-9562-d11c9c8fdf0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112788979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2112788979
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.816779168
Short name T8
Test name
Test status
Simulation time 445785201 ps
CPU time 1.28 seconds
Started Dec 27 12:34:13 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 194772 kb
Host smart-7d30a179-ee9a-4f8b-9b93-03172cb3f551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816779168 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.816779168
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2893458936
Short name T65
Test name
Test status
Simulation time 330785163 ps
CPU time 1.1 seconds
Started Dec 27 12:34:09 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183736 kb
Host smart-0fdad255-74b8-42d3-99b1-8e1c8cf073eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893458936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2893458936
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3570565091
Short name T427
Test name
Test status
Simulation time 524377597 ps
CPU time 0.7 seconds
Started Dec 27 12:33:44 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183560 kb
Host smart-dcb62713-a664-4b6b-8013-60498b22b729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570565091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3570565091
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1814958827
Short name T407
Test name
Test status
Simulation time 987840097 ps
CPU time 0.97 seconds
Started Dec 27 12:35:03 PM PST 23
Finished Dec 27 12:35:22 PM PST 23
Peak memory 193304 kb
Host smart-371931c8-b7f7-4ff5-a043-6a8678657372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814958827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1814958827
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1728570925
Short name T47
Test name
Test status
Simulation time 425736247 ps
CPU time 1.51 seconds
Started Dec 27 12:34:01 PM PST 23
Finished Dec 27 12:34:17 PM PST 23
Peak memory 198568 kb
Host smart-049df8f2-e85f-4ee5-b601-ca212929c779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728570925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1728570925
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3481602011
Short name T375
Test name
Test status
Simulation time 4374593060 ps
CPU time 6.64 seconds
Started Dec 27 12:34:35 PM PST 23
Finished Dec 27 12:34:59 PM PST 23
Peak memory 197024 kb
Host smart-4307c69f-5dcd-425a-a9fb-5ba155f34cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481602011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3481602011
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4128621240
Short name T379
Test name
Test status
Simulation time 447712725 ps
CPU time 1.34 seconds
Started Dec 27 12:33:47 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 195556 kb
Host smart-78d37c36-72fb-4c74-b95f-a5ccccb7c477
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128621240 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4128621240
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4014737112
Short name T330
Test name
Test status
Simulation time 427044674 ps
CPU time 0.77 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 183700 kb
Host smart-d97c9735-0516-4e03-9950-c29fbb985e71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014737112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4014737112
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1900716417
Short name T27
Test name
Test status
Simulation time 429363274 ps
CPU time 0.6 seconds
Started Dec 27 12:34:17 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 183468 kb
Host smart-d7292e8f-225c-45a2-8482-4ae43558ae00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900716417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1900716417
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1799107069
Short name T421
Test name
Test status
Simulation time 1086864921 ps
CPU time 2.96 seconds
Started Dec 27 12:34:12 PM PST 23
Finished Dec 27 12:34:31 PM PST 23
Peak memory 194212 kb
Host smart-da927afd-e7b2-43c0-9052-7689163f64ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799107069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1799107069
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.390996004
Short name T320
Test name
Test status
Simulation time 333027516 ps
CPU time 1.55 seconds
Started Dec 27 12:34:16 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 198640 kb
Host smart-15a3a897-fd66-4991-a961-885897c0bbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390996004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.390996004
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.135396169
Short name T376
Test name
Test status
Simulation time 8014209817 ps
CPU time 14.01 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:18 PM PST 23
Peak memory 197444 kb
Host smart-3a6ca60d-f821-4074-83e2-341b4842adce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135396169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.135396169
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1252864850
Short name T384
Test name
Test status
Simulation time 515023993 ps
CPU time 1.06 seconds
Started Dec 27 12:34:30 PM PST 23
Finished Dec 27 12:34:48 PM PST 23
Peak memory 196124 kb
Host smart-e06b60d3-45de-4b3b-9881-4778bbd69662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252864850 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1252864850
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2876627340
Short name T409
Test name
Test status
Simulation time 556691855 ps
CPU time 1.04 seconds
Started Dec 27 12:33:49 PM PST 23
Finished Dec 27 12:34:06 PM PST 23
Peak memory 183764 kb
Host smart-3bbac1ad-e9f2-4f27-8c4a-0ceb7224aa34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876627340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2876627340
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3530864529
Short name T99
Test name
Test status
Simulation time 304054468 ps
CPU time 0.64 seconds
Started Dec 27 12:34:14 PM PST 23
Finished Dec 27 12:34:31 PM PST 23
Peak memory 183444 kb
Host smart-31815ef7-4dab-4a5f-af42-2afd17b04f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530864529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3530864529
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1063527028
Short name T96
Test name
Test status
Simulation time 1503912331 ps
CPU time 3.3 seconds
Started Dec 27 12:33:46 PM PST 23
Finished Dec 27 12:34:06 PM PST 23
Peak memory 194160 kb
Host smart-dca17fff-9c93-48ee-8a65-a59f6b9303d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063527028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1063527028
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2345326721
Short name T329
Test name
Test status
Simulation time 601725942 ps
CPU time 1.76 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 198612 kb
Host smart-f22b9912-41f5-4825-867b-c58f3149a58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345326721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2345326721
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3351744445
Short name T366
Test name
Test status
Simulation time 4260515551 ps
CPU time 6.57 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:35:00 PM PST 23
Peak memory 196148 kb
Host smart-d727904a-2d4a-460e-a455-1dcde2a33fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351744445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3351744445
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.369221036
Short name T49
Test name
Test status
Simulation time 531510964 ps
CPU time 1.33 seconds
Started Dec 27 12:34:43 PM PST 23
Finished Dec 27 12:35:02 PM PST 23
Peak memory 194680 kb
Host smart-0252adfe-4ef9-43e5-8ac2-8e531dc8d719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369221036 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.369221036
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4258965939
Short name T77
Test name
Test status
Simulation time 349304779 ps
CPU time 0.71 seconds
Started Dec 27 12:33:51 PM PST 23
Finished Dec 27 12:34:08 PM PST 23
Peak memory 183712 kb
Host smart-578fd649-0d73-4e53-b3de-cbfee086addd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258965939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4258965939
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2135052544
Short name T326
Test name
Test status
Simulation time 332634407 ps
CPU time 0.64 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183488 kb
Host smart-b99c111c-0227-4922-abde-4459b3958e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135052544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2135052544
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1722389281
Short name T92
Test name
Test status
Simulation time 1026382779 ps
CPU time 1.98 seconds
Started Dec 27 12:34:12 PM PST 23
Finished Dec 27 12:34:30 PM PST 23
Peak memory 193228 kb
Host smart-afe2b19f-07cc-49d4-8563-4c096ec4ff04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722389281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1722389281
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.919858061
Short name T315
Test name
Test status
Simulation time 346571926 ps
CPU time 1.46 seconds
Started Dec 27 12:34:49 PM PST 23
Finished Dec 27 12:35:11 PM PST 23
Peak memory 198532 kb
Host smart-e0492de4-a1c9-4b50-84f2-edeb66ecd3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919858061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.919858061
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.4284920587
Short name T108
Test name
Test status
Simulation time 7879982227 ps
CPU time 4.02 seconds
Started Dec 27 12:34:39 PM PST 23
Finished Dec 27 12:35:01 PM PST 23
Peak memory 197552 kb
Host smart-91b29e19-0168-46b3-a126-294c76edbe66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284920587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.4284920587
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1106054733
Short name T337
Test name
Test status
Simulation time 521888519 ps
CPU time 1.73 seconds
Started Dec 27 12:34:50 PM PST 23
Finished Dec 27 12:35:13 PM PST 23
Peak memory 183736 kb
Host smart-6f783963-6b6f-4e7e-b7cb-670bf8b2ef96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106054733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1106054733
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1586367731
Short name T78
Test name
Test status
Simulation time 11482320110 ps
CPU time 29.84 seconds
Started Dec 27 12:34:37 PM PST 23
Finished Dec 27 12:35:24 PM PST 23
Peak memory 192284 kb
Host smart-28ad1686-4536-49cf-b8c4-9878f30a34bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586367731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1586367731
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.578029323
Short name T68
Test name
Test status
Simulation time 1102295074 ps
CPU time 2.42 seconds
Started Dec 27 12:34:49 PM PST 23
Finished Dec 27 12:35:11 PM PST 23
Peak memory 183720 kb
Host smart-70372d09-eeb6-4f5b-8d07-2ce9ab361eac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578029323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.578029323
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3859063217
Short name T19
Test name
Test status
Simulation time 567757517 ps
CPU time 1.41 seconds
Started Dec 27 12:34:45 PM PST 23
Finished Dec 27 12:35:06 PM PST 23
Peak memory 196584 kb
Host smart-c677b129-4af7-4ab0-98f4-77f69ce2516b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859063217 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3859063217
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2350833016
Short name T365
Test name
Test status
Simulation time 433287773 ps
CPU time 0.71 seconds
Started Dec 27 12:34:09 PM PST 23
Finished Dec 27 12:34:25 PM PST 23
Peak memory 183740 kb
Host smart-af25c383-e391-4398-8882-e27273f4ee62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350833016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2350833016
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.384515664
Short name T410
Test name
Test status
Simulation time 296542696 ps
CPU time 0.63 seconds
Started Dec 27 12:35:33 PM PST 23
Finished Dec 27 12:35:46 PM PST 23
Peak memory 183532 kb
Host smart-1d886ef1-36b5-463e-a941-b4972af22736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384515664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.384515664
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1089884281
Short name T378
Test name
Test status
Simulation time 384065280 ps
CPU time 1.08 seconds
Started Dec 27 12:34:47 PM PST 23
Finished Dec 27 12:35:07 PM PST 23
Peak memory 183448 kb
Host smart-c950d5db-1341-4692-b7e5-6269a206b5a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089884281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1089884281
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1003823042
Short name T404
Test name
Test status
Simulation time 305464905 ps
CPU time 0.66 seconds
Started Dec 27 12:34:41 PM PST 23
Finished Dec 27 12:34:59 PM PST 23
Peak memory 183460 kb
Host smart-bae6a571-8c3a-4f3a-9f35-481044ce6ff3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003823042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1003823042
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2989499677
Short name T6
Test name
Test status
Simulation time 1721835269 ps
CPU time 1.26 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:18 PM PST 23
Peak memory 193964 kb
Host smart-9eef2642-0cbe-4c99-be96-501c14745a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989499677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2989499677
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1662224471
Short name T333
Test name
Test status
Simulation time 704650914 ps
CPU time 1.75 seconds
Started Dec 27 12:34:35 PM PST 23
Finished Dec 27 12:34:54 PM PST 23
Peak memory 198588 kb
Host smart-13a245dd-931f-48d1-82f1-5e03e8eeeacf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662224471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1662224471
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2310125859
Short name T339
Test name
Test status
Simulation time 8563817475 ps
CPU time 4.77 seconds
Started Dec 27 12:34:45 PM PST 23
Finished Dec 27 12:35:09 PM PST 23
Peak memory 197624 kb
Host smart-c5f7f8c7-4cd3-4413-8a20-2c433f362c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310125859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2310125859
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1165971926
Short name T322
Test name
Test status
Simulation time 505341610 ps
CPU time 0.57 seconds
Started Dec 27 12:33:51 PM PST 23
Finished Dec 27 12:34:08 PM PST 23
Peak memory 183508 kb
Host smart-2975397c-74ba-41d1-9e7b-d48888d2b312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165971926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1165971926
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.3752658949
Short name T350
Test name
Test status
Simulation time 374129679 ps
CPU time 1.05 seconds
Started Dec 27 12:34:20 PM PST 23
Finished Dec 27 12:34:38 PM PST 23
Peak memory 183460 kb
Host smart-f541f3d3-dd6c-42a2-a31e-94d79b4a38b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752658949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.3752658949
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1725229205
Short name T353
Test name
Test status
Simulation time 282952621 ps
CPU time 0.78 seconds
Started Dec 27 12:34:04 PM PST 23
Finished Dec 27 12:34:19 PM PST 23
Peak memory 183692 kb
Host smart-ddc84410-956c-4e5b-8b0f-04ce1e954297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725229205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1725229205
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3927874734
Short name T369
Test name
Test status
Simulation time 529730097 ps
CPU time 0.69 seconds
Started Dec 27 12:34:27 PM PST 23
Finished Dec 27 12:34:44 PM PST 23
Peak memory 183744 kb
Host smart-be551b77-d245-4c4a-b5a6-50a2fdba7ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927874734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3927874734
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1393767719
Short name T412
Test name
Test status
Simulation time 348848293 ps
CPU time 0.79 seconds
Started Dec 27 12:34:13 PM PST 23
Finished Dec 27 12:34:31 PM PST 23
Peak memory 183508 kb
Host smart-524b4eaf-c257-470a-ad4a-64bb972fbf5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393767719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1393767719
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3737071136
Short name T420
Test name
Test status
Simulation time 481483382 ps
CPU time 0.69 seconds
Started Dec 27 12:34:02 PM PST 23
Finished Dec 27 12:34:17 PM PST 23
Peak memory 183560 kb
Host smart-efe020ba-aede-4d4a-a7fd-fd10d47daa26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737071136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3737071136
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1681404792
Short name T380
Test name
Test status
Simulation time 295087594 ps
CPU time 0.63 seconds
Started Dec 27 12:34:12 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 183476 kb
Host smart-f6af9446-83fe-4f7e-bd16-9b2360233d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681404792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1681404792
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2937746027
Short name T360
Test name
Test status
Simulation time 454920946 ps
CPU time 0.7 seconds
Started Dec 27 12:34:14 PM PST 23
Finished Dec 27 12:34:31 PM PST 23
Peak memory 183772 kb
Host smart-8874c27d-8341-474b-9829-ef307a424b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937746027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2937746027
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1612792406
Short name T371
Test name
Test status
Simulation time 447814594 ps
CPU time 1.25 seconds
Started Dec 27 12:33:50 PM PST 23
Finished Dec 27 12:34:08 PM PST 23
Peak memory 183492 kb
Host smart-f201ab5a-872f-4786-9e85-f3e261ee621e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612792406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1612792406
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4053495295
Short name T328
Test name
Test status
Simulation time 326237356 ps
CPU time 0.95 seconds
Started Dec 27 12:33:53 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 183700 kb
Host smart-43037016-ffe5-4aac-8f9f-67ccca89bd70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053495295 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4053495295
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1296363955
Short name T400
Test name
Test status
Simulation time 616698515 ps
CPU time 1.27 seconds
Started Dec 27 12:34:44 PM PST 23
Finished Dec 27 12:35:04 PM PST 23
Peak memory 193776 kb
Host smart-47c5b958-ff1e-425e-b8cd-d8bf60b26bf2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296363955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1296363955
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1395637967
Short name T331
Test name
Test status
Simulation time 6119268102 ps
CPU time 13.99 seconds
Started Dec 27 12:34:18 PM PST 23
Finished Dec 27 12:34:48 PM PST 23
Peak memory 195188 kb
Host smart-6815c9c7-3bf9-4a1b-8eb2-9e76a1a30496
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395637967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1395637967
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.562074837
Short name T30
Test name
Test status
Simulation time 1311893503 ps
CPU time 1.49 seconds
Started Dec 27 12:33:43 PM PST 23
Finished Dec 27 12:34:00 PM PST 23
Peak memory 183764 kb
Host smart-92be0c0d-92b4-4b62-8aff-99676967c016
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562074837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.562074837
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3512532246
Short name T44
Test name
Test status
Simulation time 514926751 ps
CPU time 1 seconds
Started Dec 27 12:35:10 PM PST 23
Finished Dec 27 12:35:28 PM PST 23
Peak memory 195072 kb
Host smart-20e91d0e-c116-4fc8-94ce-28023c0c1190
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512532246 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3512532246
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.909328163
Short name T385
Test name
Test status
Simulation time 325631140 ps
CPU time 1.09 seconds
Started Dec 27 12:34:16 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 183776 kb
Host smart-255a1ed4-a904-4170-8a7e-1eeb87d32b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909328163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.909328163
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3173535326
Short name T7
Test name
Test status
Simulation time 356282104 ps
CPU time 1.09 seconds
Started Dec 27 12:34:41 PM PST 23
Finished Dec 27 12:35:00 PM PST 23
Peak memory 183456 kb
Host smart-fe0246f2-e138-40bb-86e0-ff3912b51832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173535326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3173535326
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.858015468
Short name T334
Test name
Test status
Simulation time 441106681 ps
CPU time 0.67 seconds
Started Dec 27 12:34:46 PM PST 23
Finished Dec 27 12:35:06 PM PST 23
Peak memory 183484 kb
Host smart-711c23b9-00d9-45ce-8a21-dfe8848dd03c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858015468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.858015468
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2643060521
Short name T405
Test name
Test status
Simulation time 455893486 ps
CPU time 0.82 seconds
Started Dec 27 12:33:42 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 183552 kb
Host smart-68426cb4-3f38-4cf3-9c8a-9ba92496fd0e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643060521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2643060521
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.930700934
Short name T414
Test name
Test status
Simulation time 1322948025 ps
CPU time 1.03 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:34:54 PM PST 23
Peak memory 194176 kb
Host smart-5c589677-7c67-4a6e-9bd6-5ec7928b9033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930700934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.930700934
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.838878827
Short name T321
Test name
Test status
Simulation time 685844946 ps
CPU time 2.34 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:34:55 PM PST 23
Peak memory 198604 kb
Host smart-85219f70-b579-44c5-abf1-66798fee856b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838878827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.838878827
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3940068806
Short name T106
Test name
Test status
Simulation time 8869819914 ps
CPU time 13.3 seconds
Started Dec 27 12:34:23 PM PST 23
Finished Dec 27 12:34:52 PM PST 23
Peak memory 197440 kb
Host smart-9b0f43b2-cac1-4cb9-a8bc-37be39f01492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940068806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3940068806
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.451786318
Short name T370
Test name
Test status
Simulation time 565304147 ps
CPU time 0.55 seconds
Started Dec 27 12:33:55 PM PST 23
Finished Dec 27 12:34:11 PM PST 23
Peak memory 183740 kb
Host smart-ca30208b-4ee3-43c9-8f4f-cbd764b029d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451786318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.451786318
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1582864842
Short name T388
Test name
Test status
Simulation time 388106593 ps
CPU time 1.1 seconds
Started Dec 27 12:34:13 PM PST 23
Finished Dec 27 12:34:30 PM PST 23
Peak memory 183696 kb
Host smart-42a2bfef-38c3-4eb2-b5c2-b772ed2ad9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582864842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1582864842
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3726850593
Short name T348
Test name
Test status
Simulation time 501909942 ps
CPU time 1.31 seconds
Started Dec 27 12:34:12 PM PST 23
Finished Dec 27 12:34:29 PM PST 23
Peak memory 183560 kb
Host smart-9f543e23-5850-4da0-b537-22f0a67392c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726850593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3726850593
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1039579625
Short name T343
Test name
Test status
Simulation time 370073627 ps
CPU time 0.67 seconds
Started Dec 27 12:34:09 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183724 kb
Host smart-e712cfbf-5795-40c5-9c99-9f548506dbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039579625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1039579625
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1367087718
Short name T344
Test name
Test status
Simulation time 469522289 ps
CPU time 1.19 seconds
Started Dec 27 12:34:22 PM PST 23
Finished Dec 27 12:34:40 PM PST 23
Peak memory 183584 kb
Host smart-6dabb7a3-5ba5-4485-ba6a-f9ef11d3f44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367087718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1367087718
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3180051753
Short name T415
Test name
Test status
Simulation time 385463656 ps
CPU time 1.12 seconds
Started Dec 27 12:34:10 PM PST 23
Finished Dec 27 12:34:28 PM PST 23
Peak memory 183500 kb
Host smart-978bfde8-9d52-46f4-8835-df0823f3a568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180051753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3180051753
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1785819487
Short name T72
Test name
Test status
Simulation time 339573238 ps
CPU time 1.04 seconds
Started Dec 27 12:34:16 PM PST 23
Finished Dec 27 12:34:38 PM PST 23
Peak memory 183724 kb
Host smart-061873d3-338b-4cf9-81e6-821031f2d146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785819487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1785819487
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.368209213
Short name T413
Test name
Test status
Simulation time 467967154 ps
CPU time 0.95 seconds
Started Dec 27 12:34:30 PM PST 23
Finished Dec 27 12:34:48 PM PST 23
Peak memory 183468 kb
Host smart-b730acbd-137c-4503-988e-18d13aafe77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368209213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.368209213
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1796401881
Short name T316
Test name
Test status
Simulation time 380056360 ps
CPU time 0.59 seconds
Started Dec 27 12:33:42 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 183800 kb
Host smart-07841e5f-be44-4890-8813-f0b810228509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796401881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1796401881
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.628243004
Short name T317
Test name
Test status
Simulation time 511967883 ps
CPU time 0.74 seconds
Started Dec 27 12:33:55 PM PST 23
Finished Dec 27 12:34:12 PM PST 23
Peak memory 183720 kb
Host smart-9425e29f-4aa2-47cf-99dc-3361f46fe8e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628243004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.628243004
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3287040425
Short name T422
Test name
Test status
Simulation time 562497950 ps
CPU time 0.85 seconds
Started Dec 27 12:33:39 PM PST 23
Finished Dec 27 12:33:55 PM PST 23
Peak memory 183736 kb
Host smart-73429de9-0827-42f0-be0c-a87b7fe3d480
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287040425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3287040425
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3068914927
Short name T386
Test name
Test status
Simulation time 6139962630 ps
CPU time 9.64 seconds
Started Dec 27 12:35:06 PM PST 23
Finished Dec 27 12:35:33 PM PST 23
Peak memory 192224 kb
Host smart-accb7799-d99b-4096-8ea3-2c69117fcfb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068914927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3068914927
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3947905719
Short name T28
Test name
Test status
Simulation time 1099977197 ps
CPU time 2.33 seconds
Started Dec 27 12:35:37 PM PST 23
Finished Dec 27 12:35:52 PM PST 23
Peak memory 183716 kb
Host smart-b90a93c8-8d67-484e-8127-7a72895e82c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947905719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3947905719
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2706279404
Short name T5
Test name
Test status
Simulation time 471872315 ps
CPU time 1.16 seconds
Started Dec 27 12:33:52 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 198596 kb
Host smart-ed31cbd4-2738-4bb4-b072-4d417314450d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706279404 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2706279404
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1734880591
Short name T64
Test name
Test status
Simulation time 479205088 ps
CPU time 1.46 seconds
Started Dec 27 12:34:41 PM PST 23
Finished Dec 27 12:35:00 PM PST 23
Peak memory 183840 kb
Host smart-c9cc4595-a4f0-41f3-bfb9-4f8c8cb6b281
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734880591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1734880591
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2175958667
Short name T356
Test name
Test status
Simulation time 461736220 ps
CPU time 1.14 seconds
Started Dec 27 12:33:51 PM PST 23
Finished Dec 27 12:34:08 PM PST 23
Peak memory 183500 kb
Host smart-6c8a0568-c511-48c1-9499-156427ea225a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175958667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2175958667
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.83387296
Short name T416
Test name
Test status
Simulation time 353231618 ps
CPU time 0.58 seconds
Started Dec 27 12:34:32 PM PST 23
Finished Dec 27 12:34:49 PM PST 23
Peak memory 183492 kb
Host smart-7a51517b-650d-4589-b35c-7edd39a6b7da
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83387296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_mem_partial_access.83387296
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.709243546
Short name T383
Test name
Test status
Simulation time 290536849 ps
CPU time 0.59 seconds
Started Dec 27 12:35:38 PM PST 23
Finished Dec 27 12:35:53 PM PST 23
Peak memory 183716 kb
Host smart-74218428-c0c3-4974-8bbc-d546800ca1f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709243546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.709243546
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2000135213
Short name T4
Test name
Test status
Simulation time 984833946 ps
CPU time 2.64 seconds
Started Dec 27 12:33:55 PM PST 23
Finished Dec 27 12:34:13 PM PST 23
Peak memory 193700 kb
Host smart-190586b9-f6af-4de9-b724-223826b9f016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000135213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2000135213
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.4034805076
Short name T46
Test name
Test status
Simulation time 398580171 ps
CPU time 1.13 seconds
Started Dec 27 12:33:50 PM PST 23
Finished Dec 27 12:34:12 PM PST 23
Peak memory 198316 kb
Host smart-69d3cbc5-42cd-4501-9a25-cd134615072c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034805076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.4034805076
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1392749498
Short name T419
Test name
Test status
Simulation time 4634449713 ps
CPU time 7.44 seconds
Started Dec 27 12:34:19 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 195804 kb
Host smart-9c2c2ead-d5d4-49e5-a34e-9f9ac1d66dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392749498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1392749498
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2537352248
Short name T359
Test name
Test status
Simulation time 364587111 ps
CPU time 0.86 seconds
Started Dec 27 12:34:31 PM PST 23
Finished Dec 27 12:34:48 PM PST 23
Peak memory 183764 kb
Host smart-1f863128-cd59-4e89-81ff-963fc2a6985d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537352248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2537352248
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1769201021
Short name T392
Test name
Test status
Simulation time 343187608 ps
CPU time 0.56 seconds
Started Dec 27 12:34:41 PM PST 23
Finished Dec 27 12:34:59 PM PST 23
Peak memory 183720 kb
Host smart-5c3e9467-3384-4e9a-a057-afde95eec6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769201021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1769201021
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3194746876
Short name T338
Test name
Test status
Simulation time 277164233 ps
CPU time 0.67 seconds
Started Dec 27 12:34:12 PM PST 23
Finished Dec 27 12:34:34 PM PST 23
Peak memory 183488 kb
Host smart-6ec76f56-9932-4323-81a9-311d233a097c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194746876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3194746876
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1012062358
Short name T76
Test name
Test status
Simulation time 267637030 ps
CPU time 0.91 seconds
Started Dec 27 12:34:28 PM PST 23
Finished Dec 27 12:34:45 PM PST 23
Peak memory 183716 kb
Host smart-ff06ded4-f3c6-4f33-9a6c-3f6c3ea09b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012062358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1012062358
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2562932858
Short name T71
Test name
Test status
Simulation time 422342285 ps
CPU time 0.92 seconds
Started Dec 27 12:34:09 PM PST 23
Finished Dec 27 12:34:24 PM PST 23
Peak memory 183764 kb
Host smart-1dac639b-b6c4-44b5-b7ad-3a1d993b88de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562932858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2562932858
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3007554181
Short name T15
Test name
Test status
Simulation time 491492842 ps
CPU time 1.22 seconds
Started Dec 27 12:34:15 PM PST 23
Finished Dec 27 12:34:37 PM PST 23
Peak memory 183580 kb
Host smart-9374dd04-4aee-49f0-b19a-fbf2f0968394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007554181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3007554181
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1432445612
Short name T373
Test name
Test status
Simulation time 497810030 ps
CPU time 0.61 seconds
Started Dec 27 12:34:04 PM PST 23
Finished Dec 27 12:34:19 PM PST 23
Peak memory 183472 kb
Host smart-12d58c79-f50e-441d-ad50-5e9c98ed32f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432445612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1432445612
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1255926628
Short name T342
Test name
Test status
Simulation time 433991175 ps
CPU time 1.2 seconds
Started Dec 27 12:34:06 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 183556 kb
Host smart-eeb03bb8-d6a9-40e1-a2ee-9a42c0cda9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255926628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1255926628
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4239816361
Short name T429
Test name
Test status
Simulation time 490183020 ps
CPU time 1.28 seconds
Started Dec 27 12:34:36 PM PST 23
Finished Dec 27 12:34:54 PM PST 23
Peak memory 183820 kb
Host smart-1d3395b4-786f-4068-ada2-f772bcf277b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239816361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4239816361
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3549641213
Short name T406
Test name
Test status
Simulation time 264237396 ps
CPU time 0.93 seconds
Started Dec 27 12:34:30 PM PST 23
Finished Dec 27 12:34:48 PM PST 23
Peak memory 183552 kb
Host smart-dbe1b286-868c-4ed6-a87a-0dae3181b71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549641213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3549641213
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1986109725
Short name T10
Test name
Test status
Simulation time 617327215 ps
CPU time 0.77 seconds
Started Dec 27 12:33:50 PM PST 23
Finished Dec 27 12:34:07 PM PST 23
Peak memory 196412 kb
Host smart-aa153cf8-0e95-49a1-bb69-ef1656a80c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986109725 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1986109725
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2126733550
Short name T417
Test name
Test status
Simulation time 490187939 ps
CPU time 1.22 seconds
Started Dec 27 12:34:06 PM PST 23
Finished Dec 27 12:34:23 PM PST 23
Peak memory 183828 kb
Host smart-9448c2c5-0e85-44d0-abc4-7a886d5c74d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126733550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2126733550
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1482219862
Short name T428
Test name
Test status
Simulation time 512052765 ps
CPU time 0.74 seconds
Started Dec 27 12:34:49 PM PST 23
Finished Dec 27 12:35:10 PM PST 23
Peak memory 183720 kb
Host smart-c77a2ff7-5af6-4125-b476-a7db09c04706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482219862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1482219862
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.915737787
Short name T401
Test name
Test status
Simulation time 1314321347 ps
CPU time 3.13 seconds
Started Dec 27 12:33:42 PM PST 23
Finished Dec 27 12:34:01 PM PST 23
Peak memory 194232 kb
Host smart-851c7581-eefa-46cb-9753-ead64a707204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915737787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.915737787
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2994177629
Short name T364
Test name
Test status
Simulation time 553111263 ps
CPU time 1.25 seconds
Started Dec 27 12:33:48 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 198364 kb
Host smart-9e919a3e-8696-4324-b817-a124ae97c7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994177629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2994177629
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.755715564
Short name T9
Test name
Test status
Simulation time 4665972401 ps
CPU time 4.4 seconds
Started Dec 27 12:33:45 PM PST 23
Finished Dec 27 12:34:05 PM PST 23
Peak memory 196980 kb
Host smart-5f0e7cdc-55bc-4997-8310-92922b7bc12f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755715564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.755715564
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3162173221
Short name T336
Test name
Test status
Simulation time 690357005 ps
CPU time 0.99 seconds
Started Dec 27 12:34:35 PM PST 23
Finished Dec 27 12:34:53 PM PST 23
Peak memory 198244 kb
Host smart-54b87ff4-0bfe-4b1f-9057-782c419620fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162173221 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3162173221
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4108613116
Short name T82
Test name
Test status
Simulation time 333610189 ps
CPU time 0.77 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:13 PM PST 23
Peak memory 183740 kb
Host smart-2f299bc0-fcba-4280-b9b3-5f36b9de7e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108613116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4108613116
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.4091819124
Short name T16
Test name
Test status
Simulation time 430754130 ps
CPU time 0.58 seconds
Started Dec 27 12:34:13 PM PST 23
Finished Dec 27 12:34:29 PM PST 23
Peak memory 183756 kb
Host smart-d2110130-5d20-43ce-856a-f86f0f660b8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091819124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.4091819124
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.637670023
Short name T349
Test name
Test status
Simulation time 2080549807 ps
CPU time 3.28 seconds
Started Dec 27 12:33:59 PM PST 23
Finished Dec 27 12:34:18 PM PST 23
Peak memory 191916 kb
Host smart-19d4c8ba-4798-4bd8-8b53-504a5f9c42b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637670023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.637670023
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.443208005
Short name T397
Test name
Test status
Simulation time 8403421307 ps
CPU time 15.13 seconds
Started Dec 27 12:33:54 PM PST 23
Finished Dec 27 12:34:28 PM PST 23
Peak memory 197572 kb
Host smart-c6e753ff-11cc-4852-8c2c-e2d0df82ee81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443208005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.443208005
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1606216334
Short name T327
Test name
Test status
Simulation time 438824278 ps
CPU time 0.74 seconds
Started Dec 27 12:35:23 PM PST 23
Finished Dec 27 12:35:39 PM PST 23
Peak memory 195876 kb
Host smart-262f10f3-70ed-4880-874d-2e0662f41342
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606216334 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1606216334
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3227600257
Short name T425
Test name
Test status
Simulation time 457447440 ps
CPU time 0.81 seconds
Started Dec 27 12:35:13 PM PST 23
Finished Dec 27 12:35:31 PM PST 23
Peak memory 183704 kb
Host smart-b7b88e15-1efd-4d87-a47e-4fc3592244ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227600257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3227600257
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3845297748
Short name T97
Test name
Test status
Simulation time 557422710 ps
CPU time 0.56 seconds
Started Dec 27 12:34:31 PM PST 23
Finished Dec 27 12:34:54 PM PST 23
Peak memory 183824 kb
Host smart-33e7c998-c26e-43eb-a4f9-092622e45674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845297748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3845297748
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1015046873
Short name T95
Test name
Test status
Simulation time 2288882152 ps
CPU time 3.6 seconds
Started Dec 27 12:33:42 PM PST 23
Finished Dec 27 12:34:01 PM PST 23
Peak memory 194164 kb
Host smart-c5135a5a-a0a5-44c3-9a4d-f81dcc38f4b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015046873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1015046873
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3189483836
Short name T418
Test name
Test status
Simulation time 342967223 ps
CPU time 1.37 seconds
Started Dec 27 12:34:19 PM PST 23
Finished Dec 27 12:34:37 PM PST 23
Peak memory 198568 kb
Host smart-74085a44-cf61-42e2-988a-c6a8d846e682
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189483836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3189483836
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3211578976
Short name T374
Test name
Test status
Simulation time 4499633435 ps
CPU time 7.33 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:20 PM PST 23
Peak memory 197188 kb
Host smart-9e5892fc-5f83-41d1-be4c-0ed96c02a7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211578976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3211578976
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1321319533
Short name T424
Test name
Test status
Simulation time 393013605 ps
CPU time 0.82 seconds
Started Dec 27 12:33:47 PM PST 23
Finished Dec 27 12:34:04 PM PST 23
Peak memory 194444 kb
Host smart-45868f29-9ee0-47fb-ba63-59590bd564d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321319533 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1321319533
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3381685448
Short name T67
Test name
Test status
Simulation time 398258072 ps
CPU time 1.17 seconds
Started Dec 27 12:33:58 PM PST 23
Finished Dec 27 12:34:14 PM PST 23
Peak memory 183832 kb
Host smart-2e9213ae-7cbf-4d58-bc16-b3e17e85a6a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381685448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3381685448
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1643803514
Short name T423
Test name
Test status
Simulation time 394635040 ps
CPU time 0.59 seconds
Started Dec 27 12:33:56 PM PST 23
Finished Dec 27 12:34:12 PM PST 23
Peak memory 183504 kb
Host smart-0427c85a-efc5-4604-960c-0f6f7b051747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643803514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1643803514
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.767960288
Short name T91
Test name
Test status
Simulation time 1046873886 ps
CPU time 0.94 seconds
Started Dec 27 12:33:49 PM PST 23
Finished Dec 27 12:34:06 PM PST 23
Peak memory 193256 kb
Host smart-64bcd991-0256-4729-aa7d-3e9762c911ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767960288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.767960288
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4243681642
Short name T390
Test name
Test status
Simulation time 490308687 ps
CPU time 1.17 seconds
Started Dec 27 12:33:47 PM PST 23
Finished Dec 27 12:34:04 PM PST 23
Peak memory 198420 kb
Host smart-bd7ac553-947c-4f6c-ad2b-964d7d4478bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243681642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4243681642
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.1824509941
Short name T402
Test name
Test status
Simulation time 8851423218 ps
CPU time 4.35 seconds
Started Dec 27 12:34:03 PM PST 23
Finished Dec 27 12:34:21 PM PST 23
Peak memory 197680 kb
Host smart-0be6ca87-bf76-4cf8-ae7d-065ae54c3563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824509941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.1824509941
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.202984727
Short name T74
Test name
Test status
Simulation time 555225844 ps
CPU time 0.98 seconds
Started Dec 27 12:33:54 PM PST 23
Finished Dec 27 12:34:10 PM PST 23
Peak memory 195576 kb
Host smart-d5774443-f85b-4083-9db5-366398160fe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202984727 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.202984727
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3573676046
Short name T354
Test name
Test status
Simulation time 528294772 ps
CPU time 1.23 seconds
Started Dec 27 12:34:18 PM PST 23
Finished Dec 27 12:34:36 PM PST 23
Peak memory 183720 kb
Host smart-9627fee8-0ad8-418b-988a-b63b41cd5d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573676046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3573676046
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1817957725
Short name T341
Test name
Test status
Simulation time 464393775 ps
CPU time 0.85 seconds
Started Dec 27 12:33:37 PM PST 23
Finished Dec 27 12:33:53 PM PST 23
Peak memory 183532 kb
Host smart-f38441b4-26b3-4562-9307-c203f3643171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817957725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1817957725
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1861724591
Short name T93
Test name
Test status
Simulation time 1583647510 ps
CPU time 2.24 seconds
Started Dec 27 12:33:45 PM PST 23
Finished Dec 27 12:34:03 PM PST 23
Peak memory 194024 kb
Host smart-090c5b9b-fbdd-4dca-b5d2-bf1f81f883dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861724591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1861724591
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.4020602123
Short name T372
Test name
Test status
Simulation time 519531994 ps
CPU time 1.77 seconds
Started Dec 27 12:33:41 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 198548 kb
Host smart-6f6c8cbb-ed1c-4b7a-a283-05e1118f65ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020602123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.4020602123
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3879536813
Short name T207
Test name
Test status
Simulation time 599498812 ps
CPU time 0.83 seconds
Started Dec 27 12:23:59 PM PST 23
Finished Dec 27 12:24:01 PM PST 23
Peak memory 182632 kb
Host smart-2f96f8b1-b7fb-4ab8-96f5-3c1f34926c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879536813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3879536813
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1886308416
Short name T148
Test name
Test status
Simulation time 26025360556 ps
CPU time 11.94 seconds
Started Dec 27 12:20:30 PM PST 23
Finished Dec 27 12:20:46 PM PST 23
Peak memory 182676 kb
Host smart-ced0eb1a-9cdf-4b0c-8d2c-afe98feda373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886308416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1886308416
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1862716065
Short name T169
Test name
Test status
Simulation time 534598526 ps
CPU time 0.8 seconds
Started Dec 27 12:26:38 PM PST 23
Finished Dec 27 12:26:57 PM PST 23
Peak memory 181648 kb
Host smart-4d39d155-5ba1-416f-82a0-052ce88ddbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862716065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1862716065
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1442287886
Short name T141
Test name
Test status
Simulation time 17381549807 ps
CPU time 23.88 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 181852 kb
Host smart-bb402ed1-fbd0-4ea0-ab3d-75d53f6b7366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442287886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1442287886
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2724522565
Short name T308
Test name
Test status
Simulation time 493459895 ps
CPU time 0.71 seconds
Started Dec 27 12:28:27 PM PST 23
Finished Dec 27 12:29:16 PM PST 23
Peak memory 182224 kb
Host smart-da9a5355-0fae-4574-897b-3169f2e889ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724522565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2724522565
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3675137280
Short name T226
Test name
Test status
Simulation time 59275706218 ps
CPU time 82.91 seconds
Started Dec 27 12:27:02 PM PST 23
Finished Dec 27 12:28:49 PM PST 23
Peak memory 181824 kb
Host smart-7a09bb8c-cf64-4f09-9928-65e3a5afdedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675137280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3675137280
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1108710990
Short name T36
Test name
Test status
Simulation time 7502999147 ps
CPU time 10.82 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:25:28 PM PST 23
Peak memory 213532 kb
Host smart-e08ba3be-1218-40e9-afb1-1cc1dec6fac2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108710990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1108710990
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3304396294
Short name T312
Test name
Test status
Simulation time 445609009 ps
CPU time 0.73 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 182228 kb
Host smart-c6379800-e633-4755-8ec3-348adef7385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304396294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3304396294
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3887599950
Short name T247
Test name
Test status
Simulation time 32281780188 ps
CPU time 12.55 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:42 PM PST 23
Peak memory 191524 kb
Host smart-03833e95-c096-482f-8d14-77374e26f067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887599950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3887599950
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2547196612
Short name T137
Test name
Test status
Simulation time 74748865528 ps
CPU time 603.29 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:39:48 PM PST 23
Peak memory 197256 kb
Host smart-38d6956f-5554-41af-95f6-82999cc5b420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547196612 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2547196612
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2615022285
Short name T123
Test name
Test status
Simulation time 569966348 ps
CPU time 0.85 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:26:07 PM PST 23
Peak memory 181756 kb
Host smart-bd138f58-8654-480d-89e5-d611fe14a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615022285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2615022285
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3298614354
Short name T290
Test name
Test status
Simulation time 4621960571 ps
CPU time 3.49 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 12:27:11 PM PST 23
Peak memory 182472 kb
Host smart-27f6f1a7-d2a9-4c20-82fa-86f19aba8300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298614354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3298614354
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2860603293
Short name T227
Test name
Test status
Simulation time 455638003 ps
CPU time 0.82 seconds
Started Dec 27 12:25:23 PM PST 23
Finished Dec 27 12:25:33 PM PST 23
Peak memory 182308 kb
Host smart-8d1d9baf-6cfe-44e7-8333-51e565a5b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860603293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2860603293
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.121607355
Short name T109
Test name
Test status
Simulation time 305077576404 ps
CPU time 431.34 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 191680 kb
Host smart-439e6300-eb30-4cbc-ad21-e9c22e514d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121607355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.121607355
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4184233766
Short name T282
Test name
Test status
Simulation time 79334919437 ps
CPU time 139.1 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:31:17 PM PST 23
Peak memory 197260 kb
Host smart-e1c353d9-77dc-4641-9cd6-aae0ffc2adc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184233766 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4184233766
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.4279272479
Short name T259
Test name
Test status
Simulation time 348407055 ps
CPU time 0.81 seconds
Started Dec 27 12:27:30 PM PST 23
Finished Dec 27 12:28:00 PM PST 23
Peak memory 182612 kb
Host smart-59ef6f50-5741-4ed0-9239-11fb50dc34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279272479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.4279272479
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3323438855
Short name T192
Test name
Test status
Simulation time 34833577965 ps
CPU time 58.18 seconds
Started Dec 27 12:28:22 PM PST 23
Finished Dec 27 12:30:07 PM PST 23
Peak memory 182476 kb
Host smart-bbfcd55d-7628-44d0-be0c-72a15fb7fca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323438855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3323438855
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3201663249
Short name T279
Test name
Test status
Simulation time 387200128 ps
CPU time 0.6 seconds
Started Dec 27 12:22:05 PM PST 23
Finished Dec 27 12:22:07 PM PST 23
Peak memory 182540 kb
Host smart-d1dcf866-00e2-41f7-8a5e-14621a37a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201663249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3201663249
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3462396372
Short name T130
Test name
Test status
Simulation time 38691895970 ps
CPU time 60.43 seconds
Started Dec 27 12:20:09 PM PST 23
Finished Dec 27 12:21:11 PM PST 23
Peak memory 193848 kb
Host smart-8428a431-5927-4c88-9575-31a28ec58df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462396372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3462396372
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2950848952
Short name T38
Test name
Test status
Simulation time 90013639098 ps
CPU time 242.1 seconds
Started Dec 27 12:20:02 PM PST 23
Finished Dec 27 12:24:05 PM PST 23
Peak memory 196796 kb
Host smart-7ed4ef26-6b0a-45c8-aeb3-47b149271eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950848952 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2950848952
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2723556103
Short name T243
Test name
Test status
Simulation time 538748507 ps
CPU time 0.79 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:28:53 PM PST 23
Peak memory 181804 kb
Host smart-dc8616f4-38fd-4fca-a027-db5544d61e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723556103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2723556103
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3555250091
Short name T311
Test name
Test status
Simulation time 20398516716 ps
CPU time 16.52 seconds
Started Dec 27 12:26:32 PM PST 23
Finished Dec 27 12:27:03 PM PST 23
Peak memory 182536 kb
Host smart-2d85ee74-22ce-4cb8-8d94-419fabbee858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555250091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3555250091
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2702329741
Short name T219
Test name
Test status
Simulation time 541800638 ps
CPU time 0.64 seconds
Started Dec 27 12:21:24 PM PST 23
Finished Dec 27 12:21:25 PM PST 23
Peak memory 182524 kb
Host smart-aaa21340-b49e-4158-9c99-a1bb8824a519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702329741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2702329741
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3042998395
Short name T104
Test name
Test status
Simulation time 146362334567 ps
CPU time 274.52 seconds
Started Dec 27 12:22:26 PM PST 23
Finished Dec 27 12:27:02 PM PST 23
Peak memory 197540 kb
Host smart-cf7a3661-50bb-45ba-afc8-26049c724db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042998395 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3042998395
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1002521417
Short name T235
Test name
Test status
Simulation time 543471468 ps
CPU time 0.79 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:31 PM PST 23
Peak memory 180780 kb
Host smart-8abca2f8-b5c3-4e11-b8e5-715eacd882c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002521417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1002521417
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.554390656
Short name T193
Test name
Test status
Simulation time 15131556945 ps
CPU time 6.61 seconds
Started Dec 27 12:28:47 PM PST 23
Finished Dec 27 12:29:58 PM PST 23
Peak memory 182436 kb
Host smart-6be2528b-73cb-4def-bfeb-77d9bae6d161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554390656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.554390656
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3663770126
Short name T179
Test name
Test status
Simulation time 521539507 ps
CPU time 0.74 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:31 PM PST 23
Peak memory 180780 kb
Host smart-6552cf01-7fe1-40f7-a1d0-741b4466c7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663770126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3663770126
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.176359217
Short name T238
Test name
Test status
Simulation time 292365720313 ps
CPU time 120.77 seconds
Started Dec 27 12:26:23 PM PST 23
Finished Dec 27 12:28:38 PM PST 23
Peak memory 190588 kb
Host smart-5c67f317-7593-4207-86d8-672702b0f37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176359217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.176359217
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2645585271
Short name T276
Test name
Test status
Simulation time 363268457 ps
CPU time 1.09 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:20:30 PM PST 23
Peak memory 182456 kb
Host smart-ac8d92e5-7ab2-4eeb-84be-d0b73ae5e5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645585271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2645585271
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3550283426
Short name T164
Test name
Test status
Simulation time 32154461531 ps
CPU time 53.25 seconds
Started Dec 27 12:27:01 PM PST 23
Finished Dec 27 12:28:17 PM PST 23
Peak memory 182284 kb
Host smart-62d0e5fa-3854-4484-85b8-804c9d7e1dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550283426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3550283426
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3451858014
Short name T252
Test name
Test status
Simulation time 470689114 ps
CPU time 1.32 seconds
Started Dec 27 12:21:02 PM PST 23
Finished Dec 27 12:21:04 PM PST 23
Peak memory 182508 kb
Host smart-286134f2-df6c-4e3e-9b5d-37e3f0e56e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451858014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3451858014
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1987942170
Short name T136
Test name
Test status
Simulation time 76736342018 ps
CPU time 126.48 seconds
Started Dec 27 12:22:56 PM PST 23
Finished Dec 27 12:25:04 PM PST 23
Peak memory 182704 kb
Host smart-35ed8d24-f42d-479a-b348-3977e9fda0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987942170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1987942170
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2735653159
Short name T262
Test name
Test status
Simulation time 46480443572 ps
CPU time 360.69 seconds
Started Dec 27 12:28:38 PM PST 23
Finished Dec 27 12:35:30 PM PST 23
Peak memory 195968 kb
Host smart-6249ee26-3287-4a68-98e5-b6ae575796f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735653159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2735653159
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1629656554
Short name T202
Test name
Test status
Simulation time 500774537 ps
CPU time 0.71 seconds
Started Dec 27 12:24:18 PM PST 23
Finished Dec 27 12:24:19 PM PST 23
Peak memory 182792 kb
Host smart-f6ef3d09-8572-465d-8ff2-4b698fb0edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629656554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1629656554
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1840454873
Short name T287
Test name
Test status
Simulation time 31687277173 ps
CPU time 21.27 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:58 PM PST 23
Peak memory 181164 kb
Host smart-2efffa0a-4117-4536-a842-a3917ae4ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840454873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1840454873
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3079444903
Short name T182
Test name
Test status
Simulation time 605687330 ps
CPU time 0.66 seconds
Started Dec 27 12:26:21 PM PST 23
Finished Dec 27 12:26:37 PM PST 23
Peak memory 180388 kb
Host smart-0d12258e-6951-4db1-8525-8700a7ebe574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079444903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3079444903
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_jump.528499514
Short name T131
Test name
Test status
Simulation time 484368051 ps
CPU time 0.59 seconds
Started Dec 27 12:26:29 PM PST 23
Finished Dec 27 12:26:44 PM PST 23
Peak memory 182472 kb
Host smart-0ab680a3-7639-49e7-bd24-c07128948602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528499514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.528499514
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2894833919
Short name T171
Test name
Test status
Simulation time 26511894923 ps
CPU time 7.32 seconds
Started Dec 27 12:25:51 PM PST 23
Finished Dec 27 12:26:04 PM PST 23
Peak memory 182592 kb
Host smart-73e1cf07-c0d7-489f-b18e-3d201e1f4bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894833919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2894833919
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2538028003
Short name T60
Test name
Test status
Simulation time 497257026 ps
CPU time 0.61 seconds
Started Dec 27 12:24:09 PM PST 23
Finished Dec 27 12:24:11 PM PST 23
Peak memory 182672 kb
Host smart-db7ba5d1-1587-4f69-bf7c-75324eba6dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538028003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2538028003
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1073030963
Short name T213
Test name
Test status
Simulation time 199175912061 ps
CPU time 170.45 seconds
Started Dec 27 12:25:50 PM PST 23
Finished Dec 27 12:28:46 PM PST 23
Peak memory 182624 kb
Host smart-5bc1c24f-ae3a-4aff-a2ec-474362c2e226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073030963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1073030963
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1221598193
Short name T183
Test name
Test status
Simulation time 52962578518 ps
CPU time 244.82 seconds
Started Dec 27 12:25:50 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 197420 kb
Host smart-daefb952-0938-447d-8fca-5ed917a4d44d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221598193 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1221598193
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3832374204
Short name T113
Test name
Test status
Simulation time 499882168 ps
CPU time 1.33 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 180724 kb
Host smart-4af9b2b4-d697-4df5-ab23-aa5af4f08c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832374204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3832374204
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3759525276
Short name T168
Test name
Test status
Simulation time 28342442646 ps
CPU time 41.12 seconds
Started Dec 27 12:25:51 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 182592 kb
Host smart-d2771c3d-5116-4c1a-995d-7175aa853af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759525276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3759525276
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4284350881
Short name T151
Test name
Test status
Simulation time 421327565 ps
CPU time 1.19 seconds
Started Dec 27 12:25:33 PM PST 23
Finished Dec 27 12:25:40 PM PST 23
Peak memory 182212 kb
Host smart-28ad4073-a34a-4a7e-baa9-2928ab244716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284350881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4284350881
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3965856786
Short name T307
Test name
Test status
Simulation time 184301969628 ps
CPU time 91.03 seconds
Started Dec 27 12:27:16 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 192208 kb
Host smart-49858bf9-f36f-444d-9a9b-2e6d1b8bd478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965856786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3965856786
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2761612922
Short name T251
Test name
Test status
Simulation time 258990024852 ps
CPU time 455.64 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 205780 kb
Host smart-af690dba-8e36-46e1-972e-4ad12256c994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761612922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2761612922
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2503504186
Short name T143
Test name
Test status
Simulation time 443818439 ps
CPU time 0.71 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 182348 kb
Host smart-591def86-6557-48e5-864b-7cbaa8619e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503504186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2503504186
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1166489554
Short name T149
Test name
Test status
Simulation time 26149957385 ps
CPU time 11.07 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:08 PM PST 23
Peak memory 181236 kb
Host smart-69c2b23d-0dd0-4666-89a7-f1ef98c8919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166489554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1166489554
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2290505762
Short name T266
Test name
Test status
Simulation time 494626192 ps
CPU time 0.9 seconds
Started Dec 27 12:27:59 PM PST 23
Finished Dec 27 12:28:33 PM PST 23
Peak memory 182372 kb
Host smart-d2ab4ac8-8e8d-468e-9d2b-672c415352e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290505762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2290505762
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3381828330
Short name T284
Test name
Test status
Simulation time 38398293689 ps
CPU time 300.37 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:34:42 PM PST 23
Peak memory 197420 kb
Host smart-28c1408d-8ace-4cd8-9d10-bba4225443a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381828330 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3381828330
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.3051661191
Short name T304
Test name
Test status
Simulation time 438673992 ps
CPU time 1.1 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:26:41 PM PST 23
Peak memory 182572 kb
Host smart-c98cbed0-50d1-4907-8116-3d0d6d1e43d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051661191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.3051661191
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.263652648
Short name T270
Test name
Test status
Simulation time 48457779933 ps
CPU time 66.45 seconds
Started Dec 27 12:25:15 PM PST 23
Finished Dec 27 12:26:27 PM PST 23
Peak memory 182668 kb
Host smart-5182dcc5-44f9-45aa-91f5-f4406486c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263652648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.263652648
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.220373393
Short name T41
Test name
Test status
Simulation time 590265254 ps
CPU time 1.23 seconds
Started Dec 27 12:27:02 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 180532 kb
Host smart-4cc612cd-da8a-4a49-af80-cf7b219aa1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220373393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.220373393
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2240021647
Short name T248
Test name
Test status
Simulation time 180897869103 ps
CPU time 66.52 seconds
Started Dec 27 12:21:25 PM PST 23
Finished Dec 27 12:22:32 PM PST 23
Peak memory 192884 kb
Host smart-296cc9a9-89d9-4e3b-996f-e459b3ed0bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240021647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2240021647
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.324463029
Short name T196
Test name
Test status
Simulation time 29826085687 ps
CPU time 251.69 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 197544 kb
Host smart-5fd29ebb-8f20-43c5-8b33-e046efc710bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324463029 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.324463029
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3280711658
Short name T222
Test name
Test status
Simulation time 407441247 ps
CPU time 0.66 seconds
Started Dec 27 12:26:18 PM PST 23
Finished Dec 27 12:26:32 PM PST 23
Peak memory 182352 kb
Host smart-8de6659e-cac7-4627-93a7-6e22760ec15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280711658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3280711658
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1394184239
Short name T20
Test name
Test status
Simulation time 14818014470 ps
CPU time 11.69 seconds
Started Dec 27 12:25:13 PM PST 23
Finished Dec 27 12:25:28 PM PST 23
Peak memory 181948 kb
Host smart-e4f67a64-88e8-44ee-b434-985e2815626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394184239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1394184239
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2565605573
Short name T34
Test name
Test status
Simulation time 4462027048 ps
CPU time 7.67 seconds
Started Dec 27 12:26:47 PM PST 23
Finished Dec 27 12:27:16 PM PST 23
Peak memory 214008 kb
Host smart-1851c624-5797-4809-9171-335dfadf0a8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565605573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2565605573
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.892561041
Short name T274
Test name
Test status
Simulation time 412652648 ps
CPU time 0.68 seconds
Started Dec 27 12:21:50 PM PST 23
Finished Dec 27 12:21:52 PM PST 23
Peak memory 182524 kb
Host smart-39205c00-12e7-4dac-88aa-a4972a01a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892561041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.892561041
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.320970912
Short name T126
Test name
Test status
Simulation time 106833215249 ps
CPU time 163.99 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:29:30 PM PST 23
Peak memory 191132 kb
Host smart-7deef0fa-c28c-42b8-a2cd-8fd3a4af83da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320970912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.320970912
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3348853187
Short name T144
Test name
Test status
Simulation time 34318573848 ps
CPU time 252.65 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 196452 kb
Host smart-439a6f64-5199-4b2b-9031-b2252895dde4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348853187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3348853187
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1736879161
Short name T249
Test name
Test status
Simulation time 505866580 ps
CPU time 0.78 seconds
Started Dec 27 12:27:02 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 180732 kb
Host smart-8a1562b7-c221-4309-a775-e141a026dbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736879161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1736879161
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2219617684
Short name T256
Test name
Test status
Simulation time 8601766287 ps
CPU time 4.4 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:26:44 PM PST 23
Peak memory 182576 kb
Host smart-d2fc8e77-0ea3-4af9-ab8d-843608ffd790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219617684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2219617684
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2803733786
Short name T156
Test name
Test status
Simulation time 411085125 ps
CPU time 0.78 seconds
Started Dec 27 12:29:16 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 182408 kb
Host smart-bd654af4-694f-45e9-bb4e-7a1bfa2ae4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803733786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2803733786
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.4008154223
Short name T128
Test name
Test status
Simulation time 206861977287 ps
CPU time 301.13 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:31:41 PM PST 23
Peak memory 193988 kb
Host smart-4d0acdd1-fcbe-470c-9453-20af2270acf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008154223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.4008154223
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3148441653
Short name T306
Test name
Test status
Simulation time 35738886699 ps
CPU time 272.87 seconds
Started Dec 27 12:27:16 PM PST 23
Finished Dec 27 12:32:16 PM PST 23
Peak memory 197364 kb
Host smart-0b741cc3-7b68-40ea-b043-f8b8e7974924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148441653 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3148441653
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.2315144502
Short name T133
Test name
Test status
Simulation time 503108498 ps
CPU time 0.72 seconds
Started Dec 27 12:27:19 PM PST 23
Finished Dec 27 12:27:48 PM PST 23
Peak memory 182380 kb
Host smart-2254ee81-6fa2-46dd-85cb-784dd51d8eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315144502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.2315144502
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3896218020
Short name T167
Test name
Test status
Simulation time 5998582468 ps
CPU time 1.6 seconds
Started Dec 27 12:20:27 PM PST 23
Finished Dec 27 12:20:31 PM PST 23
Peak memory 182372 kb
Host smart-d9f95177-07d9-4055-a2a2-a399829fdf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896218020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3896218020
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3693059254
Short name T217
Test name
Test status
Simulation time 371951313 ps
CPU time 0.78 seconds
Started Dec 27 12:28:20 PM PST 23
Finished Dec 27 12:29:07 PM PST 23
Peak memory 182300 kb
Host smart-3084b796-1013-49ba-aa79-262f74b249b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693059254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3693059254
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2592913561
Short name T134
Test name
Test status
Simulation time 177649568769 ps
CPU time 296.45 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 191520 kb
Host smart-fa67dd7d-4f95-497a-a48d-04c3e6e6fcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592913561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2592913561
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3212615904
Short name T56
Test name
Test status
Simulation time 37722059554 ps
CPU time 152.55 seconds
Started Dec 27 12:26:30 PM PST 23
Finished Dec 27 12:29:18 PM PST 23
Peak memory 197156 kb
Host smart-b791b54a-36f5-484f-9554-9595c85a17c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212615904 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3212615904
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3911367702
Short name T178
Test name
Test status
Simulation time 487098337 ps
CPU time 0.7 seconds
Started Dec 27 12:21:18 PM PST 23
Finished Dec 27 12:21:19 PM PST 23
Peak memory 182576 kb
Host smart-a10def02-1f63-4d27-8636-f0243dd1b2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911367702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3911367702
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1842256615
Short name T253
Test name
Test status
Simulation time 17466561648 ps
CPU time 7.2 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:29:40 PM PST 23
Peak memory 182476 kb
Host smart-25ad5ba7-2492-484a-a28b-2af8baa8b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842256615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1842256615
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4155676931
Short name T188
Test name
Test status
Simulation time 338660497 ps
CPU time 0.84 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:37 PM PST 23
Peak memory 181068 kb
Host smart-93d90992-dbd6-46bc-9b29-08b2649b262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155676931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4155676931
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4228644682
Short name T267
Test name
Test status
Simulation time 297959007636 ps
CPU time 429.36 seconds
Started Dec 27 12:27:04 PM PST 23
Finished Dec 27 12:34:38 PM PST 23
Peak memory 188900 kb
Host smart-985c7e9e-9484-4e6e-a2c1-4366523929b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228644682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4228644682
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3731409349
Short name T257
Test name
Test status
Simulation time 199558473974 ps
CPU time 387.96 seconds
Started Dec 27 12:27:04 PM PST 23
Finished Dec 27 12:33:56 PM PST 23
Peak memory 195684 kb
Host smart-77355125-b8a4-4873-b474-8d99d3c0dbe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731409349 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3731409349
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2694039517
Short name T127
Test name
Test status
Simulation time 421585863 ps
CPU time 0.77 seconds
Started Dec 27 12:26:21 PM PST 23
Finished Dec 27 12:26:37 PM PST 23
Peak memory 180804 kb
Host smart-919a83d9-9980-4bcd-90df-4f7212c3fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694039517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2694039517
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.965456556
Short name T295
Test name
Test status
Simulation time 13400742012 ps
CPU time 4.98 seconds
Started Dec 27 12:21:18 PM PST 23
Finished Dec 27 12:21:24 PM PST 23
Peak memory 182700 kb
Host smart-e42dfcf2-3a45-465e-afab-2554ee1ed0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965456556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.965456556
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.98244955
Short name T154
Test name
Test status
Simulation time 422354955 ps
CPU time 0.72 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:31 PM PST 23
Peak memory 180452 kb
Host smart-c58c424d-0ba5-4e50-90fd-aa78e80062d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98244955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.98244955
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2930181396
Short name T268
Test name
Test status
Simulation time 193724373527 ps
CPU time 69.79 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:29:06 PM PST 23
Peak memory 182316 kb
Host smart-d8b31e88-5aaf-46b7-b5bc-e3a94f2cb151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930181396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2930181396
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.647578333
Short name T220
Test name
Test status
Simulation time 442852301420 ps
CPU time 804.49 seconds
Started Dec 27 12:25:22 PM PST 23
Finished Dec 27 12:38:56 PM PST 23
Peak memory 201776 kb
Host smart-7296089a-2dae-4e02-9970-c70c2113835d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647578333 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.647578333
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1355096270
Short name T190
Test name
Test status
Simulation time 435279332 ps
CPU time 0.76 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 180676 kb
Host smart-ff3fe46b-e1e5-4ee0-a45b-4ef3a147fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355096270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1355096270
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.129362858
Short name T185
Test name
Test status
Simulation time 5537490414 ps
CPU time 1.33 seconds
Started Dec 27 12:24:59 PM PST 23
Finished Dec 27 12:25:03 PM PST 23
Peak memory 182592 kb
Host smart-dedb1e94-3b49-4b59-a32e-74a01aa51ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129362858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.129362858
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2302309501
Short name T203
Test name
Test status
Simulation time 383892496 ps
CPU time 1.15 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:32 PM PST 23
Peak memory 180452 kb
Host smart-d1abc2c4-248c-4e29-9853-24736addb2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302309501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2302309501
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1414475713
Short name T84
Test name
Test status
Simulation time 268949323621 ps
CPU time 101.13 seconds
Started Dec 27 12:22:34 PM PST 23
Finished Dec 27 12:24:15 PM PST 23
Peak memory 182696 kb
Host smart-8243a1bf-053d-4b3b-8f32-e38c54638130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414475713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1414475713
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3159732856
Short name T59
Test name
Test status
Simulation time 35864022235 ps
CPU time 300.87 seconds
Started Dec 27 12:25:50 PM PST 23
Finished Dec 27 12:30:56 PM PST 23
Peak memory 197464 kb
Host smart-5f071e07-d24a-4212-9f12-10ecb55c9fcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159732856 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3159732856
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.836286130
Short name T124
Test name
Test status
Simulation time 422717846 ps
CPU time 1.19 seconds
Started Dec 27 12:25:02 PM PST 23
Finished Dec 27 12:25:06 PM PST 23
Peak memory 182788 kb
Host smart-1aab42b3-b091-47c4-bc54-df1703d9eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836286130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.836286130
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.449637791
Short name T161
Test name
Test status
Simulation time 54383265140 ps
CPU time 92.32 seconds
Started Dec 27 12:27:41 PM PST 23
Finished Dec 27 12:29:44 PM PST 23
Peak memory 181516 kb
Host smart-3276baf9-55a2-4bad-9fb0-d3107f5f9d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449637791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.449637791
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3898815813
Short name T245
Test name
Test status
Simulation time 578678552 ps
CPU time 1.44 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 181036 kb
Host smart-7ed7e63e-d7dc-4071-a953-5854ba0e74ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898815813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3898815813
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.250608832
Short name T114
Test name
Test status
Simulation time 197203162076 ps
CPU time 173.88 seconds
Started Dec 27 12:22:57 PM PST 23
Finished Dec 27 12:25:53 PM PST 23
Peak memory 182728 kb
Host smart-5873a68a-b9cb-436a-ad54-55c97c49439a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250608832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.250608832
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4213179531
Short name T275
Test name
Test status
Simulation time 43247588875 ps
CPU time 167.15 seconds
Started Dec 27 12:25:15 PM PST 23
Finished Dec 27 12:28:08 PM PST 23
Peak memory 196264 kb
Host smart-4f6dbf80-80cd-4f24-8a27-5cb076ef6616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213179531 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4213179531
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3579933209
Short name T258
Test name
Test status
Simulation time 455483768 ps
CPU time 0.86 seconds
Started Dec 27 12:29:05 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 182356 kb
Host smart-50e69852-c2b1-41bf-94d2-02406067dfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579933209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3579933209
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2164327709
Short name T297
Test name
Test status
Simulation time 7020298332 ps
CPU time 1.64 seconds
Started Dec 27 12:24:08 PM PST 23
Finished Dec 27 12:24:11 PM PST 23
Peak memory 182716 kb
Host smart-d1222a65-8ecb-4bfa-91b8-4b4393eb71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164327709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2164327709
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.267810175
Short name T163
Test name
Test status
Simulation time 460875848 ps
CPU time 0.63 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:29:55 PM PST 23
Peak memory 182244 kb
Host smart-2dab83a3-1f1d-42a0-9224-a167f6bdd6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267810175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.267810175
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1082040590
Short name T142
Test name
Test status
Simulation time 18878019425 ps
CPU time 6.99 seconds
Started Dec 27 12:25:50 PM PST 23
Finished Dec 27 12:26:02 PM PST 23
Peak memory 192816 kb
Host smart-a698bf05-b228-4ec6-b22c-6982fcc7dfaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082040590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1082040590
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2536646974
Short name T240
Test name
Test status
Simulation time 547247782 ps
CPU time 1.35 seconds
Started Dec 27 12:24:35 PM PST 23
Finished Dec 27 12:24:38 PM PST 23
Peak memory 181684 kb
Host smart-36746714-fe1c-44e7-800b-e60133d0d408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536646974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2536646974
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3418034441
Short name T242
Test name
Test status
Simulation time 10600480351 ps
CPU time 7.91 seconds
Started Dec 27 12:27:42 PM PST 23
Finished Dec 27 12:28:21 PM PST 23
Peak memory 182244 kb
Host smart-0b93e23a-f5bf-4927-aa36-5dc190ae06f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418034441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3418034441
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2803777693
Short name T158
Test name
Test status
Simulation time 541229236 ps
CPU time 0.98 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:32 PM PST 23
Peak memory 181480 kb
Host smart-e4c291a7-6bc6-43a4-bca0-ddb94b0de4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803777693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2803777693
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.901968483
Short name T289
Test name
Test status
Simulation time 174070537170 ps
CPU time 294.4 seconds
Started Dec 27 12:25:35 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 193620 kb
Host smart-246e342b-343c-4fe1-b5d1-017612265558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901968483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.901968483
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.4087860605
Short name T206
Test name
Test status
Simulation time 398730796 ps
CPU time 0.67 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:28:09 PM PST 23
Peak memory 182272 kb
Host smart-680e8dfd-b5ec-4acc-9418-919b8c20c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087860605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.4087860605
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.4246021734
Short name T283
Test name
Test status
Simulation time 35423284402 ps
CPU time 62.53 seconds
Started Dec 27 12:25:18 PM PST 23
Finished Dec 27 12:26:30 PM PST 23
Peak memory 181448 kb
Host smart-03b57e6a-d0d8-474a-bd1d-801c01215b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246021734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.4246021734
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1652173402
Short name T302
Test name
Test status
Simulation time 407390552 ps
CPU time 0.69 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:26:18 PM PST 23
Peak memory 181672 kb
Host smart-36bc0f64-bb5c-4057-9ad6-1a385f7fe5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652173402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1652173402
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2506534576
Short name T32
Test name
Test status
Simulation time 5786635428 ps
CPU time 2.9 seconds
Started Dec 27 12:27:01 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 192816 kb
Host smart-56e0dcfc-9d1a-4f2d-b3b5-7ca2335bca42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506534576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2506534576
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3143010795
Short name T301
Test name
Test status
Simulation time 45894850130 ps
CPU time 185.29 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 197528 kb
Host smart-b488229a-5d19-4442-b8cd-dd8d7b6a6ef0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143010795 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3143010795
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.703913798
Short name T187
Test name
Test status
Simulation time 480207125 ps
CPU time 1.24 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:31 PM PST 23
Peak memory 181124 kb
Host smart-7e91033f-44eb-4bad-954e-50704a04eeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703913798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.703913798
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1853707424
Short name T254
Test name
Test status
Simulation time 44488588525 ps
CPU time 5.28 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:29:00 PM PST 23
Peak memory 180852 kb
Host smart-afe4d04f-8a12-4511-a16a-382d0cee9b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853707424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1853707424
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3861469505
Short name T57
Test name
Test status
Simulation time 523811319 ps
CPU time 1.29 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 181376 kb
Host smart-60e57053-fd22-4d85-87b4-45677e9da84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861469505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3861469505
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4228639827
Short name T216
Test name
Test status
Simulation time 359134318106 ps
CPU time 528.61 seconds
Started Dec 27 12:26:34 PM PST 23
Finished Dec 27 12:35:39 PM PST 23
Peak memory 193992 kb
Host smart-177198a2-71f1-43db-870b-8134b5b9d9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228639827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4228639827
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.207658603
Short name T285
Test name
Test status
Simulation time 130663217717 ps
CPU time 363.81 seconds
Started Dec 27 12:25:34 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 197356 kb
Host smart-4b49b705-e77e-499b-bcd6-e4cbed51c05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207658603 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.207658603
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2320383105
Short name T273
Test name
Test status
Simulation time 347493346 ps
CPU time 0.67 seconds
Started Dec 27 12:26:52 PM PST 23
Finished Dec 27 12:27:13 PM PST 23
Peak memory 182340 kb
Host smart-b4f53086-e87c-4cb7-9e84-d8515a3113f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320383105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2320383105
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.922410461
Short name T218
Test name
Test status
Simulation time 54947027996 ps
CPU time 85.39 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:31:14 PM PST 23
Peak memory 182376 kb
Host smart-1bb4919d-3159-4d82-9172-b070ab465579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922410461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.922410461
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.613742981
Short name T31
Test name
Test status
Simulation time 4240958900 ps
CPU time 7.15 seconds
Started Dec 27 12:26:33 PM PST 23
Finished Dec 27 12:26:55 PM PST 23
Peak memory 214912 kb
Host smart-7bb99662-c7d3-43b2-bc25-21069b25e2d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613742981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.613742981
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2356938422
Short name T155
Test name
Test status
Simulation time 401174562 ps
CPU time 0.79 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:24:57 PM PST 23
Peak memory 182684 kb
Host smart-5e2b8723-48ef-41e0-942b-5fb49d74c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356938422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2356938422
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3812914568
Short name T299
Test name
Test status
Simulation time 251419341932 ps
CPU time 132.68 seconds
Started Dec 27 12:27:03 PM PST 23
Finished Dec 27 12:29:39 PM PST 23
Peak memory 182456 kb
Host smart-4396cdd3-f391-436f-aa9b-537254b8f78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812914568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3812914568
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1935791229
Short name T260
Test name
Test status
Simulation time 102457977106 ps
CPU time 331.01 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:35:19 PM PST 23
Peak memory 197312 kb
Host smart-22a1b59c-e73b-49ac-9b5c-1182701627a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935791229 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1935791229
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3740265452
Short name T116
Test name
Test status
Simulation time 504381686 ps
CPU time 1.31 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:29:51 PM PST 23
Peak memory 182396 kb
Host smart-d2256aff-4ec1-41cd-9fb2-c6c10591d24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740265452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3740265452
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.93029027
Short name T231
Test name
Test status
Simulation time 12028558329 ps
CPU time 4.89 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:29:50 PM PST 23
Peak memory 182364 kb
Host smart-2b1c978a-474b-418d-ade2-14a8ff0b7064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93029027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.93029027
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1580716342
Short name T186
Test name
Test status
Simulation time 524835300 ps
CPU time 1.32 seconds
Started Dec 27 12:25:33 PM PST 23
Finished Dec 27 12:25:41 PM PST 23
Peak memory 182212 kb
Host smart-3b08172d-e284-4d37-80e6-4f5ef7928072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580716342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1580716342
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.3221225729
Short name T263
Test name
Test status
Simulation time 60953601993 ps
CPU time 91.32 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 182352 kb
Host smart-730ccec4-d984-4c78-a1ee-702c47e2969b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221225729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.3221225729
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1074217305
Short name T210
Test name
Test status
Simulation time 508791272 ps
CPU time 1.25 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:29:51 PM PST 23
Peak memory 182396 kb
Host smart-2df1cce5-0b1d-4ee0-8ab4-4eabf38b6af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074217305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1074217305
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.947418278
Short name T166
Test name
Test status
Simulation time 16152418851 ps
CPU time 13.95 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:29:08 PM PST 23
Peak memory 180928 kb
Host smart-28933ab3-c7cc-4121-b991-5f1f488165ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947418278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.947418278
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.4183984716
Short name T42
Test name
Test status
Simulation time 369576668 ps
CPU time 0.63 seconds
Started Dec 27 12:20:27 PM PST 23
Finished Dec 27 12:20:30 PM PST 23
Peak memory 182512 kb
Host smart-02ee4576-5b53-4af6-8885-81bfc3d83796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183984716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.4183984716
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2395934457
Short name T241
Test name
Test status
Simulation time 119990344649 ps
CPU time 46.16 seconds
Started Dec 27 12:22:41 PM PST 23
Finished Dec 27 12:23:32 PM PST 23
Peak memory 182788 kb
Host smart-95fef98a-817b-4da1-b3dd-8c1254d1e18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395934457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2395934457
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3864725964
Short name T62
Test name
Test status
Simulation time 65695844943 ps
CPU time 483 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:37:23 PM PST 23
Peak memory 197332 kb
Host smart-3cd07558-ce21-4d7b-a793-0c5ff8cf897b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864725964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3864725964
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1673534189
Short name T165
Test name
Test status
Simulation time 544506555 ps
CPU time 0.69 seconds
Started Dec 27 12:24:34 PM PST 23
Finished Dec 27 12:24:36 PM PST 23
Peak memory 182276 kb
Host smart-77f7e7e9-4aee-423e-ada1-2e4cd1143ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673534189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1673534189
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3366622740
Short name T153
Test name
Test status
Simulation time 54868673062 ps
CPU time 85.62 seconds
Started Dec 27 12:21:31 PM PST 23
Finished Dec 27 12:22:57 PM PST 23
Peak memory 182520 kb
Host smart-6df77e8b-c62e-4516-9b7f-810b5aa25d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366622740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3366622740
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3744829216
Short name T173
Test name
Test status
Simulation time 514613092 ps
CPU time 0.64 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:29:56 PM PST 23
Peak memory 182252 kb
Host smart-f111c351-6b4e-4deb-aa75-e68136f035f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744829216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3744829216
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1536902860
Short name T125
Test name
Test status
Simulation time 3225107117 ps
CPU time 5.88 seconds
Started Dec 27 12:24:54 PM PST 23
Finished Dec 27 12:25:01 PM PST 23
Peak memory 182620 kb
Host smart-0de88771-1bbd-4e0e-a5de-b861d76aa2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536902860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1536902860
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.169713242
Short name T23
Test name
Test status
Simulation time 269639477060 ps
CPU time 278.9 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:34:27 PM PST 23
Peak memory 197260 kb
Host smart-51e09779-86f3-4387-92d9-202e69096251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169713242 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.169713242
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.314737810
Short name T135
Test name
Test status
Simulation time 344847051 ps
CPU time 1.2 seconds
Started Dec 27 12:24:33 PM PST 23
Finished Dec 27 12:24:36 PM PST 23
Peak memory 180848 kb
Host smart-6c13a4fa-a147-494f-84fc-cc658df9193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314737810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.314737810
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1802131087
Short name T175
Test name
Test status
Simulation time 4584044507 ps
CPU time 2.03 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:29:47 PM PST 23
Peak memory 182348 kb
Host smart-e2b4affe-56ad-4052-ac52-bf71d7b4e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802131087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1802131087
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1060257096
Short name T300
Test name
Test status
Simulation time 641315496 ps
CPU time 0.71 seconds
Started Dec 27 12:24:33 PM PST 23
Finished Dec 27 12:24:36 PM PST 23
Peak memory 180792 kb
Host smart-c0033135-c98a-4b80-b153-5ff66d800ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060257096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1060257096
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3737351476
Short name T129
Test name
Test status
Simulation time 144404289451 ps
CPU time 201.96 seconds
Started Dec 27 12:19:51 PM PST 23
Finished Dec 27 12:23:14 PM PST 23
Peak memory 182572 kb
Host smart-dfacadb0-96e1-4db6-a860-cfb96f5c2ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737351476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3737351476
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1152550969
Short name T305
Test name
Test status
Simulation time 107179478341 ps
CPU time 387.51 seconds
Started Dec 27 12:28:41 PM PST 23
Finished Dec 27 12:36:00 PM PST 23
Peak memory 197276 kb
Host smart-1a5f6c2b-2f63-4e44-92f4-1ebc6f7ccb53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152550969 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1152550969
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.4140141753
Short name T232
Test name
Test status
Simulation time 484833051 ps
CPU time 1.21 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:29:12 PM PST 23
Peak memory 182372 kb
Host smart-2e074c1b-b865-4c99-923c-ecb806cc0baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140141753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.4140141753
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.997346199
Short name T278
Test name
Test status
Simulation time 23336237840 ps
CPU time 37.42 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:30:13 PM PST 23
Peak memory 182404 kb
Host smart-0b2f8817-ebbe-4dba-8794-b453430e2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997346199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.997346199
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1991447326
Short name T58
Test name
Test status
Simulation time 587821336 ps
CPU time 1.37 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:29:52 PM PST 23
Peak memory 182368 kb
Host smart-0571b37c-a9c3-4b3e-8abb-90dd9493900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991447326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1991447326
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2845788457
Short name T228
Test name
Test status
Simulation time 353539128512 ps
CPU time 538.82 seconds
Started Dec 27 12:28:57 PM PST 23
Finished Dec 27 12:38:51 PM PST 23
Peak memory 192608 kb
Host smart-381b1940-231c-4ad1-846f-d9c075ffb74b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845788457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2845788457
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.352446612
Short name T102
Test name
Test status
Simulation time 141334419240 ps
CPU time 276.14 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:30:22 PM PST 23
Peak memory 197480 kb
Host smart-b0255026-be7f-4c47-af9b-3553ed67439d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352446612 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.352446612
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3573972025
Short name T139
Test name
Test status
Simulation time 497708290 ps
CPU time 0.83 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:25:45 PM PST 23
Peak memory 182576 kb
Host smart-4076e372-687b-4d7d-b1eb-9c20bbed5484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573972025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3573972025
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1453094278
Short name T194
Test name
Test status
Simulation time 24068392553 ps
CPU time 20.98 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:41 PM PST 23
Peak memory 182388 kb
Host smart-c056d3a4-706a-49e3-80d5-df3879078eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453094278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1453094278
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.902697190
Short name T246
Test name
Test status
Simulation time 499884067 ps
CPU time 0.68 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:17 PM PST 23
Peak memory 182212 kb
Host smart-9c84246d-3aee-401a-bf09-eb28ecf4475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902697190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.902697190
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.57013394
Short name T112
Test name
Test status
Simulation time 126926132996 ps
CPU time 199.63 seconds
Started Dec 27 12:21:49 PM PST 23
Finished Dec 27 12:25:09 PM PST 23
Peak memory 193884 kb
Host smart-1a4e2c03-f57f-4d04-bc00-4888de59a04b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57013394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.57013394
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.516299257
Short name T303
Test name
Test status
Simulation time 456969672 ps
CPU time 0.72 seconds
Started Dec 27 12:28:06 PM PST 23
Finished Dec 27 12:28:42 PM PST 23
Peak memory 181780 kb
Host smart-26e586ff-a645-40fb-bc6f-e7ce2cbf7868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516299257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.516299257
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.4092561753
Short name T264
Test name
Test status
Simulation time 590645738 ps
CPU time 1.37 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:25:47 PM PST 23
Peak memory 182288 kb
Host smart-e4a9804b-9598-4a99-8fd9-0c88e6569a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092561753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.4092561753
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1264508289
Short name T189
Test name
Test status
Simulation time 385821009 ps
CPU time 1.18 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:18 PM PST 23
Peak memory 182296 kb
Host smart-5585cd7b-130f-4fa9-a004-26a3d966a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264508289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1264508289
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1894258616
Short name T201
Test name
Test status
Simulation time 183627323523 ps
CPU time 70.03 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:26:55 PM PST 23
Peak memory 182624 kb
Host smart-e9ece316-023c-4102-af50-9e410ac5dd63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894258616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1894258616
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3947895648
Short name T119
Test name
Test status
Simulation time 29937297215 ps
CPU time 219.79 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:33:11 PM PST 23
Peak memory 197280 kb
Host smart-d49e8e2b-30df-4d74-864c-b53882bc4f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947895648 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3947895648
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.768234441
Short name T224
Test name
Test status
Simulation time 530914590 ps
CPU time 0.64 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:25:46 PM PST 23
Peak memory 182548 kb
Host smart-ce6b05c9-41b1-449a-85f6-5abd079008db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768234441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.768234441
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3312120533
Short name T211
Test name
Test status
Simulation time 38039729675 ps
CPU time 58.98 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:26:44 PM PST 23
Peak memory 182612 kb
Host smart-e9f29673-e3dc-4017-a11d-d44d84703508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312120533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3312120533
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4024413376
Short name T191
Test name
Test status
Simulation time 446812528 ps
CPU time 0.75 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:25:16 PM PST 23
Peak memory 180840 kb
Host smart-f69f670d-a23f-48e8-87b9-736296e4e222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024413376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4024413376
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.8385599
Short name T214
Test name
Test status
Simulation time 79388603490 ps
CPU time 622.87 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:35:38 PM PST 23
Peak memory 196572 kb
Host smart-3f7b06bd-ddce-4915-b3a3-9fde72d176f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8385599 -assert nopos
tproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.8385599
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2922046524
Short name T180
Test name
Test status
Simulation time 676161611 ps
CPU time 0.57 seconds
Started Dec 27 12:27:04 PM PST 23
Finished Dec 27 12:27:29 PM PST 23
Peak memory 182492 kb
Host smart-7f73698d-cf24-4036-9166-7eb8b1f51670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922046524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2922046524
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3002055937
Short name T152
Test name
Test status
Simulation time 37238018769 ps
CPU time 30.81 seconds
Started Dec 27 12:28:24 PM PST 23
Finished Dec 27 12:29:42 PM PST 23
Peak memory 182384 kb
Host smart-5e2b0cf9-4635-4ee9-819d-65aeaa712f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002055937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3002055937
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.312704570
Short name T298
Test name
Test status
Simulation time 583553540 ps
CPU time 0.63 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:31 PM PST 23
Peak memory 182268 kb
Host smart-74773b41-bd74-48a1-ad82-23dbe75027df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312704570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.312704570
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1897417677
Short name T199
Test name
Test status
Simulation time 291289312100 ps
CPU time 48.96 seconds
Started Dec 27 12:22:37 PM PST 23
Finished Dec 27 12:23:27 PM PST 23
Peak memory 182676 kb
Host smart-7c63bb59-69f8-414c-aac9-d78e8e88954c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897417677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1897417677
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1056855980
Short name T132
Test name
Test status
Simulation time 15574603524 ps
CPU time 144.65 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:31:49 PM PST 23
Peak memory 197276 kb
Host smart-8b5c0a58-d903-49e1-b959-8a336cfbe9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056855980 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1056855980
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.604382101
Short name T140
Test name
Test status
Simulation time 528939648 ps
CPU time 0.7 seconds
Started Dec 27 12:27:03 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 182388 kb
Host smart-9e13afe3-9df1-467d-aeb2-03bd58c4d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604382101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.604382101
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.245158702
Short name T54
Test name
Test status
Simulation time 38268435396 ps
CPU time 16.23 seconds
Started Dec 27 12:27:03 PM PST 23
Finished Dec 27 12:27:43 PM PST 23
Peak memory 182416 kb
Host smart-7339aeb2-93b5-4223-b34b-97e36972aff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245158702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.245158702
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1828096699
Short name T208
Test name
Test status
Simulation time 579978481 ps
CPU time 0.7 seconds
Started Dec 27 12:26:24 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 182392 kb
Host smart-c982d06a-4f39-4e2b-8264-11abb077a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828096699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1828096699
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2475745615
Short name T271
Test name
Test status
Simulation time 127860402736 ps
CPU time 57.79 seconds
Started Dec 27 12:20:28 PM PST 23
Finished Dec 27 12:21:31 PM PST 23
Peak memory 182660 kb
Host smart-a8be7d12-561d-47cd-8003-2f6f8211a385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475745615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2475745615
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1593066451
Short name T53
Test name
Test status
Simulation time 74378390340 ps
CPU time 374.24 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:35:42 PM PST 23
Peak memory 197292 kb
Host smart-8cc03c10-0d29-4a4e-9cc1-77657483f757
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593066451 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1593066451
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.173642824
Short name T90
Test name
Test status
Simulation time 410186385 ps
CPU time 0.77 seconds
Started Dec 27 12:26:47 PM PST 23
Finished Dec 27 12:27:09 PM PST 23
Peak memory 181884 kb
Host smart-0081bfec-94e6-493e-afa7-f31adf67b6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173642824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.173642824
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1900747684
Short name T83
Test name
Test status
Simulation time 40998846550 ps
CPU time 54.61 seconds
Started Dec 27 12:26:47 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 182308 kb
Host smart-8dbedfaa-7c66-4aaa-b892-13f63ab1f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900747684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1900747684
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2189995048
Short name T35
Test name
Test status
Simulation time 8614538933 ps
CPU time 1.65 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 213504 kb
Host smart-837f287b-10cf-4212-bd1a-beb903d98c13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189995048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2189995048
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1578345661
Short name T272
Test name
Test status
Simulation time 462215983 ps
CPU time 0.67 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 182180 kb
Host smart-9af6d2e9-a54c-4c40-aff9-927e665eda15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578345661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1578345661
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3527715010
Short name T157
Test name
Test status
Simulation time 255404370755 ps
CPU time 327.11 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:30:58 PM PST 23
Peak memory 193652 kb
Host smart-d502bf19-524e-400a-8225-104363fdd7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527715010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3527715010
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1406548655
Short name T98
Test name
Test status
Simulation time 80392397210 ps
CPU time 178.49 seconds
Started Dec 27 12:25:11 PM PST 23
Finished Dec 27 12:28:13 PM PST 23
Peak memory 197380 kb
Host smart-1f0564d7-b4ef-4fc8-88d8-422b5f1c76cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406548655 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1406548655
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2137347484
Short name T12
Test name
Test status
Simulation time 470865668 ps
CPU time 1.28 seconds
Started Dec 27 12:27:13 PM PST 23
Finished Dec 27 12:27:40 PM PST 23
Peak memory 182492 kb
Host smart-ec5287a8-1495-4f33-b67a-f6323df7bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137347484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2137347484
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.12064667
Short name T162
Test name
Test status
Simulation time 41440401356 ps
CPU time 8.25 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:29:02 PM PST 23
Peak memory 180832 kb
Host smart-9f8b34e9-d10c-4a40-bed6-9c8b8e5fd79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12064667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.12064667
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.479424233
Short name T215
Test name
Test status
Simulation time 577297682 ps
CPU time 0.74 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:28:55 PM PST 23
Peak memory 181180 kb
Host smart-bc99b5df-7605-4aa4-8fb5-e30c5be31dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479424233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.479424233
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1298646731
Short name T209
Test name
Test status
Simulation time 110135174841 ps
CPU time 44.37 seconds
Started Dec 27 12:20:18 PM PST 23
Finished Dec 27 12:21:09 PM PST 23
Peak memory 193076 kb
Host smart-4cbcfd30-c4b0-47b1-aaaf-147f470f32fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298646731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1298646731
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3858411063
Short name T177
Test name
Test status
Simulation time 53410912437 ps
CPU time 504.68 seconds
Started Dec 27 12:26:24 PM PST 23
Finished Dec 27 12:35:02 PM PST 23
Peak memory 197408 kb
Host smart-72a0d42f-b442-444d-b191-7925924a96be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858411063 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3858411063
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3725475040
Short name T200
Test name
Test status
Simulation time 16781797554 ps
CPU time 14.11 seconds
Started Dec 27 12:26:42 PM PST 23
Finished Dec 27 12:27:17 PM PST 23
Peak memory 181804 kb
Host smart-912521b9-966c-4ff2-9e40-87166cf32b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725475040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3725475040
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3884504822
Short name T150
Test name
Test status
Simulation time 542867659 ps
CPU time 1.43 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:28:55 PM PST 23
Peak memory 180400 kb
Host smart-72eaba5b-c26e-4d85-92c3-feccca611400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884504822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3884504822
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3228559574
Short name T234
Test name
Test status
Simulation time 193222836169 ps
CPU time 164.79 seconds
Started Dec 27 12:22:40 PM PST 23
Finished Dec 27 12:25:26 PM PST 23
Peak memory 192944 kb
Host smart-c4fec6d6-ad91-49f1-a88c-5c2e3433ca7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228559574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3228559574
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4079028568
Short name T293
Test name
Test status
Simulation time 80811401732 ps
CPU time 495.66 seconds
Started Dec 27 12:26:21 PM PST 23
Finished Dec 27 12:34:51 PM PST 23
Peak memory 197404 kb
Host smart-6ece83fe-81f5-4305-8066-d69cab890a5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079028568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4079028568
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3405197069
Short name T269
Test name
Test status
Simulation time 552515546 ps
CPU time 1.3 seconds
Started Dec 27 12:21:51 PM PST 23
Finished Dec 27 12:21:53 PM PST 23
Peak memory 182612 kb
Host smart-fcb5d0b0-e8dc-4c03-a488-18d28a0fef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405197069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3405197069
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2194698673
Short name T286
Test name
Test status
Simulation time 12588614304 ps
CPU time 5.66 seconds
Started Dec 27 12:26:23 PM PST 23
Finished Dec 27 12:26:43 PM PST 23
Peak memory 182512 kb
Host smart-ecd6eff7-be57-4612-8e3e-a37bc35504cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194698673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2194698673
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.464845547
Short name T212
Test name
Test status
Simulation time 471334653 ps
CPU time 1.31 seconds
Started Dec 27 12:23:14 PM PST 23
Finished Dec 27 12:23:17 PM PST 23
Peak memory 182536 kb
Host smart-768c9719-d47f-4956-add2-9119926ab66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464845547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.464845547
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.2531521889
Short name T225
Test name
Test status
Simulation time 79591772821 ps
CPU time 17.66 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 181868 kb
Host smart-835bd54e-d63c-4b98-b5df-e5f8d4f91e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531521889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.2531521889
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3887206117
Short name T296
Test name
Test status
Simulation time 233137863501 ps
CPU time 405.05 seconds
Started Dec 27 12:21:53 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 197588 kb
Host smart-15fb1f7e-d32e-412b-b999-1539b479edf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887206117 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3887206117
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.915920637
Short name T237
Test name
Test status
Simulation time 496245332 ps
CPU time 0.68 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:28:49 PM PST 23
Peak memory 182580 kb
Host smart-949b5859-731f-46c2-b13e-c2bb0f6045dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915920637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.915920637
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.295436361
Short name T181
Test name
Test status
Simulation time 40673371881 ps
CPU time 60.68 seconds
Started Dec 27 12:28:34 PM PST 23
Finished Dec 27 12:30:24 PM PST 23
Peak memory 182452 kb
Host smart-a32a6bb3-8c37-401f-b322-1863c0d5bfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295436361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.295436361
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3086848318
Short name T277
Test name
Test status
Simulation time 599200955 ps
CPU time 1.3 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:29:51 PM PST 23
Peak memory 182164 kb
Host smart-d3ccd73c-86ea-44d0-b9fe-ff3b3de36dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086848318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3086848318
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.199607086
Short name T50
Test name
Test status
Simulation time 158597946258 ps
CPU time 254.87 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 182344 kb
Host smart-245633db-8527-4524-ba75-1fa544581388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199607086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.199607086
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2162179734
Short name T121
Test name
Test status
Simulation time 22384323046 ps
CPU time 184.44 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 12:33:04 PM PST 23
Peak memory 197344 kb
Host smart-f7254e3b-74e5-4438-b9de-eed8d88d7d12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162179734 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2162179734
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.752766576
Short name T310
Test name
Test status
Simulation time 544758348 ps
CPU time 1.1 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:28:11 PM PST 23
Peak memory 180432 kb
Host smart-13d3ef26-1ced-4219-a69a-b06f4800b14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752766576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.752766576
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.688199188
Short name T146
Test name
Test status
Simulation time 5105467977 ps
CPU time 1.76 seconds
Started Dec 27 12:29:04 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 182444 kb
Host smart-5240f974-6f8a-4a40-ac05-24b7999b7bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688199188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.688199188
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.954312214
Short name T265
Test name
Test status
Simulation time 585454134 ps
CPU time 0.73 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:31 PM PST 23
Peak memory 181636 kb
Host smart-8df761c4-34e3-4b2e-a079-386172c7eb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954312214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.954312214
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.35276222
Short name T184
Test name
Test status
Simulation time 207325006805 ps
CPU time 277.07 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 180880 kb
Host smart-31dbec47-c19d-490a-abe2-60234754c6ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_al
l.35276222
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3585653828
Short name T280
Test name
Test status
Simulation time 651886805980 ps
CPU time 503.19 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:36:33 PM PST 23
Peak memory 195664 kb
Host smart-844572bf-b824-4acc-9aaa-fa11c5290b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585653828 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3585653828
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2054517054
Short name T244
Test name
Test status
Simulation time 382591184 ps
CPU time 1.11 seconds
Started Dec 27 12:29:15 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 182404 kb
Host smart-9d818967-f236-47c1-a702-23beab1b37a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054517054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2054517054
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2262171232
Short name T198
Test name
Test status
Simulation time 24808887999 ps
CPU time 7.29 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:25:35 PM PST 23
Peak memory 182344 kb
Host smart-24d10477-d8c6-48fd-9f86-8b5735a65866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262171232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2262171232
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.485681748
Short name T159
Test name
Test status
Simulation time 598576431 ps
CPU time 0.79 seconds
Started Dec 27 12:25:18 PM PST 23
Finished Dec 27 12:25:28 PM PST 23
Peak memory 181628 kb
Host smart-6f8cb77f-1f04-4ee7-b983-8dff73ae95b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485681748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.485681748
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1941593622
Short name T281
Test name
Test status
Simulation time 101847551445 ps
CPU time 21.9 seconds
Started Dec 27 12:38:10 PM PST 23
Finished Dec 27 12:38:38 PM PST 23
Peak memory 190908 kb
Host smart-f15ff8de-0794-4c9d-b1e0-96bea53a5150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941593622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1941593622
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.4250664913
Short name T110
Test name
Test status
Simulation time 231867815665 ps
CPU time 650.47 seconds
Started Dec 27 12:27:39 PM PST 23
Finished Dec 27 12:39:00 PM PST 23
Peak memory 197604 kb
Host smart-590fa015-3d27-4d49-a6a1-11c6da1fdfdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250664913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.4250664913
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3304330107
Short name T40
Test name
Test status
Simulation time 478714409 ps
CPU time 1.18 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:26:52 PM PST 23
Peak memory 182568 kb
Host smart-445c5607-4f53-4c1c-bbbf-0b95ded11af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304330107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3304330107
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2164474825
Short name T85
Test name
Test status
Simulation time 33688647030 ps
CPU time 11.49 seconds
Started Dec 27 12:28:07 PM PST 23
Finished Dec 27 12:28:55 PM PST 23
Peak memory 182404 kb
Host smart-527b9275-4704-4ad9-a888-f43c4cc42f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164474825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2164474825
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2687358498
Short name T170
Test name
Test status
Simulation time 488300667 ps
CPU time 0.68 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:25:30 PM PST 23
Peak memory 181044 kb
Host smart-d159977b-7d19-4fc3-8b62-6d10c47ab790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687358498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2687358498
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.366541214
Short name T204
Test name
Test status
Simulation time 33176650087 ps
CPU time 12.47 seconds
Started Dec 27 12:21:24 PM PST 23
Finished Dec 27 12:21:37 PM PST 23
Peak memory 182596 kb
Host smart-48c69c0e-a7bc-4a62-a3ea-46f8b0663bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366541214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.366541214
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3255573891
Short name T21
Test name
Test status
Simulation time 76655154669 ps
CPU time 270.68 seconds
Started Dec 27 12:25:31 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 205524 kb
Host smart-1f93c831-1d13-4b4f-b3bd-2e59cbada517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255573891 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3255573891
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.658283972
Short name T221
Test name
Test status
Simulation time 332186558 ps
CPU time 0.98 seconds
Started Dec 27 12:25:31 PM PST 23
Finished Dec 27 12:25:39 PM PST 23
Peak memory 182568 kb
Host smart-ed35948e-7dcd-4e5d-9e2b-d464ea3a80a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658283972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.658283972
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3946412251
Short name T230
Test name
Test status
Simulation time 41303195070 ps
CPU time 16.04 seconds
Started Dec 27 12:20:27 PM PST 23
Finished Dec 27 12:20:45 PM PST 23
Peak memory 182588 kb
Host smart-e2165965-3d7a-42b0-b57f-767512434dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946412251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3946412251
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1087326340
Short name T160
Test name
Test status
Simulation time 514271842 ps
CPU time 1.25 seconds
Started Dec 27 12:23:14 PM PST 23
Finished Dec 27 12:23:17 PM PST 23
Peak memory 182620 kb
Host smart-d25833d3-3df8-43ae-acaa-a78210d6a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087326340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1087326340
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.4135094373
Short name T255
Test name
Test status
Simulation time 441313835742 ps
CPU time 722.98 seconds
Started Dec 27 12:23:26 PM PST 23
Finished Dec 27 12:35:31 PM PST 23
Peak memory 194264 kb
Host smart-70e365d4-b999-4c10-9f4f-80698c98e122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135094373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.4135094373
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.19300998
Short name T101
Test name
Test status
Simulation time 82516251774 ps
CPU time 286.43 seconds
Started Dec 27 12:25:40 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 196268 kb
Host smart-dfbecb76-9cb3-4d7e-bbfc-131993ee8b37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300998 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.19300998
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2709593546
Short name T122
Test name
Test status
Simulation time 430334503 ps
CPU time 0.87 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 182408 kb
Host smart-96b1a57c-0a29-46ff-a8b8-156275073f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709593546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2709593546
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2943000973
Short name T313
Test name
Test status
Simulation time 36220310108 ps
CPU time 15.45 seconds
Started Dec 27 12:22:46 PM PST 23
Finished Dec 27 12:23:03 PM PST 23
Peak memory 182808 kb
Host smart-3910ebf1-1879-40d1-9302-769e505d619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943000973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2943000973
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.989089685
Short name T309
Test name
Test status
Simulation time 364601574 ps
CPU time 0.74 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:29:37 PM PST 23
Peak memory 180992 kb
Host smart-38a07627-b904-474f-9bce-2565f070eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989089685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.989089685
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1379129154
Short name T26
Test name
Test status
Simulation time 92458416385 ps
CPU time 133.07 seconds
Started Dec 27 12:25:31 PM PST 23
Finished Dec 27 12:27:51 PM PST 23
Peak memory 192764 kb
Host smart-2fc36a31-3b62-41e4-8451-6979a4d30c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379129154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1379129154
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.448851850
Short name T51
Test name
Test status
Simulation time 107252143974 ps
CPU time 522.1 seconds
Started Dec 27 12:22:42 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 197652 kb
Host smart-ccac71a3-4fb9-4574-976f-a7cefe704506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448851850 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.448851850
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.289628185
Short name T39
Test name
Test status
Simulation time 448624279 ps
CPU time 1.26 seconds
Started Dec 27 12:25:40 PM PST 23
Finished Dec 27 12:25:49 PM PST 23
Peak memory 181332 kb
Host smart-0d730e3f-4916-45ea-a549-5d58f84c7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289628185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.289628185
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3246546495
Short name T52
Test name
Test status
Simulation time 38497351827 ps
CPU time 10.48 seconds
Started Dec 27 12:25:41 PM PST 23
Finished Dec 27 12:25:59 PM PST 23
Peak memory 182632 kb
Host smart-c8134380-5a80-4081-a191-46119d383d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246546495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3246546495
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2041609388
Short name T292
Test name
Test status
Simulation time 558620817 ps
CPU time 1.4 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:26:08 PM PST 23
Peak memory 182352 kb
Host smart-012acc5c-c8da-4b38-9e91-2771b3af7f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041609388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2041609388
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2503734521
Short name T197
Test name
Test status
Simulation time 159807102683 ps
CPU time 171.56 seconds
Started Dec 27 12:25:49 PM PST 23
Finished Dec 27 12:28:46 PM PST 23
Peak memory 182572 kb
Host smart-c3eae67d-f49f-451c-8f12-7d26007d0203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503734521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2503734521
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1502376325
Short name T176
Test name
Test status
Simulation time 536265179 ps
CPU time 1.49 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 180680 kb
Host smart-8fce7777-e25a-418a-84b9-a922de983b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502376325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1502376325
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2352817516
Short name T87
Test name
Test status
Simulation time 44926045682 ps
CPU time 72.64 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:27:58 PM PST 23
Peak memory 181160 kb
Host smart-f1e2dbf5-5baa-4e6e-b9f2-4842756d2828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352817516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2352817516
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2721634209
Short name T223
Test name
Test status
Simulation time 416137307 ps
CPU time 1.17 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 181192 kb
Host smart-ada618d2-b8c4-493d-85ce-f615c9a5f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721634209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2721634209
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.35680521
Short name T229
Test name
Test status
Simulation time 188972788286 ps
CPU time 328.85 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:25:57 PM PST 23
Peak memory 190724 kb
Host smart-8281a98a-104a-4ae2-bef2-bf136af82792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35680521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all
.35680521
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3110660503
Short name T86
Test name
Test status
Simulation time 17850965014 ps
CPU time 62.26 seconds
Started Dec 27 12:25:13 PM PST 23
Finished Dec 27 12:26:18 PM PST 23
Peak memory 197336 kb
Host smart-6b9d052a-e8ee-4eb0-a306-11c240c6cb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110660503 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3110660503
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.478381679
Short name T174
Test name
Test status
Simulation time 460256638 ps
CPU time 1.21 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:25:47 PM PST 23
Peak memory 182496 kb
Host smart-c8cfe108-5b6c-4d2d-b32f-6434a6e7802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478381679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.478381679
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.164283066
Short name T88
Test name
Test status
Simulation time 36640062024 ps
CPU time 34.05 seconds
Started Dec 27 12:25:11 PM PST 23
Finished Dec 27 12:25:48 PM PST 23
Peak memory 182428 kb
Host smart-e4d3529a-03e0-4b58-8cd3-4910623c3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164283066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.164283066
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.84268558
Short name T25
Test name
Test status
Simulation time 388860745 ps
CPU time 0.67 seconds
Started Dec 27 12:25:12 PM PST 23
Finished Dec 27 12:25:17 PM PST 23
Peak memory 181520 kb
Host smart-fde968b2-c188-4e56-aabf-9ab0ce4a901a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84268558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.84268558
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3863383962
Short name T55
Test name
Test status
Simulation time 138045017541 ps
CPU time 99.68 seconds
Started Dec 27 12:25:37 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 192800 kb
Host smart-57793876-1acd-4a34-abbc-88188d09032b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863383962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3863383962
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1326491397
Short name T120
Test name
Test status
Simulation time 133158939505 ps
CPU time 341.78 seconds
Started Dec 27 12:25:38 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 197448 kb
Host smart-45650134-006f-4d87-b67b-00a220bfad36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326491397 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1326491397
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.713644788
Short name T195
Test name
Test status
Simulation time 552220433 ps
CPU time 1.45 seconds
Started Dec 27 12:23:36 PM PST 23
Finished Dec 27 12:23:38 PM PST 23
Peak memory 182632 kb
Host smart-f55ec95e-56f0-413e-ad8a-2c214303d48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713644788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.713644788
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.199952853
Short name T239
Test name
Test status
Simulation time 49048985649 ps
CPU time 82.59 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:27:40 PM PST 23
Peak memory 180652 kb
Host smart-c4b6e558-5bfe-4128-8507-c9fcb9a661c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199952853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.199952853
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.471870467
Short name T233
Test name
Test status
Simulation time 592983033 ps
CPU time 1.51 seconds
Started Dec 27 12:24:28 PM PST 23
Finished Dec 27 12:24:31 PM PST 23
Peak memory 181668 kb
Host smart-d760ef20-7ce4-46a9-96c7-50d769781a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471870467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.471870467
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2892510477
Short name T138
Test name
Test status
Simulation time 137715271772 ps
CPU time 233.36 seconds
Started Dec 27 12:24:56 PM PST 23
Finished Dec 27 12:28:50 PM PST 23
Peak memory 193112 kb
Host smart-7905ec54-bf33-4f34-95d3-90f8fb06c561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892510477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2892510477
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2626087543
Short name T261
Test name
Test status
Simulation time 47292808911 ps
CPU time 119.82 seconds
Started Dec 27 12:25:38 PM PST 23
Finished Dec 27 12:27:46 PM PST 23
Peak memory 197412 kb
Host smart-7e11822e-b499-4140-a0c0-1522b2076f64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626087543 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2626087543
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4192599707
Short name T291
Test name
Test status
Simulation time 369904728 ps
CPU time 1.13 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:24:58 PM PST 23
Peak memory 182588 kb
Host smart-2f2de8cf-b250-4c96-ab1f-6b2bdfe9aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192599707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4192599707
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4174067922
Short name T288
Test name
Test status
Simulation time 31589846764 ps
CPU time 12.64 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:25:09 PM PST 23
Peak memory 182652 kb
Host smart-7fe03889-2426-4c87-a3e8-45f363d077c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174067922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4174067922
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3280760405
Short name T172
Test name
Test status
Simulation time 562946541 ps
CPU time 0.93 seconds
Started Dec 27 12:25:38 PM PST 23
Finished Dec 27 12:25:47 PM PST 23
Peak memory 182492 kb
Host smart-48aaf7c4-e0a5-4ea4-8b37-83ced0dd3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280760405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3280760405
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.2315357974
Short name T118
Test name
Test status
Simulation time 70228306205 ps
CPU time 112.98 seconds
Started Dec 27 12:25:05 PM PST 23
Finished Dec 27 12:27:01 PM PST 23
Peak memory 192596 kb
Host smart-483826df-cd0c-4f4b-b449-44340c2eede3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315357974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.2315357974
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.3183970754
Short name T250
Test name
Test status
Simulation time 31008026164 ps
CPU time 314.64 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 196204 kb
Host smart-80397185-a634-449a-871a-5d196d74ebc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183970754 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.3183970754
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1795095115
Short name T89
Test name
Test status
Simulation time 451807031 ps
CPU time 1.26 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 182336 kb
Host smart-8f5e155b-a2d5-429a-8751-c4b2fd5f1ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795095115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1795095115
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4120509173
Short name T147
Test name
Test status
Simulation time 19308818115 ps
CPU time 34.15 seconds
Started Dec 27 12:25:23 PM PST 23
Finished Dec 27 12:26:07 PM PST 23
Peak memory 180936 kb
Host smart-e59084f2-20cb-4dd0-b2ec-2f9ec30548c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120509173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4120509173
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3205586945
Short name T294
Test name
Test status
Simulation time 498612181 ps
CPU time 0.6 seconds
Started Dec 27 12:25:23 PM PST 23
Finished Dec 27 12:25:33 PM PST 23
Peak memory 182196 kb
Host smart-a129b287-3870-4179-a7f4-97ad48e8d7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205586945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3205586945
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.428557071
Short name T43
Test name
Test status
Simulation time 288437408443 ps
CPU time 769.15 seconds
Started Dec 27 12:25:03 PM PST 23
Finished Dec 27 12:37:55 PM PST 23
Peak memory 201316 kb
Host smart-09fb36ef-657e-4d84-b012-1f0820110725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428557071 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.428557071
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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