Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 28314 1 T20 10 T21 165 T22 10
bark[1] 568 1 T27 30 T60 135 T97 16
bark[2] 615 1 T21 16 T98 16 T99 28
bark[3] 378 1 T30 17 T28 35 T97 16
bark[4] 155 1 T100 16 T101 16 T97 26
bark[5] 537 1 T30 33 T60 215 T101 54
bark[6] 697 1 T31 37 T60 61 T102 22
bark[7] 515 1 T30 158 T38 100 T103 12
bark[8] 504 1 T27 16 T65 17 T104 13
bark[9] 621 1 T105 12 T60 16 T99 128
bark[10] 346 1 T106 12 T107 37 T108 47
bark[11] 217 1 T30 2 T109 25 T110 96
bark[12] 200 1 T46 16 T100 47 T111 30
bark[13] 510 1 T31 22 T28 16 T60 137
bark[14] 367 1 T51 25 T60 17 T112 123
bark[15] 446 1 T113 16 T98 16 T114 69
bark[16] 318 1 T25 41 T41 26 T115 12
bark[17] 375 1 T25 36 T97 36 T92 16
bark[18] 534 1 T116 12 T117 176 T118 16
bark[19] 475 1 T63 12 T28 16 T101 46
bark[20] 544 1 T21 17 T60 16 T91 95
bark[21] 551 1 T30 37 T99 16 T119 16
bark[22] 274 1 T97 31 T112 75 T117 21
bark[23] 555 1 T46 3 T99 164 T118 35
bark[24] 313 1 T38 99 T120 17 T121 16
bark[25] 210 1 T23 12 T21 17 T24 12
bark[26] 296 1 T28 27 T38 16 T40 16
bark[27] 205 1 T61 12 T113 23 T100 17
bark[28] 199 1 T122 12 T99 16 T123 58
bark[29] 525 1 T124 17 T125 21 T126 12
bark[30] 511 1 T127 12 T128 229 T112 194
bark[31] 474 1 T30 16 T91 17 T117 125
bark_0 3578 1 T6 5 T14 9 T15 9


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 27631 1 T20 9 T21 164 T22 9
bite[1] 421 1 T30 36 T105 11 T97 16
bite[2] 701 1 T128 180 T129 31 T110 95
bite[3] 232 1 T99 16 T97 23 T119 45
bite[4] 637 1 T27 16 T38 26 T111 28
bite[5] 172 1 T99 16 T97 26 T102 17
bite[6] 301 1 T25 35 T60 16 T109 30
bite[7] 529 1 T60 87 T91 94 T93 32
bite[8] 328 1 T30 17 T31 36 T27 30
bite[9] 545 1 T46 2 T99 127 T130 11
bite[10] 379 1 T46 16 T113 16 T116 11
bite[11] 438 1 T30 157 T31 21 T99 28
bite[12] 228 1 T101 16 T131 20 T132 22
bite[13] 149 1 T28 16 T111 16 T108 47
bite[14] 682 1 T28 26 T97 31 T102 21
bite[15] 436 1 T23 11 T24 11 T60 214
bite[16] 361 1 T30 16 T60 17 T119 26
bite[17] 534 1 T25 16 T103 11 T133 17
bite[18] 251 1 T28 16 T104 12 T134 35
bite[19] 512 1 T21 17 T117 126 T111 16
bite[20] 439 1 T28 35 T135 11 T60 16
bite[21] 323 1 T111 16 T107 76 T136 16
bite[22] 778 1 T100 16 T65 17 T112 193
bite[23] 289 1 T30 17 T101 46 T97 12
bite[24] 291 1 T137 16 T117 124 T111 16
bite[25] 614 1 T21 16 T127 11 T60 60
bite[26] 829 1 T21 17 T60 136 T97 16
bite[27] 165 1 T138 52 T66 16 T139 16
bite[28] 245 1 T63 11 T128 47 T137 16
bite[29] 353 1 T51 25 T140 17 T110 16
bite[30] 416 1 T25 40 T91 5 T99 17
bite[31] 603 1 T113 23 T100 17 T65 26
bite_0 4115 1 T6 5 T14 9 T15 9


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 44927 1 T6 5 T14 9 T15 9


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 272 1 T64 8 T91 21 T100 45
prescale[1] 802 1 T25 8 T60 45 T141 8
prescale[2] 924 1 T65 2 T93 70 T137 99
prescale[3] 1323 1 T21 18 T51 15 T98 20
prescale[4] 808 1 T21 45 T113 59 T60 63
prescale[5] 432 1 T113 45 T102 18 T93 104
prescale[6] 696 1 T30 15 T28 15 T92 2
prescale[7] 536 1 T30 15 T31 18 T27 15
prescale[8] 908 1 T21 21 T30 97 T27 15
prescale[9] 623 1 T30 15 T31 16 T142 8
prescale[10] 807 1 T31 54 T46 99 T51 2
prescale[11] 598 1 T51 2 T98 15 T60 2
prescale[12] 1090 1 T27 15 T51 106 T28 25
prescale[13] 392 1 T26 8 T27 21 T51 2
prescale[14] 635 1 T25 15 T30 15 T27 45
prescale[15] 590 1 T60 74 T143 8 T144 8
prescale[16] 604 1 T60 61 T99 119 T92 100
prescale[17] 743 1 T21 15 T30 15 T145 8
prescale[18] 685 1 T31 16 T46 16 T60 36
prescale[19] 566 1 T30 31 T46 97 T51 15
prescale[20] 715 1 T27 8 T51 2 T60 43
prescale[21] 499 1 T21 15 T31 2 T101 23
prescale[22] 561 1 T46 15 T60 46 T97 18
prescale[23] 518 1 T25 15 T91 2 T99 70
prescale[24] 817 1 T25 2 T30 2 T46 123
prescale[25] 763 1 T25 17 T30 50 T46 8
prescale[26] 1055 1 T51 2 T28 15 T91 125
prescale[27] 535 1 T30 15 T27 18 T46 20
prescale[28] 778 1 T51 30 T60 2 T99 56
prescale[29] 639 1 T25 95 T30 47 T45 8
prescale[30] 711 1 T30 2 T46 15 T51 15
prescale[31] 837 1 T21 26 T25 76 T30 39
prescale_0 22465 1 T6 5 T14 9 T15 9


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33670 1 T6 5 T14 9 T15 9
auto[1] 11257 1 T23 10 T21 168 T24 10


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 44927 1 T6 5 T14 9 T15 9


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 26879 1 T20 11 T21 166 T22 11
wkup[1] 455 1 T28 35 T113 16 T91 16
wkup[2] 458 1 T30 21 T63 13 T46 16
wkup[3] 598 1 T51 7 T99 28 T102 16
wkup[4] 434 1 T24 13 T30 32 T31 16
wkup[5] 492 1 T30 32 T65 17 T99 58
wkup[6] 506 1 T30 16 T28 16 T98 16
wkup[7] 434 1 T46 16 T51 23 T60 16
wkup[8] 549 1 T91 16 T99 16 T97 30
wkup[9] 362 1 T30 16 T31 23 T51 16
wkup[10] 334 1 T28 16 T60 16 T128 16
wkup[11] 374 1 T30 16 T60 22 T99 16
wkup[12] 429 1 T21 16 T30 16 T31 16
wkup[13] 316 1 T30 16 T28 16 T97 47
wkup[14] 494 1 T113 16 T98 17 T60 17
wkup[15] 645 1 T30 17 T46 16 T51 22
wkup[16] 417 1 T60 32 T99 17 T109 25
wkup[17] 450 1 T27 16 T51 13 T127 13
wkup[18] 400 1 T25 16 T30 33 T60 32
wkup[19] 438 1 T30 60 T60 47 T101 16
wkup[20] 571 1 T21 17 T27 16 T46 16
wkup[21] 562 1 T105 13 T91 7 T100 17
wkup[22] 643 1 T30 3 T46 16 T51 16
wkup[23] 525 1 T21 17 T31 16 T91 13
wkup[24] 429 1 T30 16 T46 22 T97 16
wkup[25] 413 1 T25 22 T30 13 T98 13
wkup[26] 499 1 T31 16 T46 16 T60 16
wkup[27] 750 1 T25 32 T30 33 T46 16
wkup[28] 452 1 T23 13 T60 16 T101 46
wkup[29] 418 1 T30 16 T65 16 T99 57
wkup[30] 571 1 T46 4 T61 13 T51 16
wkup[31] 583 1 T27 16 T51 16 T60 16
wkup_0 3047 1 T6 5 T14 9 T15 9

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%