Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.32 100.00 99.35 100.00 96.90


Total test records in report: 430
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T277 /workspace/coverage/default/25.aon_timer_stress_all.28331519 Dec 31 12:46:18 PM PST 23 Dec 31 12:47:27 PM PST 23 117732242428 ps
T278 /workspace/coverage/default/22.aon_timer_stress_all.3053698948 Dec 31 12:46:11 PM PST 23 Dec 31 12:46:51 PM PST 23 98250685253 ps
T279 /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2855415745 Dec 31 12:45:53 PM PST 23 Dec 31 12:47:27 PM PST 23 14782812056 ps
T280 /workspace/coverage/default/16.aon_timer_jump.1833768352 Dec 31 12:46:10 PM PST 23 Dec 31 12:46:13 PM PST 23 472652268 ps
T281 /workspace/coverage/default/20.aon_timer_smoke.4273258254 Dec 31 12:46:22 PM PST 23 Dec 31 12:46:25 PM PST 23 590768171 ps
T282 /workspace/coverage/default/30.aon_timer_jump.1462882760 Dec 31 12:46:10 PM PST 23 Dec 31 12:46:13 PM PST 23 531323955 ps
T283 /workspace/coverage/default/38.aon_timer_stress_all.1319369470 Dec 31 12:46:44 PM PST 23 Dec 31 12:48:51 PM PST 23 146989549630 ps
T68 /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.452864583 Dec 31 12:45:42 PM PST 23 Dec 31 12:50:11 PM PST 23 60795850548 ps
T284 /workspace/coverage/default/35.aon_timer_prescaler.3234255946 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:53 PM PST 23 25438352398 ps
T285 /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3393390495 Dec 31 12:46:28 PM PST 23 Dec 31 12:48:49 PM PST 23 17788274134 ps
T286 /workspace/coverage/default/3.aon_timer_smoke.2409339134 Dec 31 12:45:57 PM PST 23 Dec 31 12:45:59 PM PST 23 410661961 ps
T287 /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2373921392 Dec 31 12:46:43 PM PST 23 Dec 31 01:02:11 PM PST 23 444397625041 ps
T288 /workspace/coverage/default/38.aon_timer_jump.282528981 Dec 31 12:46:50 PM PST 23 Dec 31 12:46:54 PM PST 23 549423016 ps
T289 /workspace/coverage/default/25.aon_timer_prescaler.1014307310 Dec 31 12:46:02 PM PST 23 Dec 31 12:46:20 PM PST 23 12684365437 ps
T290 /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1438949810 Dec 31 12:46:11 PM PST 23 Dec 31 12:50:57 PM PST 23 53241655899 ps
T291 /workspace/coverage/default/47.aon_timer_smoke.3772403379 Dec 31 12:46:06 PM PST 23 Dec 31 12:46:08 PM PST 23 348601933 ps
T292 /workspace/coverage/default/6.aon_timer_smoke.1337372122 Dec 31 12:45:54 PM PST 23 Dec 31 12:45:56 PM PST 23 507653741 ps
T293 /workspace/coverage/default/22.aon_timer_jump.3769563838 Dec 31 12:46:02 PM PST 23 Dec 31 12:46:04 PM PST 23 455296245 ps
T294 /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3368825808 Dec 31 12:46:34 PM PST 23 Dec 31 12:52:45 PM PST 23 202980525810 ps
T295 /workspace/coverage/default/11.aon_timer_prescaler.86690866 Dec 31 12:45:52 PM PST 23 Dec 31 12:46:01 PM PST 23 19136170872 ps
T296 /workspace/coverage/default/39.aon_timer_prescaler.537827041 Dec 31 12:46:56 PM PST 23 Dec 31 12:46:59 PM PST 23 1002224848 ps
T297 /workspace/coverage/default/24.aon_timer_jump.3082040401 Dec 31 12:46:17 PM PST 23 Dec 31 12:46:20 PM PST 23 470521249 ps
T298 /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2690554995 Dec 31 12:46:08 PM PST 23 Dec 31 12:57:18 PM PST 23 206134918337 ps
T299 /workspace/coverage/default/18.aon_timer_jump.3385928332 Dec 31 12:46:08 PM PST 23 Dec 31 12:46:11 PM PST 23 362066376 ps
T300 /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3501524515 Dec 31 12:45:45 PM PST 23 Dec 31 12:47:51 PM PST 23 59071863010 ps
T301 /workspace/coverage/default/7.aon_timer_prescaler.1910691710 Dec 31 12:45:37 PM PST 23 Dec 31 12:45:47 PM PST 23 41457430942 ps
T302 /workspace/coverage/default/44.aon_timer_smoke.3598842393 Dec 31 12:46:25 PM PST 23 Dec 31 12:46:27 PM PST 23 551471650 ps
T303 /workspace/coverage/default/5.aon_timer_prescaler.4236485928 Dec 31 12:45:35 PM PST 23 Dec 31 12:46:20 PM PST 23 58101440720 ps
T304 /workspace/coverage/default/43.aon_timer_jump.3332442894 Dec 31 12:46:11 PM PST 23 Dec 31 12:46:14 PM PST 23 487689257 ps
T305 /workspace/coverage/default/46.aon_timer_jump.2554427761 Dec 31 12:46:09 PM PST 23 Dec 31 12:46:12 PM PST 23 573505166 ps
T306 /workspace/coverage/default/37.aon_timer_smoke.61254867 Dec 31 12:46:52 PM PST 23 Dec 31 12:46:54 PM PST 23 600454976 ps
T307 /workspace/coverage/default/24.aon_timer_stress_all.2303797128 Dec 31 12:45:59 PM PST 23 Dec 31 12:46:51 PM PST 23 137651539105 ps
T308 /workspace/coverage/default/8.aon_timer_smoke.536595285 Dec 31 12:45:20 PM PST 23 Dec 31 12:45:23 PM PST 23 352309817 ps
T309 /workspace/coverage/default/12.aon_timer_prescaler.869835197 Dec 31 12:45:39 PM PST 23 Dec 31 12:45:54 PM PST 23 19450443412 ps
T310 /workspace/coverage/default/46.aon_timer_stress_all.7811579 Dec 31 12:46:11 PM PST 23 Dec 31 12:46:23 PM PST 23 31463560470 ps
T311 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3822843541 Dec 31 12:26:02 PM PST 23 Dec 31 12:26:09 PM PST 23 420199762 ps
T89 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3158785782 Dec 31 12:25:53 PM PST 23 Dec 31 12:26:01 PM PST 23 1331844043 ps
T90 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.634059227 Dec 31 12:25:06 PM PST 23 Dec 31 12:25:10 PM PST 23 515232019 ps
T312 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2651614920 Dec 31 12:24:45 PM PST 23 Dec 31 12:24:53 PM PST 23 406150272 ps
T94 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2238442827 Dec 31 12:24:07 PM PST 23 Dec 31 12:24:17 PM PST 23 7534972672 ps
T313 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3125115945 Dec 31 12:24:01 PM PST 23 Dec 31 12:24:09 PM PST 23 372871689 ps
T314 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3733218999 Dec 31 12:24:20 PM PST 23 Dec 31 12:24:23 PM PST 23 320784763 ps
T69 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2373606296 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 351131794 ps
T74 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3840127002 Dec 31 12:18:23 PM PST 23 Dec 31 12:18:25 PM PST 23 1410727578 ps
T75 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3424174263 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:34 PM PST 23 359927274 ps
T70 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3100184475 Dec 31 12:23:25 PM PST 23 Dec 31 12:23:27 PM PST 23 336105414 ps
T76 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1321982641 Dec 31 12:23:40 PM PST 23 Dec 31 12:23:44 PM PST 23 540814291 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2018308411 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:35 PM PST 23 437342567 ps
T78 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1935436438 Dec 31 12:24:13 PM PST 23 Dec 31 12:24:20 PM PST 23 8567581112 ps
T79 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.216708751 Dec 31 12:25:39 PM PST 23 Dec 31 12:25:49 PM PST 23 509507444 ps
T80 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.324135400 Dec 31 12:24:52 PM PST 23 Dec 31 12:24:59 PM PST 23 387638645 ps
T81 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1158618499 Dec 31 12:24:05 PM PST 23 Dec 31 12:24:11 PM PST 23 310600120 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1070772163 Dec 31 12:25:25 PM PST 23 Dec 31 12:25:37 PM PST 23 6164026298 ps
T316 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2002141635 Dec 31 12:23:52 PM PST 23 Dec 31 12:23:55 PM PST 23 280744688 ps
T317 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.939770952 Dec 31 12:24:11 PM PST 23 Dec 31 12:24:16 PM PST 23 511980034 ps
T318 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.690963430 Dec 31 12:25:36 PM PST 23 Dec 31 12:25:45 PM PST 23 506104060 ps
T319 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2825686933 Dec 31 12:27:08 PM PST 23 Dec 31 12:27:11 PM PST 23 488971888 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3337839151 Dec 31 12:34:34 PM PST 23 Dec 31 12:34:39 PM PST 23 512039193 ps
T321 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1450037915 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:46 PM PST 23 562169052 ps
T322 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2777864768 Dec 31 12:23:54 PM PST 23 Dec 31 12:24:02 PM PST 23 385556574 ps
T323 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3328718679 Dec 31 12:23:58 PM PST 23 Dec 31 12:24:03 PM PST 23 538862161 ps
T71 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2915096644 Dec 31 12:22:31 PM PST 23 Dec 31 12:22:33 PM PST 23 502554831 ps
T324 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.145142004 Dec 31 12:23:18 PM PST 23 Dec 31 12:23:20 PM PST 23 1216949460 ps
T325 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1819458419 Dec 31 12:24:04 PM PST 23 Dec 31 12:24:10 PM PST 23 364118104 ps
T326 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.384531786 Dec 31 12:23:06 PM PST 23 Dec 31 12:23:07 PM PST 23 524149567 ps
T72 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2822644497 Dec 31 12:27:17 PM PST 23 Dec 31 12:27:19 PM PST 23 368097327 ps
T327 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2770225439 Dec 31 12:23:58 PM PST 23 Dec 31 12:24:03 PM PST 23 535917700 ps
T328 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3292224650 Dec 31 12:23:41 PM PST 23 Dec 31 12:23:44 PM PST 23 493676102 ps
T329 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2633170257 Dec 31 12:25:39 PM PST 23 Dec 31 12:25:50 PM PST 23 651097227 ps
T330 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3813499706 Dec 31 12:23:58 PM PST 23 Dec 31 12:24:03 PM PST 23 340371255 ps
T73 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1768717480 Dec 31 12:24:23 PM PST 23 Dec 31 12:24:26 PM PST 23 366048273 ps
T82 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.653775543 Dec 31 12:26:13 PM PST 23 Dec 31 12:26:17 PM PST 23 479925690 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.164577045 Dec 31 12:22:30 PM PST 23 Dec 31 12:22:32 PM PST 23 532621819 ps
T332 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2763522374 Dec 31 12:24:29 PM PST 23 Dec 31 12:24:33 PM PST 23 489635508 ps
T333 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.98494606 Dec 31 12:23:51 PM PST 23 Dec 31 12:23:54 PM PST 23 338743203 ps
T83 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1608542410 Dec 31 12:27:01 PM PST 23 Dec 31 12:27:04 PM PST 23 996491229 ps
T334 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2073162510 Dec 31 12:23:51 PM PST 23 Dec 31 12:23:54 PM PST 23 333031366 ps
T95 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4029083724 Dec 31 12:26:10 PM PST 23 Dec 31 12:26:20 PM PST 23 8800523216 ps
T335 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4149844710 Dec 31 12:23:58 PM PST 23 Dec 31 12:24:04 PM PST 23 282723234 ps
T336 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3132163605 Dec 31 12:22:54 PM PST 23 Dec 31 12:22:56 PM PST 23 579854804 ps
T337 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.818041077 Dec 31 12:28:14 PM PST 23 Dec 31 12:28:16 PM PST 23 455895252 ps
T84 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2646898756 Dec 31 12:25:26 PM PST 23 Dec 31 12:25:46 PM PST 23 5883777521 ps
T338 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3387733379 Dec 31 12:22:09 PM PST 23 Dec 31 12:22:11 PM PST 23 518280317 ps
T339 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1343546200 Dec 31 12:25:07 PM PST 23 Dec 31 12:25:13 PM PST 23 539641599 ps
T340 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3936437427 Dec 31 12:23:52 PM PST 23 Dec 31 12:23:54 PM PST 23 426517458 ps
T341 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2878350065 Dec 31 12:26:58 PM PST 23 Dec 31 12:27:04 PM PST 23 4542835557 ps
T342 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1054804830 Dec 31 12:25:27 PM PST 23 Dec 31 12:25:36 PM PST 23 993993276 ps
T88 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.581296955 Dec 31 12:19:40 PM PST 23 Dec 31 12:19:46 PM PST 23 428012318 ps
T343 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3777699150 Dec 31 12:24:16 PM PST 23 Dec 31 12:24:21 PM PST 23 713724953 ps
T344 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2371208390 Dec 31 12:18:10 PM PST 23 Dec 31 12:18:11 PM PST 23 439737142 ps
T345 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3169865044 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:07 PM PST 23 604005043 ps
T346 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2103360657 Dec 31 12:23:58 PM PST 23 Dec 31 12:24:03 PM PST 23 470447899 ps
T347 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.536959879 Dec 31 12:24:20 PM PST 23 Dec 31 12:24:23 PM PST 23 312980873 ps
T348 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3679633857 Dec 31 12:27:14 PM PST 23 Dec 31 12:27:15 PM PST 23 430272677 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.744825439 Dec 31 12:20:09 PM PST 23 Dec 31 12:20:12 PM PST 23 507558174 ps
T350 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.250607176 Dec 31 12:23:11 PM PST 23 Dec 31 12:23:20 PM PST 23 8673821718 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.764525705 Dec 31 12:18:24 PM PST 23 Dec 31 12:18:27 PM PST 23 341593736 ps
T352 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1376353285 Dec 31 12:23:40 PM PST 23 Dec 31 12:23:44 PM PST 23 580535007 ps
T85 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2529868236 Dec 31 12:19:33 PM PST 23 Dec 31 12:19:38 PM PST 23 5896259200 ps
T353 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1594353353 Dec 31 12:24:56 PM PST 23 Dec 31 12:25:00 PM PST 23 417601669 ps
T86 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2772194496 Dec 31 12:23:45 PM PST 23 Dec 31 12:23:47 PM PST 23 414801628 ps
T354 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.742200679 Dec 31 12:25:57 PM PST 23 Dec 31 12:26:05 PM PST 23 1127927936 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.326768445 Dec 31 12:26:14 PM PST 23 Dec 31 12:26:18 PM PST 23 440227859 ps
T356 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1143077204 Dec 31 12:24:15 PM PST 23 Dec 31 12:24:19 PM PST 23 646108090 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2634335798 Dec 31 12:24:10 PM PST 23 Dec 31 12:24:17 PM PST 23 483867305 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.788108936 Dec 31 12:24:16 PM PST 23 Dec 31 12:24:19 PM PST 23 4570800041 ps
T359 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2108535222 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:47 PM PST 23 328244798 ps
T360 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1835714266 Dec 31 12:25:00 PM PST 23 Dec 31 12:25:05 PM PST 23 331779500 ps
T361 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2638482875 Dec 31 12:25:22 PM PST 23 Dec 31 12:25:32 PM PST 23 8616054384 ps
T362 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3955058271 Dec 31 12:24:27 PM PST 23 Dec 31 12:24:33 PM PST 23 1727729836 ps
T363 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1231095011 Dec 31 12:23:52 PM PST 23 Dec 31 12:23:54 PM PST 23 462703488 ps
T364 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3381324656 Dec 31 12:24:15 PM PST 23 Dec 31 12:24:18 PM PST 23 492832845 ps
T365 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2878494857 Dec 31 12:24:30 PM PST 23 Dec 31 12:24:34 PM PST 23 318390986 ps
T366 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1028983039 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:09 PM PST 23 469961533 ps
T367 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1943282747 Dec 31 12:27:40 PM PST 23 Dec 31 12:27:42 PM PST 23 2719470732 ps
T368 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1246867953 Dec 31 12:25:52 PM PST 23 Dec 31 12:26:00 PM PST 23 543681758 ps
T369 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1047116159 Dec 31 12:23:45 PM PST 23 Dec 31 12:23:47 PM PST 23 403418890 ps
T370 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1827220535 Dec 31 12:25:36 PM PST 23 Dec 31 12:25:45 PM PST 23 302247167 ps
T371 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3772785636 Dec 31 12:22:30 PM PST 23 Dec 31 12:22:32 PM PST 23 338557383 ps
T372 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3738290095 Dec 31 12:26:00 PM PST 23 Dec 31 12:26:07 PM PST 23 329804543 ps
T373 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2730742925 Dec 31 12:24:25 PM PST 23 Dec 31 12:24:30 PM PST 23 606274159 ps
T87 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4165642787 Dec 31 12:24:08 PM PST 23 Dec 31 12:24:22 PM PST 23 11075169807 ps
T374 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.698554896 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:06 PM PST 23 1013859031 ps
T375 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1418065918 Dec 31 12:26:42 PM PST 23 Dec 31 12:26:44 PM PST 23 305621648 ps
T376 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3467885714 Dec 31 12:24:17 PM PST 23 Dec 31 12:24:20 PM PST 23 284286052 ps
T377 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.333349538 Dec 31 12:23:41 PM PST 23 Dec 31 12:23:50 PM PST 23 4537748377 ps
T96 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1901355874 Dec 31 12:25:16 PM PST 23 Dec 31 12:25:24 PM PST 23 8069211604 ps
T378 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.217676303 Dec 31 12:24:39 PM PST 23 Dec 31 12:24:47 PM PST 23 497502843 ps
T379 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.766356657 Dec 31 12:24:01 PM PST 23 Dec 31 12:24:08 PM PST 23 320013599 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3137581401 Dec 31 12:24:34 PM PST 23 Dec 31 12:24:43 PM PST 23 428815897 ps
T381 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1393057873 Dec 31 12:23:36 PM PST 23 Dec 31 12:23:39 PM PST 23 310361906 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.418831526 Dec 31 12:23:00 PM PST 23 Dec 31 12:23:02 PM PST 23 399869472 ps
T383 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.876940850 Dec 31 12:23:52 PM PST 23 Dec 31 12:23:55 PM PST 23 430018097 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.805317636 Dec 31 12:23:57 PM PST 23 Dec 31 12:24:04 PM PST 23 1199320357 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4122881190 Dec 31 12:23:40 PM PST 23 Dec 31 12:23:44 PM PST 23 482002679 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2394258790 Dec 31 12:22:54 PM PST 23 Dec 31 12:22:56 PM PST 23 550449609 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1532840730 Dec 31 12:24:10 PM PST 23 Dec 31 12:24:15 PM PST 23 638119159 ps
T388 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.402801516 Dec 31 12:23:38 PM PST 23 Dec 31 12:23:43 PM PST 23 503999694 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2680523891 Dec 31 12:24:19 PM PST 23 Dec 31 12:24:22 PM PST 23 389916537 ps
T390 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1435365043 Dec 31 12:23:56 PM PST 23 Dec 31 12:24:01 PM PST 23 441653696 ps
T391 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.245999917 Dec 31 12:23:57 PM PST 23 Dec 31 12:24:04 PM PST 23 4566092731 ps
T392 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3803656103 Dec 31 12:23:10 PM PST 23 Dec 31 12:23:11 PM PST 23 523437227 ps
T393 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3195009564 Dec 31 12:23:44 PM PST 23 Dec 31 12:23:46 PM PST 23 305934938 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3267365329 Dec 31 12:25:33 PM PST 23 Dec 31 12:25:41 PM PST 23 465188499 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1231544237 Dec 31 12:25:50 PM PST 23 Dec 31 12:26:07 PM PST 23 428076003 ps
T396 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2052331596 Dec 31 12:23:41 PM PST 23 Dec 31 12:23:45 PM PST 23 413099465 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.104017482 Dec 31 12:25:37 PM PST 23 Dec 31 12:25:47 PM PST 23 447049515 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3096191268 Dec 31 12:25:36 PM PST 23 Dec 31 12:25:47 PM PST 23 459389998 ps
T399 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2657857939 Dec 31 12:24:29 PM PST 23 Dec 31 12:24:32 PM PST 23 440831178 ps
T400 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3531746186 Dec 31 12:23:51 PM PST 23 Dec 31 12:23:54 PM PST 23 341984109 ps
T401 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3332790069 Dec 31 12:25:33 PM PST 23 Dec 31 12:25:42 PM PST 23 504750631 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2711406732 Dec 31 12:24:10 PM PST 23 Dec 31 12:24:16 PM PST 23 492779695 ps
T403 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3418364888 Dec 31 12:23:51 PM PST 23 Dec 31 12:23:52 PM PST 23 462086081 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3673491078 Dec 31 12:24:02 PM PST 23 Dec 31 12:24:10 PM PST 23 433861363 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2005823736 Dec 31 12:25:15 PM PST 23 Dec 31 12:25:21 PM PST 23 634456060 ps
T406 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3126865890 Dec 31 12:25:02 PM PST 23 Dec 31 12:25:11 PM PST 23 8713407580 ps
T407 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.509994750 Dec 31 12:26:19 PM PST 23 Dec 31 12:26:22 PM PST 23 482776634 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2306633293 Dec 31 12:26:03 PM PST 23 Dec 31 12:26:10 PM PST 23 367732401 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1161430892 Dec 31 12:25:26 PM PST 23 Dec 31 12:25:33 PM PST 23 405177298 ps
T410 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1927001673 Dec 31 12:19:56 PM PST 23 Dec 31 12:19:59 PM PST 23 4035650728 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.550832281 Dec 31 12:25:00 PM PST 23 Dec 31 12:25:09 PM PST 23 1919097675 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4081937803 Dec 31 12:27:50 PM PST 23 Dec 31 12:27:53 PM PST 23 462774649 ps
T413 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2881614906 Dec 31 12:25:01 PM PST 23 Dec 31 12:25:05 PM PST 23 304134027 ps
T414 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.58928069 Dec 31 12:23:36 PM PST 23 Dec 31 12:23:47 PM PST 23 4508846698 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3114499528 Dec 31 12:18:07 PM PST 23 Dec 31 12:18:08 PM PST 23 477091804 ps
T416 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2511588375 Dec 31 12:24:01 PM PST 23 Dec 31 12:24:16 PM PST 23 4466620009 ps
T417 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1878257755 Dec 31 12:24:01 PM PST 23 Dec 31 12:24:12 PM PST 23 7832733235 ps
T418 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3500671516 Dec 31 12:26:01 PM PST 23 Dec 31 12:26:12 PM PST 23 522067541 ps
T419 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.267871811 Dec 31 12:20:09 PM PST 23 Dec 31 12:20:12 PM PST 23 1617524984 ps
T420 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1988924081 Dec 31 12:24:17 PM PST 23 Dec 31 12:24:21 PM PST 23 501916559 ps
T421 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4188521309 Dec 31 12:27:04 PM PST 23 Dec 31 12:27:07 PM PST 23 282341719 ps
T422 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2140457237 Dec 31 12:25:47 PM PST 23 Dec 31 12:25:56 PM PST 23 570352457 ps
T423 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3917665208 Dec 31 12:24:00 PM PST 23 Dec 31 12:24:07 PM PST 23 525486268 ps
T424 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3267937600 Dec 31 12:24:16 PM PST 23 Dec 31 12:24:20 PM PST 23 1050342042 ps
T425 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1449428445 Dec 31 12:24:03 PM PST 23 Dec 31 12:24:09 PM PST 23 361672916 ps
T426 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3850703359 Dec 31 12:25:44 PM PST 23 Dec 31 12:25:55 PM PST 23 2286772662 ps
T427 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2578598352 Dec 31 12:26:19 PM PST 23 Dec 31 12:26:21 PM PST 23 437513001 ps
T428 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2840185519 Dec 31 12:25:00 PM PST 23 Dec 31 12:25:05 PM PST 23 1621924421 ps
T429 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1566264018 Dec 31 12:25:25 PM PST 23 Dec 31 12:25:45 PM PST 23 7865351853 ps
T430 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2591249212 Dec 31 12:24:55 PM PST 23 Dec 31 12:25:07 PM PST 23 8471395980 ps

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2161298672
Short name T2
Test name
Test status
Simulation time 8261008556 ps
CPU time 12.9 seconds
Started Dec 31 12:25:58 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 197512 kb
Host smart-eaa2fff4-5b6c-45b4-beba-6017cded0a12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161298672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2161298672
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1510447922
Short name T30
Test name
Test status
Simulation time 41534553922 ps
CPU time 415.89 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:53:24 PM PST 23
Peak memory 197584 kb
Host smart-575031cf-fe16-4c56-b54a-f5c8c853ceda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510447922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1510447922
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1455253900
Short name T5
Test name
Test status
Simulation time 1459458797 ps
CPU time 1.81 seconds
Started Dec 31 12:24:48 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 191952 kb
Host smart-ac9e57b6-a815-45f5-81fd-63a4c928e33e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455253900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1455253900
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.146858373
Short name T60
Test name
Test status
Simulation time 243800262724 ps
CPU time 1082.57 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 01:04:18 PM PST 23
Peak memory 204080 kb
Host smart-93267e7c-5eab-451f-842d-98628cd142e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146858373 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.146858373
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2630410893
Short name T21
Test name
Test status
Simulation time 167145346452 ps
CPU time 260.09 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:50:26 PM PST 23
Peak memory 193036 kb
Host smart-7c5f1236-760a-4257-939b-5f7d86bbe63b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630410893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2630410893
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2583041788
Short name T91
Test name
Test status
Simulation time 14494563492 ps
CPU time 95.68 seconds
Started Dec 31 12:46:00 PM PST 23
Finished Dec 31 12:47:36 PM PST 23
Peak memory 197560 kb
Host smart-3da6b3b1-6591-4ada-b703-a55f357ef46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583041788 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2583041788
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.856085465
Short name T14
Test name
Test status
Simulation time 450503671 ps
CPU time 0.69 seconds
Started Dec 31 12:24:37 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 183700 kb
Host smart-1e50719a-1a3c-4fa5-8cb0-5a33023378ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856085465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.856085465
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2028223256
Short name T111
Test name
Test status
Simulation time 41955689349 ps
CPU time 19.28 seconds
Started Dec 31 12:45:14 PM PST 23
Finished Dec 31 12:45:39 PM PST 23
Peak memory 182732 kb
Host smart-681972ae-fe5a-41d1-a155-5efc247ad887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028223256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2028223256
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.295581809
Short name T110
Test name
Test status
Simulation time 75360892439 ps
CPU time 785.91 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:59:01 PM PST 23
Peak memory 200604 kb
Host smart-e362cfe6-8a58-455c-bd3c-f653e24ef368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295581809 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.295581809
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3373952785
Short name T36
Test name
Test status
Simulation time 4305837259 ps
CPU time 3.99 seconds
Started Dec 31 12:45:39 PM PST 23
Finished Dec 31 12:45:44 PM PST 23
Peak memory 214856 kb
Host smart-d3a7be48-fbdf-4a93-9457-4adc3f2df019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373952785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3373952785
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2461277466
Short name T132
Test name
Test status
Simulation time 88577260007 ps
CPU time 141.35 seconds
Started Dec 31 12:45:43 PM PST 23
Finished Dec 31 12:48:05 PM PST 23
Peak memory 182760 kb
Host smart-9d068466-1cb8-4280-aa74-bb14bd5782da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461277466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2461277466
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.299529416
Short name T133
Test name
Test status
Simulation time 43914940145 ps
CPU time 62.1 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:47:40 PM PST 23
Peak memory 182684 kb
Host smart-4a4e09be-4ceb-4876-82ce-ae96ac955d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299529416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.299529416
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2827477975
Short name T138
Test name
Test status
Simulation time 206975288514 ps
CPU time 324.35 seconds
Started Dec 31 12:46:37 PM PST 23
Finished Dec 31 12:52:04 PM PST 23
Peak memory 182864 kb
Host smart-2794bbb6-214b-43bb-90a4-3a44c33533fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827477975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2827477975
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3199560901
Short name T205
Test name
Test status
Simulation time 20543490565 ps
CPU time 30.17 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:50 PM PST 23
Peak memory 182764 kb
Host smart-99a28b3a-81a9-4571-b1fc-0b2d2361fb42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199560901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3199560901
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2950520028
Short name T8
Test name
Test status
Simulation time 8772916664 ps
CPU time 4.48 seconds
Started Dec 31 12:25:08 PM PST 23
Finished Dec 31 12:25:18 PM PST 23
Peak memory 197244 kb
Host smart-abc4b557-bcd0-4904-bbc7-3a98662b2972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950520028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2950520028
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3676341428
Short name T223
Test name
Test status
Simulation time 67431429767 ps
CPU time 21.71 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 182760 kb
Host smart-cf60ab72-317a-41f1-8a6a-f594e5acab84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676341428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3676341428
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.653775543
Short name T82
Test name
Test status
Simulation time 479925690 ps
CPU time 0.78 seconds
Started Dec 31 12:26:13 PM PST 23
Finished Dec 31 12:26:17 PM PST 23
Peak memory 183616 kb
Host smart-9c6c4baf-0521-4b85-a9f7-e7196d857dcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653775543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.653775543
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2540927606
Short name T99
Test name
Test status
Simulation time 70881292684 ps
CPU time 386.35 seconds
Started Dec 31 12:45:27 PM PST 23
Finished Dec 31 12:51:54 PM PST 23
Peak memory 197584 kb
Host smart-a99abff1-d821-45aa-82af-5f70ac458e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540927606 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2540927606
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4165642787
Short name T87
Test name
Test status
Simulation time 11075169807 ps
CPU time 8.82 seconds
Started Dec 31 12:24:08 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 192044 kb
Host smart-26cc6503-f05c-4cd5-83ba-b2b961cc51e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165642787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4165642787
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3278377836
Short name T53
Test name
Test status
Simulation time 1181367405 ps
CPU time 2.44 seconds
Started Dec 31 12:22:31 PM PST 23
Finished Dec 31 12:22:34 PM PST 23
Peak memory 183340 kb
Host smart-d265b1ac-6dd9-49de-b6fe-0c8b6675a90c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278377836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3278377836
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1231544237
Short name T395
Test name
Test status
Simulation time 428076003 ps
CPU time 1.2 seconds
Started Dec 31 12:25:50 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 194664 kb
Host smart-6d8f0b52-75bf-46c4-be8e-827e6a3a921a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231544237 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1231544237
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.509994750
Short name T407
Test name
Test status
Simulation time 482776634 ps
CPU time 0.75 seconds
Started Dec 31 12:26:19 PM PST 23
Finished Dec 31 12:26:22 PM PST 23
Peak memory 192832 kb
Host smart-1af7e5e0-a86f-4ef5-ac96-246524fd2938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509994750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.509994750
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.164577045
Short name T331
Test name
Test status
Simulation time 532621819 ps
CPU time 0.8 seconds
Started Dec 31 12:22:30 PM PST 23
Finished Dec 31 12:22:32 PM PST 23
Peak memory 181648 kb
Host smart-0e34e5bd-3c92-4737-8f37-42100cd402a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164577045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.164577045
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.4237719399
Short name T49
Test name
Test status
Simulation time 431118971 ps
CPU time 0.69 seconds
Started Dec 31 12:25:17 PM PST 23
Finished Dec 31 12:25:22 PM PST 23
Peak memory 182656 kb
Host smart-57e33fdc-71a2-4080-a9f9-0ba7409065ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237719399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.4237719399
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2680523891
Short name T389
Test name
Test status
Simulation time 389916537 ps
CPU time 1.21 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 181628 kb
Host smart-0d4b53f5-68a0-4e3f-b518-83932842a0cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680523891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2680523891
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.550832281
Short name T411
Test name
Test status
Simulation time 1919097675 ps
CPU time 4.73 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:09 PM PST 23
Peak memory 192408 kb
Host smart-435b133a-5c4f-44dd-935b-7224122d3eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550832281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.550832281
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1343546200
Short name T339
Test name
Test status
Simulation time 539641599 ps
CPU time 2.79 seconds
Started Dec 31 12:25:07 PM PST 23
Finished Dec 31 12:25:13 PM PST 23
Peak memory 197020 kb
Host smart-d97e96d1-055f-42b4-b216-8f6096ac5f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343546200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1343546200
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3126865890
Short name T406
Test name
Test status
Simulation time 8713407580 ps
CPU time 4.21 seconds
Started Dec 31 12:25:02 PM PST 23
Finished Dec 31 12:25:11 PM PST 23
Peak memory 197300 kb
Host smart-b52055f8-8337-464f-8cd4-957d545d2715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126865890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3126865890
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2306633293
Short name T408
Test name
Test status
Simulation time 367732401 ps
CPU time 1.27 seconds
Started Dec 31 12:26:03 PM PST 23
Finished Dec 31 12:26:10 PM PST 23
Peak memory 191836 kb
Host smart-10ad1fd1-0da2-475d-95ab-44416203c0e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306633293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2306633293
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2529868236
Short name T85
Test name
Test status
Simulation time 5896259200 ps
CPU time 5.21 seconds
Started Dec 31 12:19:33 PM PST 23
Finished Dec 31 12:19:38 PM PST 23
Peak memory 195480 kb
Host smart-0becdcda-1bb6-42f7-95f9-bc7a2638bd45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529868236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2529868236
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1608542410
Short name T83
Test name
Test status
Simulation time 996491229 ps
CPU time 0.94 seconds
Started Dec 31 12:27:01 PM PST 23
Finished Dec 31 12:27:04 PM PST 23
Peak memory 183652 kb
Host smart-57bfa334-0928-4909-842b-1ced21ba00d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608542410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1608542410
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3132163605
Short name T336
Test name
Test status
Simulation time 579854804 ps
CPU time 1.18 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 195212 kb
Host smart-108e9dd7-2fa0-4475-ba0f-536a670045ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132163605 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3132163605
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.581296955
Short name T88
Test name
Test status
Simulation time 428012318 ps
CPU time 1.2 seconds
Started Dec 31 12:19:40 PM PST 23
Finished Dec 31 12:19:46 PM PST 23
Peak memory 183656 kb
Host smart-6c199e5e-1022-424d-b5d9-5cc0f5c37eaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581296955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.581296955
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3114499528
Short name T415
Test name
Test status
Simulation time 477091804 ps
CPU time 0.9 seconds
Started Dec 31 12:18:07 PM PST 23
Finished Dec 31 12:18:08 PM PST 23
Peak memory 183768 kb
Host smart-46b98a46-cdaf-468b-bff5-3b8d4bf0cc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114499528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3114499528
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2651614920
Short name T312
Test name
Test status
Simulation time 406150272 ps
CPU time 0.59 seconds
Started Dec 31 12:24:45 PM PST 23
Finished Dec 31 12:24:53 PM PST 23
Peak memory 182960 kb
Host smart-1cab18cd-803e-484d-8f2b-2e1a9ee3e42d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651614920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2651614920
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.2374222345
Short name T59
Test name
Test status
Simulation time 315467899 ps
CPU time 0.75 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 183124 kb
Host smart-28b235f4-c994-447d-bf4e-2823a41be710
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374222345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.2374222345
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3840127002
Short name T74
Test name
Test status
Simulation time 1410727578 ps
CPU time 1.53 seconds
Started Dec 31 12:18:23 PM PST 23
Finished Dec 31 12:18:25 PM PST 23
Peak memory 192580 kb
Host smart-2b4e15d2-6345-4822-a0d9-e5bc8e19f480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840127002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3840127002
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3125115945
Short name T313
Test name
Test status
Simulation time 372871689 ps
CPU time 1.27 seconds
Started Dec 31 12:24:01 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 198084 kb
Host smart-b56d350a-d002-4c54-8c56-3cda27a34343
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125115945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3125115945
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2511588375
Short name T416
Test name
Test status
Simulation time 4466620009 ps
CPU time 4.04 seconds
Started Dec 31 12:24:01 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 196492 kb
Host smart-191baa6a-3188-49ae-88fe-96daceb83ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511588375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2511588375
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1988924081
Short name T420
Test name
Test status
Simulation time 501916559 ps
CPU time 0.85 seconds
Started Dec 31 12:24:17 PM PST 23
Finished Dec 31 12:24:21 PM PST 23
Peak memory 196160 kb
Host smart-ee1fe799-34f4-4ab5-89bb-b86bc65e9e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988924081 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1988924081
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3803656103
Short name T392
Test name
Test status
Simulation time 523437227 ps
CPU time 0.74 seconds
Started Dec 31 12:23:10 PM PST 23
Finished Dec 31 12:23:11 PM PST 23
Peak memory 183616 kb
Host smart-aa5a7afe-78d4-46e6-b79a-2d3a667f6406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803656103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3803656103
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3733218999
Short name T314
Test name
Test status
Simulation time 320784763 ps
CPU time 0.57 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 183376 kb
Host smart-b9caffae-1b15-4d12-9f45-ab52fd2a3518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733218999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3733218999
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.267871811
Short name T419
Test name
Test status
Simulation time 1617524984 ps
CPU time 2.38 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:12 PM PST 23
Peak memory 194452 kb
Host smart-c5156363-51f6-458f-8d9e-f7b35a51e843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267871811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.267871811
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2633170257
Short name T329
Test name
Test status
Simulation time 651097227 ps
CPU time 1.79 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 198472 kb
Host smart-dc2460e4-03b7-4a35-ab69-46a051ef6ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633170257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2633170257
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2638482875
Short name T361
Test name
Test status
Simulation time 8616054384 ps
CPU time 5.37 seconds
Started Dec 31 12:25:22 PM PST 23
Finished Dec 31 12:25:32 PM PST 23
Peak memory 197384 kb
Host smart-fe66ae7a-65d1-494e-80ad-861595a33431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638482875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2638482875
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.324135400
Short name T80
Test name
Test status
Simulation time 387638645 ps
CPU time 1.17 seconds
Started Dec 31 12:24:52 PM PST 23
Finished Dec 31 12:24:59 PM PST 23
Peak memory 195244 kb
Host smart-54c70525-305b-45f5-93fa-1247bea52eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324135400 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.324135400
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3500671516
Short name T418
Test name
Test status
Simulation time 522067541 ps
CPU time 0.88 seconds
Started Dec 31 12:26:01 PM PST 23
Finished Dec 31 12:26:12 PM PST 23
Peak memory 183652 kb
Host smart-ade62d84-ed8b-4dc4-a9f0-220c2e433f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500671516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3500671516
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4188521309
Short name T421
Test name
Test status
Simulation time 282341719 ps
CPU time 0.93 seconds
Started Dec 31 12:27:04 PM PST 23
Finished Dec 31 12:27:07 PM PST 23
Peak memory 183672 kb
Host smart-b836f7e1-5a6b-4ea5-8048-33437f601887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188521309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4188521309
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1943282747
Short name T367
Test name
Test status
Simulation time 2719470732 ps
CPU time 1.04 seconds
Started Dec 31 12:27:40 PM PST 23
Finished Dec 31 12:27:42 PM PST 23
Peak memory 192008 kb
Host smart-7582e54a-9dc5-4b55-9e9d-54d454aacaab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943282747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1943282747
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2005823736
Short name T405
Test name
Test status
Simulation time 634456060 ps
CPU time 2.28 seconds
Started Dec 31 12:25:15 PM PST 23
Finished Dec 31 12:25:21 PM PST 23
Peak memory 198564 kb
Host smart-b263656b-0f1e-4d1f-b802-2ba1f691ded9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005823736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2005823736
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1901355874
Short name T96
Test name
Test status
Simulation time 8069211604 ps
CPU time 4.32 seconds
Started Dec 31 12:25:16 PM PST 23
Finished Dec 31 12:25:24 PM PST 23
Peak memory 197420 kb
Host smart-f9c537b0-5371-4d9b-8ec2-b260d6629202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901355874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1901355874
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.926584159
Short name T7
Test name
Test status
Simulation time 368805979 ps
CPU time 0.9 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 195648 kb
Host smart-945f98c9-0388-4d10-b898-d58bceb81fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926584159 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.926584159
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1450037915
Short name T321
Test name
Test status
Simulation time 562169052 ps
CPU time 0.83 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:46 PM PST 23
Peak memory 193376 kb
Host smart-fa9c6561-9288-41ba-bda0-baf3339dbcac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450037915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1450037915
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1418065918
Short name T375
Test name
Test status
Simulation time 305621648 ps
CPU time 0.94 seconds
Started Dec 31 12:26:42 PM PST 23
Finished Dec 31 12:26:44 PM PST 23
Peak memory 183504 kb
Host smart-c5ede6ba-f247-47f2-b0d8-028ff79918c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418065918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1418065918
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3955058271
Short name T362
Test name
Test status
Simulation time 1727729836 ps
CPU time 3.95 seconds
Started Dec 31 12:24:27 PM PST 23
Finished Dec 31 12:24:33 PM PST 23
Peak memory 192652 kb
Host smart-ee5c9e47-9933-4bde-be4b-2f1d54f966e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955058271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3955058271
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.217676303
Short name T378
Test name
Test status
Simulation time 497502843 ps
CPU time 2.09 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 198588 kb
Host smart-ad6339eb-65ed-4406-a640-981a8655cb33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217676303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.217676303
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2591249212
Short name T430
Test name
Test status
Simulation time 8471395980 ps
CPU time 7.56 seconds
Started Dec 31 12:24:55 PM PST 23
Finished Dec 31 12:25:07 PM PST 23
Peak memory 197524 kb
Host smart-e8bc2d73-cc3a-4327-8164-668522e69575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591249212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2591249212
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3843422598
Short name T1
Test name
Test status
Simulation time 598469733 ps
CPU time 0.88 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:27 PM PST 23
Peak memory 195460 kb
Host smart-a463f176-a9b7-46a8-ab1e-fc9978d9123d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843422598 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3843422598
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2373606296
Short name T69
Test name
Test status
Simulation time 351131794 ps
CPU time 0.73 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:22 PM PST 23
Peak memory 181900 kb
Host smart-5506700d-e0f8-4e0c-9549-6ec528629241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373606296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2373606296
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.536959879
Short name T347
Test name
Test status
Simulation time 312980873 ps
CPU time 0.79 seconds
Started Dec 31 12:24:20 PM PST 23
Finished Dec 31 12:24:23 PM PST 23
Peak memory 183056 kb
Host smart-6a0500a7-b371-4f0e-a66f-ec7bf459ca49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536959879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.536959879
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3314530026
Short name T12
Test name
Test status
Simulation time 643507129 ps
CPU time 1.33 seconds
Started Dec 31 12:20:43 PM PST 23
Finished Dec 31 12:20:44 PM PST 23
Peak memory 193544 kb
Host smart-2764f975-1eb0-4cc7-a3d7-29182988a344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314530026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3314530026
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.2730742925
Short name T373
Test name
Test status
Simulation time 606274159 ps
CPU time 1.35 seconds
Started Dec 31 12:24:25 PM PST 23
Finished Dec 31 12:24:30 PM PST 23
Peak memory 198480 kb
Host smart-e2ddcfd1-ee6b-4eb8-a22a-19359843e8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730742925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.2730742925
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1935436438
Short name T78
Test name
Test status
Simulation time 8567581112 ps
CPU time 4.56 seconds
Started Dec 31 12:24:13 PM PST 23
Finished Dec 31 12:24:20 PM PST 23
Peak memory 197824 kb
Host smart-0549fe4c-de35-4fcc-be60-ec0c27070eed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935436438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1935436438
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3679633857
Short name T348
Test name
Test status
Simulation time 430272677 ps
CPU time 0.76 seconds
Started Dec 31 12:27:14 PM PST 23
Finished Dec 31 12:27:15 PM PST 23
Peak memory 194644 kb
Host smart-179c6d7b-3af9-480f-b60e-c5f1fee57077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679633857 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3679633857
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.634059227
Short name T90
Test name
Test status
Simulation time 515232019 ps
CPU time 0.73 seconds
Started Dec 31 12:25:06 PM PST 23
Finished Dec 31 12:25:10 PM PST 23
Peak memory 182648 kb
Host smart-be8a1d24-33af-47e9-b821-6041c63d645f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634059227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.634059227
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.326768445
Short name T355
Test name
Test status
Simulation time 440227859 ps
CPU time 0.65 seconds
Started Dec 31 12:26:14 PM PST 23
Finished Dec 31 12:26:18 PM PST 23
Peak memory 183464 kb
Host smart-b6dd7939-5056-46a6-9311-0f436433b45c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326768445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.326768445
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1971973837
Short name T3
Test name
Test status
Simulation time 2128366058 ps
CPU time 2.65 seconds
Started Dec 31 12:24:19 PM PST 23
Finished Dec 31 12:24:24 PM PST 23
Peak memory 191428 kb
Host smart-7566d2e0-0c7f-41ad-af97-c16347dafae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971973837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1971973837
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2825686933
Short name T319
Test name
Test status
Simulation time 488971888 ps
CPU time 1.23 seconds
Started Dec 31 12:27:08 PM PST 23
Finished Dec 31 12:27:11 PM PST 23
Peak memory 198136 kb
Host smart-e036646f-df41-45cd-96c9-3340f91709c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825686933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2825686933
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4029083724
Short name T95
Test name
Test status
Simulation time 8800523216 ps
CPU time 2.25 seconds
Started Dec 31 12:26:10 PM PST 23
Finished Dec 31 12:26:20 PM PST 23
Peak memory 197188 kb
Host smart-e1f0a39e-d76d-4b9b-9e66-3fd3c8ac9679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029083724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4029083724
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1376353285
Short name T352
Test name
Test status
Simulation time 580535007 ps
CPU time 1.1 seconds
Started Dec 31 12:23:40 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 196868 kb
Host smart-1c4fcbd0-3dae-46b0-870f-34cabd81ca73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376353285 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1376353285
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3292224650
Short name T328
Test name
Test status
Simulation time 493676102 ps
CPU time 0.99 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 183020 kb
Host smart-a2064241-81fa-4a80-9e74-907e64780dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292224650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3292224650
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.216708751
Short name T79
Test name
Test status
Simulation time 509507444 ps
CPU time 0.66 seconds
Started Dec 31 12:25:39 PM PST 23
Finished Dec 31 12:25:49 PM PST 23
Peak memory 183424 kb
Host smart-9f908025-0561-4cc4-b7d8-231eab20f224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216708751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.216708751
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1054804830
Short name T342
Test name
Test status
Simulation time 993993276 ps
CPU time 2.12 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:36 PM PST 23
Peak memory 194020 kb
Host smart-7903763b-ea94-4f6e-96d0-418c9a256deb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054804830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1054804830
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.832408339
Short name T58
Test name
Test status
Simulation time 537727066 ps
CPU time 2.5 seconds
Started Dec 31 12:20:17 PM PST 23
Finished Dec 31 12:20:20 PM PST 23
Peak memory 198604 kb
Host smart-c08c2281-92df-4c16-9b0a-fe2e7b8ed614
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832408339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.832408339
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.58928069
Short name T414
Test name
Test status
Simulation time 4508846698 ps
CPU time 7.24 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:47 PM PST 23
Peak memory 196896 kb
Host smart-5481ad71-ce1a-48a4-b66d-be085cc235b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58928069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_
intg_err.58928069
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2763522374
Short name T332
Test name
Test status
Simulation time 489635508 ps
CPU time 1.35 seconds
Started Dec 31 12:24:29 PM PST 23
Finished Dec 31 12:24:33 PM PST 23
Peak memory 195832 kb
Host smart-bf0d5f7b-d9d9-422c-946f-719f003634f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763522374 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2763522374
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1768717480
Short name T73
Test name
Test status
Simulation time 366048273 ps
CPU time 0.83 seconds
Started Dec 31 12:24:23 PM PST 23
Finished Dec 31 12:24:26 PM PST 23
Peak memory 183424 kb
Host smart-07e9ad1c-95d6-473b-bdaa-00a4f90f5943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768717480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1768717480
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2878494857
Short name T365
Test name
Test status
Simulation time 318390986 ps
CPU time 0.64 seconds
Started Dec 31 12:24:30 PM PST 23
Finished Dec 31 12:24:34 PM PST 23
Peak memory 183648 kb
Host smart-8ac30348-2419-485b-851c-efd477e0d4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878494857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2878494857
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2840185519
Short name T428
Test name
Test status
Simulation time 1621924421 ps
CPU time 1.58 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 194240 kb
Host smart-dbf26f80-87e7-4d35-9246-d8e947b3ce28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840185519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2840185519
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.4122881190
Short name T385
Test name
Test status
Simulation time 482002679 ps
CPU time 1.3 seconds
Started Dec 31 12:23:40 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 197148 kb
Host smart-bff75674-baef-491d-9e2e-5077d9c511cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122881190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.4122881190
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.303454084
Short name T9
Test name
Test status
Simulation time 8501268746 ps
CPU time 2.27 seconds
Started Dec 31 12:26:14 PM PST 23
Finished Dec 31 12:26:19 PM PST 23
Peak memory 197616 kb
Host smart-2006528b-a6b6-4677-bcbd-9956dd6f5aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303454084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.303454084
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1246867953
Short name T368
Test name
Test status
Simulation time 543681758 ps
CPU time 1.41 seconds
Started Dec 31 12:25:52 PM PST 23
Finished Dec 31 12:26:00 PM PST 23
Peak memory 196080 kb
Host smart-be39ba08-c0b1-48e6-8fea-22a7e620d0a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246867953 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1246867953
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2657857939
Short name T399
Test name
Test status
Simulation time 440831178 ps
CPU time 1.15 seconds
Started Dec 31 12:24:29 PM PST 23
Finished Dec 31 12:24:32 PM PST 23
Peak memory 183632 kb
Host smart-dca82c39-d779-4d1c-b539-adc5daa8f96e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657857939 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2657857939
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.690963430
Short name T318
Test name
Test status
Simulation time 506104060 ps
CPU time 1.2 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 183404 kb
Host smart-da5496b4-6b15-4462-b033-d26277908109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690963430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.690963430
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.201131969
Short name T11
Test name
Test status
Simulation time 834028488 ps
CPU time 2.06 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:42 PM PST 23
Peak memory 193944 kb
Host smart-9180b3eb-929f-4fd9-a8d4-cc99016383f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201131969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.201131969
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3332790069
Short name T401
Test name
Test status
Simulation time 504750631 ps
CPU time 1.88 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:42 PM PST 23
Peak memory 198436 kb
Host smart-13f0eff1-dcd6-400a-bf8b-107e010db6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332790069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3332790069
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2317429935
Short name T10
Test name
Test status
Simulation time 463471893 ps
CPU time 1.07 seconds
Started Dec 31 12:32:29 PM PST 23
Finished Dec 31 12:32:33 PM PST 23
Peak memory 198368 kb
Host smart-1fa68231-48ed-400a-8253-0ad4a29ee544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317429935 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2317429935
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.764525705
Short name T351
Test name
Test status
Simulation time 341593736 ps
CPU time 1.19 seconds
Started Dec 31 12:18:24 PM PST 23
Finished Dec 31 12:18:27 PM PST 23
Peak memory 182368 kb
Host smart-3fd6c5bc-ff3f-428d-915a-22f035493c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764525705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.764525705
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3424174263
Short name T75
Test name
Test status
Simulation time 359927274 ps
CPU time 0.78 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:34 PM PST 23
Peak memory 183408 kb
Host smart-36bd10d1-4542-438e-bf9b-f33c7d9015ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424174263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3424174263
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.735477378
Short name T18
Test name
Test status
Simulation time 833932717 ps
CPU time 1.56 seconds
Started Dec 31 12:24:27 PM PST 23
Finished Dec 31 12:24:31 PM PST 23
Peak memory 192588 kb
Host smart-023f191d-5c1c-4248-998d-7a9e08fec6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735477378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.735477378
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3673491078
Short name T404
Test name
Test status
Simulation time 433861363 ps
CPU time 2.26 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:10 PM PST 23
Peak memory 197000 kb
Host smart-7483afbd-9e35-43cf-ad1c-b4323df1d4cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673491078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3673491078
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1878257755
Short name T417
Test name
Test status
Simulation time 7832733235 ps
CPU time 4.01 seconds
Started Dec 31 12:24:01 PM PST 23
Finished Dec 31 12:24:12 PM PST 23
Peak memory 196480 kb
Host smart-58d7b277-bd5f-43fb-8676-f68894ef615e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878257755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1878257755
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3337839151
Short name T320
Test name
Test status
Simulation time 512039193 ps
CPU time 1.43 seconds
Started Dec 31 12:34:34 PM PST 23
Finished Dec 31 12:34:39 PM PST 23
Peak memory 194920 kb
Host smart-cc4c101e-27c3-4951-83c3-fb687c824b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337839151 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3337839151
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2052331596
Short name T396
Test name
Test status
Simulation time 413099465 ps
CPU time 1.31 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:45 PM PST 23
Peak memory 182852 kb
Host smart-e08dcfb0-12e6-4c91-b5e0-34145424fc24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052331596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2052331596
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1393057873
Short name T381
Test name
Test status
Simulation time 310361906 ps
CPU time 1.07 seconds
Started Dec 31 12:23:36 PM PST 23
Finished Dec 31 12:23:39 PM PST 23
Peak memory 183388 kb
Host smart-f19a4b46-8b75-4280-b6b4-54283707c6b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393057873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1393057873
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3096191268
Short name T398
Test name
Test status
Simulation time 459389998 ps
CPU time 1.34 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 198488 kb
Host smart-aa58c95b-a86a-4540-8dfd-bb480c1b61df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096191268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3096191268
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1143077204
Short name T356
Test name
Test status
Simulation time 646108090 ps
CPU time 1 seconds
Started Dec 31 12:24:15 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 192812 kb
Host smart-0d1d325b-0a46-4cb6-8069-f9eb2914b81b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143077204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1143077204
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1521588845
Short name T13
Test name
Test status
Simulation time 6163564808 ps
CPU time 3.51 seconds
Started Dec 31 12:19:10 PM PST 23
Finished Dec 31 12:19:14 PM PST 23
Peak memory 192464 kb
Host smart-cd2770bb-217e-4d96-984c-1b913c8814d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521588845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1521588845
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.145142004
Short name T324
Test name
Test status
Simulation time 1216949460 ps
CPU time 1.45 seconds
Started Dec 31 12:23:18 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 182232 kb
Host smart-bdb7579f-6b33-4648-8c85-913ef45d6d87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145142004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_hw
_reset.145142004
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.818041077
Short name T337
Test name
Test status
Simulation time 455895252 ps
CPU time 0.97 seconds
Started Dec 31 12:28:14 PM PST 23
Finished Dec 31 12:28:16 PM PST 23
Peak memory 198344 kb
Host smart-1f61689b-7090-4948-9720-d2fb50ef1302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818041077 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.818041077
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.418831526
Short name T382
Test name
Test status
Simulation time 399869472 ps
CPU time 0.69 seconds
Started Dec 31 12:23:00 PM PST 23
Finished Dec 31 12:23:02 PM PST 23
Peak memory 183696 kb
Host smart-a63c7737-90cb-4aed-94dc-4a1a2ed3b790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418831526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.418831526
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3387733379
Short name T338
Test name
Test status
Simulation time 518280317 ps
CPU time 1.22 seconds
Started Dec 31 12:22:09 PM PST 23
Finished Dec 31 12:22:11 PM PST 23
Peak memory 183768 kb
Host smart-3cfd5c18-563d-4aa0-b035-80fa9d8fb635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387733379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3387733379
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1827220535
Short name T370
Test name
Test status
Simulation time 302247167 ps
CPU time 1 seconds
Started Dec 31 12:25:36 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 182556 kb
Host smart-95e455f7-a312-49f1-b1d6-d3518b9390e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827220535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1827220535
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.3267365329
Short name T394
Test name
Test status
Simulation time 465188499 ps
CPU time 1.24 seconds
Started Dec 31 12:25:33 PM PST 23
Finished Dec 31 12:25:41 PM PST 23
Peak memory 183420 kb
Host smart-66345560-7479-4d04-8594-d22580b9c226
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267365329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.3267365329
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3359116359
Short name T19
Test name
Test status
Simulation time 1891846380 ps
CPU time 0.92 seconds
Started Dec 31 12:26:22 PM PST 23
Finished Dec 31 12:26:25 PM PST 23
Peak memory 193036 kb
Host smart-de5523a3-fbe8-421c-a7cb-87a36c3d3605
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359116359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3359116359
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3777699150
Short name T343
Test name
Test status
Simulation time 713724953 ps
CPU time 2.09 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:21 PM PST 23
Peak memory 198220 kb
Host smart-afd46680-2bc4-4828-b3e9-ff33f1e30472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777699150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3777699150
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2878350065
Short name T341
Test name
Test status
Simulation time 4542835557 ps
CPU time 4.3 seconds
Started Dec 31 12:26:58 PM PST 23
Finished Dec 31 12:27:04 PM PST 23
Peak memory 197024 kb
Host smart-630a5342-ab36-468d-b950-beac50a47927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878350065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2878350065
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2770225439
Short name T327
Test name
Test status
Simulation time 535917700 ps
CPU time 0.71 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183452 kb
Host smart-a74f9241-7a92-4c3d-b2d9-6a958450ecfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770225439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2770225439
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2108535222
Short name T359
Test name
Test status
Simulation time 328244798 ps
CPU time 1.02 seconds
Started Dec 31 12:24:39 PM PST 23
Finished Dec 31 12:24:47 PM PST 23
Peak memory 183456 kb
Host smart-a97c610b-a21d-4e38-ae59-bd1188c02aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108535222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2108535222
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1047116159
Short name T369
Test name
Test status
Simulation time 403418890 ps
CPU time 1.14 seconds
Started Dec 31 12:23:45 PM PST 23
Finished Dec 31 12:23:47 PM PST 23
Peak memory 183660 kb
Host smart-a8dd1e4c-2849-42bf-832a-698895d26e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047116159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1047116159
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3195009564
Short name T393
Test name
Test status
Simulation time 305934938 ps
CPU time 1 seconds
Started Dec 31 12:23:44 PM PST 23
Finished Dec 31 12:23:46 PM PST 23
Peak memory 183492 kb
Host smart-95d9ef5d-39bd-4270-b7e9-6c3d7579aee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195009564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3195009564
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3727584890
Short name T15
Test name
Test status
Simulation time 565432808 ps
CPU time 0.61 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183432 kb
Host smart-e7795945-a043-408c-82c3-a1bb1694f877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727584890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3727584890
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1321982641
Short name T76
Test name
Test status
Simulation time 540814291 ps
CPU time 0.74 seconds
Started Dec 31 12:23:40 PM PST 23
Finished Dec 31 12:23:44 PM PST 23
Peak memory 183376 kb
Host smart-27697961-e99c-448f-819e-5a21ca596e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321982641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1321982641
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2073162510
Short name T334
Test name
Test status
Simulation time 333031366 ps
CPU time 0.78 seconds
Started Dec 31 12:23:51 PM PST 23
Finished Dec 31 12:23:54 PM PST 23
Peak memory 183448 kb
Host smart-c39ba770-10c1-449f-8e2c-49e2641a8751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073162510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2073162510
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1231095011
Short name T363
Test name
Test status
Simulation time 462703488 ps
CPU time 0.58 seconds
Started Dec 31 12:23:52 PM PST 23
Finished Dec 31 12:23:54 PM PST 23
Peak memory 183668 kb
Host smart-f5949ece-1ed6-4f74-9297-0694ea207e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231095011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1231095011
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.443544646
Short name T50
Test name
Test status
Simulation time 501251665 ps
CPU time 0.75 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183080 kb
Host smart-3bfd1f49-1541-455e-bb26-3dd5982e9871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443544646 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.443544646
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.4081937803
Short name T412
Test name
Test status
Simulation time 462774649 ps
CPU time 0.67 seconds
Started Dec 31 12:27:50 PM PST 23
Finished Dec 31 12:27:53 PM PST 23
Peak memory 183752 kb
Host smart-c498a3a2-677a-40d7-b28d-c9d9b9bf19f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081937803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.4081937803
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2646898756
Short name T84
Test name
Test status
Simulation time 5883777521 ps
CPU time 13.98 seconds
Started Dec 31 12:25:26 PM PST 23
Finished Dec 31 12:25:46 PM PST 23
Peak memory 191752 kb
Host smart-8838d327-e5e6-4a72-9fe7-975084137d3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646898756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2646898756
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1539497975
Short name T52
Test name
Test status
Simulation time 1260133850 ps
CPU time 2.51 seconds
Started Dec 31 12:26:59 PM PST 23
Finished Dec 31 12:27:03 PM PST 23
Peak memory 183680 kb
Host smart-601d61e6-7bb9-48aa-830f-96662e5598a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539497975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1539497975
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.3137581401
Short name T380
Test name
Test status
Simulation time 428815897 ps
CPU time 1.04 seconds
Started Dec 31 12:24:34 PM PST 23
Finished Dec 31 12:24:43 PM PST 23
Peak memory 197952 kb
Host smart-a0e58508-bef7-4ca3-8caf-eb1794b44c3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137581401 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.3137581401
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3100184475
Short name T70
Test name
Test status
Simulation time 336105414 ps
CPU time 0.82 seconds
Started Dec 31 12:23:25 PM PST 23
Finished Dec 31 12:23:27 PM PST 23
Peak memory 183664 kb
Host smart-c1687c88-b1de-4bea-970f-d33aab33c46a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100184475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3100184475
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3381324656
Short name T364
Test name
Test status
Simulation time 492832845 ps
CPU time 1.25 seconds
Started Dec 31 12:24:15 PM PST 23
Finished Dec 31 12:24:18 PM PST 23
Peak memory 183092 kb
Host smart-dad7d922-3ba2-4b13-a3b4-656563747c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381324656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3381324656
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2828983214
Short name T55
Test name
Test status
Simulation time 496666298 ps
CPU time 0.86 seconds
Started Dec 31 12:18:23 PM PST 23
Finished Dec 31 12:18:24 PM PST 23
Peak memory 183368 kb
Host smart-d0799549-5a96-428b-8ecd-db0241094ac8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828983214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2828983214
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.384531786
Short name T326
Test name
Test status
Simulation time 524149567 ps
CPU time 0.9 seconds
Started Dec 31 12:23:06 PM PST 23
Finished Dec 31 12:23:07 PM PST 23
Peak memory 182232 kb
Host smart-e9ad056c-a3cc-4d9f-8536-faa5e6f813f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384531786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.384531786
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3267937600
Short name T424
Test name
Test status
Simulation time 1050342042 ps
CPU time 1.22 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:20 PM PST 23
Peak memory 192284 kb
Host smart-64744182-e3d1-46a1-8359-7dced2a3de1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267937600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3267937600
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.744825439
Short name T349
Test name
Test status
Simulation time 507558174 ps
CPU time 1.76 seconds
Started Dec 31 12:20:09 PM PST 23
Finished Dec 31 12:20:12 PM PST 23
Peak memory 198820 kb
Host smart-d0b4b173-caa3-4a7b-b77d-13b9f8698c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744825439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.744825439
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.788108936
Short name T358
Test name
Test status
Simulation time 4570800041 ps
CPU time 1.17 seconds
Started Dec 31 12:24:16 PM PST 23
Finished Dec 31 12:24:19 PM PST 23
Peak memory 195496 kb
Host smart-3b567ba5-4b12-4821-b6f2-6e9c10e79b37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788108936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.788108936
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1435365043
Short name T390
Test name
Test status
Simulation time 441653696 ps
CPU time 0.84 seconds
Started Dec 31 12:23:56 PM PST 23
Finished Dec 31 12:24:01 PM PST 23
Peak memory 183500 kb
Host smart-5d1c9bdd-5369-4243-9049-8494bb04d116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435365043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1435365043
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.876940850
Short name T383
Test name
Test status
Simulation time 430018097 ps
CPU time 0.85 seconds
Started Dec 31 12:23:52 PM PST 23
Finished Dec 31 12:23:55 PM PST 23
Peak memory 183696 kb
Host smart-863970b3-e804-498e-a50e-661b56ba3f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876940850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.876940850
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3813499706
Short name T330
Test name
Test status
Simulation time 340371255 ps
CPU time 0.71 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183452 kb
Host smart-7a36f608-09bf-47f3-8913-b8a8940aeb9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813499706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3813499706
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2777864768
Short name T322
Test name
Test status
Simulation time 385556574 ps
CPU time 1.1 seconds
Started Dec 31 12:23:54 PM PST 23
Finished Dec 31 12:24:02 PM PST 23
Peak memory 183012 kb
Host smart-67ab1507-7270-46b2-bece-911fe29df0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777864768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2777864768
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2103360657
Short name T346
Test name
Test status
Simulation time 470447899 ps
CPU time 0.87 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183268 kb
Host smart-be72e447-6de9-4e90-acef-e802934cb51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103360657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2103360657
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.917155003
Short name T48
Test name
Test status
Simulation time 319639086 ps
CPU time 1.06 seconds
Started Dec 31 12:23:54 PM PST 23
Finished Dec 31 12:24:00 PM PST 23
Peak memory 183640 kb
Host smart-355a2d0c-bf4d-498e-8ac4-710d13912b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917155003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.917155003
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1449428445
Short name T425
Test name
Test status
Simulation time 361672916 ps
CPU time 0.55 seconds
Started Dec 31 12:24:03 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 183688 kb
Host smart-bde9edfe-0e62-430d-88c3-0a5ce0d5f80c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449428445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1449428445
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.98494606
Short name T333
Test name
Test status
Simulation time 338743203 ps
CPU time 0.65 seconds
Started Dec 31 12:23:51 PM PST 23
Finished Dec 31 12:23:54 PM PST 23
Peak memory 183688 kb
Host smart-e8bd7c50-f831-4cb8-8020-ee15c1bfa272
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98494606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.98494606
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3418364888
Short name T403
Test name
Test status
Simulation time 462086081 ps
CPU time 0.68 seconds
Started Dec 31 12:23:51 PM PST 23
Finished Dec 31 12:23:52 PM PST 23
Peak memory 183428 kb
Host smart-a1c51015-d907-442a-8f61-9784149ce6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418364888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3418364888
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3936437427
Short name T340
Test name
Test status
Simulation time 426517458 ps
CPU time 0.57 seconds
Started Dec 31 12:23:52 PM PST 23
Finished Dec 31 12:23:54 PM PST 23
Peak memory 183476 kb
Host smart-43b538a0-e41c-4f37-86e0-5b1db0203a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936437427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3936437427
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2915096644
Short name T71
Test name
Test status
Simulation time 502554831 ps
CPU time 1.64 seconds
Started Dec 31 12:22:31 PM PST 23
Finished Dec 31 12:22:33 PM PST 23
Peak memory 192608 kb
Host smart-32ae1ec3-dafa-4f24-bb4a-df379d4a9092
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915096644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2915096644
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1070772163
Short name T315
Test name
Test status
Simulation time 6164026298 ps
CPU time 6.43 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:37 PM PST 23
Peak memory 192080 kb
Host smart-06e86284-2d37-452a-834c-17254a86337e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070772163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1070772163
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3872933821
Short name T54
Test name
Test status
Simulation time 1039540500 ps
CPU time 0.78 seconds
Started Dec 31 12:25:40 PM PST 23
Finished Dec 31 12:25:50 PM PST 23
Peak memory 183676 kb
Host smart-d6fc1c2f-0d18-4570-b53a-5ad545ee2868
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872933821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3872933821
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1835714266
Short name T360
Test name
Test status
Simulation time 331779500 ps
CPU time 0.96 seconds
Started Dec 31 12:25:00 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 192704 kb
Host smart-8f28abde-bf0d-4929-97a4-39ae6b96155a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835714266 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1835714266
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3772785636
Short name T371
Test name
Test status
Simulation time 338557383 ps
CPU time 1.13 seconds
Started Dec 31 12:22:30 PM PST 23
Finished Dec 31 12:22:32 PM PST 23
Peak memory 181556 kb
Host smart-fe85f944-1a14-4187-ae55-e9ded19eebaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772785636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3772785636
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1161430892
Short name T409
Test name
Test status
Simulation time 405177298 ps
CPU time 1.1 seconds
Started Dec 31 12:25:26 PM PST 23
Finished Dec 31 12:25:33 PM PST 23
Peak memory 183072 kb
Host smart-1c6829c8-c24e-448e-bd4a-98d78b351b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161430892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1161430892
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2371208390
Short name T344
Test name
Test status
Simulation time 439737142 ps
CPU time 0.82 seconds
Started Dec 31 12:18:10 PM PST 23
Finished Dec 31 12:18:11 PM PST 23
Peak memory 183824 kb
Host smart-f81af2ee-6c09-4849-bba1-26f176b87b9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371208390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2371208390
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.104017482
Short name T397
Test name
Test status
Simulation time 447049515 ps
CPU time 0.92 seconds
Started Dec 31 12:25:37 PM PST 23
Finished Dec 31 12:25:47 PM PST 23
Peak memory 182224 kb
Host smart-f8f5ae12-2f08-4d48-9544-c37137dcf736
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104017482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.104017482
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.742200679
Short name T354
Test name
Test status
Simulation time 1127927936 ps
CPU time 1.09 seconds
Started Dec 31 12:25:57 PM PST 23
Finished Dec 31 12:26:05 PM PST 23
Peak memory 194088 kb
Host smart-2c0899c8-fd98-46c5-9254-11ba024dbeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742200679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.742200679
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.887774660
Short name T57
Test name
Test status
Simulation time 368711820 ps
CPU time 1.43 seconds
Started Dec 31 12:20:54 PM PST 23
Finished Dec 31 12:20:56 PM PST 23
Peak memory 198348 kb
Host smart-daca19a1-bee3-403d-a66a-ca905dc8b999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887774660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.887774660
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1566264018
Short name T429
Test name
Test status
Simulation time 7865351853 ps
CPU time 14.28 seconds
Started Dec 31 12:25:25 PM PST 23
Finished Dec 31 12:25:45 PM PST 23
Peak memory 196916 kb
Host smart-e1411ecc-c867-4c58-8114-b0cd64bc711c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566264018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1566264018
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1158618499
Short name T81
Test name
Test status
Simulation time 310600120 ps
CPU time 0.69 seconds
Started Dec 31 12:24:05 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 183440 kb
Host smart-4495718d-63b5-4d40-a351-622db76835f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158618499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1158618499
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2615042866
Short name T6
Test name
Test status
Simulation time 339789432 ps
CPU time 0.76 seconds
Started Dec 31 12:23:54 PM PST 23
Finished Dec 31 12:24:02 PM PST 23
Peak memory 183264 kb
Host smart-aa762126-949e-4836-b522-82e9db3b3b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615042866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2615042866
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2664214767
Short name T16
Test name
Test status
Simulation time 293558270 ps
CPU time 0.94 seconds
Started Dec 31 12:24:04 PM PST 23
Finished Dec 31 12:24:11 PM PST 23
Peak memory 183680 kb
Host smart-f8c02621-0794-44f2-a6f1-df685d39d484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664214767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2664214767
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1819458419
Short name T325
Test name
Test status
Simulation time 364118104 ps
CPU time 0.71 seconds
Started Dec 31 12:24:04 PM PST 23
Finished Dec 31 12:24:10 PM PST 23
Peak memory 183440 kb
Host smart-16affd6e-8571-4d32-83c0-1945daa0a160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819458419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1819458419
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2002141635
Short name T316
Test name
Test status
Simulation time 280744688 ps
CPU time 0.96 seconds
Started Dec 31 12:23:52 PM PST 23
Finished Dec 31 12:23:55 PM PST 23
Peak memory 183412 kb
Host smart-46a10044-0014-422c-8c03-3c138579f806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002141635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2002141635
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3917665208
Short name T423
Test name
Test status
Simulation time 525486268 ps
CPU time 0.67 seconds
Started Dec 31 12:24:00 PM PST 23
Finished Dec 31 12:24:07 PM PST 23
Peak memory 183448 kb
Host smart-4772c8d3-f8c6-4511-9d19-8b6ca87058c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917665208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3917665208
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.766356657
Short name T379
Test name
Test status
Simulation time 320013599 ps
CPU time 0.96 seconds
Started Dec 31 12:24:01 PM PST 23
Finished Dec 31 12:24:08 PM PST 23
Peak memory 183376 kb
Host smart-c511171d-d9f9-4e49-a7bf-440b016a33ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766356657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.766356657
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.4149844710
Short name T335
Test name
Test status
Simulation time 282723234 ps
CPU time 0.97 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 183452 kb
Host smart-89777815-08e2-4726-a203-70ae0511faee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149844710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.4149844710
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3531746186
Short name T400
Test name
Test status
Simulation time 341984109 ps
CPU time 0.97 seconds
Started Dec 31 12:23:51 PM PST 23
Finished Dec 31 12:23:54 PM PST 23
Peak memory 183448 kb
Host smart-ce7561e3-0a44-453a-9170-c90688fa8e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531746186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3531746186
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3328718679
Short name T323
Test name
Test status
Simulation time 538862161 ps
CPU time 0.78 seconds
Started Dec 31 12:23:58 PM PST 23
Finished Dec 31 12:24:03 PM PST 23
Peak memory 183452 kb
Host smart-ad911abc-01d3-4b6b-b10d-39ce591496d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328718679 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3328718679
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2140457237
Short name T422
Test name
Test status
Simulation time 570352457 ps
CPU time 0.74 seconds
Started Dec 31 12:25:47 PM PST 23
Finished Dec 31 12:25:56 PM PST 23
Peak memory 195676 kb
Host smart-57fbce65-dbb3-45cb-be11-029f5522e933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140457237 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2140457237
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2881614906
Short name T413
Test name
Test status
Simulation time 304134027 ps
CPU time 0.8 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:05 PM PST 23
Peak memory 183284 kb
Host smart-ac44d749-5cd6-4211-a542-ed6d80683fa9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881614906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2881614906
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3738290095
Short name T372
Test name
Test status
Simulation time 329804543 ps
CPU time 0.75 seconds
Started Dec 31 12:26:00 PM PST 23
Finished Dec 31 12:26:07 PM PST 23
Peak memory 183368 kb
Host smart-fa03af92-24e0-44cf-9395-99a389577b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738290095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3738290095
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3158785782
Short name T89
Test name
Test status
Simulation time 1331844043 ps
CPU time 0.92 seconds
Started Dec 31 12:25:53 PM PST 23
Finished Dec 31 12:26:01 PM PST 23
Peak memory 193152 kb
Host smart-4d749ca6-90ac-4b12-8ebf-93f1371956fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158785782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3158785782
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3169865044
Short name T345
Test name
Test status
Simulation time 604005043 ps
CPU time 2.35 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:07 PM PST 23
Peak memory 198108 kb
Host smart-628d3623-103c-41c2-b463-6684675f9aef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169865044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3169865044
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1927001673
Short name T410
Test name
Test status
Simulation time 4035650728 ps
CPU time 2.13 seconds
Started Dec 31 12:19:56 PM PST 23
Finished Dec 31 12:19:59 PM PST 23
Peak memory 195976 kb
Host smart-d86b3a1b-0c1a-4f4f-a3f4-9e4f6008ede3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927001673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1927001673
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1594353353
Short name T353
Test name
Test status
Simulation time 417601669 ps
CPU time 0.75 seconds
Started Dec 31 12:24:56 PM PST 23
Finished Dec 31 12:25:00 PM PST 23
Peak memory 194764 kb
Host smart-92434f03-5fd4-447e-8a43-be6d3a77de39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594353353 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1594353353
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1028983039
Short name T366
Test name
Test status
Simulation time 469961533 ps
CPU time 0.77 seconds
Started Dec 31 12:24:02 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 182180 kb
Host smart-8c9bd8be-2c97-43fb-8c84-9d43fb0a4717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028983039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1028983039
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2394258790
Short name T386
Test name
Test status
Simulation time 550449609 ps
CPU time 0.65 seconds
Started Dec 31 12:22:54 PM PST 23
Finished Dec 31 12:22:56 PM PST 23
Peak memory 183372 kb
Host smart-bbd26ac2-d096-40d2-9fe1-45826b3bfa53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394258790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2394258790
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3850703359
Short name T426
Test name
Test status
Simulation time 2286772662 ps
CPU time 2.17 seconds
Started Dec 31 12:25:44 PM PST 23
Finished Dec 31 12:25:55 PM PST 23
Peak memory 191480 kb
Host smart-fb121f49-0c8c-411c-86ae-648b0612b26a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850703359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3850703359
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.40036522
Short name T56
Test name
Test status
Simulation time 550123416 ps
CPU time 1.89 seconds
Started Dec 31 12:24:01 PM PST 23
Finished Dec 31 12:24:09 PM PST 23
Peak memory 198068 kb
Host smart-982aa011-2608-474d-a9a4-a9eefb24617a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40036522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.40036522
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2238442827
Short name T94
Test name
Test status
Simulation time 7534972672 ps
CPU time 3.68 seconds
Started Dec 31 12:24:07 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 197492 kb
Host smart-1a8ff56b-b8f0-4b06-a69c-7d639635b95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238442827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2238442827
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2018308411
Short name T77
Test name
Test status
Simulation time 437342567 ps
CPU time 1.2 seconds
Started Dec 31 12:25:27 PM PST 23
Finished Dec 31 12:25:35 PM PST 23
Peak memory 195240 kb
Host smart-b2890397-1504-4eaf-b34e-611f1e2b64ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018308411 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2018308411
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2822644497
Short name T72
Test name
Test status
Simulation time 368097327 ps
CPU time 1.05 seconds
Started Dec 31 12:27:17 PM PST 23
Finished Dec 31 12:27:19 PM PST 23
Peak memory 183668 kb
Host smart-614575ef-d8eb-4a71-bb80-d3f0f76c9c7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822644497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2822644497
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2578598352
Short name T427
Test name
Test status
Simulation time 437513001 ps
CPU time 0.54 seconds
Started Dec 31 12:26:19 PM PST 23
Finished Dec 31 12:26:21 PM PST 23
Peak memory 183652 kb
Host smart-1282ccdf-a549-492b-8b64-a145b82e8424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578598352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2578598352
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1388962999
Short name T4
Test name
Test status
Simulation time 1892178399 ps
CPU time 1.82 seconds
Started Dec 31 12:22:26 PM PST 23
Finished Dec 31 12:22:29 PM PST 23
Peak memory 193792 kb
Host smart-4f4a79d8-c47f-4ff0-b3e2-8548e6e80bf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388962999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1388962999
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.939770952
Short name T317
Test name
Test status
Simulation time 511980034 ps
CPU time 1.93 seconds
Started Dec 31 12:24:11 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 198584 kb
Host smart-fc1a3f7d-f615-44f3-9118-66ca3440bbf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939770952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.939770952
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.245999917
Short name T391
Test name
Test status
Simulation time 4566092731 ps
CPU time 2.78 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 197112 kb
Host smart-1b44c8a9-7858-469d-893b-62edb3c6e0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245999917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.245999917
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2711406732
Short name T402
Test name
Test status
Simulation time 492779695 ps
CPU time 1.33 seconds
Started Dec 31 12:24:10 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 194784 kb
Host smart-bdcb7170-7582-4395-abfc-bb84eb1332f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711406732 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2711406732
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.402801516
Short name T388
Test name
Test status
Simulation time 503999694 ps
CPU time 0.76 seconds
Started Dec 31 12:23:38 PM PST 23
Finished Dec 31 12:23:43 PM PST 23
Peak memory 183760 kb
Host smart-5b2ad36b-706e-464b-b4bb-5a396de6794b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402801516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.402801516
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1532840730
Short name T387
Test name
Test status
Simulation time 638119159 ps
CPU time 0.6 seconds
Started Dec 31 12:24:10 PM PST 23
Finished Dec 31 12:24:15 PM PST 23
Peak memory 183736 kb
Host smart-c3cfff79-01ab-4d14-8c33-805bff210afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532840730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1532840730
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.805317636
Short name T384
Test name
Test status
Simulation time 1199320357 ps
CPU time 2.33 seconds
Started Dec 31 12:23:57 PM PST 23
Finished Dec 31 12:24:04 PM PST 23
Peak memory 194128 kb
Host smart-23b8e226-2f56-4090-803c-8e686b5c8650
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805317636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.805317636
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3822843541
Short name T311
Test name
Test status
Simulation time 420199762 ps
CPU time 1.95 seconds
Started Dec 31 12:26:02 PM PST 23
Finished Dec 31 12:26:09 PM PST 23
Peak memory 198520 kb
Host smart-9040ceba-8753-426a-83d8-8fa4b2da76c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822843541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3822843541
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.333349538
Short name T377
Test name
Test status
Simulation time 4537748377 ps
CPU time 6.85 seconds
Started Dec 31 12:23:41 PM PST 23
Finished Dec 31 12:23:50 PM PST 23
Peak memory 195380 kb
Host smart-7d973e69-22a0-4456-b7d5-08f1fb077387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333349538 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.333349538
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.265549116
Short name T17
Test name
Test status
Simulation time 605691512 ps
CPU time 1.6 seconds
Started Dec 31 12:24:12 PM PST 23
Finished Dec 31 12:24:16 PM PST 23
Peak memory 194996 kb
Host smart-52c82ab1-ebfa-4337-8c08-2635e86d5f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265549116 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.265549116
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2772194496
Short name T86
Test name
Test status
Simulation time 414801628 ps
CPU time 1.28 seconds
Started Dec 31 12:23:45 PM PST 23
Finished Dec 31 12:23:47 PM PST 23
Peak memory 183736 kb
Host smart-ace07fec-6a5d-451f-a89e-caf78fc57611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772194496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2772194496
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.3467885714
Short name T376
Test name
Test status
Simulation time 284286052 ps
CPU time 0.8 seconds
Started Dec 31 12:24:17 PM PST 23
Finished Dec 31 12:24:20 PM PST 23
Peak memory 183244 kb
Host smart-2bb12579-b41c-4a10-8218-30edaa5b89cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467885714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.3467885714
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.698554896
Short name T374
Test name
Test status
Simulation time 1013859031 ps
CPU time 1.94 seconds
Started Dec 31 12:25:01 PM PST 23
Finished Dec 31 12:25:06 PM PST 23
Peak memory 192596 kb
Host smart-a3e035f4-bb82-40ae-9b56-5226ed2e31c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698554896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.698554896
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.2634335798
Short name T357
Test name
Test status
Simulation time 483867305 ps
CPU time 2.41 seconds
Started Dec 31 12:24:10 PM PST 23
Finished Dec 31 12:24:17 PM PST 23
Peak memory 198560 kb
Host smart-440c6bfa-21b1-4d4b-a285-86e054fbebb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634335798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.2634335798
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.250607176
Short name T350
Test name
Test status
Simulation time 8673821718 ps
CPU time 8.07 seconds
Started Dec 31 12:23:11 PM PST 23
Finished Dec 31 12:23:20 PM PST 23
Peak memory 197448 kb
Host smart-e974e76b-1d0c-4ae5-8bde-01f66a67809b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250607176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.250607176
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1826147144
Short name T218
Test name
Test status
Simulation time 444730045 ps
CPU time 1.15 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:45:54 PM PST 23
Peak memory 182668 kb
Host smart-4b80a1fc-d1d8-46dc-9807-d7b8fce02bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826147144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1826147144
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1471536572
Short name T236
Test name
Test status
Simulation time 40476763269 ps
CPU time 27.95 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 182592 kb
Host smart-2b52d49e-e4d5-48d7-a797-888c4e30d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471536572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1471536572
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3760048641
Short name T147
Test name
Test status
Simulation time 369443543 ps
CPU time 1.05 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:45:38 PM PST 23
Peak memory 182536 kb
Host smart-d58ff8b5-33d7-4156-b8fb-fd250d759d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760048641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3760048641
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3084406722
Short name T97
Test name
Test status
Simulation time 189940759412 ps
CPU time 304.24 seconds
Started Dec 31 12:45:15 PM PST 23
Finished Dec 31 12:50:25 PM PST 23
Peak memory 182628 kb
Host smart-2a140094-b636-4151-b0ca-98800891a09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084406722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3084406722
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.329480685
Short name T229
Test name
Test status
Simulation time 543736259 ps
CPU time 1.37 seconds
Started Dec 31 12:45:22 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 182664 kb
Host smart-e9ef30e6-0143-4765-80f5-dda19fb1fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329480685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.329480685
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1480269228
Short name T171
Test name
Test status
Simulation time 53316044377 ps
CPU time 87.28 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:46:58 PM PST 23
Peak memory 182816 kb
Host smart-706e5b92-f020-4bda-be30-5768530c8d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480269228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1480269228
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3976671607
Short name T34
Test name
Test status
Simulation time 4511687531 ps
CPU time 3.07 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:45:40 PM PST 23
Peak memory 214824 kb
Host smart-d779caed-6c7c-41c9-9b79-2280bb797d05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976671607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3976671607
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.368038477
Short name T190
Test name
Test status
Simulation time 510503888 ps
CPU time 0.74 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:45:47 PM PST 23
Peak memory 182700 kb
Host smart-dcc29fc9-f63c-4908-a304-e7dd96da9d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368038477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.368038477
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.716017116
Short name T129
Test name
Test status
Simulation time 107563145337 ps
CPU time 43.55 seconds
Started Dec 31 12:45:30 PM PST 23
Finished Dec 31 12:46:14 PM PST 23
Peak memory 182812 kb
Host smart-44d55686-2371-4b7b-ad37-ed77e140f5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716017116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.716017116
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2633792772
Short name T264
Test name
Test status
Simulation time 78695093830 ps
CPU time 201.3 seconds
Started Dec 31 12:45:33 PM PST 23
Finished Dec 31 12:48:55 PM PST 23
Peak memory 197684 kb
Host smart-5fddd29e-c00a-4479-9c5a-04755318f077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633792772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2633792772
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3197397797
Short name T212
Test name
Test status
Simulation time 430051390 ps
CPU time 0.59 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 182676 kb
Host smart-cbafaee4-0774-4dfc-a7b3-7896571182ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197397797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3197397797
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4134148849
Short name T45
Test name
Test status
Simulation time 38366056444 ps
CPU time 28.66 seconds
Started Dec 31 12:45:43 PM PST 23
Finished Dec 31 12:46:13 PM PST 23
Peak memory 182772 kb
Host smart-768167cd-3e35-4234-b3bb-af2ae63658fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134148849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4134148849
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.788084510
Short name T231
Test name
Test status
Simulation time 569198435 ps
CPU time 0.9 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:45:54 PM PST 23
Peak memory 182552 kb
Host smart-41b015ce-187a-4a42-9486-84275923dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788084510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.788084510
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.791767116
Short name T263
Test name
Test status
Simulation time 872422675349 ps
CPU time 583.2 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:55:36 PM PST 23
Peak memory 205856 kb
Host smart-55579d3d-bbe1-4c69-a990-fc81932dbe08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791767116 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.791767116
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2357457194
Short name T135
Test name
Test status
Simulation time 413604083 ps
CPU time 0.8 seconds
Started Dec 31 12:45:38 PM PST 23
Finished Dec 31 12:45:40 PM PST 23
Peak memory 182680 kb
Host smart-69035ee4-699f-4369-a131-24f28f37e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357457194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2357457194
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.86690866
Short name T295
Test name
Test status
Simulation time 19136170872 ps
CPU time 8.45 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:46:01 PM PST 23
Peak memory 182800 kb
Host smart-668c0f85-0382-4a0f-8a88-41a1113a1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86690866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.86690866
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2896595793
Short name T203
Test name
Test status
Simulation time 581508698 ps
CPU time 0.75 seconds
Started Dec 31 12:45:30 PM PST 23
Finished Dec 31 12:45:31 PM PST 23
Peak memory 182632 kb
Host smart-738b8ea5-795a-4776-8058-a8d05e7624fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896595793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2896595793
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2331031683
Short name T109
Test name
Test status
Simulation time 554580125006 ps
CPU time 421.37 seconds
Started Dec 31 12:45:48 PM PST 23
Finished Dec 31 12:52:50 PM PST 23
Peak memory 192712 kb
Host smart-bf3da285-242b-4411-91d9-8b0fa52eb8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331031683 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2331031683
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.4208451784
Short name T137
Test name
Test status
Simulation time 11685859432 ps
CPU time 123.09 seconds
Started Dec 31 12:45:27 PM PST 23
Finished Dec 31 12:47:31 PM PST 23
Peak memory 197588 kb
Host smart-72f85605-1e02-423c-9950-ef376bd06aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208451784 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.4208451784
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3296685704
Short name T176
Test name
Test status
Simulation time 600912759 ps
CPU time 0.78 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:46:15 PM PST 23
Peak memory 182708 kb
Host smart-d1ae1de2-0cf4-4de0-bf08-fc73642c5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296685704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3296685704
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.869835197
Short name T309
Test name
Test status
Simulation time 19450443412 ps
CPU time 13.88 seconds
Started Dec 31 12:45:39 PM PST 23
Finished Dec 31 12:45:54 PM PST 23
Peak memory 182700 kb
Host smart-374b7085-3c8a-4de9-83b5-868902540571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869835197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.869835197
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2649306628
Short name T168
Test name
Test status
Simulation time 506282292 ps
CPU time 0.68 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182588 kb
Host smart-31cf4ff5-1cdd-4099-ab48-fc9cd19eebd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649306628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2649306628
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1671078143
Short name T98
Test name
Test status
Simulation time 56746415980 ps
CPU time 49.72 seconds
Started Dec 31 12:45:51 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 182772 kb
Host smart-2e59f26f-6c9e-4647-8b94-c585150b226b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671078143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1671078143
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1743245317
Short name T65
Test name
Test status
Simulation time 64381411204 ps
CPU time 302.25 seconds
Started Dec 31 12:45:42 PM PST 23
Finished Dec 31 12:50:45 PM PST 23
Peak memory 197588 kb
Host smart-dd48a356-e372-4b2f-9413-51058170adba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743245317 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1743245317
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3273741813
Short name T250
Test name
Test status
Simulation time 380653864 ps
CPU time 1.03 seconds
Started Dec 31 12:45:25 PM PST 23
Finished Dec 31 12:45:27 PM PST 23
Peak memory 182644 kb
Host smart-bda19118-fc29-4eae-9c36-691b889d180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273741813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3273741813
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.702796650
Short name T201
Test name
Test status
Simulation time 29081251413 ps
CPU time 12.37 seconds
Started Dec 31 12:45:53 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182824 kb
Host smart-c5eed9ec-c613-40b5-afa0-b08748a9d745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702796650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.702796650
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3209295736
Short name T261
Test name
Test status
Simulation time 504355613 ps
CPU time 0.72 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:45:58 PM PST 23
Peak memory 182592 kb
Host smart-8a6f760a-1d56-4e10-a0fb-8ed118e39334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209295736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3209295736
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2603946261
Short name T119
Test name
Test status
Simulation time 187583511672 ps
CPU time 151.71 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:48:09 PM PST 23
Peak memory 193224 kb
Host smart-adac5d45-863b-4137-b614-7097f4aeb3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603946261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2603946261
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.424770761
Short name T232
Test name
Test status
Simulation time 70165767361 ps
CPU time 193.64 seconds
Started Dec 31 12:46:03 PM PST 23
Finished Dec 31 12:49:18 PM PST 23
Peak memory 197604 kb
Host smart-9e1f97f3-c5ee-4d2a-8410-ffbb96413dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424770761 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.424770761
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1957299059
Short name T122
Test name
Test status
Simulation time 523802016 ps
CPU time 0.67 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182648 kb
Host smart-ffa8c016-b228-4928-9c3f-88d1a6528681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957299059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1957299059
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1457032178
Short name T144
Test name
Test status
Simulation time 29889949546 ps
CPU time 12.61 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:46:06 PM PST 23
Peak memory 182764 kb
Host smart-8378b8ef-ce9b-406f-bd99-e2ba46267b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457032178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1457032178
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3273642509
Short name T173
Test name
Test status
Simulation time 363464741 ps
CPU time 0.7 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:45:57 PM PST 23
Peak memory 182592 kb
Host smart-286916ed-053c-4472-bc6e-eb3bb859e992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273642509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3273642509
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1712622754
Short name T101
Test name
Test status
Simulation time 122671707535 ps
CPU time 47.19 seconds
Started Dec 31 12:46:04 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 182640 kb
Host smart-27a48cd1-670b-4c17-890a-8fa249c6ac17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712622754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1712622754
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3485000036
Short name T184
Test name
Test status
Simulation time 446164243533 ps
CPU time 565.59 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:55:57 PM PST 23
Peak memory 198252 kb
Host smart-fc2dc893-587c-4ac0-ab64-a61a5eb015ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485000036 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3485000036
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2965931025
Short name T61
Test name
Test status
Simulation time 437778754 ps
CPU time 0.87 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:45:56 PM PST 23
Peak memory 182556 kb
Host smart-e392fd73-a837-4d85-b255-852b10e39c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965931025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2965931025
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1118725751
Short name T181
Test name
Test status
Simulation time 39964395903 ps
CPU time 62.41 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 182724 kb
Host smart-52910b67-e309-4b53-8521-18ecedb9e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118725751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1118725751
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.54880350
Short name T246
Test name
Test status
Simulation time 501770095 ps
CPU time 0.71 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 12:46:26 PM PST 23
Peak memory 182732 kb
Host smart-952aa4e8-ea7a-4390-97b0-8d2f3587ead7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54880350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.54880350
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3436682637
Short name T100
Test name
Test status
Simulation time 99894271885 ps
CPU time 140.92 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:48:42 PM PST 23
Peak memory 182712 kb
Host smart-c8fd6fc8-c9e7-4c4d-af3f-06c22dde4e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436682637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3436682637
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2690554995
Short name T298
Test name
Test status
Simulation time 206134918337 ps
CPU time 667.67 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:57:18 PM PST 23
Peak memory 207244 kb
Host smart-3177d250-110c-4c5d-85d3-cc1176ce92c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690554995 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2690554995
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1833768352
Short name T280
Test name
Test status
Simulation time 472652268 ps
CPU time 0.69 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 12:46:13 PM PST 23
Peak memory 182652 kb
Host smart-9201fb3f-d9d1-4dd3-97a0-f60f547a3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833768352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1833768352
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.122579242
Short name T251
Test name
Test status
Simulation time 23664049905 ps
CPU time 17.8 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182720 kb
Host smart-879b3ba8-28ac-41d6-9b2f-700ca7ad29ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122579242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.122579242
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1655499640
Short name T42
Test name
Test status
Simulation time 586179918 ps
CPU time 0.94 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182744 kb
Host smart-259e52c8-8446-4049-862a-fed7760fd6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655499640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1655499640
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1910050786
Short name T27
Test name
Test status
Simulation time 242090715071 ps
CPU time 88.96 seconds
Started Dec 31 12:46:09 PM PST 23
Finished Dec 31 12:47:40 PM PST 23
Peak memory 182804 kb
Host smart-ff01d099-dbc2-4a6f-bec9-fe741f8ac031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910050786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1910050786
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1018417071
Short name T254
Test name
Test status
Simulation time 260472039465 ps
CPU time 507.41 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:54:24 PM PST 23
Peak memory 197644 kb
Host smart-1ad37774-5035-4e80-8f34-8f119a86c042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018417071 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1018417071
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3762659492
Short name T166
Test name
Test status
Simulation time 375893684 ps
CPU time 1.15 seconds
Started Dec 31 12:45:33 PM PST 23
Finished Dec 31 12:45:35 PM PST 23
Peak memory 182596 kb
Host smart-801f0d29-bbad-4507-981d-2a6130a7a2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762659492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3762659492
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3791737081
Short name T178
Test name
Test status
Simulation time 61578161393 ps
CPU time 94.57 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:47:31 PM PST 23
Peak memory 182768 kb
Host smart-734dfac6-73c1-46ba-ba0f-e4081691baf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791737081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3791737081
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1759323307
Short name T186
Test name
Test status
Simulation time 545340606 ps
CPU time 0.91 seconds
Started Dec 31 12:45:53 PM PST 23
Finished Dec 31 12:45:54 PM PST 23
Peak memory 182568 kb
Host smart-835c7e6c-dc60-4a62-8dac-3294c223fc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759323307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1759323307
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3511750401
Short name T189
Test name
Test status
Simulation time 137279291552 ps
CPU time 14.31 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:45:45 PM PST 23
Peak memory 192728 kb
Host smart-804ded75-77fa-4b8c-a717-c640b02a384a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511750401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3511750401
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2499240155
Short name T25
Test name
Test status
Simulation time 28885526066 ps
CPU time 194.25 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:49:31 PM PST 23
Peak memory 197600 kb
Host smart-384339cb-327b-48bd-9b02-4f583c8eff4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499240155 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2499240155
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3385928332
Short name T299
Test name
Test status
Simulation time 362066376 ps
CPU time 1.1 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:11 PM PST 23
Peak memory 182620 kb
Host smart-75f9e667-0173-493f-9282-2289277974e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385928332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3385928332
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1814773441
Short name T219
Test name
Test status
Simulation time 3028777458 ps
CPU time 1.45 seconds
Started Dec 31 12:45:40 PM PST 23
Finished Dec 31 12:45:42 PM PST 23
Peak memory 182712 kb
Host smart-d9d2dc70-9e9d-4f53-b9d6-836a4df088d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814773441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1814773441
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1858334358
Short name T262
Test name
Test status
Simulation time 410437975 ps
CPU time 1.2 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:45:58 PM PST 23
Peak memory 182652 kb
Host smart-b211cf88-c2d1-4af3-a344-be4980178e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858334358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1858334358
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2650850707
Short name T241
Test name
Test status
Simulation time 213354525578 ps
CPU time 75.87 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 12:47:28 PM PST 23
Peak memory 182760 kb
Host smart-73e294cb-2f9a-4d58-8491-47bfd31b4d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650850707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2650850707
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1258316976
Short name T125
Test name
Test status
Simulation time 61277206834 ps
CPU time 338.86 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:51:57 PM PST 23
Peak memory 197568 kb
Host smart-251bceee-ba6c-424a-b8e0-da5a75d44cb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258316976 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1258316976
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1920269484
Short name T116
Test name
Test status
Simulation time 511486682 ps
CPU time 1.1 seconds
Started Dec 31 12:46:06 PM PST 23
Finished Dec 31 12:46:10 PM PST 23
Peak memory 182652 kb
Host smart-c5582bcc-1e62-4eeb-9ab4-fa91755ed844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920269484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1920269484
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2767198372
Short name T207
Test name
Test status
Simulation time 36262235178 ps
CPU time 15 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 182728 kb
Host smart-47b7e60b-fa6e-404a-9278-22a39686e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767198372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2767198372
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.521770072
Short name T22
Test name
Test status
Simulation time 372334234 ps
CPU time 0.65 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:21 PM PST 23
Peak memory 182552 kb
Host smart-77c42b41-579a-45b0-a52b-9ecc98aede2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521770072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.521770072
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1883840832
Short name T180
Test name
Test status
Simulation time 167155447885 ps
CPU time 249.69 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 12:50:35 PM PST 23
Peak memory 182692 kb
Host smart-aab9e40b-91be-444a-ab56-2493789b263a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883840832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1883840832
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1193836885
Short name T272
Test name
Test status
Simulation time 22660303184 ps
CPU time 233.15 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:49:43 PM PST 23
Peak memory 197616 kb
Host smart-36131079-ba79-4c76-844e-9003f4441191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193836885 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1193836885
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3819268498
Short name T167
Test name
Test status
Simulation time 603597579 ps
CPU time 0.69 seconds
Started Dec 31 12:45:23 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 182652 kb
Host smart-a2880976-309d-4ffc-81e8-48bd9df8201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819268498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3819268498
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.4127761921
Short name T39
Test name
Test status
Simulation time 41638292276 ps
CPU time 32.44 seconds
Started Dec 31 12:45:28 PM PST 23
Finished Dec 31 12:46:01 PM PST 23
Peak memory 182688 kb
Host smart-647c469c-0533-4802-88de-f7c43b7bcb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127761921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.4127761921
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.3785756668
Short name T33
Test name
Test status
Simulation time 4600462320 ps
CPU time 5.51 seconds
Started Dec 31 12:45:47 PM PST 23
Finished Dec 31 12:45:53 PM PST 23
Peak memory 214888 kb
Host smart-dbf853b3-80f6-42e7-a99e-5e0e16506128
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785756668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.3785756668
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.2663045948
Short name T159
Test name
Test status
Simulation time 358008718 ps
CPU time 1 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:45:50 PM PST 23
Peak memory 182648 kb
Host smart-4eacaa29-33b4-48ad-af07-5b6bae7ca13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663045948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.2663045948
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2855415745
Short name T279
Test name
Test status
Simulation time 14782812056 ps
CPU time 93.42 seconds
Started Dec 31 12:45:53 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 197576 kb
Host smart-00da86a9-312e-4d01-9b48-72ef410a1bc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855415745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2855415745
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2092235159
Short name T23
Test name
Test status
Simulation time 473455292 ps
CPU time 0.89 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:45:56 PM PST 23
Peak memory 182700 kb
Host smart-f2cc73ad-4953-418c-ade2-3dc5ce4d1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092235159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2092235159
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1104812701
Short name T141
Test name
Test status
Simulation time 2481587204 ps
CPU time 1.49 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:09 PM PST 23
Peak memory 182712 kb
Host smart-222749db-c5ae-4c88-a6f0-2b4edfdf9aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104812701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1104812701
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4273258254
Short name T281
Test name
Test status
Simulation time 590768171 ps
CPU time 0.73 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:46:25 PM PST 23
Peak memory 182524 kb
Host smart-0e36823d-b996-4e64-be62-84c7944c7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273258254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4273258254
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1906391495
Short name T31
Test name
Test status
Simulation time 124440074792 ps
CPU time 260.76 seconds
Started Dec 31 12:46:21 PM PST 23
Finished Dec 31 12:50:44 PM PST 23
Peak memory 197588 kb
Host smart-f2a94f30-a54c-4b4f-a867-cf5a2c268608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906391495 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1906391495
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.207595707
Short name T206
Test name
Test status
Simulation time 387924512 ps
CPU time 1.1 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182644 kb
Host smart-416d457d-7c5d-4d7b-b2da-ce37de0e0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207595707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.207595707
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.951652929
Short name T162
Test name
Test status
Simulation time 16020501334 ps
CPU time 6.04 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 182728 kb
Host smart-463cc394-340b-4c1c-bebb-1c3bd8ad177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951652929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.951652929
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.725358762
Short name T152
Test name
Test status
Simulation time 514543778 ps
CPU time 1.17 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:46:36 PM PST 23
Peak memory 182524 kb
Host smart-bbf11368-82e7-449b-ac0d-c785ea13b0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725358762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.725358762
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3149920211
Short name T121
Test name
Test status
Simulation time 284469075797 ps
CPU time 229.09 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:49:58 PM PST 23
Peak memory 182828 kb
Host smart-a336f52f-e848-4a7e-a61f-9c0fd92b4e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149920211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3149920211
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.949749133
Short name T273
Test name
Test status
Simulation time 352890605566 ps
CPU time 484.08 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:54:00 PM PST 23
Peak memory 197620 kb
Host smart-f6a56c5d-6c13-4e71-8d40-c4a586753e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949749133 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.949749133
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3769563838
Short name T293
Test name
Test status
Simulation time 455296245 ps
CPU time 0.88 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:04 PM PST 23
Peak memory 182584 kb
Host smart-8d1ef4c5-2e1b-4942-8a93-d0931a0ea5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769563838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3769563838
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1923849422
Short name T64
Test name
Test status
Simulation time 2092440974 ps
CPU time 1.25 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:46:16 PM PST 23
Peak memory 182472 kb
Host smart-02db0a60-0ec2-440d-b768-2b924f623c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923849422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1923849422
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1313878888
Short name T230
Test name
Test status
Simulation time 573738172 ps
CPU time 1.36 seconds
Started Dec 31 12:45:51 PM PST 23
Finished Dec 31 12:45:53 PM PST 23
Peak memory 182532 kb
Host smart-0087d46d-9e98-4930-a827-35befca97fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313878888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1313878888
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3053698948
Short name T278
Test name
Test status
Simulation time 98250685253 ps
CPU time 38.72 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 193012 kb
Host smart-6dfc7522-0e6b-4bbd-93f4-96a7fa9a61de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053698948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3053698948
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2127295147
Short name T66
Test name
Test status
Simulation time 1129764911187 ps
CPU time 337.61 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:51:50 PM PST 23
Peak memory 197712 kb
Host smart-e6c6dbd3-f11e-4276-bec7-02f7fff25215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127295147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2127295147
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.253876668
Short name T244
Test name
Test status
Simulation time 518765377 ps
CPU time 1.35 seconds
Started Dec 31 12:46:36 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 182608 kb
Host smart-28f033f7-49dd-45b6-8e3f-c11e0f040739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253876668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.253876668
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1106854632
Short name T208
Test name
Test status
Simulation time 43390807131 ps
CPU time 15.2 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 182772 kb
Host smart-85a66678-f888-40ac-bba8-08aa950db2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106854632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1106854632
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2902093175
Short name T151
Test name
Test status
Simulation time 384061209 ps
CPU time 1.09 seconds
Started Dec 31 12:46:03 PM PST 23
Finished Dec 31 12:46:05 PM PST 23
Peak memory 182512 kb
Host smart-d8304229-28db-48aa-8037-5a53ba9104af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902093175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2902093175
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2112877350
Short name T51
Test name
Test status
Simulation time 49606459472 ps
CPU time 534.6 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 197536 kb
Host smart-c4cafd66-2c92-4f29-9115-de062b710b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112877350 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2112877350
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3082040401
Short name T297
Test name
Test status
Simulation time 470521249 ps
CPU time 1.33 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182580 kb
Host smart-25a325f5-c40f-493e-b1f3-74e114567295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082040401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3082040401
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.941553255
Short name T150
Test name
Test status
Simulation time 36006552315 ps
CPU time 14.68 seconds
Started Dec 31 12:46:03 PM PST 23
Finished Dec 31 12:46:19 PM PST 23
Peak memory 182672 kb
Host smart-a3a4a8b5-288c-48e8-99af-6bfe82cc98fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941553255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.941553255
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3403729440
Short name T156
Test name
Test status
Simulation time 579388029 ps
CPU time 0.59 seconds
Started Dec 31 12:45:59 PM PST 23
Finished Dec 31 12:46:01 PM PST 23
Peak memory 182656 kb
Host smart-b29ece61-db48-4c82-9610-5463f92ad0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403729440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3403729440
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2303797128
Short name T307
Test name
Test status
Simulation time 137651539105 ps
CPU time 51.27 seconds
Started Dec 31 12:45:59 PM PST 23
Finished Dec 31 12:46:51 PM PST 23
Peak memory 193064 kb
Host smart-a24e322b-7807-4c4b-bd33-8e4d16f61145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303797128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2303797128
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3876295993
Short name T123
Test name
Test status
Simulation time 208082516043 ps
CPU time 819.27 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:59:54 PM PST 23
Peak memory 201392 kb
Host smart-0186f485-5550-4864-b24d-3b9379571f07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876295993 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3876295993
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1445016978
Short name T163
Test name
Test status
Simulation time 430527993 ps
CPU time 0.87 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 182648 kb
Host smart-e4635eac-8c83-4578-825f-d5904800ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445016978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1445016978
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1014307310
Short name T289
Test name
Test status
Simulation time 12684365437 ps
CPU time 17.55 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182724 kb
Host smart-ae90dc9c-c64e-409f-a1ba-a806ac0ab15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014307310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1014307310
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1003865236
Short name T253
Test name
Test status
Simulation time 525459737 ps
CPU time 1.08 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:28 PM PST 23
Peak memory 182512 kb
Host smart-da9536a4-a89f-4c2b-a310-e20938fa1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003865236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1003865236
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.28331519
Short name T277
Test name
Test status
Simulation time 117732242428 ps
CPU time 67.78 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:47:27 PM PST 23
Peak memory 182776 kb
Host smart-157fe121-b5a8-4708-8a02-3098d3e47c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28331519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_al
l.28331519
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.1933894515
Short name T235
Test name
Test status
Simulation time 946202690553 ps
CPU time 640.91 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:57:00 PM PST 23
Peak memory 198672 kb
Host smart-2fc34fb6-010e-4c65-9d87-075c12810961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933894515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.1933894515
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2731483785
Short name T104
Test name
Test status
Simulation time 462144630 ps
CPU time 0.93 seconds
Started Dec 31 12:46:04 PM PST 23
Finished Dec 31 12:46:06 PM PST 23
Peak memory 182648 kb
Host smart-fda36400-a36c-4a91-b000-a5b68c475c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731483785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2731483785
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.189471499
Short name T195
Test name
Test status
Simulation time 57550696284 ps
CPU time 85.68 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182736 kb
Host smart-f5c58b5e-0ca7-42d0-b94e-4905d25771ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189471499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.189471499
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3374637878
Short name T149
Test name
Test status
Simulation time 526247991 ps
CPU time 0.71 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:46:15 PM PST 23
Peak memory 182484 kb
Host smart-9207f488-20cb-49dc-a001-995634333cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374637878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3374637878
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2048535360
Short name T276
Test name
Test status
Simulation time 409066088071 ps
CPU time 718.29 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:58:16 PM PST 23
Peak memory 193820 kb
Host smart-05c4be83-dc7b-47dd-88e8-4c191ace50e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048535360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2048535360
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2203116922
Short name T124
Test name
Test status
Simulation time 102370290908 ps
CPU time 215.29 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 197612 kb
Host smart-334866a4-6c28-4dd5-884c-30c9e3dce54f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203116922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2203116922
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.288095536
Short name T191
Test name
Test status
Simulation time 617426122 ps
CPU time 0.98 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182644 kb
Host smart-d40c7612-1242-4bc4-a7ed-0a3ea17822cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288095536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.288095536
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3303697445
Short name T233
Test name
Test status
Simulation time 12728809755 ps
CPU time 19.7 seconds
Started Dec 31 12:46:01 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 182684 kb
Host smart-5126960b-24e4-44ae-9b94-a96e62017ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303697445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3303697445
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1800712067
Short name T158
Test name
Test status
Simulation time 399112966 ps
CPU time 0.67 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182472 kb
Host smart-12c200ca-d92d-41ff-99e9-ee7d83ace3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800712067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1800712067
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.4195506733
Short name T102
Test name
Test status
Simulation time 328344751271 ps
CPU time 503.98 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:54:39 PM PST 23
Peak memory 182720 kb
Host smart-7143d9f0-81b3-4e67-bab7-31d7237ecbde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195506733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.4195506733
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1215957630
Short name T46
Test name
Test status
Simulation time 253948354118 ps
CPU time 346.55 seconds
Started Dec 31 12:45:47 PM PST 23
Finished Dec 31 12:51:34 PM PST 23
Peak memory 197596 kb
Host smart-ea44521a-cae4-43c2-999c-5cb0e46621cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215957630 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1215957630
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.324595369
Short name T115
Test name
Test status
Simulation time 446894146 ps
CPU time 1.2 seconds
Started Dec 31 12:45:50 PM PST 23
Finished Dec 31 12:45:52 PM PST 23
Peak memory 182700 kb
Host smart-569e967f-c8f4-42eb-9726-f8471e70b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324595369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.324595369
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3951607322
Short name T62
Test name
Test status
Simulation time 15672403609 ps
CPU time 6.52 seconds
Started Dec 31 12:45:45 PM PST 23
Finished Dec 31 12:45:52 PM PST 23
Peak memory 182736 kb
Host smart-dcbd1744-f637-4baa-bad1-9af77a2f5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951607322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3951607322
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1854682511
Short name T165
Test name
Test status
Simulation time 556739687 ps
CPU time 1.01 seconds
Started Dec 31 12:45:51 PM PST 23
Finished Dec 31 12:45:58 PM PST 23
Peak memory 182600 kb
Host smart-6150bc79-b789-4b56-a658-a2d40d0f3bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854682511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1854682511
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2479804799
Short name T41
Test name
Test status
Simulation time 180054823221 ps
CPU time 204.02 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:50:00 PM PST 23
Peak memory 193888 kb
Host smart-90d4b2de-3444-47e9-865e-3712ca74f01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479804799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2479804799
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.242265406
Short name T40
Test name
Test status
Simulation time 15227922179 ps
CPU time 101.3 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:48:11 PM PST 23
Peak memory 197724 kb
Host smart-5e28cdb9-1785-40da-985b-b17d4e30bfcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242265406 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.242265406
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4138975531
Short name T258
Test name
Test status
Simulation time 458958412 ps
CPU time 0.7 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:46:19 PM PST 23
Peak memory 182696 kb
Host smart-30bf7ba1-acb9-457b-9ddd-f76aa0c1cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138975531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4138975531
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2587207739
Short name T194
Test name
Test status
Simulation time 2743026642 ps
CPU time 2.61 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:46:09 PM PST 23
Peak memory 182684 kb
Host smart-896f8f37-27d9-4e18-9d39-58a4fefd6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587207739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2587207739
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3952862577
Short name T187
Test name
Test status
Simulation time 515953088 ps
CPU time 1.41 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:45:57 PM PST 23
Peak memory 182560 kb
Host smart-4609166f-8cfd-41e3-90dd-b06700d84ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952862577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3952862577
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1245344929
Short name T249
Test name
Test status
Simulation time 58754125862 ps
CPU time 116.36 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:48:12 PM PST 23
Peak memory 197588 kb
Host smart-a03dbf8d-3659-4c15-84fc-238599705087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245344929 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1245344929
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2967804601
Short name T103
Test name
Test status
Simulation time 403393257 ps
CPU time 0.74 seconds
Started Dec 31 12:45:31 PM PST 23
Finished Dec 31 12:45:33 PM PST 23
Peak memory 182712 kb
Host smart-ed300dc6-32cc-429e-b14e-a7ee565414d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967804601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2967804601
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1234842044
Short name T242
Test name
Test status
Simulation time 24555370809 ps
CPU time 9.7 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182740 kb
Host smart-8ef2699d-fb58-49fa-8eb4-31fe034edbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234842044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1234842044
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1336331109
Short name T32
Test name
Test status
Simulation time 4065664469 ps
CPU time 1.4 seconds
Started Dec 31 12:45:50 PM PST 23
Finished Dec 31 12:45:52 PM PST 23
Peak memory 214592 kb
Host smart-8f29b1ff-249e-45b0-9341-28ef0c4b6bbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336331109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1336331109
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2409339134
Short name T286
Test name
Test status
Simulation time 410661961 ps
CPU time 0.81 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182640 kb
Host smart-d0f9ebf9-5050-4f86-bb5c-19507cb4c88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409339134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2409339134
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3482244379
Short name T174
Test name
Test status
Simulation time 261282186229 ps
CPU time 109.45 seconds
Started Dec 31 12:45:58 PM PST 23
Finished Dec 31 12:47:48 PM PST 23
Peak memory 182752 kb
Host smart-e42280eb-578d-4c1a-ab4c-48d4c4b0ffd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482244379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3482244379
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1244914480
Short name T228
Test name
Test status
Simulation time 325675412883 ps
CPU time 273.74 seconds
Started Dec 31 12:45:33 PM PST 23
Finished Dec 31 12:50:07 PM PST 23
Peak memory 197556 kb
Host smart-f94ea724-e883-4117-a8e6-6fc685b45d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244914480 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1244914480
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1462882760
Short name T282
Test name
Test status
Simulation time 531323955 ps
CPU time 1.34 seconds
Started Dec 31 12:46:10 PM PST 23
Finished Dec 31 12:46:13 PM PST 23
Peak memory 182700 kb
Host smart-178fa8b1-1480-44ec-8d39-5ea9e7f4b877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462882760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1462882760
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3268516712
Short name T153
Test name
Test status
Simulation time 3569653929 ps
CPU time 5.48 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:46:03 PM PST 23
Peak memory 182664 kb
Host smart-b0a0abac-7841-446d-b94d-0ee727163cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268516712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3268516712
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.897096135
Short name T44
Test name
Test status
Simulation time 537226756 ps
CPU time 0.89 seconds
Started Dec 31 12:45:47 PM PST 23
Finished Dec 31 12:45:48 PM PST 23
Peak memory 182636 kb
Host smart-86853100-d2d8-46b7-b63d-097b61b0d20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897096135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.897096135
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.4280096057
Short name T199
Test name
Test status
Simulation time 484554897214 ps
CPU time 843.77 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 01:00:01 PM PST 23
Peak memory 182792 kb
Host smart-6d301134-44e6-46ed-b049-d951965b83ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280096057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.4280096057
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3393390495
Short name T285
Test name
Test status
Simulation time 17788274134 ps
CPU time 139.1 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:48:49 PM PST 23
Peak memory 197616 kb
Host smart-1b3b3fcf-919a-45a3-b8f0-0e3f945969ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393390495 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3393390495
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3653116919
Short name T266
Test name
Test status
Simulation time 482380396 ps
CPU time 0.95 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:29 PM PST 23
Peak memory 182652 kb
Host smart-4932233c-1b80-46ca-826b-ac1a9061c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653116919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3653116919
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.582851880
Short name T143
Test name
Test status
Simulation time 20306182660 ps
CPU time 7.89 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 182672 kb
Host smart-9d5e093d-de60-42bf-8e3e-17cdcce15604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582851880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.582851880
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2140348671
Short name T247
Test name
Test status
Simulation time 420617855 ps
CPU time 0.64 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:21 PM PST 23
Peak memory 182596 kb
Host smart-043bed1f-3b4b-4d0e-a9da-418575e183f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140348671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2140348671
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2559009584
Short name T28
Test name
Test status
Simulation time 40373330490 ps
CPU time 58.48 seconds
Started Dec 31 12:45:59 PM PST 23
Finished Dec 31 12:46:58 PM PST 23
Peak memory 193016 kb
Host smart-bd985620-89ea-48a0-a4f7-a7866e875a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559009584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2559009584
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.369606886
Short name T131
Test name
Test status
Simulation time 38788461185 ps
CPU time 405.11 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:53:27 PM PST 23
Peak memory 197592 kb
Host smart-a1120ac6-e99c-4ddd-ac08-ebc40b6e3754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369606886 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.369606886
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.1438131534
Short name T269
Test name
Test status
Simulation time 543942649 ps
CPU time 0.96 seconds
Started Dec 31 12:46:20 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 182652 kb
Host smart-6e3876b3-a4f7-4b91-baa7-d173fc3cf314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438131534 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.1438131534
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2466605577
Short name T193
Test name
Test status
Simulation time 17262981195 ps
CPU time 14.31 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 182752 kb
Host smart-a65c7bc9-3ff5-4531-9291-e5611256bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466605577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2466605577
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.649432346
Short name T234
Test name
Test status
Simulation time 557693982 ps
CPU time 1.4 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:12 PM PST 23
Peak memory 182672 kb
Host smart-dfa2e783-9002-4769-b00b-7fb614f5ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649432346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.649432346
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2589574297
Short name T274
Test name
Test status
Simulation time 141100755000 ps
CPU time 219.54 seconds
Started Dec 31 12:46:17 PM PST 23
Finished Dec 31 12:49:58 PM PST 23
Peak memory 182780 kb
Host smart-d1d6e379-0422-49b5-abe8-6b5db913f0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589574297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2589574297
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3476318303
Short name T117
Test name
Test status
Simulation time 59726868145 ps
CPU time 463.42 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:54:24 PM PST 23
Peak memory 197592 kb
Host smart-b9ab87eb-20bb-4a72-8164-a58dde9034b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476318303 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3476318303
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2847420812
Short name T170
Test name
Test status
Simulation time 342035558 ps
CPU time 1.07 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:31 PM PST 23
Peak memory 182624 kb
Host smart-0790ebbd-dde1-44f6-abc6-59d7802bba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847420812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2847420812
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.59416863
Short name T220
Test name
Test status
Simulation time 819841273 ps
CPU time 1 seconds
Started Dec 31 12:46:42 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 182640 kb
Host smart-48a352d0-b37c-4415-9813-38c17d5bb684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59416863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.59416863
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.821386426
Short name T257
Test name
Test status
Simulation time 386272452 ps
CPU time 1.12 seconds
Started Dec 31 12:46:13 PM PST 23
Finished Dec 31 12:46:16 PM PST 23
Peak memory 182640 kb
Host smart-046f2a5e-5448-438c-86a3-22533ae2f763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821386426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.821386426
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1948036668
Short name T139
Test name
Test status
Simulation time 115123240122 ps
CPU time 44.96 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:55 PM PST 23
Peak memory 193044 kb
Host smart-668271d0-3dc3-4c31-9aea-c0aff7adcd13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948036668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1948036668
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.489055030
Short name T140
Test name
Test status
Simulation time 87922035686 ps
CPU time 180.32 seconds
Started Dec 31 12:46:31 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 197620 kb
Host smart-01f665b7-a5e2-4909-96b8-88da83692cdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489055030 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.489055030
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3055779783
Short name T161
Test name
Test status
Simulation time 499167452 ps
CPU time 1.34 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182660 kb
Host smart-341149ec-d766-4fa2-bf21-078452590de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055779783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3055779783
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.81599055
Short name T192
Test name
Test status
Simulation time 8955237447 ps
CPU time 3.23 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:45 PM PST 23
Peak memory 182696 kb
Host smart-07d2fbe9-2d17-4fa3-bc5f-8634f14dc2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81599055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.81599055
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2369894022
Short name T213
Test name
Test status
Simulation time 462517304 ps
CPU time 0.98 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 182564 kb
Host smart-1a96c1c0-2c71-44a0-a802-c500ed6ced52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369894022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2369894022
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.268077145
Short name T252
Test name
Test status
Simulation time 108326517179 ps
CPU time 35.36 seconds
Started Dec 31 12:46:30 PM PST 23
Finished Dec 31 12:47:08 PM PST 23
Peak memory 182760 kb
Host smart-588ff1bd-a676-4ea0-8f3b-06960d55c5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268077145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.268077145
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3535251667
Short name T211
Test name
Test status
Simulation time 204806894692 ps
CPU time 536.32 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 197960 kb
Host smart-a00c793d-903c-4710-ad78-565a87203f47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535251667 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3535251667
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1891914742
Short name T106
Test name
Test status
Simulation time 509898394 ps
CPU time 0.91 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 182712 kb
Host smart-76ef3be7-0d9a-4425-afa4-e555b762d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891914742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1891914742
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3234255946
Short name T284
Test name
Test status
Simulation time 25438352398 ps
CPU time 25.53 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:53 PM PST 23
Peak memory 182676 kb
Host smart-d40f31b5-0c4a-4ed0-a1db-95248818b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234255946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3234255946
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.771320179
Short name T185
Test name
Test status
Simulation time 364558355 ps
CPU time 1.06 seconds
Started Dec 31 12:46:38 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 182512 kb
Host smart-0c63d945-0aa1-4bb1-bc52-34ea66d3536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771320179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.771320179
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.44095783
Short name T136
Test name
Test status
Simulation time 248322131319 ps
CPU time 391.29 seconds
Started Dec 31 12:46:41 PM PST 23
Finished Dec 31 12:53:15 PM PST 23
Peak memory 194096 kb
Host smart-7a004cd8-43c6-4727-afa9-bf2355023e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44095783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.44095783
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2373921392
Short name T287
Test name
Test status
Simulation time 444397625041 ps
CPU time 925.33 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 01:02:11 PM PST 23
Peak memory 202288 kb
Host smart-c9191c01-cc36-49cd-9916-8a52900745e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373921392 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2373921392
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3573074092
Short name T215
Test name
Test status
Simulation time 378804400 ps
CPU time 0.67 seconds
Started Dec 31 12:46:40 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 182612 kb
Host smart-ec080cd4-a5d4-48bc-84ab-b69bb5c791ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573074092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3573074092
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.388465331
Short name T188
Test name
Test status
Simulation time 42141826235 ps
CPU time 14.25 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:46 PM PST 23
Peak memory 182692 kb
Host smart-8e3ab670-123b-4db8-aed7-80c777b5a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388465331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.388465331
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2220849035
Short name T182
Test name
Test status
Simulation time 546660992 ps
CPU time 1.39 seconds
Started Dec 31 12:46:29 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 182540 kb
Host smart-82df019f-e5cd-4e7e-ad49-eb82e23e9041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220849035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2220849035
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.655832126
Short name T237
Test name
Test status
Simulation time 46650162017 ps
CPU time 33.81 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:47:22 PM PST 23
Peak memory 182752 kb
Host smart-f97d95a1-ff72-4b31-a47e-416c74fb5474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655832126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.655832126
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3010107314
Short name T222
Test name
Test status
Simulation time 53367780594 ps
CPU time 390.29 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:52:58 PM PST 23
Peak memory 197600 kb
Host smart-a4b9b097-1818-436b-b898-c1b93c7cdac5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010107314 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3010107314
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.660807149
Short name T226
Test name
Test status
Simulation time 389758993 ps
CPU time 0.68 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:46:43 PM PST 23
Peak memory 182736 kb
Host smart-ab0c7e61-a2aa-41d5-a850-5e2fe5070280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660807149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.660807149
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.394874434
Short name T26
Test name
Test status
Simulation time 17990161134 ps
CPU time 6.2 seconds
Started Dec 31 12:46:39 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 182732 kb
Host smart-2e625ae2-dc27-4cd4-b263-48e97adf93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394874434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.394874434
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.61254867
Short name T306
Test name
Test status
Simulation time 600454976 ps
CPU time 0.73 seconds
Started Dec 31 12:46:52 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 182592 kb
Host smart-54968e96-47dd-44ee-a0d8-5c957e717a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61254867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.61254867
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3368825808
Short name T294
Test name
Test status
Simulation time 202980525810 ps
CPU time 367.56 seconds
Started Dec 31 12:46:34 PM PST 23
Finished Dec 31 12:52:45 PM PST 23
Peak memory 197676 kb
Host smart-7abc1457-0c49-478e-a151-8b5be3bdf8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368825808 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3368825808
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.282528981
Short name T288
Test name
Test status
Simulation time 549423016 ps
CPU time 1.49 seconds
Started Dec 31 12:46:50 PM PST 23
Finished Dec 31 12:46:54 PM PST 23
Peak memory 182580 kb
Host smart-166e79ee-32b7-40f3-9707-e50a02d27953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282528981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.282528981
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1812871497
Short name T155
Test name
Test status
Simulation time 38579802382 ps
CPU time 15.15 seconds
Started Dec 31 12:46:47 PM PST 23
Finished Dec 31 12:47:04 PM PST 23
Peak memory 182808 kb
Host smart-06962506-eae7-4d62-8e68-1c2561012ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812871497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1812871497
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1739864929
Short name T224
Test name
Test status
Simulation time 398840899 ps
CPU time 1.28 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 182780 kb
Host smart-907ecdd7-fdc2-41a5-a160-7f127faf8c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739864929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1739864929
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1319369470
Short name T283
Test name
Test status
Simulation time 146989549630 ps
CPU time 124.56 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:48:51 PM PST 23
Peak memory 182760 kb
Host smart-2f04eebb-5edd-4804-bfac-47f782624de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319369470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1319369470
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1379491222
Short name T128
Test name
Test status
Simulation time 333473363728 ps
CPU time 803.97 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:59:45 PM PST 23
Peak memory 209856 kb
Host smart-2da1218e-912e-4acd-bd02-e99ce3116280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379491222 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1379491222
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1915328586
Short name T126
Test name
Test status
Simulation time 562543150 ps
CPU time 0.94 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182640 kb
Host smart-f81d3838-06a1-4583-95ca-95718ba8ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915328586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1915328586
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.537827041
Short name T296
Test name
Test status
Simulation time 1002224848 ps
CPU time 2 seconds
Started Dec 31 12:46:56 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 182552 kb
Host smart-bed646af-0509-4307-936f-fe8c9b64455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537827041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.537827041
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.4043947663
Short name T148
Test name
Test status
Simulation time 415901660 ps
CPU time 0.65 seconds
Started Dec 31 12:46:37 PM PST 23
Finished Dec 31 12:46:41 PM PST 23
Peak memory 182656 kb
Host smart-9ee8123c-aaec-4c09-8d68-a3b830a722af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043947663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.4043947663
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1890560840
Short name T214
Test name
Test status
Simulation time 4160777984 ps
CPU time 4.22 seconds
Started Dec 31 12:46:15 PM PST 23
Finished Dec 31 12:46:21 PM PST 23
Peak memory 192792 kb
Host smart-c0eb7bb4-6547-4669-b283-d349a830a393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890560840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1890560840
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1593769897
Short name T92
Test name
Test status
Simulation time 48404578085 ps
CPU time 295.98 seconds
Started Dec 31 12:45:58 PM PST 23
Finished Dec 31 12:50:56 PM PST 23
Peak memory 197628 kb
Host smart-053f614d-879c-472f-9d73-2324df70cd0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593769897 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1593769897
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3740910239
Short name T43
Test name
Test status
Simulation time 400279544 ps
CPU time 1.05 seconds
Started Dec 31 12:46:28 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 182736 kb
Host smart-620fdd74-529f-4bde-9bcb-e008fe1478e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740910239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3740910239
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.4293147741
Short name T183
Test name
Test status
Simulation time 16363246514 ps
CPU time 6.68 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:46:02 PM PST 23
Peak memory 182796 kb
Host smart-13fd9e0e-20a3-4d1a-9ecc-a4ce9deb5e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293147741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.4293147741
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1403056922
Short name T35
Test name
Test status
Simulation time 4204979429 ps
CPU time 2.33 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:45:33 PM PST 23
Peak memory 214548 kb
Host smart-e1aff1b5-14e0-4a34-90f2-4c396c2b3bea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403056922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1403056922
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.1977291269
Short name T197
Test name
Test status
Simulation time 588150832 ps
CPU time 1.5 seconds
Started Dec 31 12:45:43 PM PST 23
Finished Dec 31 12:45:50 PM PST 23
Peak memory 182656 kb
Host smart-859bc930-b0ee-49e7-977a-26d2a409e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977291269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.1977291269
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1302886417
Short name T245
Test name
Test status
Simulation time 194872998428 ps
CPU time 221.25 seconds
Started Dec 31 12:45:43 PM PST 23
Finished Dec 31 12:49:25 PM PST 23
Peak memory 194068 kb
Host smart-034b4a1c-36e3-4092-baa8-1874a9a8a461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302886417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1302886417
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1251141476
Short name T112
Test name
Test status
Simulation time 268969879873 ps
CPU time 687.95 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:56:58 PM PST 23
Peak memory 205804 kb
Host smart-8e4e7b08-3b91-4f11-b58f-28a9401d35fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251141476 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1251141476
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.103994171
Short name T267
Test name
Test status
Simulation time 392418818 ps
CPU time 0.66 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:46:19 PM PST 23
Peak memory 182664 kb
Host smart-345add10-eb4c-42bf-8ee4-bf63328968bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103994171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.103994171
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.399685499
Short name T145
Test name
Test status
Simulation time 22077647617 ps
CPU time 32.52 seconds
Started Dec 31 12:46:04 PM PST 23
Finished Dec 31 12:46:38 PM PST 23
Peak memory 182716 kb
Host smart-eabeeffb-b2fc-4be7-bf03-1c9bd2ef2376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399685499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.399685499
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1950366229
Short name T20
Test name
Test status
Simulation time 601772334 ps
CPU time 0.6 seconds
Started Dec 31 12:46:07 PM PST 23
Finished Dec 31 12:46:09 PM PST 23
Peak memory 182532 kb
Host smart-d7db70c5-e3b6-4c3f-b3c8-dd6b6e4265ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950366229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1950366229
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3970737120
Short name T268
Test name
Test status
Simulation time 141097344946 ps
CPU time 33.23 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:59 PM PST 23
Peak memory 192824 kb
Host smart-89603b7f-ad63-432a-a6db-071d94e64d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970737120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3970737120
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3927091262
Short name T216
Test name
Test status
Simulation time 52745892633 ps
CPU time 142.57 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:48:32 PM PST 23
Peak memory 197552 kb
Host smart-ff5a031e-fe25-4409-b7c7-9a33a508ac36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927091262 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3927091262
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3064212333
Short name T255
Test name
Test status
Simulation time 514293911 ps
CPU time 0.71 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:46:14 PM PST 23
Peak memory 182708 kb
Host smart-89d2c2af-9dbd-4c99-9fde-31f1a221b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064212333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3064212333
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.518958176
Short name T37
Test name
Test status
Simulation time 15969525953 ps
CPU time 12.34 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:34 PM PST 23
Peak memory 183012 kb
Host smart-841c11f3-8ec8-42f5-a3bc-8e15b45a3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518958176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.518958176
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3358621160
Short name T146
Test name
Test status
Simulation time 391074796 ps
CPU time 0.8 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182596 kb
Host smart-1338b296-21b3-437f-b428-4f26af8f452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358621160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3358621160
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3134172120
Short name T134
Test name
Test status
Simulation time 520055531010 ps
CPU time 193.04 seconds
Started Dec 31 12:46:22 PM PST 23
Finished Dec 31 12:49:42 PM PST 23
Peak memory 182712 kb
Host smart-bc31ff77-f9fe-4186-b920-f4a8ac5fc5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134172120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3134172120
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.84970940
Short name T67
Test name
Test status
Simulation time 117748226020 ps
CPU time 966.39 seconds
Started Dec 31 12:46:23 PM PST 23
Finished Dec 31 01:02:32 PM PST 23
Peak memory 203120 kb
Host smart-bc5eb268-188d-4e9f-8b5c-4d2221f675d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84970940 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.84970940
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.673818128
Short name T271
Test name
Test status
Simulation time 522828596 ps
CPU time 0.72 seconds
Started Dec 31 12:46:24 PM PST 23
Finished Dec 31 12:46:27 PM PST 23
Peak memory 182732 kb
Host smart-0e369b2a-91ba-4758-822c-2101cafe3987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673818128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.673818128
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3851539587
Short name T202
Test name
Test status
Simulation time 22931277795 ps
CPU time 37.01 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:40 PM PST 23
Peak memory 182740 kb
Host smart-08253254-dab4-41d2-a45f-4ea81c5704ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851539587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3851539587
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2513554678
Short name T29
Test name
Test status
Simulation time 505298910 ps
CPU time 0.86 seconds
Started Dec 31 12:46:05 PM PST 23
Finished Dec 31 12:46:07 PM PST 23
Peak memory 182528 kb
Host smart-d72497c0-52e3-49ff-8bf5-d576c3321d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513554678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2513554678
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3667981185
Short name T107
Test name
Test status
Simulation time 92239149611 ps
CPU time 700.67 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:57:54 PM PST 23
Peak memory 198804 kb
Host smart-1f5d8541-882f-4cb0-a122-5f25d87c8302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667981185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3667981185
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3332442894
Short name T304
Test name
Test status
Simulation time 487689257 ps
CPU time 0.74 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:46:14 PM PST 23
Peak memory 182700 kb
Host smart-5ec2abbb-83c9-44f0-aee6-65afefa7a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332442894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3332442894
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2165417707
Short name T172
Test name
Test status
Simulation time 59620005099 ps
CPU time 11.51 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182780 kb
Host smart-03677937-a837-47d8-9ade-998702224edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165417707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2165417707
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3856648368
Short name T160
Test name
Test status
Simulation time 560946029 ps
CPU time 0.95 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:22 PM PST 23
Peak memory 182592 kb
Host smart-d18a9d9f-8e27-4c0e-93f9-7999fbe7e513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856648368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3856648368
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2691460919
Short name T118
Test name
Test status
Simulation time 11852643755 ps
CPU time 8.79 seconds
Started Dec 31 12:45:58 PM PST 23
Finished Dec 31 12:46:08 PM PST 23
Peak memory 182700 kb
Host smart-9777d96f-ad30-4ac7-9abc-2d5c5b26aae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691460919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2691460919
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.181565310
Short name T93
Test name
Test status
Simulation time 87365902329 ps
CPU time 645.55 seconds
Started Dec 31 12:45:52 PM PST 23
Finished Dec 31 12:56:38 PM PST 23
Peak memory 198556 kb
Host smart-b7fd7526-0fa1-4e13-9a4b-5acafb6b27b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181565310 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.181565310
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2631548065
Short name T204
Test name
Test status
Simulation time 552210418 ps
CPU time 1.51 seconds
Started Dec 31 12:45:56 PM PST 23
Finished Dec 31 12:45:59 PM PST 23
Peak memory 182660 kb
Host smart-91adc20f-ea92-4da1-ae93-72d1894341a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631548065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2631548065
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.920918027
Short name T175
Test name
Test status
Simulation time 27455632710 ps
CPU time 3.83 seconds
Started Dec 31 12:46:35 PM PST 23
Finished Dec 31 12:46:42 PM PST 23
Peak memory 182764 kb
Host smart-f2ac5e3e-0d64-4ee1-9ba7-cbd866fc1535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920918027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.920918027
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3598842393
Short name T302
Test name
Test status
Simulation time 551471650 ps
CPU time 0.74 seconds
Started Dec 31 12:46:25 PM PST 23
Finished Dec 31 12:46:27 PM PST 23
Peak memory 182592 kb
Host smart-827d0572-13c3-445f-a029-19a8e09202a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598842393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3598842393
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2850952493
Short name T225
Test name
Test status
Simulation time 223457424048 ps
CPU time 159.12 seconds
Started Dec 31 12:46:07 PM PST 23
Finished Dec 31 12:48:47 PM PST 23
Peak memory 182756 kb
Host smart-110df94b-f043-4ae4-a2eb-795d286c5099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850952493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2850952493
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1228983268
Short name T198
Test name
Test status
Simulation time 382807000 ps
CPU time 1.13 seconds
Started Dec 31 12:45:55 PM PST 23
Finished Dec 31 12:45:57 PM PST 23
Peak memory 182640 kb
Host smart-fd12ffce-ae40-4aae-8cc1-d1584ec8c48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228983268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1228983268
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2860335361
Short name T270
Test name
Test status
Simulation time 21118345749 ps
CPU time 8.26 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:18 PM PST 23
Peak memory 182732 kb
Host smart-35587677-ee26-43b5-98d2-f2045053bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860335361 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2860335361
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1938410759
Short name T260
Test name
Test status
Simulation time 544054181 ps
CPU time 1.36 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:45:57 PM PST 23
Peak memory 182536 kb
Host smart-c5d2a6f2-cd42-49ae-9b93-821c6d238664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938410759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1938410759
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2587130542
Short name T120
Test name
Test status
Simulation time 257821651528 ps
CPU time 428.8 seconds
Started Dec 31 12:45:57 PM PST 23
Finished Dec 31 12:53:07 PM PST 23
Peak memory 182744 kb
Host smart-f6b123e3-c78c-4341-a5d0-5d24aecbdb25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587130542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2587130542
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2554427761
Short name T305
Test name
Test status
Simulation time 573505166 ps
CPU time 0.77 seconds
Started Dec 31 12:46:09 PM PST 23
Finished Dec 31 12:46:12 PM PST 23
Peak memory 182640 kb
Host smart-7657a336-4d4a-4e02-b8d0-8b3d9bfe0caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554427761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2554427761
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1170466254
Short name T217
Test name
Test status
Simulation time 42975739325 ps
CPU time 9.87 seconds
Started Dec 31 12:46:12 PM PST 23
Finished Dec 31 12:46:24 PM PST 23
Peak memory 182684 kb
Host smart-2b097461-93ca-4719-89e4-069a695b00c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170466254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1170466254
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2393936300
Short name T47
Test name
Test status
Simulation time 534299088 ps
CPU time 1.07 seconds
Started Dec 31 12:45:46 PM PST 23
Finished Dec 31 12:45:48 PM PST 23
Peak memory 182456 kb
Host smart-af7ecb39-98d0-495e-b79b-9ddad179af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393936300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2393936300
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.7811579
Short name T310
Test name
Test status
Simulation time 31463560470 ps
CPU time 9.66 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 182756 kb
Host smart-580f8ed6-4323-4963-87a2-204f42088297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7811579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all.7811579
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1818705158
Short name T63
Test name
Test status
Simulation time 569993618 ps
CPU time 1.35 seconds
Started Dec 31 12:46:19 PM PST 23
Finished Dec 31 12:46:23 PM PST 23
Peak memory 182696 kb
Host smart-3e3c6544-6932-4f31-9aa2-92b716575126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818705158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1818705158
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3825636509
Short name T196
Test name
Test status
Simulation time 23031941385 ps
CPU time 29.9 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:33 PM PST 23
Peak memory 182740 kb
Host smart-1b195b68-c848-4179-9189-6e25fe3ed11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825636509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3825636509
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3772403379
Short name T291
Test name
Test status
Simulation time 348601933 ps
CPU time 1.05 seconds
Started Dec 31 12:46:06 PM PST 23
Finished Dec 31 12:46:08 PM PST 23
Peak memory 182588 kb
Host smart-7ec079c2-e921-40b1-a289-fd7acd762fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772403379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3772403379
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1218755025
Short name T209
Test name
Test status
Simulation time 155521429849 ps
CPU time 65.95 seconds
Started Dec 31 12:46:09 PM PST 23
Finished Dec 31 12:47:17 PM PST 23
Peak memory 192960 kb
Host smart-d8950568-7bc1-4e76-94f6-93de891435ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218755025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1218755025
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1438949810
Short name T290
Test name
Test status
Simulation time 53241655899 ps
CPU time 283.79 seconds
Started Dec 31 12:46:11 PM PST 23
Finished Dec 31 12:50:57 PM PST 23
Peak memory 197672 kb
Host smart-0fd10ac0-2f18-46a2-beb8-028b5028fbe6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438949810 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1438949810
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3050782207
Short name T24
Test name
Test status
Simulation time 362924156 ps
CPU time 1 seconds
Started Dec 31 12:45:51 PM PST 23
Finished Dec 31 12:45:52 PM PST 23
Peak memory 182636 kb
Host smart-e03b758d-ff80-434f-84e4-38809b6885ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050782207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3050782207
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4062692720
Short name T142
Test name
Test status
Simulation time 19060231890 ps
CPU time 14.96 seconds
Started Dec 31 12:45:51 PM PST 23
Finished Dec 31 12:46:13 PM PST 23
Peak memory 182696 kb
Host smart-fb430c98-0177-4230-9909-634aca2420cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062692720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4062692720
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1621033864
Short name T164
Test name
Test status
Simulation time 567968084 ps
CPU time 0.72 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 182540 kb
Host smart-118df5fa-a9b6-45d5-9ad6-20005ed11c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621033864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1621033864
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3685956051
Short name T179
Test name
Test status
Simulation time 330496780725 ps
CPU time 115.5 seconds
Started Dec 31 12:46:18 PM PST 23
Finished Dec 31 12:48:16 PM PST 23
Peak memory 192820 kb
Host smart-1dca75f3-a1c7-4c8e-93a8-26d5a06de763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685956051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3685956051
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3017445914
Short name T227
Test name
Test status
Simulation time 68067271352 ps
CPU time 189.17 seconds
Started Dec 31 12:45:47 PM PST 23
Finished Dec 31 12:48:57 PM PST 23
Peak memory 197876 kb
Host smart-fab62b19-6705-424a-b240-b626f731ddf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017445914 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3017445914
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1360647226
Short name T105
Test name
Test status
Simulation time 356269341 ps
CPU time 0.72 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:45:51 PM PST 23
Peak memory 182624 kb
Host smart-55d04a8f-d78f-4093-bb71-05020d3d46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360647226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1360647226
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2284170583
Short name T169
Test name
Test status
Simulation time 7703567629 ps
CPU time 12.3 seconds
Started Dec 31 12:45:59 PM PST 23
Finished Dec 31 12:46:12 PM PST 23
Peak memory 182736 kb
Host smart-d72e697f-6d54-4482-9a71-aeb4aa1fd456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284170583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2284170583
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1979180794
Short name T240
Test name
Test status
Simulation time 369752943 ps
CPU time 0.66 seconds
Started Dec 31 12:45:53 PM PST 23
Finished Dec 31 12:45:55 PM PST 23
Peak memory 182700 kb
Host smart-52363e79-5ae2-4855-9195-afadebf8a283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979180794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1979180794
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2712428325
Short name T265
Test name
Test status
Simulation time 154787356224 ps
CPU time 68.82 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:46:58 PM PST 23
Peak memory 182716 kb
Host smart-482cca1f-3581-4cd7-bb6d-b3a6f76dece7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712428325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2712428325
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3264236246
Short name T127
Test name
Test status
Simulation time 482174014 ps
CPU time 1.22 seconds
Started Dec 31 12:45:23 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 182644 kb
Host smart-de5f8e72-5b94-4c9f-8db0-eaba44273183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264236246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3264236246
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.4236485928
Short name T303
Test name
Test status
Simulation time 58101440720 ps
CPU time 44.17 seconds
Started Dec 31 12:45:35 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 182740 kb
Host smart-45d0041d-d79f-4463-a9ee-56f102544850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236485928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.4236485928
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.26306728
Short name T154
Test name
Test status
Simulation time 543693646 ps
CPU time 1.31 seconds
Started Dec 31 12:45:50 PM PST 23
Finished Dec 31 12:45:53 PM PST 23
Peak memory 182692 kb
Host smart-4ee9156e-24b3-4155-b598-c8dd809049df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26306728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.26306728
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.4082950153
Short name T108
Test name
Test status
Simulation time 302407829630 ps
CPU time 110.62 seconds
Started Dec 31 12:46:03 PM PST 23
Finished Dec 31 12:47:55 PM PST 23
Peak memory 192636 kb
Host smart-6c39505e-3c89-4df1-b9cb-54f579776921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082950153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.4082950153
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3174328894
Short name T38
Test name
Test status
Simulation time 60364360181 ps
CPU time 602.41 seconds
Started Dec 31 12:45:29 PM PST 23
Finished Dec 31 12:55:33 PM PST 23
Peak memory 197648 kb
Host smart-103de202-a5e5-4c9a-a190-71441eae980a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174328894 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3174328894
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1179105731
Short name T130
Test name
Test status
Simulation time 542102265 ps
CPU time 0.73 seconds
Started Dec 31 12:45:49 PM PST 23
Finished Dec 31 12:45:51 PM PST 23
Peak memory 182664 kb
Host smart-a2f3c89d-b7d1-4fdf-afd4-5e6abfd7a5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179105731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1179105731
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3168264128
Short name T256
Test name
Test status
Simulation time 2564062328 ps
CPU time 2.38 seconds
Started Dec 31 12:45:37 PM PST 23
Finished Dec 31 12:45:40 PM PST 23
Peak memory 182676 kb
Host smart-ced2aa5f-7aec-4f54-89b7-36dcded3e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168264128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3168264128
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1337372122
Short name T292
Test name
Test status
Simulation time 507653741 ps
CPU time 0.86 seconds
Started Dec 31 12:45:54 PM PST 23
Finished Dec 31 12:45:56 PM PST 23
Peak memory 182592 kb
Host smart-6a088843-16d2-42e4-86ea-fee6579bde83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337372122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1337372122
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1102618212
Short name T248
Test name
Test status
Simulation time 65468502762 ps
CPU time 101.98 seconds
Started Dec 31 12:45:30 PM PST 23
Finished Dec 31 12:47:13 PM PST 23
Peak memory 182808 kb
Host smart-b5ea2b88-e0ac-4ecb-94bf-13d87cbaf65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102618212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1102618212
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3708576401
Short name T210
Test name
Test status
Simulation time 211406150195 ps
CPU time 587.36 seconds
Started Dec 31 12:45:26 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 198484 kb
Host smart-d06c9932-11f2-463b-a4a2-d21beaebe04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708576401 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3708576401
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3738754292
Short name T275
Test name
Test status
Simulation time 497794580 ps
CPU time 0.72 seconds
Started Dec 31 12:45:42 PM PST 23
Finished Dec 31 12:45:43 PM PST 23
Peak memory 182696 kb
Host smart-06ca01fa-8172-4d8d-a219-b7f134fd2173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738754292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3738754292
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1910691710
Short name T301
Test name
Test status
Simulation time 41457430942 ps
CPU time 8.93 seconds
Started Dec 31 12:45:37 PM PST 23
Finished Dec 31 12:45:47 PM PST 23
Peak memory 182704 kb
Host smart-c06a838a-97d9-45db-a6b5-4587b0ebf5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910691710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1910691710
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.423037786
Short name T239
Test name
Test status
Simulation time 444022831 ps
CPU time 0.75 seconds
Started Dec 31 12:45:39 PM PST 23
Finished Dec 31 12:45:41 PM PST 23
Peak memory 182552 kb
Host smart-7ae28019-580e-4dbd-8c54-065a45b8312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423037786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.423037786
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1358909629
Short name T114
Test name
Test status
Simulation time 215154794475 ps
CPU time 329.25 seconds
Started Dec 31 12:46:14 PM PST 23
Finished Dec 31 12:51:44 PM PST 23
Peak memory 182760 kb
Host smart-43bceed2-45b7-4448-a2f5-b69176f174fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358909629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1358909629
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2396605309
Short name T259
Test name
Test status
Simulation time 15850944037 ps
CPU time 122.96 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:47:39 PM PST 23
Peak memory 197676 kb
Host smart-5c7a01f7-7b71-4a0d-a219-6f2d67c3d8cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396605309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2396605309
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2288493665
Short name T221
Test name
Test status
Simulation time 566462139 ps
CPU time 0.72 seconds
Started Dec 31 12:46:08 PM PST 23
Finished Dec 31 12:46:11 PM PST 23
Peak memory 182656 kb
Host smart-cb3cdc87-6fd9-4ac5-9790-e382553f29f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288493665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2288493665
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4178229514
Short name T200
Test name
Test status
Simulation time 16859431844 ps
CPU time 14.32 seconds
Started Dec 31 12:45:36 PM PST 23
Finished Dec 31 12:45:51 PM PST 23
Peak memory 182644 kb
Host smart-a947abef-1603-4396-b311-652e39dc409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178229514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4178229514
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.536595285
Short name T308
Test name
Test status
Simulation time 352309817 ps
CPU time 1.01 seconds
Started Dec 31 12:45:20 PM PST 23
Finished Dec 31 12:45:23 PM PST 23
Peak memory 182548 kb
Host smart-1f814928-a42d-4eaf-ab78-c4f88d0317a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536595285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.536595285
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3159595608
Short name T113
Test name
Test status
Simulation time 179216955163 ps
CPU time 278.2 seconds
Started Dec 31 12:45:47 PM PST 23
Finished Dec 31 12:50:25 PM PST 23
Peak memory 182760 kb
Host smart-76bc32f4-11f0-4b71-8d9f-685f8c328e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159595608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3159595608
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.452864583
Short name T68
Test name
Test status
Simulation time 60795850548 ps
CPU time 268.57 seconds
Started Dec 31 12:45:42 PM PST 23
Finished Dec 31 12:50:11 PM PST 23
Peak memory 197536 kb
Host smart-a99d94d8-67b6-4c92-b8be-8108c12f1fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452864583 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.452864583
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1876270356
Short name T243
Test name
Test status
Simulation time 492764558 ps
CPU time 0.73 seconds
Started Dec 31 12:45:23 PM PST 23
Finished Dec 31 12:45:25 PM PST 23
Peak memory 182676 kb
Host smart-86bb8661-5596-47bf-bdbd-37246597f429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876270356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1876270356
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.312028237
Short name T238
Test name
Test status
Simulation time 12143734999 ps
CPU time 19.44 seconds
Started Dec 31 12:45:32 PM PST 23
Finished Dec 31 12:45:52 PM PST 23
Peak memory 182796 kb
Host smart-a2c6c03b-f9c6-4939-9448-563777078989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312028237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.312028237
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1732489125
Short name T157
Test name
Test status
Simulation time 559502184 ps
CPU time 0.72 seconds
Started Dec 31 12:45:39 PM PST 23
Finished Dec 31 12:45:40 PM PST 23
Peak memory 182552 kb
Host smart-403f84e9-788e-474a-80ff-ac7ad61040bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732489125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1732489125
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.679204094
Short name T177
Test name
Test status
Simulation time 348667445533 ps
CPU time 524.3 seconds
Started Dec 31 12:45:25 PM PST 23
Finished Dec 31 12:54:10 PM PST 23
Peak memory 193004 kb
Host smart-f57545ad-cf10-4a2b-aa0e-3c6437548138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679204094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.679204094
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3501524515
Short name T300
Test name
Test status
Simulation time 59071863010 ps
CPU time 125.72 seconds
Started Dec 31 12:45:45 PM PST 23
Finished Dec 31 12:47:51 PM PST 23
Peak memory 197644 kb
Host smart-0dcca934-a076-4739-9491-697df888d2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501524515 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3501524515
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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