Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 27867 1 T1 355 T2 11 T3 11
bark[1] 290 1 T29 16 T95 22 T96 12
bark[2] 432 1 T1 17 T13 130 T95 57
bark[3] 386 1 T32 16 T43 141 T97 12
bark[4] 549 1 T1 16 T47 31 T40 17
bark[5] 600 1 T1 27 T98 12 T99 25
bark[6] 975 1 T10 12 T100 59 T32 39
bark[7] 632 1 T52 13 T89 109 T101 22
bark[8] 245 1 T13 17 T102 13 T103 16
bark[9] 869 1 T11 142 T13 53 T104 13
bark[10] 523 1 T105 16 T106 16 T20 12
bark[11] 393 1 T8 25 T17 12 T13 27
bark[12] 117 1 T95 16 T107 17 T108 16
bark[13] 1080 1 T1 71 T109 12 T43 79
bark[14] 649 1 T28 25 T43 16 T83 230
bark[15] 230 1 T17 17 T110 16 T99 106
bark[16] 224 1 T12 16 T47 12 T24 16
bark[17] 1098 1 T8 16 T11 213 T29 32
bark[18] 681 1 T46 12 T95 12 T50 51
bark[19] 329 1 T28 16 T110 16 T45 16
bark[20] 586 1 T111 44 T50 16 T101 17
bark[21] 600 1 T100 16 T83 36 T112 186
bark[22] 699 1 T41 16 T110 26 T113 40
bark[23] 200 1 T12 31 T32 17 T99 23
bark[24] 833 1 T11 56 T111 33 T95 16
bark[25] 364 1 T13 16 T44 25 T23 21
bark[26] 576 1 T13 122 T114 13 T40 76
bark[27] 593 1 T1 17 T12 46 T44 324
bark[28] 539 1 T100 17 T47 16 T99 33
bark[29] 596 1 T100 16 T115 12 T116 12
bark[30] 796 1 T47 16 T40 79 T84 117
bark[31] 537 1 T117 12 T40 213 T41 32
bark_0 3543 1 T1 32 T2 4 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 27503 1 T1 373 T2 10 T3 10
bite[1] 1191 1 T100 16 T32 186 T52 12
bite[2] 375 1 T111 21 T45 32 T24 16
bite[3] 203 1 T1 16 T118 11 T48 16
bite[4] 669 1 T11 353 T24 20 T101 16
bite[5] 861 1 T32 33 T47 16 T48 17
bite[6] 335 1 T1 70 T41 16 T119 107
bite[7] 455 1 T17 11 T47 31 T110 16
bite[8] 922 1 T46 11 T40 75 T83 208
bite[9] 673 1 T13 52 T114 12 T40 78
bite[10] 508 1 T111 44 T47 16 T119 16
bite[11] 903 1 T11 55 T13 250 T100 16
bite[12] 605 1 T28 25 T13 17 T44 34
bite[13] 365 1 T99 26 T113 25 T107 16
bite[14] 1014 1 T43 140 T120 11 T121 11
bite[15] 463 1 T29 16 T100 16 T104 12
bite[16] 499 1 T100 47 T111 32 T115 11
bite[17] 338 1 T28 16 T95 22 T41 16
bite[18] 517 1 T99 23 T113 39 T122 11
bite[19] 538 1 T12 62 T50 17 T91 39
bite[20] 301 1 T99 16 T123 11 T24 17
bite[21] 383 1 T13 27 T100 17 T111 33
bite[22] 676 1 T32 39 T95 16 T116 11
bite[23] 570 1 T29 31 T117 11 T43 16
bite[24] 171 1 T1 27 T24 17 T124 20
bite[25] 295 1 T1 17 T95 11 T110 26
bite[26] 821 1 T17 17 T95 73 T47 16
bite[27] 256 1 T109 11 T113 38 T101 17
bite[28] 305 1 T110 16 T44 25 T125 11
bite[29] 667 1 T8 41 T10 11 T50 16
bite[30] 484 1 T100 11 T105 16 T24 205
bite[31] 719 1 T12 31 T96 11 T44 203
bite_0 4046 1 T1 32 T2 5 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 48631 1 T1 535 T2 15 T3 15


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1369 1 T1 100 T11 31 T29 34
prescale[1] 1026 1 T8 15 T13 8 T41 66
prescale[2] 978 1 T11 86 T13 2 T47 15
prescale[3] 580 1 T17 15 T126 8 T45 2
prescale[4] 607 1 T13 104 T32 49 T41 30
prescale[5] 822 1 T8 15 T12 39 T32 56
prescale[6] 996 1 T11 2 T13 2 T40 57
prescale[7] 774 1 T1 2 T8 28 T12 18
prescale[8] 627 1 T13 8 T44 113 T99 55
prescale[9] 680 1 T100 15 T110 15 T45 85
prescale[10] 1037 1 T8 29 T11 2 T38 8
prescale[11] 569 1 T32 122 T50 45 T99 64
prescale[12] 944 1 T11 33 T47 15 T41 33
prescale[13] 574 1 T28 30 T127 37 T45 103
prescale[14] 1434 1 T2 8 T11 17 T29 37
prescale[15] 403 1 T11 2 T13 2 T32 43
prescale[16] 775 1 T1 64 T9 8 T11 33
prescale[17] 566 1 T29 18 T32 17 T50 55
prescale[18] 817 1 T11 15 T28 15 T13 55
prescale[19] 407 1 T11 38 T100 29 T110 8
prescale[20] 633 1 T11 36 T12 18 T13 71
prescale[21] 486 1 T1 2 T11 82 T13 50
prescale[22] 536 1 T32 15 T41 18 T45 15
prescale[23] 711 1 T47 18 T40 36 T41 24
prescale[24] 352 1 T28 22 T32 38 T44 2
prescale[25] 704 1 T8 38 T11 31 T12 15
prescale[26] 1030 1 T8 8 T17 15 T28 15
prescale[27] 588 1 T1 2 T3 8 T4 8
prescale[28] 976 1 T11 15 T12 8 T32 17
prescale[29] 470 1 T17 15 T13 91 T42 2
prescale[30] 790 1 T11 103 T17 15 T13 15
prescale[31] 634 1 T32 16 T40 123 T41 86
prescale_0 24736 1 T1 365 T2 7 T3 7


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36493 1 T1 318 T2 6 T3 15
auto[1] 12138 1 T1 217 T2 9 T6 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 48631 1 T1 535 T2 15 T3 15


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28804 1 T1 264 T2 12 T3 12
wkup[1] 523 1 T11 17 T95 16 T40 16
wkup[2] 395 1 T12 16 T100 17 T32 16
wkup[3] 488 1 T28 16 T29 16 T100 16
wkup[4] 448 1 T13 17 T100 47 T32 16
wkup[5] 514 1 T1 17 T11 21 T115 13
wkup[6] 482 1 T1 13 T11 16 T40 16
wkup[7] 585 1 T1 42 T10 13 T17 17
wkup[8] 519 1 T1 16 T114 14 T40 49
wkup[9] 592 1 T13 52 T32 32 T44 32
wkup[10] 667 1 T11 17 T12 31 T29 32
wkup[11] 552 1 T1 16 T11 73 T12 16
wkup[12] 388 1 T47 16 T41 16 T43 26
wkup[13] 330 1 T11 16 T13 16 T32 16
wkup[14] 659 1 T1 33 T100 16 T32 16
wkup[15] 646 1 T11 16 T13 21 T95 26
wkup[16] 568 1 T1 26 T11 56 T13 32
wkup[17] 607 1 T1 21 T11 16 T13 22
wkup[18] 543 1 T1 16 T11 65 T13 16
wkup[19] 571 1 T11 48 T32 39 T41 22
wkup[20] 579 1 T11 16 T13 38 T32 34
wkup[21] 537 1 T17 13 T13 41 T46 13
wkup[22] 373 1 T1 17 T11 16 T13 16
wkup[23] 691 1 T8 16 T11 32 T13 44
wkup[24] 644 1 T11 16 T12 16 T29 16
wkup[25] 582 1 T11 16 T17 22 T110 22
wkup[26] 376 1 T111 16 T44 16 T89 22
wkup[27] 687 1 T1 27 T11 16 T17 16
wkup[28] 548 1 T8 25 T11 16 T100 16
wkup[29] 720 1 T13 16 T100 13 T32 57
wkup[30] 562 1 T13 16 T43 16 T45 16
wkup[31] 485 1 T13 30 T40 42 T45 16
wkup_0 2966 1 T1 27 T2 3 T3 3

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