Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
14020 |
1 |
|
T1 |
158 |
|
T8 |
56 |
|
T11 |
314 |
all_values[1] |
14020 |
1 |
|
T1 |
158 |
|
T8 |
56 |
|
T11 |
314 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for cp_intr_en
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
[auto[1]] |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28040 |
1 |
|
T1 |
316 |
|
T8 |
112 |
|
T11 |
628 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7704 |
1 |
|
T1 |
64 |
|
T8 |
36 |
|
T11 |
210 |
auto[1] |
20336 |
1 |
|
T1 |
252 |
|
T8 |
76 |
|
T11 |
418 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
16018 |
1 |
|
T1 |
170 |
|
T8 |
62 |
|
T11 |
366 |
auto[1] |
12022 |
1 |
|
T1 |
146 |
|
T8 |
50 |
|
T11 |
262 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
6 |
6 |
50.00 |
6 |
Automatically Generated Cross Bins |
12 |
6 |
6 |
50.00 |
6 |
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Element holes
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | NUMBER |
* |
[auto[0]] |
[auto[1]] |
* |
-- |
-- |
4 |
* |
[auto[1]] |
[auto[1]] |
[auto[1]] |
-- |
-- |
2 |
Covered bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
3784 |
1 |
|
T1 |
24 |
|
T8 |
10 |
|
T11 |
118 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
4172 |
1 |
|
T1 |
56 |
|
T8 |
14 |
|
T11 |
70 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
6064 |
1 |
|
T1 |
78 |
|
T8 |
32 |
|
T11 |
126 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
3920 |
1 |
|
T1 |
40 |
|
T8 |
26 |
|
T11 |
92 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
4142 |
1 |
|
T1 |
50 |
|
T8 |
12 |
|
T11 |
86 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
5958 |
1 |
|
T1 |
68 |
|
T8 |
18 |
|
T11 |
136 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |