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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.32 100.00 99.35 100.00 96.90


Total test records in report: 393
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T285 /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.785322325 Jan 03 12:50:58 PM PST 24 Jan 03 01:07:05 PM PST 24 357570235446 ps
T286 /workspace/coverage/default/32.aon_timer_prescaler.1154170461 Jan 03 12:50:40 PM PST 24 Jan 03 12:51:27 PM PST 24 22472314682 ps
T287 /workspace/coverage/default/34.aon_timer_prescaler.1559612656 Jan 03 12:50:48 PM PST 24 Jan 03 12:51:39 PM PST 24 24117137557 ps
T288 /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1724190609 Jan 03 12:50:35 PM PST 24 Jan 03 01:00:15 PM PST 24 76220492767 ps
T39 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1683824899 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:41 PM PST 24 420159219 ps
T289 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.351752869 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:38 PM PST 24 564578133 ps
T33 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3332636414 Jan 03 12:35:59 PM PST 24 Jan 03 12:37:49 PM PST 24 8226880813 ps
T34 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2987629468 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:27 PM PST 24 471819864 ps
T290 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1169455288 Jan 03 12:36:30 PM PST 24 Jan 03 12:38:19 PM PST 24 509557232 ps
T35 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2799489561 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:36 PM PST 24 1211838622 ps
T36 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2681234115 Jan 03 12:35:46 PM PST 24 Jan 03 12:37:39 PM PST 24 8236169036 ps
T291 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3381465376 Jan 03 12:35:45 PM PST 24 Jan 03 12:37:28 PM PST 24 409457216 ps
T292 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3778806626 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:35 PM PST 24 368985622 ps
T58 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.939682288 Jan 03 12:36:19 PM PST 24 Jan 03 12:37:56 PM PST 24 516442286 ps
T76 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2435831979 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:28 PM PST 24 995604044 ps
T37 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.266213903 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:30 PM PST 24 9479762049 ps
T77 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4116990778 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:32 PM PST 24 2387929627 ps
T59 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.674846633 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:47 PM PST 24 404784947 ps
T63 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2612967311 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:28 PM PST 24 350084342 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.749788631 Jan 03 12:38:08 PM PST 24 Jan 03 12:39:41 PM PST 24 534434920 ps
T65 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.144333243 Jan 03 12:35:58 PM PST 24 Jan 03 12:37:32 PM PST 24 1859282398 ps
T66 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1784993779 Jan 03 12:35:45 PM PST 24 Jan 03 12:37:29 PM PST 24 856709536 ps
T67 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2082587593 Jan 03 12:35:24 PM PST 24 Jan 03 12:37:02 PM PST 24 4719775322 ps
T68 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3674823172 Jan 03 12:35:53 PM PST 24 Jan 03 12:37:31 PM PST 24 268390151 ps
T69 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.284052397 Jan 03 12:36:23 PM PST 24 Jan 03 12:38:16 PM PST 24 451611102 ps
T70 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1042119221 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:37 PM PST 24 414866621 ps
T293 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1425716267 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:28 PM PST 24 488681693 ps
T294 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3286332629 Jan 03 12:36:39 PM PST 24 Jan 03 12:38:16 PM PST 24 442451838 ps
T295 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.873600622 Jan 03 12:36:04 PM PST 24 Jan 03 12:37:38 PM PST 24 366427040 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2556832380 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:29 PM PST 24 4830343495 ps
T297 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.829668512 Jan 03 12:36:16 PM PST 24 Jan 03 12:38:00 PM PST 24 505024219 ps
T298 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3989802824 Jan 03 12:37:20 PM PST 24 Jan 03 12:38:41 PM PST 24 510414216 ps
T299 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1166793708 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:43 PM PST 24 464501910 ps
T78 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1031840944 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:36 PM PST 24 1159645569 ps
T300 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1550639778 Jan 03 12:36:14 PM PST 24 Jan 03 12:37:53 PM PST 24 375355079 ps
T301 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3575005980 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:33 PM PST 24 314589088 ps
T79 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.611194709 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:26 PM PST 24 1600268529 ps
T302 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3146646912 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:34 PM PST 24 352895451 ps
T80 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1671131596 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:26 PM PST 24 1118571444 ps
T303 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1166875817 Jan 03 12:36:01 PM PST 24 Jan 03 12:37:45 PM PST 24 368385935 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2563655268 Jan 03 12:35:58 PM PST 24 Jan 03 12:37:35 PM PST 24 383637444 ps
T305 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1409544053 Jan 03 12:35:53 PM PST 24 Jan 03 12:37:44 PM PST 24 318464996 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2129330705 Jan 03 12:36:18 PM PST 24 Jan 03 12:38:06 PM PST 24 4297735737 ps
T307 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2094558440 Jan 03 12:36:27 PM PST 24 Jan 03 12:38:21 PM PST 24 521518185 ps
T308 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2084031056 Jan 03 12:36:35 PM PST 24 Jan 03 12:37:59 PM PST 24 294203918 ps
T309 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1344620866 Jan 03 12:35:58 PM PST 24 Jan 03 12:37:45 PM PST 24 369967845 ps
T310 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1959029500 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:32 PM PST 24 498229451 ps
T311 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1276245658 Jan 03 12:35:59 PM PST 24 Jan 03 12:37:36 PM PST 24 312075782 ps
T81 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1771892687 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:28 PM PST 24 456888366 ps
T312 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.893290395 Jan 03 12:35:54 PM PST 24 Jan 03 12:37:48 PM PST 24 728302474 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1450027539 Jan 03 12:35:53 PM PST 24 Jan 03 12:37:41 PM PST 24 431403166 ps
T314 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1268585919 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:34 PM PST 24 412761773 ps
T315 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3616010957 Jan 03 12:35:13 PM PST 24 Jan 03 12:36:35 PM PST 24 342139324 ps
T316 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3422682539 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:44 PM PST 24 622003843 ps
T317 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3637493296 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:37 PM PST 24 534229878 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1367774708 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:28 PM PST 24 498749975 ps
T319 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.349490737 Jan 03 12:36:13 PM PST 24 Jan 03 12:37:45 PM PST 24 1352921083 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2231925747 Jan 03 12:36:21 PM PST 24 Jan 03 12:37:58 PM PST 24 335057899 ps
T82 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.415580444 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:31 PM PST 24 1124588556 ps
T321 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1367661671 Jan 03 12:36:41 PM PST 24 Jan 03 12:38:12 PM PST 24 449704793 ps
T322 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3847379088 Jan 03 12:36:30 PM PST 24 Jan 03 12:38:22 PM PST 24 405242068 ps
T60 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2766819218 Jan 03 12:35:45 PM PST 24 Jan 03 12:37:29 PM PST 24 328952384 ps
T323 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1903101568 Jan 03 12:36:30 PM PST 24 Jan 03 12:38:21 PM PST 24 360157687 ps
T324 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2378467838 Jan 03 12:36:01 PM PST 24 Jan 03 12:37:46 PM PST 24 4186044825 ps
T325 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4214433072 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:28 PM PST 24 295341825 ps
T326 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3403530120 Jan 03 12:35:51 PM PST 24 Jan 03 12:37:35 PM PST 24 992871626 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4110291042 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:34 PM PST 24 458127798 ps
T328 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2239626009 Jan 03 12:37:08 PM PST 24 Jan 03 12:38:15 PM PST 24 471013949 ps
T329 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3730662148 Jan 03 12:36:42 PM PST 24 Jan 03 12:38:05 PM PST 24 446773693 ps
T330 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3154271997 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:30 PM PST 24 476193927 ps
T331 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.686916467 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:50 PM PST 24 416533673 ps
T61 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1613128068 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:34 PM PST 24 6012600611 ps
T332 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.27268258 Jan 03 12:36:26 PM PST 24 Jan 03 12:38:17 PM PST 24 1110575967 ps
T62 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2561234986 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:51 PM PST 24 354955869 ps
T333 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.890789826 Jan 03 12:37:07 PM PST 24 Jan 03 12:38:16 PM PST 24 357297571 ps
T75 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1527436637 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:38 PM PST 24 469472747 ps
T334 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.795431940 Jan 03 12:35:14 PM PST 24 Jan 03 12:36:55 PM PST 24 502722366 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2604839090 Jan 03 12:35:52 PM PST 24 Jan 03 12:37:26 PM PST 24 878846786 ps
T336 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1179819386 Jan 03 12:35:58 PM PST 24 Jan 03 12:37:31 PM PST 24 469379607 ps
T337 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2275781963 Jan 03 12:36:46 PM PST 24 Jan 03 12:37:59 PM PST 24 465254917 ps
T338 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.826613775 Jan 03 12:36:17 PM PST 24 Jan 03 12:38:05 PM PST 24 553242627 ps
T339 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2757558901 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:34 PM PST 24 512066232 ps
T340 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3384889693 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:33 PM PST 24 526196447 ps
T341 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.876779274 Jan 03 12:35:58 PM PST 24 Jan 03 12:37:31 PM PST 24 529062610 ps
T342 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.251621908 Jan 03 12:36:12 PM PST 24 Jan 03 12:37:47 PM PST 24 333655888 ps
T343 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4030536434 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:34 PM PST 24 561436509 ps
T92 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1312895780 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:46 PM PST 24 8533956620 ps
T71 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2959078096 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:53 PM PST 24 11111742360 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2483545275 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:34 PM PST 24 1048244641 ps
T345 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2238778331 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:29 PM PST 24 359398248 ps
T346 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2440746735 Jan 03 12:35:45 PM PST 24 Jan 03 12:37:33 PM PST 24 4567010160 ps
T347 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.379182378 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:48 PM PST 24 1175586943 ps
T72 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1384317353 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:47 PM PST 24 514979388 ps
T348 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.7776181 Jan 03 12:36:35 PM PST 24 Jan 03 12:38:00 PM PST 24 363996206 ps
T349 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.239716595 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:33 PM PST 24 479584839 ps
T350 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4048160999 Jan 03 12:35:56 PM PST 24 Jan 03 12:37:35 PM PST 24 573030373 ps
T351 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2734499035 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:41 PM PST 24 547655643 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2031163352 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:31 PM PST 24 377184913 ps
T353 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1431864340 Jan 03 12:36:21 PM PST 24 Jan 03 12:37:56 PM PST 24 508759690 ps
T354 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1126826 Jan 03 12:35:29 PM PST 24 Jan 03 12:37:04 PM PST 24 613660860 ps
T355 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.67787187 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:35 PM PST 24 338646676 ps
T356 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1953902001 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:50 PM PST 24 900725590 ps
T357 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1563957906 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:50 PM PST 24 461482180 ps
T94 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2054232385 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:48 PM PST 24 8164683180 ps
T358 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3576057498 Jan 03 12:36:04 PM PST 24 Jan 03 12:37:39 PM PST 24 526460153 ps
T359 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2345249240 Jan 03 12:36:20 PM PST 24 Jan 03 12:38:21 PM PST 24 532277403 ps
T360 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1352934482 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:37 PM PST 24 373721879 ps
T93 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3005626786 Jan 03 12:35:54 PM PST 24 Jan 03 12:37:29 PM PST 24 9061378056 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1905964225 Jan 03 12:35:53 PM PST 24 Jan 03 12:37:31 PM PST 24 504658148 ps
T362 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2851483239 Jan 03 12:36:21 PM PST 24 Jan 03 12:38:32 PM PST 24 415870719 ps
T363 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2829102553 Jan 03 12:36:25 PM PST 24 Jan 03 12:38:03 PM PST 24 481948609 ps
T364 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2836505597 Jan 03 12:36:23 PM PST 24 Jan 03 12:38:05 PM PST 24 483291709 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1705162398 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:31 PM PST 24 422642989 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2763608360 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:51 PM PST 24 332257261 ps
T367 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3331016685 Jan 03 12:35:54 PM PST 24 Jan 03 12:37:42 PM PST 24 447883893 ps
T368 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1937636594 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:37 PM PST 24 7593904704 ps
T369 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.428713381 Jan 03 12:35:54 PM PST 24 Jan 03 12:37:32 PM PST 24 6047034217 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3284008144 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:50 PM PST 24 4197450453 ps
T371 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1032868624 Jan 03 12:36:34 PM PST 24 Jan 03 12:38:00 PM PST 24 438935342 ps
T372 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1180826319 Jan 03 12:36:01 PM PST 24 Jan 03 12:37:50 PM PST 24 985682919 ps
T373 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3617755575 Jan 03 12:35:55 PM PST 24 Jan 03 12:37:40 PM PST 24 1244246061 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2264479299 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:43 PM PST 24 5976681747 ps
T375 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1242312357 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:47 PM PST 24 530106282 ps
T376 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.10091354 Jan 03 12:35:47 PM PST 24 Jan 03 12:37:24 PM PST 24 593398168 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1322958189 Jan 03 12:35:52 PM PST 24 Jan 03 12:37:35 PM PST 24 557563289 ps
T378 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2243639701 Jan 03 12:36:21 PM PST 24 Jan 03 12:38:02 PM PST 24 443950735 ps
T379 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4210691060 Jan 03 12:35:51 PM PST 24 Jan 03 12:37:47 PM PST 24 364059177 ps
T380 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2207805291 Jan 03 12:35:50 PM PST 24 Jan 03 12:37:38 PM PST 24 548720937 ps
T381 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2326404738 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:55 PM PST 24 4294527395 ps
T382 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.27283419 Jan 03 12:36:26 PM PST 24 Jan 03 12:38:11 PM PST 24 301467856 ps
T383 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.547180705 Jan 03 12:36:24 PM PST 24 Jan 03 12:37:57 PM PST 24 509213884 ps
T384 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1203154017 Jan 03 12:36:22 PM PST 24 Jan 03 12:37:57 PM PST 24 300381405 ps
T385 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.168893553 Jan 03 12:36:19 PM PST 24 Jan 03 12:38:00 PM PST 24 334600937 ps
T73 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1264867179 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:47 PM PST 24 439564968 ps
T74 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2038095968 Jan 03 12:35:49 PM PST 24 Jan 03 12:37:37 PM PST 24 478937691 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1017917371 Jan 03 12:35:52 PM PST 24 Jan 03 12:37:29 PM PST 24 419038785 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2258966316 Jan 03 12:35:46 PM PST 24 Jan 03 12:37:30 PM PST 24 1012846532 ps
T388 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2059208894 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:44 PM PST 24 4288639123 ps
T389 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1269579005 Jan 03 12:35:52 PM PST 24 Jan 03 12:37:43 PM PST 24 435377939 ps
T390 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3944531391 Jan 03 12:36:00 PM PST 24 Jan 03 12:37:37 PM PST 24 543073831 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3144149381 Jan 03 12:35:48 PM PST 24 Jan 03 12:37:35 PM PST 24 724495698 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1411183975 Jan 03 12:35:57 PM PST 24 Jan 03 12:37:32 PM PST 24 453290143 ps
T393 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1633575611 Jan 03 12:35:53 PM PST 24 Jan 03 12:37:43 PM PST 24 4679951141 ps

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.3178912189
Short name T1
Test name
Test status
Simulation time 17059743317 ps
CPU time 123.19 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:53:16 PM PST 24
Peak memory 197644 kb
Host smart-0dc0dffb-cbd0-4332-ae79-2bf85537892c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178912189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.3178912189
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2828610722
Short name T99
Test name
Test status
Simulation time 979788235543 ps
CPU time 412.16 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:58:13 PM PST 24
Peak memory 197564 kb
Host smart-30b5689e-e94c-4bac-a0d0-2856c308889f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828610722 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2828610722
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3332636414
Short name T33
Test name
Test status
Simulation time 8226880813 ps
CPU time 13.38 seconds
Started Jan 03 12:35:59 PM PST 24
Finished Jan 03 12:37:49 PM PST 24
Peak memory 197632 kb
Host smart-17cbf2d8-60d4-446f-a4ce-b98ece79aa4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332636414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3332636414
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1828156476
Short name T13
Test name
Test status
Simulation time 183320178647 ps
CPU time 283.93 seconds
Started Jan 03 12:51:20 PM PST 24
Finished Jan 03 12:56:20 PM PST 24
Peak memory 197368 kb
Host smart-271c4cb4-d736-4051-a63f-6f57b58734c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828156476 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1828156476
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1062429874
Short name T44
Test name
Test status
Simulation time 147326141234 ps
CPU time 502.04 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:59:34 PM PST 24
Peak memory 197560 kb
Host smart-a6a8378d-2d97-4fb6-8d80-42afcad7b4f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062429874 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1062429874
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.475480000
Short name T24
Test name
Test status
Simulation time 51875299164 ps
CPU time 392.48 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:57:50 PM PST 24
Peak memory 196712 kb
Host smart-84e27d8b-3ba6-4499-a329-c3fc5d4cd63b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475480000 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.475480000
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.608522609
Short name T12
Test name
Test status
Simulation time 136338166758 ps
CPU time 57.77 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 12:52:07 PM PST 24
Peak memory 192792 kb
Host smart-4d1a591c-1d4a-4dc1-8d1a-4969f12993c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608522609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.608522609
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3536921145
Short name T209
Test name
Test status
Simulation time 211953427982 ps
CPU time 303.04 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:56:24 PM PST 24
Peak memory 182792 kb
Host smart-5963efa1-9adb-40cd-9ffc-3e591ad8ac37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536921145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3536921145
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.4111250040
Short name T18
Test name
Test status
Simulation time 7849128355 ps
CPU time 4.11 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 214820 kb
Host smart-aad94c52-be7e-4ad5-a09b-1aa990ae6601
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111250040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.4111250040
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1689939006
Short name T212
Test name
Test status
Simulation time 50131858846 ps
CPU time 19.66 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 182656 kb
Host smart-db46b07d-8dcf-450f-9cb0-9ccb10a4697c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689939006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1689939006
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3005626786
Short name T93
Test name
Test status
Simulation time 9061378056 ps
CPU time 1.87 seconds
Started Jan 03 12:35:54 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 197564 kb
Host smart-bdb8a71d-5953-4de6-ae38-236ceca24e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005626786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3005626786
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.674846633
Short name T59
Test name
Test status
Simulation time 404784947 ps
CPU time 0.66 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 193008 kb
Host smart-662514a5-9fa3-43d5-821b-31c513bf2dd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674846633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.674846633
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3490731496
Short name T207
Test name
Test status
Simulation time 206161235454 ps
CPU time 687.87 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 01:02:59 PM PST 24
Peak memory 208360 kb
Host smart-fe983fad-e563-4c14-bbef-5147e24e49b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490731496 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3490731496
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2775837266
Short name T95
Test name
Test status
Simulation time 161371802736 ps
CPU time 61.43 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:52:23 PM PST 24
Peak memory 182720 kb
Host smart-238b2402-1a5d-40fc-8b61-ca9d74ecc8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775837266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2775837266
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3438940171
Short name T274
Test name
Test status
Simulation time 111226525638 ps
CPU time 313.43 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:56:09 PM PST 24
Peak memory 205876 kb
Host smart-8dde05c8-8d2f-42cb-a958-e6d3320b9f45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438940171 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3438940171
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1411183975
Short name T392
Test name
Test status
Simulation time 453290143 ps
CPU time 1.23 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:32 PM PST 24
Peak memory 183860 kb
Host smart-bf12244e-94dc-4fa2-959a-1d9d42e23528
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411183975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1411183975
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1784993779
Short name T66
Test name
Test status
Simulation time 856709536 ps
CPU time 1.69 seconds
Started Jan 03 12:35:45 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 183836 kb
Host smart-3fc1c2f9-a889-46b4-b057-89499f547c95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784993779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1784993779
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1905964225
Short name T361
Test name
Test status
Simulation time 504658148 ps
CPU time 0.97 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 195340 kb
Host smart-e64cc24e-bac4-442e-b742-c0470c846da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905964225 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1905964225
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1771892687
Short name T81
Test name
Test status
Simulation time 456888366 ps
CPU time 0.73 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 183844 kb
Host smart-f78b6ee9-efd9-450e-bf3b-a289c23b1a4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771892687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1771892687
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.795431940
Short name T334
Test name
Test status
Simulation time 502722366 ps
CPU time 0.62 seconds
Started Jan 03 12:35:14 PM PST 24
Finished Jan 03 12:36:55 PM PST 24
Peak memory 183552 kb
Host smart-af908553-44a7-4eae-8eb2-799398370813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795431940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.795431940
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3616010957
Short name T315
Test name
Test status
Simulation time 342139324 ps
CPU time 0.64 seconds
Started Jan 03 12:35:13 PM PST 24
Finished Jan 03 12:36:35 PM PST 24
Peak memory 183800 kb
Host smart-2705bcee-1a6e-4ca3-9cff-4c1b39de8c84
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616010957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3616010957
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1126826
Short name T354
Test name
Test status
Simulation time 613660860 ps
CPU time 1.72 seconds
Started Jan 03 12:35:29 PM PST 24
Finished Jan 03 12:37:04 PM PST 24
Peak memory 198708 kb
Host smart-111e5870-9133-44b3-b267-2fae4fb743ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1126826
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2082587593
Short name T67
Test name
Test status
Simulation time 4719775322 ps
CPU time 4.82 seconds
Started Jan 03 12:35:24 PM PST 24
Finished Jan 03 12:37:02 PM PST 24
Peak memory 197324 kb
Host smart-3cc84db0-d7d5-4d06-a6f8-89211bbe0e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082587593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2082587593
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.428713381
Short name T369
Test name
Test status
Simulation time 6047034217 ps
CPU time 4.54 seconds
Started Jan 03 12:35:54 PM PST 24
Finished Jan 03 12:37:32 PM PST 24
Peak memory 195052 kb
Host smart-5034b483-fa3b-46bd-a0c8-e678b5e74c3d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428713381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_bi
t_bash.428713381
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3144149381
Short name T391
Test name
Test status
Simulation time 724495698 ps
CPU time 1.19 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 183696 kb
Host smart-6aba3cee-13bd-4d29-b734-0b1dc49b2839
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144149381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3144149381
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1269579005
Short name T389
Test name
Test status
Simulation time 435377939 ps
CPU time 0.69 seconds
Started Jan 03 12:35:52 PM PST 24
Finished Jan 03 12:37:43 PM PST 24
Peak memory 183792 kb
Host smart-41f107a9-f2f2-4601-9ce7-4e5976e981d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269579005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1269579005
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4110291042
Short name T327
Test name
Test status
Simulation time 458127798 ps
CPU time 1.18 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 183504 kb
Host smart-152297e5-7060-4105-b2be-c64689ebf019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110291042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4110291042
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.611194709
Short name T79
Test name
Test status
Simulation time 1600268529 ps
CPU time 3.33 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:26 PM PST 24
Peak memory 194608 kb
Host smart-2b1f4f99-bb58-439b-872d-cbd3ed4ae87a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611194709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.611194709
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1042119221
Short name T70
Test name
Test status
Simulation time 414866621 ps
CPU time 0.97 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 196292 kb
Host smart-4e40944d-31d8-4d23-8d89-9ac7aafb81ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042119221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1042119221
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2556832380
Short name T296
Test name
Test status
Simulation time 4830343495 ps
CPU time 2.46 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 195940 kb
Host smart-79b3ba18-f0f6-4878-9ed6-da733c7665df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556832380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2556832380
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3944531391
Short name T390
Test name
Test status
Simulation time 543073831 ps
CPU time 1.42 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 193108 kb
Host smart-6601c245-8d78-4c6a-b2b1-8e3253616e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944531391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3944531391
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.873600622
Short name T295
Test name
Test status
Simulation time 366427040 ps
CPU time 0.63 seconds
Started Jan 03 12:36:04 PM PST 24
Finished Jan 03 12:37:38 PM PST 24
Peak memory 183512 kb
Host smart-11ff977e-c7b8-4c80-9eff-f3f3355b8c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873600622 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.873600622
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2435831979
Short name T76
Test name
Test status
Simulation time 995604044 ps
CPU time 0.93 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 192724 kb
Host smart-f5004f66-ab83-4dc7-b4c5-aa7337c0b148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435831979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2435831979
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2054232385
Short name T94
Test name
Test status
Simulation time 8164683180 ps
CPU time 12.22 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:48 PM PST 24
Peak memory 197396 kb
Host smart-01f80e8e-b458-4a39-987e-df04513717bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054232385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2054232385
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3331016685
Short name T367
Test name
Test status
Simulation time 447883893 ps
CPU time 0.88 seconds
Started Jan 03 12:35:54 PM PST 24
Finished Jan 03 12:37:42 PM PST 24
Peak memory 197240 kb
Host smart-1ca5fa9a-40b4-4f80-842f-9ea243292cc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331016685 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3331016685
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1242312357
Short name T375
Test name
Test status
Simulation time 530106282 ps
CPU time 0.81 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 183776 kb
Host smart-36cca793-dcce-4c9e-bc17-3111a76d6f9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242312357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1242312357
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1276245658
Short name T311
Test name
Test status
Simulation time 312075782 ps
CPU time 0.63 seconds
Started Jan 03 12:35:59 PM PST 24
Finished Jan 03 12:37:36 PM PST 24
Peak memory 183516 kb
Host smart-8f2aea45-27f5-44c7-b44a-dcb7e036215f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276245658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1276245658
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4048160999
Short name T350
Test name
Test status
Simulation time 573030373 ps
CPU time 1.91 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 198560 kb
Host smart-f4d7b5ec-be69-4d9f-b43a-ac2989d764de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048160999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4048160999
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1953902001
Short name T356
Test name
Test status
Simulation time 900725590 ps
CPU time 1.03 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:50 PM PST 24
Peak memory 198504 kb
Host smart-40a2eac7-973e-47fa-9648-d40c6b30a832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953902001 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1953902001
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3575005980
Short name T301
Test name
Test status
Simulation time 314589088 ps
CPU time 0.59 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:33 PM PST 24
Peak memory 183648 kb
Host smart-04e1b966-84b5-4a13-a89c-7a6b68acb93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575005980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3575005980
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2799489561
Short name T35
Test name
Test status
Simulation time 1211838622 ps
CPU time 3.03 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:36 PM PST 24
Peak memory 193312 kb
Host smart-f0737c0e-0f5b-43c8-ab2d-f7c34d0707e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799489561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2799489561
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2059208894
Short name T388
Test name
Test status
Simulation time 4288639123 ps
CPU time 7.75 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:44 PM PST 24
Peak memory 195740 kb
Host smart-3bc31c40-f151-4db0-b521-65229508ad02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059208894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2059208894
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.686916467
Short name T331
Test name
Test status
Simulation time 416533673 ps
CPU time 1.19 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:50 PM PST 24
Peak memory 195540 kb
Host smart-177e5a51-18b0-4fd5-85ee-ccaa3a47b575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686916467 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.686916467
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.415580444
Short name T82
Test name
Test status
Simulation time 1124588556 ps
CPU time 1.27 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 194176 kb
Host smart-c9f656e8-c9a9-41b0-b0ba-6f825a96bd1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415580444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.415580444
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.351752869
Short name T289
Test name
Test status
Simulation time 564578133 ps
CPU time 2.01 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:38 PM PST 24
Peak memory 198652 kb
Host smart-7f098610-a930-424c-9bb9-63124fcc8634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351752869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.351752869
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1633575611
Short name T393
Test name
Test status
Simulation time 4679951141 ps
CPU time 2.63 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:37:43 PM PST 24
Peak memory 195940 kb
Host smart-d107e7d8-60e6-4d29-95c8-51d41924a30a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633575611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1633575611
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3422682539
Short name T316
Test name
Test status
Simulation time 622003843 ps
CPU time 1.55 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:44 PM PST 24
Peak memory 195928 kb
Host smart-9b5efb93-4b32-45a0-9469-d63d831ae2b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422682539 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3422682539
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1527436637
Short name T75
Test name
Test status
Simulation time 469472747 ps
CPU time 0.68 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:38 PM PST 24
Peak memory 183824 kb
Host smart-96f244de-4b96-409e-a766-d3ab7644b5d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527436637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1527436637
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2612967311
Short name T63
Test name
Test status
Simulation time 350084342 ps
CPU time 0.62 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 183636 kb
Host smart-2aed9774-2e91-48ce-834c-eeffe6f84e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612967311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2612967311
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1671131596
Short name T80
Test name
Test status
Simulation time 1118571444 ps
CPU time 0.88 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:26 PM PST 24
Peak memory 194180 kb
Host smart-9bcc9eb3-6c11-4988-8843-0314e691b899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671131596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1671131596
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.749788631
Short name T64
Test name
Test status
Simulation time 534434920 ps
CPU time 1.33 seconds
Started Jan 03 12:38:08 PM PST 24
Finished Jan 03 12:39:41 PM PST 24
Peak memory 198604 kb
Host smart-4aef346e-942d-4036-ba57-23b16e83ebe6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749788631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.749788631
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2440746735
Short name T346
Test name
Test status
Simulation time 4567010160 ps
CPU time 2.34 seconds
Started Jan 03 12:35:45 PM PST 24
Finished Jan 03 12:37:33 PM PST 24
Peak memory 195764 kb
Host smart-8c2c1f31-cf3f-4656-8828-1b46e4756162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440746735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2440746735
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1322958189
Short name T377
Test name
Test status
Simulation time 557563289 ps
CPU time 0.86 seconds
Started Jan 03 12:35:52 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 196576 kb
Host smart-a6cd591b-3007-4280-a3d5-12a4b57f3c96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322958189 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1322958189
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.4214433072
Short name T325
Test name
Test status
Simulation time 295341825 ps
CPU time 1 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 183736 kb
Host smart-a66b47bf-16a9-4429-aa0d-f3ccfbc980d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214433072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.4214433072
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1268585919
Short name T314
Test name
Test status
Simulation time 412761773 ps
CPU time 0.82 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 183544 kb
Host smart-93511752-90eb-445d-a7fb-b379a5d2acc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268585919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1268585919
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.379182378
Short name T347
Test name
Test status
Simulation time 1175586943 ps
CPU time 1.28 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:48 PM PST 24
Peak memory 192696 kb
Host smart-82b6b1bf-7656-4009-9827-b63a2f02c682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379182378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.379182378
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1937636594
Short name T368
Test name
Test status
Simulation time 7593904704 ps
CPU time 3.96 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 197296 kb
Host smart-57e9894b-c5be-426c-b111-67ba17bc35dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937636594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1937636594
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1959029500
Short name T310
Test name
Test status
Simulation time 498229451 ps
CPU time 1.4 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:32 PM PST 24
Peak memory 195656 kb
Host smart-b5cf861b-82a3-4345-8261-450fda580895
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959029500 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1959029500
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.4030536434
Short name T343
Test name
Test status
Simulation time 561436509 ps
CPU time 0.98 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 183792 kb
Host smart-2449bd1d-14b3-45ad-a9bd-ce87df74feaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030536434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.4030536434
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2563655268
Short name T304
Test name
Test status
Simulation time 383637444 ps
CPU time 1.1 seconds
Started Jan 03 12:35:58 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 183588 kb
Host smart-9069d598-0f88-4b34-bad5-34ff79cd3f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563655268 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2563655268
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3576057498
Short name T358
Test name
Test status
Simulation time 526460153 ps
CPU time 1.67 seconds
Started Jan 03 12:36:04 PM PST 24
Finished Jan 03 12:37:39 PM PST 24
Peak memory 198600 kb
Host smart-fee5c8f4-00fb-4699-9c50-d08b6ce1f104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576057498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3576057498
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2681234115
Short name T36
Test name
Test status
Simulation time 8236169036 ps
CPU time 13.08 seconds
Started Jan 03 12:35:46 PM PST 24
Finished Jan 03 12:37:39 PM PST 24
Peak memory 197548 kb
Host smart-905178d9-717c-4a04-98c8-31d04fa15cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681234115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2681234115
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1264867179
Short name T73
Test name
Test status
Simulation time 439564968 ps
CPU time 0.62 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 183764 kb
Host smart-7e0e3077-d8ca-4a96-a01c-83bcf91687da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264867179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1264867179
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3146646912
Short name T302
Test name
Test status
Simulation time 352895451 ps
CPU time 0.65 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 183536 kb
Host smart-f3d1a589-e9dd-4de6-a132-49863ad4663f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146646912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3146646912
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1031840944
Short name T78
Test name
Test status
Simulation time 1159645569 ps
CPU time 2.97 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:36 PM PST 24
Peak memory 193556 kb
Host smart-b509f331-11aa-4e54-b602-59b06d8b1d79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031840944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1031840944
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3778806626
Short name T292
Test name
Test status
Simulation time 368985622 ps
CPU time 2.23 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 198564 kb
Host smart-39513876-f9cb-49a4-b824-2e2dbb00e26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778806626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3778806626
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.266213903
Short name T37
Test name
Test status
Simulation time 9479762049 ps
CPU time 3.35 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:30 PM PST 24
Peak memory 197660 kb
Host smart-ccda5286-3e63-40d6-958c-5eebfec0b3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266213903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl
_intg_err.266213903
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2038095968
Short name T74
Test name
Test status
Simulation time 478937691 ps
CPU time 1.34 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 183708 kb
Host smart-9ca88408-f5ef-49b5-a289-1cadcc4e509a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038095968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2038095968
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1344620866
Short name T309
Test name
Test status
Simulation time 369967845 ps
CPU time 0.6 seconds
Started Jan 03 12:35:58 PM PST 24
Finished Jan 03 12:37:45 PM PST 24
Peak memory 183476 kb
Host smart-b6c45b44-a98e-4135-9a88-fc613178067b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344620866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1344620866
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2483545275
Short name T344
Test name
Test status
Simulation time 1048244641 ps
CPU time 1.16 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 194072 kb
Host smart-86b47488-cf63-475a-ab2b-578fcc007129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483545275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2483545275
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1166875817
Short name T303
Test name
Test status
Simulation time 368385935 ps
CPU time 2.13 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:37:45 PM PST 24
Peak memory 198692 kb
Host smart-8a434e16-7c78-4989-a173-b9be22806cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166875817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1166875817
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1312895780
Short name T92
Test name
Test status
Simulation time 8533956620 ps
CPU time 13.98 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:46 PM PST 24
Peak memory 197540 kb
Host smart-d1fcd0a6-e559-495a-b5ee-0b63a8f8b74a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312895780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1312895780
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.826613775
Short name T338
Test name
Test status
Simulation time 553242627 ps
CPU time 0.85 seconds
Started Jan 03 12:36:17 PM PST 24
Finished Jan 03 12:38:05 PM PST 24
Peak memory 197356 kb
Host smart-f96f2e04-5805-43b5-b5a9-76827893d805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826613775 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.826613775
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.939682288
Short name T58
Test name
Test status
Simulation time 516442286 ps
CPU time 0.89 seconds
Started Jan 03 12:36:19 PM PST 24
Finished Jan 03 12:37:56 PM PST 24
Peak memory 183876 kb
Host smart-acde74f3-1d12-4160-9d2a-3b6a4f2bffd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939682288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.939682288
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2231925747
Short name T320
Test name
Test status
Simulation time 335057899 ps
CPU time 1 seconds
Started Jan 03 12:36:21 PM PST 24
Finished Jan 03 12:37:58 PM PST 24
Peak memory 183544 kb
Host smart-b51208a8-8ebe-4102-84fa-18243d9b03a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231925747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2231925747
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.27268258
Short name T332
Test name
Test status
Simulation time 1110575967 ps
CPU time 1 seconds
Started Jan 03 12:36:26 PM PST 24
Finished Jan 03 12:38:17 PM PST 24
Peak memory 192744 kb
Host smart-06792002-a7b7-40f6-bdd8-b0dc2c26ed7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_
timer_same_csr_outstanding.27268258
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.349490737
Short name T319
Test name
Test status
Simulation time 1352921083 ps
CPU time 2.01 seconds
Started Jan 03 12:36:13 PM PST 24
Finished Jan 03 12:37:45 PM PST 24
Peak memory 198624 kb
Host smart-f87bfe0c-10f2-4a9a-a332-5c4511c915a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349490737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.349490737
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2129330705
Short name T306
Test name
Test status
Simulation time 4297735737 ps
CPU time 1.97 seconds
Started Jan 03 12:36:18 PM PST 24
Finished Jan 03 12:38:06 PM PST 24
Peak memory 197064 kb
Host smart-d89d2b78-d07d-4547-92d6-abf5d1577d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129330705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2129330705
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2987629468
Short name T34
Test name
Test status
Simulation time 471819864 ps
CPU time 0.79 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:27 PM PST 24
Peak memory 183720 kb
Host smart-f83bfbce-a5e5-4e80-ac7a-c3456f813001
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987629468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2987629468
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1613128068
Short name T61
Test name
Test status
Simulation time 6012600611 ps
CPU time 5.73 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 192208 kb
Host smart-595c92fd-cd99-4526-b3f4-44b2f6f5dd7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613128068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1613128068
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2604839090
Short name T335
Test name
Test status
Simulation time 878846786 ps
CPU time 1.25 seconds
Started Jan 03 12:35:52 PM PST 24
Finished Jan 03 12:37:26 PM PST 24
Peak memory 183696 kb
Host smart-17e87509-38fd-44e1-9d24-ef05b3f10d54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604839090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2604839090
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1425716267
Short name T293
Test name
Test status
Simulation time 488681693 ps
CPU time 0.82 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 195968 kb
Host smart-78850d19-4d11-43c3-b4bf-b243a0c4a473
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425716267 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1425716267
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2766819218
Short name T60
Test name
Test status
Simulation time 328952384 ps
CPU time 0.63 seconds
Started Jan 03 12:35:45 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 183848 kb
Host smart-56841ef7-fb7b-4004-a073-aa6ff206dab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766819218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2766819218
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3154271997
Short name T330
Test name
Test status
Simulation time 476193927 ps
CPU time 1.18 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:30 PM PST 24
Peak memory 183540 kb
Host smart-1637061f-31e5-41f4-9f8c-243bd0e6e6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154271997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3154271997
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1409544053
Short name T305
Test name
Test status
Simulation time 318464996 ps
CPU time 0.98 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:37:44 PM PST 24
Peak memory 183796 kb
Host smart-17856fb9-73fb-43b4-80b7-4e52de8c20f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409544053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1409544053
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1550639778
Short name T300
Test name
Test status
Simulation time 375355079 ps
CPU time 0.62 seconds
Started Jan 03 12:36:14 PM PST 24
Finished Jan 03 12:37:53 PM PST 24
Peak memory 183584 kb
Host smart-e77fcaa8-bfc8-4372-a4d1-a7b5b6db0dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550639778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1550639778
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2239626009
Short name T328
Test name
Test status
Simulation time 471013949 ps
CPU time 1.36 seconds
Started Jan 03 12:37:08 PM PST 24
Finished Jan 03 12:38:15 PM PST 24
Peak memory 183752 kb
Host smart-038c56eb-b6fb-4eb8-8ef4-3c5aad27f1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239626009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2239626009
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.829668512
Short name T297
Test name
Test status
Simulation time 505024219 ps
CPU time 0.69 seconds
Started Jan 03 12:36:16 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 183576 kb
Host smart-272a1eae-7a20-47d2-848d-3c1fa3e8a1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829668512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.829668512
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2851483239
Short name T362
Test name
Test status
Simulation time 415870719 ps
CPU time 0.66 seconds
Started Jan 03 12:36:21 PM PST 24
Finished Jan 03 12:38:32 PM PST 24
Peak memory 183828 kb
Host smart-9613638d-d8ce-47ae-b24d-4f5c69b6dc6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851483239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2851483239
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.547180705
Short name T383
Test name
Test status
Simulation time 509213884 ps
CPU time 0.71 seconds
Started Jan 03 12:36:24 PM PST 24
Finished Jan 03 12:37:57 PM PST 24
Peak memory 183556 kb
Host smart-ba116b46-96e5-4d5f-9388-1135376ee62d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547180705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.547180705
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1431864340
Short name T353
Test name
Test status
Simulation time 508759690 ps
CPU time 1.11 seconds
Started Jan 03 12:36:21 PM PST 24
Finished Jan 03 12:37:56 PM PST 24
Peak memory 183776 kb
Host smart-ec50c9b6-21ed-4101-8f0b-b9fdb8210b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431864340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1431864340
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.251621908
Short name T342
Test name
Test status
Simulation time 333655888 ps
CPU time 0.66 seconds
Started Jan 03 12:36:12 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 183648 kb
Host smart-a2bd857f-ed1b-43fd-99b5-2713c8efe381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251621908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.251621908
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.168893553
Short name T385
Test name
Test status
Simulation time 334600937 ps
CPU time 0.8 seconds
Started Jan 03 12:36:19 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 183756 kb
Host smart-01114180-23a7-41d1-8a8e-6c47c497ec14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168893553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.168893553
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3847379088
Short name T322
Test name
Test status
Simulation time 405242068 ps
CPU time 0.71 seconds
Started Jan 03 12:36:30 PM PST 24
Finished Jan 03 12:38:22 PM PST 24
Peak memory 183484 kb
Host smart-eecb1511-9f71-433c-9c5c-f72af1f96b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847379088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3847379088
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3730662148
Short name T329
Test name
Test status
Simulation time 446773693 ps
CPU time 0.85 seconds
Started Jan 03 12:36:42 PM PST 24
Finished Jan 03 12:38:05 PM PST 24
Peak memory 183488 kb
Host smart-07c396d9-5a38-4730-87f9-849bc27404ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730662148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3730662148
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1384317353
Short name T72
Test name
Test status
Simulation time 514979388 ps
CPU time 0.81 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 193060 kb
Host smart-159bc859-2795-48b6-915a-478e3d8eb578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384317353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1384317353
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2959078096
Short name T71
Test name
Test status
Simulation time 11111742360 ps
CPU time 6.83 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:53 PM PST 24
Peak memory 192312 kb
Host smart-e2007029-3bfd-4111-8bb8-9ecba8e3a879
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959078096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2959078096
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3381465376
Short name T291
Test name
Test status
Simulation time 409457216 ps
CPU time 1.09 seconds
Started Jan 03 12:35:45 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 183484 kb
Host smart-832df0bf-e54d-4aea-ad40-997c5cb7c1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381465376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3381465376
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2763608360
Short name T366
Test name
Test status
Simulation time 332257261 ps
CPU time 0.74 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:51 PM PST 24
Peak memory 183524 kb
Host smart-41863845-88af-41c3-a645-93079a02dea0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763608360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2763608360
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1367774708
Short name T318
Test name
Test status
Simulation time 498749975 ps
CPU time 1.16 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:28 PM PST 24
Peak memory 183512 kb
Host smart-fe0a822e-012e-4c57-864a-b99523ace9f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367774708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1367774708
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2258966316
Short name T387
Test name
Test status
Simulation time 1012846532 ps
CPU time 1.48 seconds
Started Jan 03 12:35:46 PM PST 24
Finished Jan 03 12:37:30 PM PST 24
Peak memory 194288 kb
Host smart-dc5f37b1-a061-4e0e-ae9f-4d5a5c1b8c58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258966316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2258966316
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.893290395
Short name T312
Test name
Test status
Simulation time 728302474 ps
CPU time 2.22 seconds
Started Jan 03 12:35:54 PM PST 24
Finished Jan 03 12:37:48 PM PST 24
Peak memory 198584 kb
Host smart-5cc8ef13-a12d-4870-9c4a-796cf91f9e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893290395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.893290395
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.7776181
Short name T348
Test name
Test status
Simulation time 363996206 ps
CPU time 1.05 seconds
Started Jan 03 12:36:35 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 183328 kb
Host smart-3a512211-79ed-481b-a52c-ff501b4f28b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7776181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.7776181
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3286332629
Short name T294
Test name
Test status
Simulation time 442451838 ps
CPU time 0.67 seconds
Started Jan 03 12:36:39 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 183796 kb
Host smart-42912761-8122-4c67-a924-989d843e0fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286332629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3286332629
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1203154017
Short name T384
Test name
Test status
Simulation time 300381405 ps
CPU time 0.73 seconds
Started Jan 03 12:36:22 PM PST 24
Finished Jan 03 12:37:57 PM PST 24
Peak memory 183516 kb
Host smart-0d53d496-5d82-46b5-af8d-192b792ceefe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203154017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1203154017
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.284052397
Short name T69
Test name
Test status
Simulation time 451611102 ps
CPU time 0.69 seconds
Started Jan 03 12:36:23 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 183540 kb
Host smart-ed82d5dc-c107-43a5-98fc-b948ce749db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284052397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.284052397
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2275781963
Short name T337
Test name
Test status
Simulation time 465254917 ps
CPU time 0.8 seconds
Started Jan 03 12:36:46 PM PST 24
Finished Jan 03 12:37:59 PM PST 24
Peak memory 183512 kb
Host smart-913ffef0-72f0-4878-be8d-6492fb19ce16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275781963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2275781963
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2345249240
Short name T359
Test name
Test status
Simulation time 532277403 ps
CPU time 0.71 seconds
Started Jan 03 12:36:20 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 183580 kb
Host smart-e91a9f2a-736d-4428-a3a3-9b44526fabdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345249240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2345249240
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2836505597
Short name T364
Test name
Test status
Simulation time 483291709 ps
CPU time 1.32 seconds
Started Jan 03 12:36:23 PM PST 24
Finished Jan 03 12:38:05 PM PST 24
Peak memory 183776 kb
Host smart-3ecd10c4-33cf-4420-a479-826a2bcd8d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836505597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2836505597
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1367661671
Short name T321
Test name
Test status
Simulation time 449704793 ps
CPU time 1.17 seconds
Started Jan 03 12:36:41 PM PST 24
Finished Jan 03 12:38:12 PM PST 24
Peak memory 183512 kb
Host smart-93a705ab-b101-4bae-b902-25590ef2241a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367661671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1367661671
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1169455288
Short name T290
Test name
Test status
Simulation time 509557232 ps
CPU time 1.27 seconds
Started Jan 03 12:36:30 PM PST 24
Finished Jan 03 12:38:19 PM PST 24
Peak memory 183512 kb
Host smart-4a8269be-cdff-4c7e-91f4-8cac71648947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169455288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1169455288
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1179819386
Short name T336
Test name
Test status
Simulation time 469379607 ps
CPU time 0.93 seconds
Started Jan 03 12:35:58 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 183808 kb
Host smart-9ff9a1de-0e76-4d1a-833e-e81504533ef6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179819386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1179819386
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2264479299
Short name T374
Test name
Test status
Simulation time 5976681747 ps
CPU time 16.52 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:43 PM PST 24
Peak memory 192260 kb
Host smart-cadfec05-0616-4aff-8488-04f7b7816d39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264479299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2264479299
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1180826319
Short name T372
Test name
Test status
Simulation time 985682919 ps
CPU time 1.28 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:37:50 PM PST 24
Peak memory 183780 kb
Host smart-ffdbcc88-ab7c-40bf-8ba4-9c3b215f88e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180826319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1180826319
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.10091354
Short name T376
Test name
Test status
Simulation time 593398168 ps
CPU time 0.85 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:24 PM PST 24
Peak memory 196536 kb
Host smart-bb096b62-51ca-4d08-87a6-64d92fe59490
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10091354 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.10091354
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.876779274
Short name T341
Test name
Test status
Simulation time 529062610 ps
CPU time 0.66 seconds
Started Jan 03 12:35:58 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 183840 kb
Host smart-3ab67681-3e6e-482c-b7dd-353990400b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876779274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.876779274
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2031163352
Short name T352
Test name
Test status
Simulation time 377184913 ps
CPU time 0.95 seconds
Started Jan 03 12:35:47 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 183468 kb
Host smart-b434543f-72a7-4057-a912-80cc682eac54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031163352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2031163352
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2238778331
Short name T345
Test name
Test status
Simulation time 359398248 ps
CPU time 0.62 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 183456 kb
Host smart-64ff36f2-383c-4836-b46a-cc932a791ede
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238778331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2238778331
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1705162398
Short name T365
Test name
Test status
Simulation time 422642989 ps
CPU time 1.71 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 198668 kb
Host smart-4bfc5004-5c1e-4f40-b8ba-7b341b3084c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705162398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1705162398
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2243639701
Short name T378
Test name
Test status
Simulation time 443950735 ps
CPU time 1.09 seconds
Started Jan 03 12:36:21 PM PST 24
Finished Jan 03 12:38:02 PM PST 24
Peak memory 183828 kb
Host smart-00943a27-a4bd-4c58-9ce7-d77952487bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243639701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2243639701
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2829102553
Short name T363
Test name
Test status
Simulation time 481948609 ps
CPU time 1.07 seconds
Started Jan 03 12:36:25 PM PST 24
Finished Jan 03 12:38:03 PM PST 24
Peak memory 183848 kb
Host smart-353408fc-b31c-4dd5-ac57-0f1b2609fdcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829102553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2829102553
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2094558440
Short name T307
Test name
Test status
Simulation time 521518185 ps
CPU time 0.9 seconds
Started Jan 03 12:36:27 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 183628 kb
Host smart-6a3baae1-416a-4cf3-91b4-b7757c007d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094558440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2094558440
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.27283419
Short name T382
Test name
Test status
Simulation time 301467856 ps
CPU time 0.95 seconds
Started Jan 03 12:36:26 PM PST 24
Finished Jan 03 12:38:11 PM PST 24
Peak memory 183840 kb
Host smart-26f15b12-9cb8-4b22-8ce7-c7e8e156028f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27283419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.27283419
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.890789826
Short name T333
Test name
Test status
Simulation time 357297571 ps
CPU time 0.95 seconds
Started Jan 03 12:37:07 PM PST 24
Finished Jan 03 12:38:16 PM PST 24
Peak memory 183604 kb
Host smart-d15de720-c8c6-48ef-9817-9c672b2a8ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890789826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.890789826
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1903101568
Short name T323
Test name
Test status
Simulation time 360157687 ps
CPU time 0.61 seconds
Started Jan 03 12:36:30 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 183492 kb
Host smart-af94cb38-650b-46b4-8cad-1a6af00079eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903101568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1903101568
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1032868624
Short name T371
Test name
Test status
Simulation time 438935342 ps
CPU time 0.59 seconds
Started Jan 03 12:36:34 PM PST 24
Finished Jan 03 12:38:00 PM PST 24
Peak memory 183520 kb
Host smart-1c5a0512-6dc2-4a43-9575-9dfa702928c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032868624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1032868624
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2084031056
Short name T308
Test name
Test status
Simulation time 294203918 ps
CPU time 0.6 seconds
Started Jan 03 12:36:35 PM PST 24
Finished Jan 03 12:37:59 PM PST 24
Peak memory 183500 kb
Host smart-1e7e9324-e0bd-4720-ac03-1dd0ff363ec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084031056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2084031056
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3989802824
Short name T298
Test name
Test status
Simulation time 510414216 ps
CPU time 0.68 seconds
Started Jan 03 12:37:20 PM PST 24
Finished Jan 03 12:38:41 PM PST 24
Peak memory 183740 kb
Host smart-cb863082-08ec-4099-a5ab-9838ce06c747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989802824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3989802824
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.239716595
Short name T349
Test name
Test status
Simulation time 479584839 ps
CPU time 0.74 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:37:33 PM PST 24
Peak memory 194832 kb
Host smart-9e6e221e-440d-473b-832e-2b143826517f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239716595 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.239716595
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1683824899
Short name T39
Test name
Test status
Simulation time 420159219 ps
CPU time 0.78 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:41 PM PST 24
Peak memory 183864 kb
Host smart-79338e73-56bd-4622-b3b6-eb12987b5d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683824899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1683824899
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1166793708
Short name T299
Test name
Test status
Simulation time 464501910 ps
CPU time 1.22 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:43 PM PST 24
Peak memory 183852 kb
Host smart-e153b56a-2fe5-4e4c-a7ae-dd20350ea14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166793708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1166793708
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3617755575
Short name T373
Test name
Test status
Simulation time 1244246061 ps
CPU time 2.1 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:40 PM PST 24
Peak memory 192852 kb
Host smart-19ebea2e-9eaa-413e-bd17-c57c85c97239
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617755575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3617755575
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1352934482
Short name T360
Test name
Test status
Simulation time 373721879 ps
CPU time 1.33 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 198692 kb
Host smart-f74bd67f-b87d-40fe-b3c1-015f76d35ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352934482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1352934482
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3284008144
Short name T370
Test name
Test status
Simulation time 4197450453 ps
CPU time 4.18 seconds
Started Jan 03 12:35:57 PM PST 24
Finished Jan 03 12:37:50 PM PST 24
Peak memory 197108 kb
Host smart-41e16c6c-f9b0-48f6-ace1-e61fc8529652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284008144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3284008144
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3637493296
Short name T317
Test name
Test status
Simulation time 534229878 ps
CPU time 0.97 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:37 PM PST 24
Peak memory 194936 kb
Host smart-c430f1b9-5601-4187-b216-cb71baa6ab0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637493296 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3637493296
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1017917371
Short name T386
Test name
Test status
Simulation time 419038785 ps
CPU time 0.65 seconds
Started Jan 03 12:35:52 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 183756 kb
Host smart-694eead4-476c-4cbb-98f7-8526ae37c599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017917371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1017917371
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3674823172
Short name T68
Test name
Test status
Simulation time 268390151 ps
CPU time 0.91 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:37:31 PM PST 24
Peak memory 183472 kb
Host smart-071be0ed-96fa-4167-a2c1-62bf76ab76f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674823172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3674823172
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.144333243
Short name T65
Test name
Test status
Simulation time 1859282398 ps
CPU time 1.4 seconds
Started Jan 03 12:35:58 PM PST 24
Finished Jan 03 12:37:32 PM PST 24
Peak memory 194460 kb
Host smart-5ab9b6dc-c309-440c-84f0-f47f55152b59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144333243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.144333243
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.67787187
Short name T355
Test name
Test status
Simulation time 338646676 ps
CPU time 1.59 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 198708 kb
Host smart-82347a58-def0-4d53-a57b-38347d12f213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67787187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.67787187
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2561234986
Short name T62
Test name
Test status
Simulation time 354955869 ps
CPU time 0.67 seconds
Started Jan 03 12:35:55 PM PST 24
Finished Jan 03 12:37:51 PM PST 24
Peak memory 183816 kb
Host smart-f4cfa5ab-0a78-4df0-ae7e-32b0fba48a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561234986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2561234986
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4116990778
Short name T77
Test name
Test status
Simulation time 2387929627 ps
CPU time 3.43 seconds
Started Jan 03 12:35:48 PM PST 24
Finished Jan 03 12:37:32 PM PST 24
Peak memory 191980 kb
Host smart-5f5cfa83-a2fd-475e-924a-f5e62edceaad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116990778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4116990778
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1563957906
Short name T357
Test name
Test status
Simulation time 461482180 ps
CPU time 2 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:50 PM PST 24
Peak memory 198604 kb
Host smart-937f3d6d-024c-42cc-994a-d16697a0a0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563957906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1563957906
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.2326404738
Short name T381
Test name
Test status
Simulation time 4294527395 ps
CPU time 6.11 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 12:37:55 PM PST 24
Peak memory 195896 kb
Host smart-b44d3f85-3495-48e3-bd74-8641ee517f54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326404738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.2326404738
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.2734499035
Short name T351
Test name
Test status
Simulation time 547655643 ps
CPU time 0.78 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:41 PM PST 24
Peak memory 194748 kb
Host smart-a5263d50-17d9-4d54-84db-94e9d0e2f343
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734499035 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.2734499035
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3384889693
Short name T340
Test name
Test status
Simulation time 526196447 ps
CPU time 0.69 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:33 PM PST 24
Peak memory 183772 kb
Host smart-9647b522-b287-472d-bb46-6cdb65021824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384889693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3384889693
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.4210691060
Short name T379
Test name
Test status
Simulation time 364059177 ps
CPU time 2.4 seconds
Started Jan 03 12:35:51 PM PST 24
Finished Jan 03 12:37:47 PM PST 24
Peak memory 198576 kb
Host smart-1124ac8b-2ef6-4f46-bb2a-346683279441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210691060 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.4210691060
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2378467838
Short name T324
Test name
Test status
Simulation time 4186044825 ps
CPU time 6.85 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:37:46 PM PST 24
Peak memory 197440 kb
Host smart-53b93bd1-04da-44dc-940e-64b67c9cc44d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378467838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2378467838
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2207805291
Short name T380
Test name
Test status
Simulation time 548720937 ps
CPU time 1.41 seconds
Started Jan 03 12:35:50 PM PST 24
Finished Jan 03 12:37:38 PM PST 24
Peak memory 195616 kb
Host smart-ddaefdaa-59c2-4f23-a3a6-53fd72fff6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207805291 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2207805291
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2757558901
Short name T339
Test name
Test status
Simulation time 512066232 ps
CPU time 0.71 seconds
Started Jan 03 12:35:56 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 183780 kb
Host smart-f98968b3-80ca-40f6-b5df-fcbb5f59d35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757558901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2757558901
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.3403530120
Short name T326
Test name
Test status
Simulation time 992871626 ps
CPU time 0.72 seconds
Started Jan 03 12:35:51 PM PST 24
Finished Jan 03 12:37:35 PM PST 24
Peak memory 194180 kb
Host smart-7481288f-05a4-4718-b520-5db613ab77ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403530120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.3403530120
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1450027539
Short name T313
Test name
Test status
Simulation time 431403166 ps
CPU time 1.48 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:37:41 PM PST 24
Peak memory 198584 kb
Host smart-199b1e1b-07cf-4b57-bd66-69fe86643251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450027539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1450027539
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3350300453
Short name T263
Test name
Test status
Simulation time 565672000 ps
CPU time 0.98 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 182592 kb
Host smart-f48e6d65-adaf-4957-a080-bc2eeb557738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350300453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3350300453
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4004836880
Short name T158
Test name
Test status
Simulation time 21064508895 ps
CPU time 9.28 seconds
Started Jan 03 12:50:35 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 182596 kb
Host smart-0ca11375-bf85-42b5-98d0-0fdca0f2c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004836880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4004836880
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1117909091
Short name T146
Test name
Test status
Simulation time 423471924 ps
CPU time 1.17 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 182700 kb
Host smart-a51dd186-b5de-4ca7-a91a-d3bbf6aab850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117909091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1117909091
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.509350501
Short name T193
Test name
Test status
Simulation time 107246463434 ps
CPU time 178.46 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:53:33 PM PST 24
Peak memory 182804 kb
Host smart-e927ddc0-d674-4de8-a2cf-504fb59b7687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509350501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.509350501
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1701441122
Short name T89
Test name
Test status
Simulation time 54761444580 ps
CPU time 393.33 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:57:35 PM PST 24
Peak memory 197528 kb
Host smart-22564776-0cb8-4a0f-97e4-6bf98e4abbbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701441122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1701441122
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3508125445
Short name T253
Test name
Test status
Simulation time 526289500 ps
CPU time 0.94 seconds
Started Jan 03 12:51:22 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 182300 kb
Host smart-a2ced9e8-f4a7-433e-96a2-7d5df2881d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508125445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3508125445
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3966015510
Short name T151
Test name
Test status
Simulation time 28362767326 ps
CPU time 39.71 seconds
Started Jan 03 12:50:12 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 182740 kb
Host smart-0d70bc70-0b33-4dbf-a997-11aec53c62ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966015510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3966015510
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.209300151
Short name T16
Test name
Test status
Simulation time 8036478940 ps
CPU time 4.26 seconds
Started Jan 03 12:51:20 PM PST 24
Finished Jan 03 12:51:40 PM PST 24
Peak memory 214556 kb
Host smart-31b11732-ab8d-48f6-ab36-f310d6a1dd63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209300151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.209300151
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2868334470
Short name T257
Test name
Test status
Simulation time 575000718 ps
CPU time 0.63 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 182600 kb
Host smart-d75d7a4b-ef7d-4373-a0db-bee77aee1632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868334470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2868334470
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.183768507
Short name T185
Test name
Test status
Simulation time 6406460765 ps
CPU time 5.95 seconds
Started Jan 03 12:50:26 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 192812 kb
Host smart-b023a8a5-6178-47b1-a57f-e2561e82bfe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183768507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.183768507
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2868315431
Short name T114
Test name
Test status
Simulation time 494228995 ps
CPU time 1.31 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 182704 kb
Host smart-4008aeef-7fb1-482b-a825-b7351545190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868315431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2868315431
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1560827358
Short name T147
Test name
Test status
Simulation time 620117169 ps
CPU time 0.73 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 182652 kb
Host smart-af86a850-5d00-47fa-af62-778a0033741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560827358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1560827358
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2600194487
Short name T136
Test name
Test status
Simulation time 465319228 ps
CPU time 1.35 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:51:48 PM PST 24
Peak memory 180880 kb
Host smart-1a712cb2-c5c2-4d94-828f-6da2b2cd49d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600194487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2600194487
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.4014339620
Short name T264
Test name
Test status
Simulation time 53867071235 ps
CPU time 80.31 seconds
Started Jan 03 12:52:02 PM PST 24
Finished Jan 03 12:53:26 PM PST 24
Peak memory 192548 kb
Host smart-919fe1a9-fc3e-49e0-bd14-9e79a2c13cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014339620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.4014339620
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3493996598
Short name T91
Test name
Test status
Simulation time 451593855674 ps
CPU time 346.23 seconds
Started Jan 03 12:52:11 PM PST 24
Finished Jan 03 12:58:15 PM PST 24
Peak memory 197416 kb
Host smart-378e176d-c41d-4109-a2b6-eda34ad71a5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493996598 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3493996598
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3468796057
Short name T229
Test name
Test status
Simulation time 611592318 ps
CPU time 1.58 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 182632 kb
Host smart-14e13ef0-3cd4-44f3-b3d6-4f2adaa227e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468796057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3468796057
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.717460824
Short name T234
Test name
Test status
Simulation time 26545463043 ps
CPU time 25.23 seconds
Started Jan 03 12:50:24 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 182740 kb
Host smart-66ae3eca-49d0-4579-b77e-1e3fa2e6b451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717460824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.717460824
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2520627291
Short name T277
Test name
Test status
Simulation time 417118988 ps
CPU time 0.71 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 182552 kb
Host smart-27ec7278-4ca1-4227-abb8-f626259ccb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520627291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2520627291
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2892821115
Short name T205
Test name
Test status
Simulation time 378984228948 ps
CPU time 139.42 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:53:03 PM PST 24
Peak memory 182696 kb
Host smart-953868f5-3ad4-4302-a371-e68c38abe52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892821115 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2892821115
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.4120667990
Short name T11
Test name
Test status
Simulation time 146298373773 ps
CPU time 197.97 seconds
Started Jan 03 12:52:05 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 197416 kb
Host smart-d222612f-54a3-4f26-ac36-02e499635687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120667990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.4120667990
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.212091559
Short name T117
Test name
Test status
Simulation time 337328374 ps
CPU time 1.04 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 182576 kb
Host smart-8a5b1019-f49d-4615-a801-511dd796abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212091559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.212091559
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2007062614
Short name T144
Test name
Test status
Simulation time 21022698640 ps
CPU time 32.77 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:42 PM PST 24
Peak memory 182788 kb
Host smart-f320598d-71e8-4fbc-8a4b-1636e617bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007062614 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2007062614
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.244012682
Short name T219
Test name
Test status
Simulation time 542323208 ps
CPU time 0.97 seconds
Started Jan 03 12:52:07 PM PST 24
Finished Jan 03 12:52:17 PM PST 24
Peak memory 181980 kb
Host smart-5f90d851-f3ca-4cd5-a70d-cb430136bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244012682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.244012682
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.704975239
Short name T103
Test name
Test status
Simulation time 137682135580 ps
CPU time 174.53 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:53:45 PM PST 24
Peak memory 182784 kb
Host smart-fe76bc13-6bfb-4600-bcbe-c26a867dfee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704975239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.704975239
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3330952837
Short name T156
Test name
Test status
Simulation time 373456635 ps
CPU time 1.15 seconds
Started Jan 03 12:50:31 PM PST 24
Finished Jan 03 12:50:56 PM PST 24
Peak memory 182700 kb
Host smart-f6f93d3a-337c-4853-8b17-4168b41914e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330952837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3330952837
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.623764537
Short name T197
Test name
Test status
Simulation time 18541239156 ps
CPU time 3.92 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 182672 kb
Host smart-33a59c4a-96b9-4745-9b5e-93e0e07700f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623764537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.623764537
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.1633880445
Short name T198
Test name
Test status
Simulation time 507546270 ps
CPU time 0.71 seconds
Started Jan 03 12:50:27 PM PST 24
Finished Jan 03 12:50:51 PM PST 24
Peak memory 182572 kb
Host smart-e65cfd6e-0976-489f-aae6-c349cc04eadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633880445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.1633880445
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3745744202
Short name T48
Test name
Test status
Simulation time 12627991603 ps
CPU time 5.14 seconds
Started Jan 03 12:50:31 PM PST 24
Finished Jan 03 12:50:59 PM PST 24
Peak memory 182776 kb
Host smart-77d7c335-5787-4912-921d-3c007dff71a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745744202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3745744202
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.317606078
Short name T90
Test name
Test status
Simulation time 108471861122 ps
CPU time 379.12 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 12:57:30 PM PST 24
Peak memory 197560 kb
Host smart-30e81cfd-d9f5-48a9-8881-fe8aaa9cbc2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317606078 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.317606078
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2191540943
Short name T109
Test name
Test status
Simulation time 477918387 ps
CPU time 1.17 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 182660 kb
Host smart-a8c43c98-6a93-49f6-bccc-a27fcb5bf19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191540943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2191540943
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.604737578
Short name T9
Test name
Test status
Simulation time 20847407536 ps
CPU time 8.44 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 182756 kb
Host smart-149e712a-5cae-4ec2-9bf6-c8ff550b9d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604737578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.604737578
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1279634250
Short name T31
Test name
Test status
Simulation time 590132053 ps
CPU time 1.03 seconds
Started Jan 03 12:50:34 PM PST 24
Finished Jan 03 12:50:58 PM PST 24
Peak memory 182668 kb
Host smart-a8000b48-3ae8-4678-96fc-9ff23054c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279634250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1279634250
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1829853802
Short name T111
Test name
Test status
Simulation time 19569122912 ps
CPU time 16.61 seconds
Started Jan 03 12:50:34 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 182708 kb
Host smart-d5f249ce-7649-46ad-ae5a-4f05ade44bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829853802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1829853802
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4031132831
Short name T180
Test name
Test status
Simulation time 576777559 ps
CPU time 0.59 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 182716 kb
Host smart-512ff17e-1234-4339-b27e-757c95733dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031132831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4031132831
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1517285795
Short name T2
Test name
Test status
Simulation time 18913000633 ps
CPU time 24.75 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 182624 kb
Host smart-e8d49c3b-5300-40b4-af23-2e8279536e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517285795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1517285795
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2755477577
Short name T182
Test name
Test status
Simulation time 471980438 ps
CPU time 0.72 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:09 PM PST 24
Peak memory 182532 kb
Host smart-1705aa7b-5f54-4404-9a74-611630a3bbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755477577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2755477577
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3286549092
Short name T240
Test name
Test status
Simulation time 146088951879 ps
CPU time 32.58 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:41 PM PST 24
Peak memory 182704 kb
Host smart-c77b738b-a760-4538-b832-0b2e5e651e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286549092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3286549092
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3712168890
Short name T283
Test name
Test status
Simulation time 23522867952 ps
CPU time 168.48 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:53:54 PM PST 24
Peak memory 197564 kb
Host smart-9229a687-3d3a-4f9c-bfe7-b01e6538d624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712168890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3712168890
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.4217499441
Short name T249
Test name
Test status
Simulation time 380808701 ps
CPU time 0.64 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 182712 kb
Host smart-26cbc2f5-ff4c-45ed-9aa1-595337f10e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217499441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.4217499441
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3864344607
Short name T161
Test name
Test status
Simulation time 40650492329 ps
CPU time 58.48 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:51:52 PM PST 24
Peak memory 182632 kb
Host smart-05d9cc4d-eba5-49ed-9366-2373f221ca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864344607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3864344607
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1489366944
Short name T191
Test name
Test status
Simulation time 576938775 ps
CPU time 0.95 seconds
Started Jan 03 12:50:57 PM PST 24
Finished Jan 03 12:51:19 PM PST 24
Peak memory 182656 kb
Host smart-a67a7326-1766-4c7c-b007-3f194988b392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489366944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1489366944
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1707490189
Short name T203
Test name
Test status
Simulation time 86693589338 ps
CPU time 71.11 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:52:15 PM PST 24
Peak memory 194160 kb
Host smart-91674164-5b17-46cd-a2a8-f01d255becc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707490189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1707490189
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2826117776
Short name T41
Test name
Test status
Simulation time 304803756879 ps
CPU time 572.79 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 01:00:37 PM PST 24
Peak memory 197916 kb
Host smart-400969d4-b268-45bd-bab5-49cff616714a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826117776 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2826117776
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.368378396
Short name T102
Test name
Test status
Simulation time 387571185 ps
CPU time 0.66 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 182708 kb
Host smart-f754b925-f54a-4d7c-a130-0089f01e486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368378396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.368378396
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.3497270468
Short name T225
Test name
Test status
Simulation time 2197228873 ps
CPU time 1.36 seconds
Started Jan 03 12:50:29 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 182644 kb
Host smart-dab70bfb-3451-401f-9a21-ba331b5320cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497270468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.3497270468
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3242998481
Short name T173
Test name
Test status
Simulation time 409207222 ps
CPU time 0.72 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 182596 kb
Host smart-a63326a9-5b1b-450a-a35d-4877a0d2edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242998481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3242998481
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1304597000
Short name T22
Test name
Test status
Simulation time 82760889962 ps
CPU time 11.8 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:28 PM PST 24
Peak memory 192956 kb
Host smart-1cdc04ca-5b5c-4bdd-ad64-637276677651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304597000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1304597000
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.204156571
Short name T241
Test name
Test status
Simulation time 143473304609 ps
CPU time 267.06 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:55:32 PM PST 24
Peak memory 197576 kb
Host smart-df601168-2ed5-4c12-a7c5-a29c27c11c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204156571 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.204156571
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3138356995
Short name T199
Test name
Test status
Simulation time 401069472 ps
CPU time 0.81 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 182728 kb
Host smart-271b9b27-fea8-4789-a08a-bc9a380dd7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138356995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3138356995
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3346004887
Short name T4
Test name
Test status
Simulation time 35600003236 ps
CPU time 55.01 seconds
Started Jan 03 12:50:35 PM PST 24
Finished Jan 03 12:51:53 PM PST 24
Peak memory 182740 kb
Host smart-2c014b09-4364-4d90-b4b0-1649ed5863ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346004887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3346004887
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.714953713
Short name T134
Test name
Test status
Simulation time 439984417 ps
CPU time 0.65 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 182556 kb
Host smart-24cd96b2-ddaf-4561-b881-973836136ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714953713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.714953713
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3347518136
Short name T216
Test name
Test status
Simulation time 4512785461 ps
CPU time 4.56 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:09 PM PST 24
Peak memory 194108 kb
Host smart-47193e16-02a3-4081-a77a-3084e316b853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347518136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3347518136
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.785322325
Short name T285
Test name
Test status
Simulation time 357570235446 ps
CPU time 946.12 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 01:07:05 PM PST 24
Peak memory 211380 kb
Host smart-06297b17-ebeb-4e28-9199-96b9a87e9a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785322325 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.785322325
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1179645488
Short name T266
Test name
Test status
Simulation time 488295593 ps
CPU time 0.82 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 182652 kb
Host smart-2d590fcf-101e-4f3d-b459-84a2392951df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179645488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1179645488
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.526272071
Short name T130
Test name
Test status
Simulation time 13478721275 ps
CPU time 1.5 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:07 PM PST 24
Peak memory 182696 kb
Host smart-56ed021f-79a3-4c6b-b7dc-2d33eceaea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526272071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.526272071
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1140077605
Short name T175
Test name
Test status
Simulation time 395502704 ps
CPU time 0.66 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 182588 kb
Host smart-1ee73acf-ca72-4baa-9d67-ed556c11b3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140077605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1140077605
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.485232605
Short name T170
Test name
Test status
Simulation time 19251482356 ps
CPU time 22.37 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 193144 kb
Host smart-48b92fab-f505-4822-ac9b-9f5b7b5b9891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485232605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.485232605
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3236497991
Short name T220
Test name
Test status
Simulation time 58375511223 ps
CPU time 221.98 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:55:29 PM PST 24
Peak memory 195988 kb
Host smart-4a83b73e-1979-4a06-9a5f-e979b6a804e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236497991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3236497991
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3569386705
Short name T262
Test name
Test status
Simulation time 477509963 ps
CPU time 0.6 seconds
Started Jan 03 12:51:17 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 182232 kb
Host smart-0617b705-071b-43ff-b257-2c9cb3ed3bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569386705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3569386705
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1319020900
Short name T51
Test name
Test status
Simulation time 9683614500 ps
CPU time 3.69 seconds
Started Jan 03 12:51:20 PM PST 24
Finished Jan 03 12:51:40 PM PST 24
Peak memory 182460 kb
Host smart-25ff0efc-911d-4d78-bdaa-dc04ed15c136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319020900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1319020900
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1823356502
Short name T14
Test name
Test status
Simulation time 7479052308 ps
CPU time 6.66 seconds
Started Jan 03 12:50:34 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 215008 kb
Host smart-a6496744-2014-4506-91a7-0a4eb12fcb44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823356502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1823356502
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.4114324187
Short name T236
Test name
Test status
Simulation time 468430466 ps
CPU time 0.75 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 182452 kb
Host smart-5f42e60f-cf8c-4234-bfc3-6f9dbacb06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114324187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.4114324187
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.376597422
Short name T270
Test name
Test status
Simulation time 185384715011 ps
CPU time 67.02 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 192996 kb
Host smart-f880db20-9b4e-40b1-ac88-2041a6554cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376597422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.376597422
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3635001915
Short name T104
Test name
Test status
Simulation time 580333356 ps
CPU time 1.15 seconds
Started Jan 03 12:50:20 PM PST 24
Finished Jan 03 12:50:43 PM PST 24
Peak memory 182768 kb
Host smart-3c3961de-54fc-4cf9-ab3c-eed1b3cf1b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635001915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3635001915
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1756114871
Short name T38
Test name
Test status
Simulation time 20252324753 ps
CPU time 27.24 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 182776 kb
Host smart-b4e6e040-2ebf-44d9-b30c-fee2d38bee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756114871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1756114871
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.291203151
Short name T195
Test name
Test status
Simulation time 517219539 ps
CPU time 0.75 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:50:57 PM PST 24
Peak memory 182604 kb
Host smart-d7533d6e-bf8a-48a4-a642-d8b2509211da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291203151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.291203151
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3257463994
Short name T108
Test name
Test status
Simulation time 230534734419 ps
CPU time 80.21 seconds
Started Jan 03 12:52:06 PM PST 24
Finished Jan 03 12:53:33 PM PST 24
Peak memory 182532 kb
Host smart-26210dc3-0a79-44c7-bcaf-f83824f59af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257463994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3257463994
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1663570097
Short name T210
Test name
Test status
Simulation time 138084182173 ps
CPU time 250.11 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:55:17 PM PST 24
Peak memory 197712 kb
Host smart-d773e06f-4d0e-4c23-abb6-fac1b0cd3127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663570097 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1663570097
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3372880581
Short name T149
Test name
Test status
Simulation time 455012277 ps
CPU time 0.69 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 182744 kb
Host smart-f1822e34-4017-41e5-bc29-31e8dd58aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372880581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3372880581
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3486242979
Short name T131
Test name
Test status
Simulation time 19886667132 ps
CPU time 7.64 seconds
Started Jan 03 12:50:34 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 182700 kb
Host smart-57ba5669-0284-4dc3-8209-b67b6f24e8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486242979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3486242979
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.47020823
Short name T7
Test name
Test status
Simulation time 516004248 ps
CPU time 0.61 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 182836 kb
Host smart-a4f1bc0a-4439-4c62-bb6a-cabb5bb0e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47020823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.47020823
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1192859338
Short name T28
Test name
Test status
Simulation time 205485601760 ps
CPU time 141.98 seconds
Started Jan 03 12:51:11 PM PST 24
Finished Jan 03 12:53:51 PM PST 24
Peak memory 182712 kb
Host smart-5b7a0848-884b-4c95-afb7-483c09d763f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192859338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1192859338
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1351329874
Short name T40
Test name
Test status
Simulation time 235187833053 ps
CPU time 655.76 seconds
Started Jan 03 12:51:09 PM PST 24
Finished Jan 03 01:02:23 PM PST 24
Peak memory 199592 kb
Host smart-fdc551fa-ddd2-42ce-ae3d-79fc78079a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351329874 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1351329874
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2956258217
Short name T265
Test name
Test status
Simulation time 514064624 ps
CPU time 0.58 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 182764 kb
Host smart-8a454696-f0f3-4885-a84d-d7076bf94552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956258217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2956258217
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1671539510
Short name T204
Test name
Test status
Simulation time 1960158379 ps
CPU time 3.25 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 182580 kb
Host smart-a5b681e6-8ed7-4067-bc7f-493443e47e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671539510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1671539510
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1867655746
Short name T129
Test name
Test status
Simulation time 615033323 ps
CPU time 0.75 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 182600 kb
Host smart-1e5ac755-83d7-4fea-9934-c2784fd8e6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867655746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1867655746
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2056894120
Short name T8
Test name
Test status
Simulation time 178776383955 ps
CPU time 76.93 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 192904 kb
Host smart-2b8b3ab1-6ab4-4bde-a071-8b192f86bc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056894120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2056894120
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1120362024
Short name T83
Test name
Test status
Simulation time 348631236817 ps
CPU time 663.65 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 01:02:26 PM PST 24
Peak memory 199012 kb
Host smart-dc7f8019-9e83-44c5-95ac-19a0a1fbbfd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120362024 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1120362024
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1623749408
Short name T52
Test name
Test status
Simulation time 554817264 ps
CPU time 0.65 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 182724 kb
Host smart-a5e4a40e-09a6-4903-a035-cb5494566d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623749408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1623749408
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.260337135
Short name T169
Test name
Test status
Simulation time 832532545 ps
CPU time 1.77 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:51:19 PM PST 24
Peak memory 182516 kb
Host smart-864cdce2-8e28-485b-af60-d258d65e3619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260337135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.260337135
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3257219162
Short name T145
Test name
Test status
Simulation time 601172059 ps
CPU time 1.42 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 182736 kb
Host smart-61d5ebaf-33c0-4dde-8d73-eed241f6747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257219162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3257219162
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1693304019
Short name T273
Test name
Test status
Simulation time 215374299332 ps
CPU time 38.43 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 182696 kb
Host smart-f01a6032-2445-405c-af25-a50aeb9e1c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693304019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1693304019
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2656803090
Short name T10
Test name
Test status
Simulation time 405624537 ps
CPU time 0.86 seconds
Started Jan 03 12:51:08 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 182700 kb
Host smart-57230957-55a1-4d27-9afb-0c4008170f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656803090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2656803090
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3249018141
Short name T162
Test name
Test status
Simulation time 19048162730 ps
CPU time 7.38 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 182820 kb
Host smart-cd8b37fb-6e59-4bcc-a868-9e589ceaa7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249018141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3249018141
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1403979930
Short name T186
Test name
Test status
Simulation time 535676719 ps
CPU time 0.72 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182668 kb
Host smart-a8f3c0f9-9539-47ce-962b-c48c498e066b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403979930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1403979930
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.373264844
Short name T254
Test name
Test status
Simulation time 551624460 ps
CPU time 1.24 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:02 PM PST 24
Peak memory 182748 kb
Host smart-8bd7dfc7-e498-42cd-97f6-38f06b998dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373264844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.373264844
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3587510124
Short name T165
Test name
Test status
Simulation time 41154638908 ps
CPU time 63.45 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:52:19 PM PST 24
Peak memory 182768 kb
Host smart-16957649-c69a-4836-804a-d8350876a04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587510124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3587510124
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1952941667
Short name T163
Test name
Test status
Simulation time 490978540 ps
CPU time 0.85 seconds
Started Jan 03 12:51:08 PM PST 24
Finished Jan 03 12:51:28 PM PST 24
Peak memory 182520 kb
Host smart-4ff8716c-920f-439e-ae9b-c6d223a81317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952941667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1952941667
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.848572435
Short name T29
Test name
Test status
Simulation time 122553409892 ps
CPU time 90.72 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:52:25 PM PST 24
Peak memory 192752 kb
Host smart-a287161f-265e-4c49-84e8-f94e02fe1f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848572435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.848572435
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.972473957
Short name T87
Test name
Test status
Simulation time 122195169478 ps
CPU time 225.83 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:55:07 PM PST 24
Peak memory 197620 kb
Host smart-cd79eb16-3ce0-4c07-98c8-228b6c02b16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972473957 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.972473957
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4127753759
Short name T97
Test name
Test status
Simulation time 529448302 ps
CPU time 0.58 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 12:51:19 PM PST 24
Peak memory 182592 kb
Host smart-62c3e4c2-5f70-4d08-bd52-49a9f3bcb317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127753759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4127753759
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3137377053
Short name T208
Test name
Test status
Simulation time 26081644275 ps
CPU time 22.73 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:30 PM PST 24
Peak memory 182744 kb
Host smart-1282766e-a6ef-4841-a3ef-40bc6bcd7b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137377053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3137377053
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.592426086
Short name T30
Test name
Test status
Simulation time 444897494 ps
CPU time 0.75 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182600 kb
Host smart-1653076b-3df9-4032-b9cd-2618273680cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592426086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.592426086
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.248847412
Short name T45
Test name
Test status
Simulation time 32420905497 ps
CPU time 331.64 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:56:35 PM PST 24
Peak memory 197644 kb
Host smart-b3bb8cd2-deba-4bb0-a005-3604137ea487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248847412 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.248847412
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3117771691
Short name T20
Test name
Test status
Simulation time 501521309 ps
CPU time 0.71 seconds
Started Jan 03 12:50:55 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182684 kb
Host smart-7bb0b067-7739-44ed-8879-07d9ae07e486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117771691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3117771691
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3920188077
Short name T177
Test name
Test status
Simulation time 53849705804 ps
CPU time 37.96 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 12:51:57 PM PST 24
Peak memory 182776 kb
Host smart-016dfdc1-14dc-4c74-ba4b-8690dec18f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920188077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3920188077
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3379577404
Short name T6
Test name
Test status
Simulation time 387361208 ps
CPU time 0.67 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 182584 kb
Host smart-6e869484-568d-4dcf-a42e-5d9f45661c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379577404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3379577404
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.2621884898
Short name T221
Test name
Test status
Simulation time 70136093873 ps
CPU time 28.84 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:52 PM PST 24
Peak memory 182728 kb
Host smart-baa2b51b-e60b-4d4d-bf68-aec95add7b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621884898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.2621884898
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4029171451
Short name T86
Test name
Test status
Simulation time 11318720871 ps
CPU time 82.87 seconds
Started Jan 03 12:51:20 PM PST 24
Finished Jan 03 12:52:59 PM PST 24
Peak memory 197596 kb
Host smart-c206e118-9642-483d-9ff3-62e03090e526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029171451 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4029171451
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2773160655
Short name T118
Test name
Test status
Simulation time 526288277 ps
CPU time 1.36 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 182704 kb
Host smart-f3d5d4b3-ca42-4240-b78e-da0effa6d4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773160655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2773160655
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3918981235
Short name T271
Test name
Test status
Simulation time 61570421519 ps
CPU time 23.77 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:46 PM PST 24
Peak memory 182740 kb
Host smart-6c969fa6-ab21-473f-b51c-bb18b399f54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918981235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3918981235
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1397681328
Short name T255
Test name
Test status
Simulation time 455555913 ps
CPU time 1.23 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 182652 kb
Host smart-ac657ec8-d377-4b6e-b091-363f7998cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397681328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1397681328
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3306065993
Short name T282
Test name
Test status
Simulation time 278380375653 ps
CPU time 108.64 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:52:59 PM PST 24
Peak memory 192972 kb
Host smart-b41d2e71-c79c-4774-88ab-bab1ef91410b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306065993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3306065993
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3206979000
Short name T280
Test name
Test status
Simulation time 95698608465 ps
CPU time 128.46 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:53:30 PM PST 24
Peak memory 197732 kb
Host smart-f6e7b23c-f14a-4339-a3a4-bdafe4a898fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206979000 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3206979000
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.106108420
Short name T157
Test name
Test status
Simulation time 603375635 ps
CPU time 0.79 seconds
Started Jan 03 12:51:13 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 182704 kb
Host smart-b2f94c40-ca29-45c7-a96c-863cd72d987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106108420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.106108420
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3379422743
Short name T248
Test name
Test status
Simulation time 30541201774 ps
CPU time 20.35 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:26 PM PST 24
Peak memory 182740 kb
Host smart-5c9ded42-e5c0-4fd3-b2ab-d9920b105a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379422743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3379422743
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1642777647
Short name T143
Test name
Test status
Simulation time 352561330 ps
CPU time 1.02 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 182632 kb
Host smart-fcd398f5-e768-4daa-897d-4f2a0e15c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642777647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1642777647
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.4213849382
Short name T213
Test name
Test status
Simulation time 218958047490 ps
CPU time 33.23 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 193040 kb
Host smart-f1eaf995-7f5f-418d-a5df-65776c6aa0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213849382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.4213849382
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1847148027
Short name T206
Test name
Test status
Simulation time 33136277087 ps
CPU time 265.17 seconds
Started Jan 03 12:50:57 PM PST 24
Finished Jan 03 12:55:43 PM PST 24
Peak memory 197656 kb
Host smart-734c3f79-7555-4d12-888a-54f63dc874a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847148027 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1847148027
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.792503256
Short name T46
Test name
Test status
Simulation time 447288678 ps
CPU time 0.6 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 182676 kb
Host smart-49a20884-2596-47aa-8b48-fd81cdd01ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792503256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.792503256
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3287140378
Short name T284
Test name
Test status
Simulation time 17973156994 ps
CPU time 28.43 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:51:43 PM PST 24
Peak memory 182768 kb
Host smart-86911b3a-11bf-4764-b469-9c5628db58b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287140378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3287140378
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.4116217842
Short name T19
Test name
Test status
Simulation time 8090478025 ps
CPU time 10.56 seconds
Started Jan 03 12:50:32 PM PST 24
Finished Jan 03 12:51:06 PM PST 24
Peak memory 215092 kb
Host smart-0b3ce27c-4b25-4bce-9a33-7563d2181776
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116217842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.4116217842
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.42291573
Short name T137
Test name
Test status
Simulation time 458539179 ps
CPU time 0.68 seconds
Started Jan 03 12:50:22 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 182696 kb
Host smart-349130a3-0864-45cc-b2df-d412ee614a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42291573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.42291573
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2167773521
Short name T110
Test name
Test status
Simulation time 94244392701 ps
CPU time 71.21 seconds
Started Jan 03 12:50:35 PM PST 24
Finished Jan 03 12:52:10 PM PST 24
Peak memory 193960 kb
Host smart-0a01fd40-e7ff-4a25-9c52-8f87e8046d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167773521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2167773521
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.3273173806
Short name T84
Test name
Test status
Simulation time 88186466501 ps
CPU time 744.27 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 01:03:34 PM PST 24
Peak memory 199228 kb
Host smart-ff190d59-182e-4aa3-83b5-176a869246c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273173806 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.3273173806
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1188860867
Short name T276
Test name
Test status
Simulation time 516392090 ps
CPU time 0.69 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 12:51:28 PM PST 24
Peak memory 182708 kb
Host smart-d1a2aa16-173f-4f8e-82b9-b42e8602fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188860867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1188860867
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2065228742
Short name T239
Test name
Test status
Simulation time 25969227373 ps
CPU time 37.44 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:51:47 PM PST 24
Peak memory 182708 kb
Host smart-15d3397e-30e0-46f2-b623-ce54d97213cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065228742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2065228742
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1069306958
Short name T189
Test name
Test status
Simulation time 562887907 ps
CPU time 0.75 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 182652 kb
Host smart-bce1eabb-4a99-4c30-8540-1ebd375d714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069306958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1069306958
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2374084269
Short name T100
Test name
Test status
Simulation time 206880375945 ps
CPU time 55.54 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:51:56 PM PST 24
Peak memory 182836 kb
Host smart-022c8c53-4699-4bc7-8b1c-09fe88521886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374084269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2374084269
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1862550658
Short name T43
Test name
Test status
Simulation time 21427120050 ps
CPU time 142.76 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:53:38 PM PST 24
Peak memory 197572 kb
Host smart-b496b52c-bb29-4931-8973-e3089b63f9fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862550658 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1862550658
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1370135929
Short name T244
Test name
Test status
Simulation time 544164972 ps
CPU time 0.7 seconds
Started Jan 03 12:51:18 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 182720 kb
Host smart-019604fc-1d68-4eb6-b60c-d07a8ce346ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370135929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1370135929
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2984634632
Short name T226
Test name
Test status
Simulation time 15645465089 ps
CPU time 3.66 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 182772 kb
Host smart-1f9f7e69-6e0d-472c-b8cc-d31eb13b856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984634632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2984634632
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1206277158
Short name T53
Test name
Test status
Simulation time 522541321 ps
CPU time 0.66 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:11 PM PST 24
Peak memory 182668 kb
Host smart-c41c1b69-c8f8-419c-80b7-6a3221f9f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206277158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1206277158
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3282226834
Short name T172
Test name
Test status
Simulation time 508200805315 ps
CPU time 366.3 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:57:14 PM PST 24
Peak memory 192880 kb
Host smart-6b5a80ba-1cc4-4b81-931a-a82e98aa3474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282226834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3282226834
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.53221342
Short name T256
Test name
Test status
Simulation time 45046429317 ps
CPU time 449.04 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:58:45 PM PST 24
Peak memory 197524 kb
Host smart-bce60272-e54e-46d1-b291-55556692099e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53221342 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.53221342
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.844378494
Short name T179
Test name
Test status
Simulation time 551157541 ps
CPU time 0.67 seconds
Started Jan 03 12:51:18 PM PST 24
Finished Jan 03 12:51:35 PM PST 24
Peak memory 182780 kb
Host smart-30ce2d8f-aa26-44f4-87e5-be36d515b481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844378494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.844378494
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1154170461
Short name T286
Test name
Test status
Simulation time 22472314682 ps
CPU time 22.03 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 182664 kb
Host smart-28ff073b-6ecd-49be-b7aa-a85d8675fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154170461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1154170461
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3341957404
Short name T128
Test name
Test status
Simulation time 502894175 ps
CPU time 0.95 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182596 kb
Host smart-21a39b79-0c2e-4fd3-adf9-8d32e54e83d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341957404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3341957404
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3313185861
Short name T218
Test name
Test status
Simulation time 206437248066 ps
CPU time 315.41 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:56:39 PM PST 24
Peak memory 192952 kb
Host smart-9184f004-3247-4df9-a62d-a4e03e8c5a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313185861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3313185861
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2360036151
Short name T231
Test name
Test status
Simulation time 50982663096 ps
CPU time 220.42 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:54:51 PM PST 24
Peak memory 197724 kb
Host smart-e70f92b1-6a73-4c36-9b60-a3e7b86148af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360036151 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2360036151
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.4062470673
Short name T142
Test name
Test status
Simulation time 585298648 ps
CPU time 0.75 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 182632 kb
Host smart-37959d20-630e-4451-b15a-efc555a5205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062470673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.4062470673
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3419236925
Short name T201
Test name
Test status
Simulation time 10831831862 ps
CPU time 4.57 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 182700 kb
Host smart-d5471255-a284-4c18-b14e-6730bfb57b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419236925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3419236925
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.3855717203
Short name T56
Test name
Test status
Simulation time 518198454 ps
CPU time 1.34 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 182720 kb
Host smart-b625d19f-1547-480b-8a4e-9b7d7c1a8410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855717203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.3855717203
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3334113517
Short name T106
Test name
Test status
Simulation time 141661583120 ps
CPU time 229.23 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:55:10 PM PST 24
Peak memory 197692 kb
Host smart-318562b6-be52-4424-b29a-71d2b6825877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334113517 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3334113517
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2961562174
Short name T267
Test name
Test status
Simulation time 519276351 ps
CPU time 0.87 seconds
Started Jan 03 12:50:57 PM PST 24
Finished Jan 03 12:51:19 PM PST 24
Peak memory 182764 kb
Host smart-71a613f0-a215-48e6-80bc-6adb1526d9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961562174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2961562174
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1559612656
Short name T287
Test name
Test status
Simulation time 24117137557 ps
CPU time 28.4 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:39 PM PST 24
Peak memory 182656 kb
Host smart-2d627fe3-78b6-4e07-a0b5-e82d6cd322b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559612656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1559612656
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.4218217976
Short name T230
Test name
Test status
Simulation time 383218536 ps
CPU time 1.16 seconds
Started Jan 03 12:51:14 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 182520 kb
Host smart-4da49c72-bcd5-4873-9ac6-ab3524eaff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218217976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.4218217976
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2852224155
Short name T269
Test name
Test status
Simulation time 78172812906 ps
CPU time 67.32 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 12:52:16 PM PST 24
Peak memory 193268 kb
Host smart-eceaa20a-4bf6-4be2-9c39-d131ff0c78f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852224155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2852224155
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2667740244
Short name T23
Test name
Test status
Simulation time 22594385818 ps
CPU time 83.58 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:52:34 PM PST 24
Peak memory 197636 kb
Host smart-160eda61-0aa4-4300-a737-881f4f4f591f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667740244 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2667740244
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1737960702
Short name T120
Test name
Test status
Simulation time 569943657 ps
CPU time 0.73 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:51:15 PM PST 24
Peak memory 182764 kb
Host smart-c499d3d3-47ff-4b76-a201-5ee6aa4765ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737960702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1737960702
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2200503973
Short name T233
Test name
Test status
Simulation time 29465373853 ps
CPU time 15.15 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 182800 kb
Host smart-3c70ec13-55b2-4ce9-9098-145344bcbc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200503973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2200503973
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.201381201
Short name T160
Test name
Test status
Simulation time 547278488 ps
CPU time 1.47 seconds
Started Jan 03 12:50:44 PM PST 24
Finished Jan 03 12:51:09 PM PST 24
Peak memory 182544 kb
Host smart-06715f37-1355-494b-9a01-0e7a227ace8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201381201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.201381201
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3321954378
Short name T50
Test name
Test status
Simulation time 85092973077 ps
CPU time 30.91 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:33 PM PST 24
Peak memory 182744 kb
Host smart-daedb399-e6ac-4055-9d8d-bb0327e77064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321954378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3321954378
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1971819098
Short name T42
Test name
Test status
Simulation time 64333079547 ps
CPU time 170.11 seconds
Started Jan 03 12:50:44 PM PST 24
Finished Jan 03 12:53:58 PM PST 24
Peak memory 197668 kb
Host smart-c8683595-7866-4b3a-896d-925cbe6a88e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971819098 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1971819098
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.895254442
Short name T98
Test name
Test status
Simulation time 497423766 ps
CPU time 1.23 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182628 kb
Host smart-ded8834e-25fc-44b3-adec-1d8bc34440d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895254442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.895254442
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.928829375
Short name T211
Test name
Test status
Simulation time 16906662376 ps
CPU time 6.87 seconds
Started Jan 03 12:50:44 PM PST 24
Finished Jan 03 12:51:15 PM PST 24
Peak memory 182720 kb
Host smart-dd1f71a3-b713-44b4-af7c-ca37eaa1e5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928829375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.928829375
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1690806326
Short name T138
Test name
Test status
Simulation time 361091595 ps
CPU time 0.95 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 182516 kb
Host smart-102821cf-075f-4bd4-9f6e-0da8be1b050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690806326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1690806326
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3890344291
Short name T127
Test name
Test status
Simulation time 211396042337 ps
CPU time 148.2 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:53:43 PM PST 24
Peak memory 193080 kb
Host smart-27dc69e1-554e-4803-b767-f8ae10091fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890344291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3890344291
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3661390516
Short name T107
Test name
Test status
Simulation time 23434695357 ps
CPU time 184.6 seconds
Started Jan 03 12:50:58 PM PST 24
Finished Jan 03 12:54:24 PM PST 24
Peak memory 197592 kb
Host smart-2b01a23e-1dbd-49c8-a2f3-a902bf4fca4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661390516 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3661390516
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1035165377
Short name T281
Test name
Test status
Simulation time 363712664 ps
CPU time 1.03 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:51:25 PM PST 24
Peak memory 182724 kb
Host smart-108e8dca-eabe-409b-8a18-8e87a48e9bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035165377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1035165377
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3758671578
Short name T200
Test name
Test status
Simulation time 59011884775 ps
CPU time 82.56 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:52:31 PM PST 24
Peak memory 182612 kb
Host smart-3fef5993-5b5a-4b6a-86b3-d857fc4ca1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758671578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3758671578
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2943808195
Short name T202
Test name
Test status
Simulation time 606175175 ps
CPU time 0.71 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:51:05 PM PST 24
Peak memory 182512 kb
Host smart-b6c19a5e-4337-4858-947d-60aa98637f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943808195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2943808195
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2807275368
Short name T105
Test name
Test status
Simulation time 155022150672 ps
CPU time 72.43 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:52:34 PM PST 24
Peak memory 193012 kb
Host smart-5d74feb8-704d-4e29-8fbe-83fd35fecf0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807275368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2807275368
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2861652880
Short name T88
Test name
Test status
Simulation time 84723158166 ps
CPU time 586.2 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 01:00:58 PM PST 24
Peak memory 197664 kb
Host smart-8f85d88d-4afe-4ae3-a3b8-05f8a48d19ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861652880 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2861652880
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2381596503
Short name T171
Test name
Test status
Simulation time 382646401 ps
CPU time 1.16 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 182664 kb
Host smart-764a3292-4f16-4cd0-8277-da7c8e79ba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381596503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2381596503
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.343209155
Short name T251
Test name
Test status
Simulation time 16498144558 ps
CPU time 24.74 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:51:40 PM PST 24
Peak memory 182668 kb
Host smart-aa1672f6-cbdc-492f-8ad1-b43e53b0d4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343209155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.343209155
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3401365600
Short name T135
Test name
Test status
Simulation time 417921226 ps
CPU time 0.68 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:51:15 PM PST 24
Peak memory 182636 kb
Host smart-51411d6d-cbeb-4019-b9e8-5012474ccefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401365600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3401365600
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2069708802
Short name T245
Test name
Test status
Simulation time 73820558873 ps
CPU time 27.42 seconds
Started Jan 03 12:50:33 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 182832 kb
Host smart-ff71c4d5-41aa-41cf-b45b-66bb3a408f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069708802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2069708802
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1131594747
Short name T125
Test name
Test status
Simulation time 380153050 ps
CPU time 1.09 seconds
Started Jan 03 12:51:11 PM PST 24
Finished Jan 03 12:51:30 PM PST 24
Peak memory 182712 kb
Host smart-99890574-3d71-4c8f-8319-a5c89d38ff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131594747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1131594747
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.684211085
Short name T190
Test name
Test status
Simulation time 20689195979 ps
CPU time 7.74 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:24 PM PST 24
Peak memory 182584 kb
Host smart-05e31eda-40bd-4a7e-ad3c-ba67f6f6a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684211085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.684211085
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.148488617
Short name T49
Test name
Test status
Simulation time 369084776 ps
CPU time 0.68 seconds
Started Jan 03 12:51:19 PM PST 24
Finished Jan 03 12:51:36 PM PST 24
Peak memory 182512 kb
Host smart-800c7624-0688-4394-95a3-d03f8b3c682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148488617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.148488617
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3173342909
Short name T278
Test name
Test status
Simulation time 70895318477 ps
CPU time 140.53 seconds
Started Jan 03 12:51:07 PM PST 24
Finished Jan 03 12:53:46 PM PST 24
Peak memory 197640 kb
Host smart-d644b9db-219c-4298-854b-acbdf712cb5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173342909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3173342909
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1027250173
Short name T261
Test name
Test status
Simulation time 377472873 ps
CPU time 0.79 seconds
Started Jan 03 12:50:44 PM PST 24
Finished Jan 03 12:51:08 PM PST 24
Peak memory 182652 kb
Host smart-89cf4ee2-f765-44a2-8f2f-e89fde5a476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027250173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1027250173
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3399225530
Short name T133
Test name
Test status
Simulation time 12499517705 ps
CPU time 10.16 seconds
Started Jan 03 12:50:15 PM PST 24
Finished Jan 03 12:50:47 PM PST 24
Peak memory 182728 kb
Host smart-12c2bfdb-da14-4386-adf8-4088acbb5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399225530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3399225530
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.744389127
Short name T15
Test name
Test status
Simulation time 8376178791 ps
CPU time 4.28 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 214900 kb
Host smart-5c055683-b1c7-443a-bae3-d1997ceecd9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744389127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.744389127
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4059858488
Short name T141
Test name
Test status
Simulation time 440390054 ps
CPU time 0.82 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:03 PM PST 24
Peak memory 182508 kb
Host smart-c32b2f93-03e3-43ce-b4ec-9a945ed8af74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059858488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4059858488
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2574532125
Short name T17
Test name
Test status
Simulation time 227355388455 ps
CPU time 172.94 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:53:58 PM PST 24
Peak memory 192976 kb
Host smart-5d65f089-9c99-4395-b0fd-536c0d641730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574532125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2574532125
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1251153762
Short name T217
Test name
Test status
Simulation time 725165359614 ps
CPU time 315.84 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:56:21 PM PST 24
Peak memory 197648 kb
Host smart-e1564172-ace2-4297-be96-254eef20c0b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251153762 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1251153762
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2204481510
Short name T215
Test name
Test status
Simulation time 634475507 ps
CPU time 0.71 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:51:04 PM PST 24
Peak memory 182600 kb
Host smart-2fe6815c-70fc-4b71-b898-e947894522e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204481510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2204481510
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2534174908
Short name T187
Test name
Test status
Simulation time 3604866133 ps
CPU time 5.63 seconds
Started Jan 03 12:50:42 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 182808 kb
Host smart-d487d344-3eac-47e5-af6d-38e8d2c129df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534174908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2534174908
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1638287699
Short name T272
Test name
Test status
Simulation time 491595140 ps
CPU time 0.69 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182568 kb
Host smart-f9d2abcb-dad7-49ff-b484-41a1f48b5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638287699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1638287699
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1020651946
Short name T119
Test name
Test status
Simulation time 175624313592 ps
CPU time 133.72 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:53:34 PM PST 24
Peak memory 182720 kb
Host smart-0d4d22c5-a76d-46e9-a6d5-f4f88e54b289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020651946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1020651946
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.28586981
Short name T32
Test name
Test status
Simulation time 234598257432 ps
CPU time 655.96 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 01:01:58 PM PST 24
Peak memory 199864 kb
Host smart-9871f6ae-b10b-48d2-9c39-0f392e50f895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28586981 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.28586981
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2629357173
Short name T122
Test name
Test status
Simulation time 398404934 ps
CPU time 0.7 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 182592 kb
Host smart-418b0912-b598-43a9-ae58-8c488753cf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629357173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2629357173
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2793827215
Short name T279
Test name
Test status
Simulation time 22073943211 ps
CPU time 32.72 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:45 PM PST 24
Peak memory 182692 kb
Host smart-76ca3720-c8aa-4205-8f52-acf491839d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793827215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2793827215
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4103644364
Short name T27
Test name
Test status
Simulation time 555858990 ps
CPU time 1.3 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182528 kb
Host smart-0a959aa1-e771-4cf7-8575-6c44e96cb00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103644364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4103644364
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3055244851
Short name T47
Test name
Test status
Simulation time 340254086486 ps
CPU time 120.12 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:53:18 PM PST 24
Peak memory 182776 kb
Host smart-70e5872c-8d09-4b9a-8c22-ee7a0e88260a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055244851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3055244851
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2728110556
Short name T246
Test name
Test status
Simulation time 635788734847 ps
CPU time 711 seconds
Started Jan 03 12:51:11 PM PST 24
Finished Jan 03 01:03:20 PM PST 24
Peak memory 200496 kb
Host smart-b5c06be1-a1a6-4501-94bf-1e310ec50cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728110556 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2728110556
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2970710195
Short name T152
Test name
Test status
Simulation time 367918625 ps
CPU time 1.1 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:51:25 PM PST 24
Peak memory 182712 kb
Host smart-0e4934e8-9291-4d96-ac59-a1869a94167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970710195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2970710195
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.4212733340
Short name T176
Test name
Test status
Simulation time 34070275938 ps
CPU time 52.45 seconds
Started Jan 03 12:50:46 PM PST 24
Finished Jan 03 12:52:02 PM PST 24
Peak memory 182796 kb
Host smart-0db9bbb8-ccfc-4c50-892c-a19d85d4ce58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212733340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.4212733340
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1279583296
Short name T159
Test name
Test status
Simulation time 402664142 ps
CPU time 0.67 seconds
Started Jan 03 12:50:50 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182648 kb
Host smart-13088c1b-d788-4aec-ba24-f07730805794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279583296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1279583296
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.4049159114
Short name T250
Test name
Test status
Simulation time 19310147003 ps
CPU time 32.15 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:40 PM PST 24
Peak memory 192976 kb
Host smart-7f2b8f9c-616f-4c24-a4cc-01543ad1cd1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049159114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.4049159114
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2290907680
Short name T275
Test name
Test status
Simulation time 116060966817 ps
CPU time 430.26 seconds
Started Jan 03 12:50:57 PM PST 24
Finished Jan 03 12:58:28 PM PST 24
Peak memory 197620 kb
Host smart-df0554ce-6a3e-46f0-9a43-c73c37b35deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290907680 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2290907680
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3862416047
Short name T116
Test name
Test status
Simulation time 411419521 ps
CPU time 0.87 seconds
Started Jan 03 12:51:07 PM PST 24
Finished Jan 03 12:51:27 PM PST 24
Peak memory 182740 kb
Host smart-bc646252-02e4-4cb5-8c4e-6bb2b7f2bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862416047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3862416047
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2206472616
Short name T153
Test name
Test status
Simulation time 58907273880 ps
CPU time 93.24 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 182732 kb
Host smart-f6af767f-d1c1-4545-9495-31a5a792b652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206472616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2206472616
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3232790152
Short name T54
Test name
Test status
Simulation time 487134247 ps
CPU time 1.22 seconds
Started Jan 03 12:51:12 PM PST 24
Finished Jan 03 12:51:31 PM PST 24
Peak memory 182588 kb
Host smart-d208b9c5-e1a5-4cc4-b9ad-bfc1385515f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232790152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3232790152
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3152467761
Short name T167
Test name
Test status
Simulation time 14686701018 ps
CPU time 9.57 seconds
Started Jan 03 12:51:05 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 182768 kb
Host smart-e1d31003-5d55-4f41-b7ff-fe8b8b07b2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152467761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3152467761
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2798217853
Short name T101
Test name
Test status
Simulation time 146712151508 ps
CPU time 209 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:54:45 PM PST 24
Peak memory 197704 kb
Host smart-d0595cef-8ced-4c21-b7d4-6959ce0e9743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798217853 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2798217853
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1623606168
Short name T121
Test name
Test status
Simulation time 416975624 ps
CPU time 1.09 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 182728 kb
Host smart-cb3a1c61-4be0-4aaf-b690-bbf7bc7ed978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623606168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1623606168
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2879024409
Short name T3
Test name
Test status
Simulation time 35075654561 ps
CPU time 28.98 seconds
Started Jan 03 12:51:04 PM PST 24
Finished Jan 03 12:51:53 PM PST 24
Peak memory 182700 kb
Host smart-442bedf2-be50-4f2e-97f6-7b5d815aa4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879024409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2879024409
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.4049816073
Short name T164
Test name
Test status
Simulation time 558632770 ps
CPU time 0.89 seconds
Started Jan 03 12:51:02 PM PST 24
Finished Jan 03 12:51:23 PM PST 24
Peak memory 182556 kb
Host smart-c5292f91-177e-4417-9a91-9f334fa44e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049816073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.4049816073
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1635774236
Short name T260
Test name
Test status
Simulation time 224459652623 ps
CPU time 58.72 seconds
Started Jan 03 12:50:52 PM PST 24
Finished Jan 03 12:52:13 PM PST 24
Peak memory 193012 kb
Host smart-f1a6de5c-ef68-4f31-b965-a61b9fbfa0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635774236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1635774236
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.440370565
Short name T112
Test name
Test status
Simulation time 17681011409 ps
CPU time 140.14 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:53:38 PM PST 24
Peak memory 197656 kb
Host smart-4eb598a5-3b57-4637-8bc9-9117e5d50a78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440370565 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.440370565
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3910918312
Short name T96
Test name
Test status
Simulation time 581409060 ps
CPU time 1.3 seconds
Started Jan 03 12:51:11 PM PST 24
Finished Jan 03 12:51:30 PM PST 24
Peak memory 182656 kb
Host smart-40e5c913-3b18-4a49-bf3d-576ca7555c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910918312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3910918312
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1019069624
Short name T238
Test name
Test status
Simulation time 33797366997 ps
CPU time 52.12 seconds
Started Jan 03 12:51:12 PM PST 24
Finished Jan 03 12:52:22 PM PST 24
Peak memory 182848 kb
Host smart-c8e3439a-dd51-471f-a83c-cda6b7a640c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019069624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1019069624
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3137080519
Short name T154
Test name
Test status
Simulation time 545484273 ps
CPU time 0.69 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 182628 kb
Host smart-59fd69dd-a172-4612-8d0a-7a7e732ef2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137080519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3137080519
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.109660872
Short name T243
Test name
Test status
Simulation time 90965070660 ps
CPU time 36.75 seconds
Started Jan 03 12:50:54 PM PST 24
Finished Jan 03 12:51:53 PM PST 24
Peak memory 182836 kb
Host smart-972cb540-254e-462e-9fc0-0c97d6bbabdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109660872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.109660872
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.623864142
Short name T223
Test name
Test status
Simulation time 317806544221 ps
CPU time 600.23 seconds
Started Jan 03 12:51:06 PM PST 24
Finished Jan 03 01:01:25 PM PST 24
Peak memory 198736 kb
Host smart-925d8b52-f706-4617-acbc-abeca1d49f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623864142 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.623864142
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2639783675
Short name T222
Test name
Test status
Simulation time 424313241 ps
CPU time 0.85 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182664 kb
Host smart-ce4a9f2c-dd79-4726-b1e1-400dccff042f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639783675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2639783675
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.731402702
Short name T26
Test name
Test status
Simulation time 23942599984 ps
CPU time 6.96 seconds
Started Jan 03 12:51:12 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 182792 kb
Host smart-3e37c129-7915-4ae1-80c2-ecdff48fe573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731402702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.731402702
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2462560564
Short name T5
Test name
Test status
Simulation time 486370294 ps
CPU time 0.71 seconds
Started Jan 03 12:50:48 PM PST 24
Finished Jan 03 12:51:12 PM PST 24
Peak memory 182656 kb
Host smart-bf1c487c-54b8-4568-9567-8d1d239841c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462560564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2462560564
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.324759806
Short name T259
Test name
Test status
Simulation time 90199838414 ps
CPU time 32.96 seconds
Started Jan 03 12:50:41 PM PST 24
Finished Jan 03 12:51:38 PM PST 24
Peak memory 182732 kb
Host smart-19e9741a-14ed-4220-8acb-1c901db1ece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324759806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.324759806
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2849384926
Short name T57
Test name
Test status
Simulation time 474941758661 ps
CPU time 655.45 seconds
Started Jan 03 12:51:03 PM PST 24
Finished Jan 03 01:02:18 PM PST 24
Peak memory 199828 kb
Host smart-26a3c683-1805-4bc4-a67d-8db69f618fab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849384926 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2849384926
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1503561313
Short name T115
Test name
Test status
Simulation time 401062163 ps
CPU time 0.83 seconds
Started Jan 03 12:50:56 PM PST 24
Finished Jan 03 12:51:18 PM PST 24
Peak memory 182676 kb
Host smart-b6d12741-2083-41fb-b3e1-595d9cb09db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503561313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1503561313
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2715487436
Short name T166
Test name
Test status
Simulation time 5212260723 ps
CPU time 4.76 seconds
Started Jan 03 12:51:27 PM PST 24
Finished Jan 03 12:51:45 PM PST 24
Peak memory 182796 kb
Host smart-e23ef1c2-874e-4d49-b37e-06a23bfc069c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715487436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2715487436
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3316175733
Short name T150
Test name
Test status
Simulation time 420520243 ps
CPU time 0.68 seconds
Started Jan 03 12:50:59 PM PST 24
Finished Jan 03 12:51:20 PM PST 24
Peak memory 182532 kb
Host smart-bdefb641-9c2f-40be-a049-07cffd05e172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316175733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3316175733
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.102932279
Short name T237
Test name
Test status
Simulation time 84120189690 ps
CPU time 619.42 seconds
Started Jan 03 12:51:06 PM PST 24
Finished Jan 03 01:01:44 PM PST 24
Peak memory 198704 kb
Host smart-cf46a3ef-5979-4ab8-b225-378b60147663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102932279 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.102932279
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3649899313
Short name T192
Test name
Test status
Simulation time 399900876 ps
CPU time 0.64 seconds
Started Jan 03 12:50:49 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182668 kb
Host smart-ec086019-97bc-4ff5-9074-36a0d42098b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649899313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3649899313
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3508352756
Short name T184
Test name
Test status
Simulation time 968273082 ps
CPU time 0.92 seconds
Started Jan 03 12:51:17 PM PST 24
Finished Jan 03 12:51:34 PM PST 24
Peak memory 182732 kb
Host smart-7271a461-9d88-4398-9e03-2d405788ad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508352756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3508352756
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1264527682
Short name T227
Test name
Test status
Simulation time 416230885 ps
CPU time 1.23 seconds
Started Jan 03 12:51:10 PM PST 24
Finished Jan 03 12:51:29 PM PST 24
Peak memory 182544 kb
Host smart-5108a351-ad5b-496a-8194-279141f8a6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264527682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1264527682
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3421228161
Short name T194
Test name
Test status
Simulation time 335032223268 ps
CPU time 118.66 seconds
Started Jan 03 12:51:07 PM PST 24
Finished Jan 03 12:53:25 PM PST 24
Peak memory 182832 kb
Host smart-7bef076d-4676-4f9c-b9e0-6cd1bad632c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421228161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3421228161
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.3419249941
Short name T188
Test name
Test status
Simulation time 30062314632 ps
CPU time 201.73 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:54:26 PM PST 24
Peak memory 197628 kb
Host smart-fe3a09bd-26fd-4fb7-8565-2b13f71f3ec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419249941 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.3419249941
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3837227812
Short name T224
Test name
Test status
Simulation time 341890286 ps
CPU time 1.05 seconds
Started Jan 03 12:51:01 PM PST 24
Finished Jan 03 12:51:22 PM PST 24
Peak memory 182764 kb
Host smart-7569d5c0-ca00-406d-ad26-6c02f748b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837227812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3837227812
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.807625764
Short name T148
Test name
Test status
Simulation time 12911474694 ps
CPU time 9.81 seconds
Started Jan 03 12:51:19 PM PST 24
Finished Jan 03 12:51:45 PM PST 24
Peak memory 182696 kb
Host smart-2f63203e-9d01-49cf-97de-72c74a022304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807625764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.807625764
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2605012149
Short name T139
Test name
Test status
Simulation time 478646661 ps
CPU time 1.3 seconds
Started Jan 03 12:50:53 PM PST 24
Finished Jan 03 12:51:17 PM PST 24
Peak memory 182596 kb
Host smart-5f560efd-16f8-43bf-91cd-52d3d3df34a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605012149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2605012149
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3454603922
Short name T113
Test name
Test status
Simulation time 173760629800 ps
CPU time 128.55 seconds
Started Jan 03 12:51:19 PM PST 24
Finished Jan 03 12:53:43 PM PST 24
Peak memory 182732 kb
Host smart-856aebe7-239b-4f28-b378-1d019ad5abd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454603922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3454603922
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2952745115
Short name T178
Test name
Test status
Simulation time 174883973317 ps
CPU time 323.08 seconds
Started Jan 03 12:51:00 PM PST 24
Finished Jan 03 12:56:43 PM PST 24
Peak memory 197668 kb
Host smart-8425839f-5e49-4bee-afa1-2327bb4d82f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952745115 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2952745115
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3399627401
Short name T21
Test name
Test status
Simulation time 529929529 ps
CPU time 0.73 seconds
Started Jan 03 12:50:36 PM PST 24
Finished Jan 03 12:51:00 PM PST 24
Peak memory 182756 kb
Host smart-a9f1e78d-1fc8-4bc4-97d2-a7f3967a0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399627401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3399627401
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1678718184
Short name T132
Test name
Test status
Simulation time 787703248 ps
CPU time 0.83 seconds
Started Jan 03 12:50:25 PM PST 24
Finished Jan 03 12:50:48 PM PST 24
Peak memory 182668 kb
Host smart-e663c391-29d6-47b8-862e-64d44862b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678718184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1678718184
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2227433991
Short name T140
Test name
Test status
Simulation time 530408145 ps
CPU time 0.87 seconds
Started Jan 03 12:50:22 PM PST 24
Finished Jan 03 12:50:45 PM PST 24
Peak memory 182504 kb
Host smart-cddef121-b870-4a40-89c3-9ec0cbd3de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227433991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2227433991
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3506346895
Short name T268
Test name
Test status
Simulation time 68343011329 ps
CPU time 106.2 seconds
Started Jan 03 12:50:39 PM PST 24
Finished Jan 03 12:52:50 PM PST 24
Peak memory 182680 kb
Host smart-45a3ae9b-83fa-460c-a5ad-8661af74adf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506346895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3506346895
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3919092296
Short name T85
Test name
Test status
Simulation time 17879896514 ps
CPU time 171.75 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:53:52 PM PST 24
Peak memory 197732 kb
Host smart-4c7754f6-e152-4ffe-a703-5bb448960072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919092296 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3919092296
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3353522319
Short name T232
Test name
Test status
Simulation time 421463702 ps
CPU time 0.66 seconds
Started Jan 03 12:50:31 PM PST 24
Finished Jan 03 12:50:55 PM PST 24
Peak memory 182796 kb
Host smart-f554684d-7b54-48b8-aec1-c878201f2b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353522319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3353522319
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.168763410
Short name T126
Test name
Test status
Simulation time 7022370637 ps
CPU time 6.22 seconds
Started Jan 03 12:51:04 PM PST 24
Finished Jan 03 12:51:30 PM PST 24
Peak memory 182704 kb
Host smart-c459ce9e-8e78-45c7-9ad4-98268afb75b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168763410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.168763410
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3010330358
Short name T168
Test name
Test status
Simulation time 374460596 ps
CPU time 1.01 seconds
Started Jan 03 12:50:51 PM PST 24
Finished Jan 03 12:51:14 PM PST 24
Peak memory 182588 kb
Host smart-23032c55-3fb2-4a78-a7c5-654776080df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010330358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3010330358
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1064935693
Short name T183
Test name
Test status
Simulation time 239041081695 ps
CPU time 84.59 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:52:26 PM PST 24
Peak memory 190972 kb
Host smart-e6b92a48-b053-4ff7-a2e6-db09654760f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064935693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1064935693
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3769845921
Short name T124
Test name
Test status
Simulation time 130327699140 ps
CPU time 472.23 seconds
Started Jan 03 12:50:37 PM PST 24
Finished Jan 03 12:58:54 PM PST 24
Peak memory 197472 kb
Host smart-b4138157-c771-449e-88ae-4d9c3f93b57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769845921 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3769845921
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3980114123
Short name T214
Test name
Test status
Simulation time 440146101 ps
CPU time 1.22 seconds
Started Jan 03 12:50:45 PM PST 24
Finished Jan 03 12:51:10 PM PST 24
Peak memory 182576 kb
Host smart-9471d070-0109-443e-a57b-ac87d821f74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980114123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3980114123
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.4028816042
Short name T181
Test name
Test status
Simulation time 43431402813 ps
CPU time 8.73 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:51:16 PM PST 24
Peak memory 182736 kb
Host smart-bf7b2e06-69ab-49f6-9e66-a37bb58ef958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028816042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.4028816042
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3628677947
Short name T55
Test name
Test status
Simulation time 463938134 ps
CPU time 1.1 seconds
Started Jan 03 12:51:14 PM PST 24
Finished Jan 03 12:51:36 PM PST 24
Peak memory 182664 kb
Host smart-d092a704-3ea2-4e4b-8f92-52cebde0d71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628677947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3628677947
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3956521071
Short name T258
Test name
Test status
Simulation time 218061771101 ps
CPU time 85.76 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:52:30 PM PST 24
Peak memory 193956 kb
Host smart-9238ca8c-8df7-492a-bf20-1da709b471da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956521071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3956521071
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1724190609
Short name T288
Test name
Test status
Simulation time 76220492767 ps
CPU time 556.79 seconds
Started Jan 03 12:50:35 PM PST 24
Finished Jan 03 01:00:15 PM PST 24
Peak memory 197648 kb
Host smart-b4b3028a-0259-4b94-a766-b913b26582c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724190609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1724190609
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2948768224
Short name T228
Test name
Test status
Simulation time 357001206 ps
CPU time 0.86 seconds
Started Jan 03 12:51:35 PM PST 24
Finished Jan 03 12:51:48 PM PST 24
Peak memory 181180 kb
Host smart-72a44916-bada-48fa-977c-ecd962794cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948768224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2948768224
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3477102889
Short name T196
Test name
Test status
Simulation time 34967121072 ps
CPU time 56.95 seconds
Started Jan 03 12:52:07 PM PST 24
Finished Jan 03 12:53:12 PM PST 24
Peak memory 182492 kb
Host smart-8baab768-8320-44f1-82f8-bb6c567b1f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477102889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3477102889
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.980907825
Short name T174
Test name
Test status
Simulation time 530651844 ps
CPU time 0.88 seconds
Started Jan 03 12:50:21 PM PST 24
Finished Jan 03 12:50:44 PM PST 24
Peak memory 182664 kb
Host smart-ca291f82-da25-49a5-a233-28502b954622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980907825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.980907825
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3960348438
Short name T235
Test name
Test status
Simulation time 83443414126 ps
CPU time 30.61 seconds
Started Jan 03 12:50:38 PM PST 24
Finished Jan 03 12:51:32 PM PST 24
Peak memory 182736 kb
Host smart-4768feab-9e81-41cb-a4dc-0e3c775a1218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960348438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3960348438
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1817998635
Short name T242
Test name
Test status
Simulation time 470894202776 ps
CPU time 352.29 seconds
Started Jan 03 12:50:40 PM PST 24
Finished Jan 03 12:56:57 PM PST 24
Peak memory 205820 kb
Host smart-26e1211c-9a18-4fa7-9fe3-866622e85e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817998635 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1817998635
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3349635814
Short name T123
Test name
Test status
Simulation time 607997532 ps
CPU time 0.76 seconds
Started Jan 03 12:52:02 PM PST 24
Finished Jan 03 12:52:06 PM PST 24
Peak memory 182468 kb
Host smart-a721eeef-fd2f-41ed-bb74-f067efa30d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349635814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3349635814
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1986122785
Short name T247
Test name
Test status
Simulation time 7377739179 ps
CPU time 3.32 seconds
Started Jan 03 12:50:47 PM PST 24
Finished Jan 03 12:51:13 PM PST 24
Peak memory 182652 kb
Host smart-2d970411-53e1-464e-9129-a2d1040a855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986122785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1986122785
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.390107935
Short name T25
Test name
Test status
Simulation time 458316012 ps
CPU time 0.68 seconds
Started Jan 03 12:50:30 PM PST 24
Finished Jan 03 12:50:54 PM PST 24
Peak memory 182552 kb
Host smart-45e29f6e-6177-4dca-9316-ca9c6530c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390107935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.390107935
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4261528186
Short name T252
Test name
Test status
Simulation time 170245426700 ps
CPU time 58.45 seconds
Started Jan 03 12:52:07 PM PST 24
Finished Jan 03 12:53:14 PM PST 24
Peak memory 182180 kb
Host smart-1e0dbebd-86f0-481e-a575-a7d3d10afefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261528186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4261528186
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.372403345
Short name T155
Test name
Test status
Simulation time 77431951158 ps
CPU time 113.85 seconds
Started Jan 03 12:50:43 PM PST 24
Finished Jan 03 12:53:01 PM PST 24
Peak memory 197596 kb
Host smart-7a744d3f-8fa7-4fcf-ba8f-132ba531e583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372403345 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.372403345
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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