Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 28999 1 T20 10 T21 10 T22 195
bark[1] 322 1 T75 97 T76 28 T77 16
bark[2] 198 1 T24 16 T41 16 T78 16
bark[3] 515 1 T26 21 T79 17 T80 21
bark[4] 801 1 T42 12 T81 12 T82 211
bark[5] 699 1 T67 38 T68 217 T69 17
bark[6] 416 1 T83 12 T69 17 T82 39
bark[7] 303 1 T84 16 T69 156 T85 17
bark[8] 1001 1 T27 16 T84 16 T69 2
bark[9] 351 1 T26 16 T43 17 T86 16
bark[10] 356 1 T87 12 T66 37 T50 16
bark[11] 456 1 T26 142 T27 58 T87 16
bark[12] 358 1 T88 13 T84 23 T69 16
bark[13] 367 1 T32 12 T89 23 T90 61
bark[14] 586 1 T24 17 T39 35 T68 16
bark[15] 523 1 T41 21 T91 12 T92 156
bark[16] 496 1 T41 16 T78 17 T93 12
bark[17] 394 1 T26 82 T41 124 T67 16
bark[18] 487 1 T84 71 T92 51 T94 31
bark[19] 1000 1 T39 36 T95 17 T94 16
bark[20] 461 1 T26 164 T41 119 T96 16
bark[21] 345 1 T97 102 T90 55 T98 74
bark[22] 362 1 T68 16 T99 12 T85 16
bark[23] 416 1 T41 51 T87 87 T44 17
bark[24] 671 1 T66 85 T100 17 T101 12
bark[25] 409 1 T102 12 T103 16 T104 16
bark[26] 550 1 T84 16 T95 46 T100 108
bark[27] 739 1 T27 16 T41 17 T79 224
bark[28] 462 1 T69 17 T105 12 T76 22
bark[29] 340 1 T24 16 T79 35 T106 12
bark[30] 511 1 T24 22 T38 12 T68 16
bark[31] 780 1 T22 13 T69 5 T107 12
bark_0 3580 1 T6 6 T14 6 T25 5


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28378 1 T20 9 T21 9 T22 195
bite[1] 194 1 T69 16 T105 11 T108 17
bite[2] 569 1 T24 17 T39 69 T41 50
bite[3] 581 1 T24 16 T27 16 T75 64
bite[4] 731 1 T79 17 T99 11 T50 16
bite[5] 697 1 T41 97 T69 17 T109 16
bite[6] 480 1 T44 17 T68 16 T84 16
bite[7] 666 1 T27 58 T87 16 T84 23
bite[8] 790 1 T24 27 T81 11 T84 16
bite[9] 914 1 T26 20 T68 216 T69 155
bite[10] 707 1 T44 17 T100 20 T92 155
bite[11] 636 1 T41 41 T67 16 T102 11
bite[12] 538 1 T26 163 T82 22 T92 50
bite[13] 970 1 T26 141 T79 223 T78 17
bite[14] 501 1 T66 84 T83 11 T76 28
bite[15] 425 1 T26 81 T41 123 T103 27
bite[16] 336 1 T109 16 T86 52 T110 16
bite[17] 158 1 T88 12 T67 38 T111 16
bite[18] 259 1 T22 12 T43 17 T112 11
bite[19] 446 1 T79 34 T69 1 T100 107
bite[20] 246 1 T87 11 T84 17 T107 11
bite[21] 400 1 T32 11 T38 11 T108 87
bite[22] 247 1 T41 16 T113 11 T86 47
bite[23] 672 1 T68 16 T85 16 T114 370
bite[24] 252 1 T26 16 T95 35 T115 11
bite[25] 322 1 T50 16 T106 11 T110 21
bite[26] 554 1 T24 22 T27 16 T41 16
bite[27] 285 1 T66 36 T69 17 T116 16
bite[28] 827 1 T24 16 T84 50 T69 17
bite[29] 585 1 T95 46 T117 12 T118 12
bite[30] 523 1 T41 17 T68 16 T100 16
bite[31] 272 1 T84 70 T119 11 T92 36
bite_0 4093 1 T6 6 T14 6 T25 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 48254 1 T6 6 T14 6 T25 5


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1174 1 T24 33 T82 45 T116 8
prescale[1] 1190 1 T84 15 T69 130 T95 15
prescale[2] 832 1 T24 51 T41 72 T44 15
prescale[3] 978 1 T27 18 T67 2 T68 47
prescale[4] 766 1 T39 18 T43 2 T67 2
prescale[5] 977 1 T26 85 T41 22 T68 72
prescale[6] 740 1 T44 18 T66 72 T78 68
prescale[7] 598 1 T26 15 T41 18 T69 2
prescale[8] 767 1 T26 2 T31 8 T87 15
prescale[9] 1072 1 T22 30 T84 15 T120 8
prescale[10] 676 1 T67 2 T68 70 T84 24
prescale[11] 571 1 T26 15 T96 15 T121 8
prescale[12] 856 1 T27 8 T44 32 T66 40
prescale[13] 640 1 T84 31 T69 31 T82 15
prescale[14] 1020 1 T26 2 T44 2 T84 31
prescale[15] 698 1 T26 72 T41 2 T67 28
prescale[16] 834 1 T26 66 T122 8 T84 50
prescale[17] 708 1 T22 15 T27 40 T66 4
prescale[18] 727 1 T41 2 T84 49 T92 18
prescale[19] 739 1 T26 32 T67 68 T68 22
prescale[20] 591 1 T79 15 T82 17 T98 24
prescale[21] 581 1 T69 37 T50 2 T82 26
prescale[22] 766 1 T23 8 T26 34 T41 2
prescale[23] 703 1 T22 49 T39 2 T76 29
prescale[24] 917 1 T96 22 T82 24 T100 44
prescale[25] 846 1 T26 204 T43 2 T123 8
prescale[26] 710 1 T26 2 T41 2 T44 32
prescale[27] 480 1 T27 15 T41 2 T43 2
prescale[28] 703 1 T66 3 T84 116 T100 17
prescale[29] 556 1 T27 18 T79 2 T69 15
prescale[30] 841 1 T79 4 T84 15 T82 178
prescale[31] 886 1 T27 25 T41 105 T43 2
prescale_0 23111 1 T6 6 T14 6 T25 5


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35294 1 T6 6 T14 6 T25 5
auto[1] 12960 1 T21 8 T22 26 T23 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 48254 1 T6 6 T14 6 T25 5


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 29393 1 T20 11 T21 11 T22 195
wkup[1] 611 1 T41 16 T68 31 T78 16
wkup[2] 518 1 T26 22 T68 16 T84 39
wkup[3] 479 1 T26 16 T67 10 T79 16
wkup[4] 438 1 T27 16 T87 16 T84 13
wkup[5] 506 1 T66 25 T79 16 T84 16
wkup[6] 445 1 T41 16 T96 16 T44 17
wkup[7] 658 1 T26 43 T41 16 T43 17
wkup[8] 586 1 T26 16 T39 16 T44 16
wkup[9] 697 1 T26 16 T39 7 T42 13
wkup[10] 620 1 T39 16 T27 33 T68 16
wkup[11] 452 1 T26 48 T41 17 T66 22
wkup[12] 362 1 T82 29 T75 16 T124 13
wkup[13] 558 1 T26 16 T39 16 T41 16
wkup[14] 462 1 T24 27 T39 16 T87 16
wkup[15] 577 1 T26 74 T41 55 T79 16
wkup[16] 410 1 T26 16 T87 17 T79 16
wkup[17] 507 1 T26 21 T41 44 T69 16
wkup[18] 463 1 T26 16 T41 22 T68 38
wkup[19] 427 1 T26 16 T68 17 T84 16
wkup[20] 491 1 T26 16 T27 16 T41 7
wkup[21] 734 1 T26 22 T67 38 T68 44
wkup[22] 516 1 T22 14 T26 37 T79 42
wkup[23] 545 1 T24 22 T26 45 T87 16
wkup[24] 619 1 T24 16 T26 22 T87 30
wkup[25] 587 1 T26 48 T41 21 T96 16
wkup[26] 656 1 T24 16 T87 23 T66 32
wkup[27] 466 1 T26 16 T66 43 T79 16
wkup[28] 369 1 T38 13 T96 16 T112 13
wkup[29] 494 1 T26 16 T41 44 T44 17
wkup[30] 295 1 T41 16 T87 16 T84 16
wkup[31] 276 1 T50 16 T100 16 T92 16
wkup_0 3037 1 T6 6 T14 6 T25 5

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