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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.32 100.00 99.35 100.00 96.90


Total test records in report: 430
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T269 /workspace/coverage/default/34.aon_timer_smoke.1362291024 Jan 10 12:53:54 PM PST 24 Jan 10 12:55:05 PM PST 24 433053490 ps
T270 /workspace/coverage/default/49.aon_timer_stress_all.1001082757 Jan 10 12:54:18 PM PST 24 Jan 10 12:58:03 PM PST 24 116996454277 ps
T271 /workspace/coverage/default/47.aon_timer_stress_all.816373888 Jan 10 12:54:19 PM PST 24 Jan 10 12:57:21 PM PST 24 78474448739 ps
T272 /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1162702577 Jan 10 12:53:21 PM PST 24 Jan 10 01:01:59 PM PST 24 395787322336 ps
T273 /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1720150227 Jan 10 12:54:20 PM PST 24 Jan 10 12:55:51 PM PST 24 3241323262 ps
T274 /workspace/coverage/default/13.aon_timer_smoke.2027128445 Jan 10 12:53:28 PM PST 24 Jan 10 12:54:41 PM PST 24 422110813 ps
T275 /workspace/coverage/default/41.aon_timer_stress_all.1678902336 Jan 10 12:54:11 PM PST 24 Jan 10 01:01:49 PM PST 24 261228028343 ps
T276 /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1795218949 Jan 10 12:53:58 PM PST 24 Jan 10 01:03:04 PM PST 24 757165019667 ps
T277 /workspace/coverage/default/47.aon_timer_smoke.4137211074 Jan 10 12:54:17 PM PST 24 Jan 10 12:55:24 PM PST 24 526052553 ps
T278 /workspace/coverage/default/45.aon_timer_smoke.3954562316 Jan 10 12:54:12 PM PST 24 Jan 10 12:55:19 PM PST 24 387701779 ps
T279 /workspace/coverage/default/35.aon_timer_prescaler.462494459 Jan 10 12:53:57 PM PST 24 Jan 10 12:55:55 PM PST 24 42239223869 ps
T280 /workspace/coverage/default/10.aon_timer_prescaler.2516216648 Jan 10 12:53:28 PM PST 24 Jan 10 12:54:53 PM PST 24 8292927796 ps
T281 /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2328900504 Jan 10 12:53:51 PM PST 24 Jan 10 12:57:40 PM PST 24 22853803569 ps
T282 /workspace/coverage/default/13.aon_timer_stress_all.1354169000 Jan 10 12:53:38 PM PST 24 Jan 10 12:55:52 PM PST 24 292664553265 ps
T283 /workspace/coverage/default/14.aon_timer_stress_all.2988850574 Jan 10 12:53:42 PM PST 24 Jan 10 12:58:16 PM PST 24 139722651384 ps
T284 /workspace/coverage/default/28.aon_timer_prescaler.1657311648 Jan 10 12:53:49 PM PST 24 Jan 10 12:55:03 PM PST 24 12788952720 ps
T285 /workspace/coverage/default/45.aon_timer_jump.2910446175 Jan 10 12:54:10 PM PST 24 Jan 10 12:55:17 PM PST 24 439284474 ps
T286 /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2270596082 Jan 10 12:53:44 PM PST 24 Jan 10 01:04:37 PM PST 24 367800253384 ps
T287 /workspace/coverage/default/44.aon_timer_prescaler.800641613 Jan 10 12:54:12 PM PST 24 Jan 10 12:55:22 PM PST 24 20341496986 ps
T288 /workspace/coverage/default/10.aon_timer_smoke.1200358046 Jan 10 12:53:28 PM PST 24 Jan 10 12:54:42 PM PST 24 421965965 ps
T289 /workspace/coverage/default/12.aon_timer_jump.195003248 Jan 10 12:53:27 PM PST 24 Jan 10 12:54:40 PM PST 24 618673559 ps
T290 /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3376273667 Jan 10 12:53:29 PM PST 24 Jan 10 12:57:50 PM PST 24 62984769252 ps
T291 /workspace/coverage/default/18.aon_timer_smoke.2594671744 Jan 10 12:53:38 PM PST 24 Jan 10 12:54:51 PM PST 24 461281936 ps
T292 /workspace/coverage/default/17.aon_timer_stress_all.680974632 Jan 10 12:53:40 PM PST 24 Jan 10 12:57:14 PM PST 24 171565997718 ps
T293 /workspace/coverage/default/20.aon_timer_prescaler.4048236685 Jan 10 12:53:41 PM PST 24 Jan 10 12:55:51 PM PST 24 37442911041 ps
T294 /workspace/coverage/default/20.aon_timer_stress_all.667849854 Jan 10 12:53:37 PM PST 24 Jan 10 12:57:20 PM PST 24 118705348946 ps
T295 /workspace/coverage/default/11.aon_timer_smoke.1233423738 Jan 10 12:53:27 PM PST 24 Jan 10 12:54:40 PM PST 24 584192872 ps
T296 /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1082158429 Jan 10 12:53:54 PM PST 24 Jan 10 01:02:46 PM PST 24 53131585766 ps
T297 /workspace/coverage/default/23.aon_timer_stress_all.2141976673 Jan 10 12:53:46 PM PST 24 Jan 10 12:57:46 PM PST 24 234123950751 ps
T298 /workspace/coverage/default/44.aon_timer_jump.625131348 Jan 10 12:54:07 PM PST 24 Jan 10 12:55:15 PM PST 24 454080305 ps
T299 /workspace/coverage/default/48.aon_timer_prescaler.535320389 Jan 10 12:54:19 PM PST 24 Jan 10 12:55:42 PM PST 24 33222438673 ps
T300 /workspace/coverage/default/43.aon_timer_prescaler.3829771094 Jan 10 12:54:11 PM PST 24 Jan 10 12:55:28 PM PST 24 31517467141 ps
T301 /workspace/coverage/default/46.aon_timer_jump.556968192 Jan 10 12:54:11 PM PST 24 Jan 10 12:55:18 PM PST 24 501578468 ps
T36 /workspace/coverage/default/3.aon_timer_sec_cm.3982149078 Jan 10 12:53:23 PM PST 24 Jan 10 12:54:49 PM PST 24 8385968718 ps
T302 /workspace/coverage/default/38.aon_timer_prescaler.446666920 Jan 10 12:54:01 PM PST 24 Jan 10 12:55:27 PM PST 24 10659382668 ps
T303 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3630634056 Jan 10 12:27:13 PM PST 24 Jan 10 12:27:19 PM PST 24 434764222 ps
T61 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.759462256 Jan 10 12:24:50 PM PST 24 Jan 10 12:24:51 PM PST 24 359136602 ps
T62 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1673672059 Jan 10 12:27:01 PM PST 24 Jan 10 12:27:09 PM PST 24 1516597022 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.455539250 Jan 10 12:27:35 PM PST 24 Jan 10 12:27:43 PM PST 24 502515033 ps
T305 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2253322411 Jan 10 12:29:38 PM PST 24 Jan 10 12:30:09 PM PST 24 352357064 ps
T306 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2538086532 Jan 10 12:28:55 PM PST 24 Jan 10 12:29:15 PM PST 24 381039263 ps
T307 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3575014468 Jan 10 12:29:51 PM PST 24 Jan 10 12:30:28 PM PST 24 393107121 ps
T308 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2170070444 Jan 10 12:27:07 PM PST 24 Jan 10 12:27:15 PM PST 24 463079309 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.30251957 Jan 10 12:27:30 PM PST 24 Jan 10 12:27:36 PM PST 24 363662023 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.961668044 Jan 10 12:28:13 PM PST 24 Jan 10 12:28:39 PM PST 24 8029775793 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1892612276 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:53 PM PST 24 414539816 ps
T52 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2493112245 Jan 10 12:23:14 PM PST 24 Jan 10 12:23:19 PM PST 24 376023820 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3400413680 Jan 10 12:29:18 PM PST 24 Jan 10 12:29:45 PM PST 24 959491632 ps
T311 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3552639926 Jan 10 12:28:51 PM PST 24 Jan 10 12:29:09 PM PST 24 442799386 ps
T53 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4158142979 Jan 10 12:29:56 PM PST 24 Jan 10 12:30:36 PM PST 24 641524983 ps
T312 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1088493444 Jan 10 12:28:30 PM PST 24 Jan 10 12:28:53 PM PST 24 5815369373 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1808361860 Jan 10 12:28:24 PM PST 24 Jan 10 12:28:37 PM PST 24 356777228 ps
T314 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1760809922 Jan 10 12:24:59 PM PST 24 Jan 10 12:25:05 PM PST 24 4497287662 ps
T315 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2172491639 Jan 10 12:28:41 PM PST 24 Jan 10 12:28:55 PM PST 24 409987455 ps
T316 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2363059938 Jan 10 12:30:28 PM PST 24 Jan 10 12:31:10 PM PST 24 296334827 ps
T317 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.284344341 Jan 10 12:27:11 PM PST 24 Jan 10 12:27:17 PM PST 24 453975543 ps
T318 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3080820370 Jan 10 12:29:33 PM PST 24 Jan 10 12:30:01 PM PST 24 430178962 ps
T319 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3217450559 Jan 10 12:27:11 PM PST 24 Jan 10 12:27:17 PM PST 24 298710442 ps
T320 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.42609980 Jan 10 12:28:23 PM PST 24 Jan 10 12:28:38 PM PST 24 2010479724 ps
T70 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.398651809 Jan 10 12:28:52 PM PST 24 Jan 10 12:29:17 PM PST 24 4063329345 ps
T321 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3569254382 Jan 10 12:27:12 PM PST 24 Jan 10 12:27:18 PM PST 24 377964942 ps
T322 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2152624884 Jan 10 12:30:32 PM PST 24 Jan 10 12:31:17 PM PST 24 509057938 ps
T323 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.612259783 Jan 10 12:25:11 PM PST 24 Jan 10 12:25:14 PM PST 24 479852611 ps
T54 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.306339721 Jan 10 12:28:23 PM PST 24 Jan 10 12:28:35 PM PST 24 398835816 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3355910171 Jan 10 12:26:45 PM PST 24 Jan 10 12:26:52 PM PST 24 1185473063 ps
T324 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1164933670 Jan 10 12:29:34 PM PST 24 Jan 10 12:30:02 PM PST 24 346020886 ps
T325 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2551884650 Jan 10 12:24:17 PM PST 24 Jan 10 12:24:19 PM PST 24 413050614 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2460485075 Jan 10 12:27:52 PM PST 24 Jan 10 12:28:08 PM PST 24 742998431 ps
T326 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3675680513 Jan 10 12:29:58 PM PST 24 Jan 10 12:30:46 PM PST 24 1967622362 ps
T327 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2440973608 Jan 10 12:27:01 PM PST 24 Jan 10 12:27:09 PM PST 24 479295024 ps
T60 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4205356218 Jan 10 12:29:34 PM PST 24 Jan 10 12:30:02 PM PST 24 506101361 ps
T328 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1586458440 Jan 10 12:24:46 PM PST 24 Jan 10 12:24:48 PM PST 24 335824850 ps
T329 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1639912558 Jan 10 12:28:23 PM PST 24 Jan 10 12:28:36 PM PST 24 319292734 ps
T330 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3420556047 Jan 10 12:27:49 PM PST 24 Jan 10 12:28:06 PM PST 24 414125144 ps
T331 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3743072719 Jan 10 12:28:29 PM PST 24 Jan 10 12:28:40 PM PST 24 446357842 ps
T332 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3901554959 Jan 10 12:29:15 PM PST 24 Jan 10 12:29:39 PM PST 24 298747081 ps
T333 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4262475658 Jan 10 12:29:07 PM PST 24 Jan 10 12:29:29 PM PST 24 303122230 ps
T334 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3552134217 Jan 10 12:29:37 PM PST 24 Jan 10 12:30:07 PM PST 24 404522956 ps
T335 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1529099941 Jan 10 12:26:45 PM PST 24 Jan 10 12:26:51 PM PST 24 410397019 ps
T336 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3169302288 Jan 10 12:30:26 PM PST 24 Jan 10 12:31:07 PM PST 24 646558900 ps
T337 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4010063067 Jan 10 12:28:11 PM PST 24 Jan 10 12:28:31 PM PST 24 7907360106 ps
T338 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3010875733 Jan 10 12:26:36 PM PST 24 Jan 10 12:26:40 PM PST 24 346850079 ps
T339 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1373039571 Jan 10 12:30:21 PM PST 24 Jan 10 12:31:03 PM PST 24 456491339 ps
T340 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.141930337 Jan 10 12:28:52 PM PST 24 Jan 10 12:29:11 PM PST 24 1066529406 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.236926733 Jan 10 12:27:07 PM PST 24 Jan 10 12:27:15 PM PST 24 435814132 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2285419173 Jan 10 12:23:47 PM PST 24 Jan 10 12:23:49 PM PST 24 461617230 ps
T343 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1938226069 Jan 10 12:30:31 PM PST 24 Jan 10 12:31:15 PM PST 24 410248514 ps
T344 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.420666574 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:52 PM PST 24 333227455 ps
T345 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3486189123 Jan 10 12:26:29 PM PST 24 Jan 10 12:26:32 PM PST 24 588052727 ps
T346 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.268777518 Jan 10 12:27:04 PM PST 24 Jan 10 12:27:11 PM PST 24 576058920 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3297809234 Jan 10 12:29:58 PM PST 24 Jan 10 12:30:39 PM PST 24 1352898902 ps
T348 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3475463076 Jan 10 12:30:24 PM PST 24 Jan 10 12:31:05 PM PST 24 493650035 ps
T56 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1567127775 Jan 10 12:23:40 PM PST 24 Jan 10 12:23:41 PM PST 24 386091752 ps
T349 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2438922039 Jan 10 12:24:52 PM PST 24 Jan 10 12:24:56 PM PST 24 1168246903 ps
T74 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1039939827 Jan 10 12:25:36 PM PST 24 Jan 10 12:25:41 PM PST 24 8504182171 ps
T350 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3912279211 Jan 10 12:26:56 PM PST 24 Jan 10 12:27:05 PM PST 24 1772154316 ps
T351 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.227038944 Jan 10 12:28:49 PM PST 24 Jan 10 12:29:09 PM PST 24 2345896236 ps
T352 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2379488869 Jan 10 12:27:13 PM PST 24 Jan 10 12:27:19 PM PST 24 327159065 ps
T353 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3107977101 Jan 10 12:23:18 PM PST 24 Jan 10 12:23:27 PM PST 24 342178696 ps
T354 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3398708502 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:53 PM PST 24 567981283 ps
T355 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.314429752 Jan 10 12:27:38 PM PST 24 Jan 10 12:27:48 PM PST 24 425522325 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.256843411 Jan 10 12:26:20 PM PST 24 Jan 10 12:26:24 PM PST 24 4781092278 ps
T357 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.688642843 Jan 10 12:29:59 PM PST 24 Jan 10 12:30:44 PM PST 24 4313241215 ps
T358 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1602845547 Jan 10 12:28:51 PM PST 24 Jan 10 12:29:10 PM PST 24 483148338 ps
T57 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3027872242 Jan 10 12:28:02 PM PST 24 Jan 10 12:28:18 PM PST 24 469374897 ps
T359 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.833933520 Jan 10 12:29:31 PM PST 24 Jan 10 12:29:58 PM PST 24 397564147 ps
T360 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3302345824 Jan 10 12:30:27 PM PST 24 Jan 10 12:31:09 PM PST 24 454074396 ps
T361 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2548623088 Jan 10 12:27:53 PM PST 24 Jan 10 12:28:07 PM PST 24 400675699 ps
T362 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.661009877 Jan 10 12:28:02 PM PST 24 Jan 10 12:28:18 PM PST 24 428057229 ps
T363 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2796805253 Jan 10 12:29:56 PM PST 24 Jan 10 12:30:36 PM PST 24 322762051 ps
T364 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2136355068 Jan 10 12:27:11 PM PST 24 Jan 10 12:27:17 PM PST 24 375587087 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2295439370 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:53 PM PST 24 453465094 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.891219750 Jan 10 12:25:00 PM PST 24 Jan 10 12:25:02 PM PST 24 595168343 ps
T367 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2956492123 Jan 10 12:31:16 PM PST 24 Jan 10 12:32:01 PM PST 24 280578365 ps
T368 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1964455101 Jan 10 12:28:22 PM PST 24 Jan 10 12:28:35 PM PST 24 516977056 ps
T369 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1293002380 Jan 10 12:30:21 PM PST 24 Jan 10 12:31:02 PM PST 24 334748940 ps
T370 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4283046149 Jan 10 12:26:32 PM PST 24 Jan 10 12:26:36 PM PST 24 279307634 ps
T371 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1761334574 Jan 10 12:26:32 PM PST 24 Jan 10 12:26:35 PM PST 24 363488158 ps
T372 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1076851410 Jan 10 12:26:50 PM PST 24 Jan 10 12:26:55 PM PST 24 313943144 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2520510993 Jan 10 12:22:40 PM PST 24 Jan 10 12:22:43 PM PST 24 1618394739 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1985781535 Jan 10 12:26:42 PM PST 24 Jan 10 12:26:49 PM PST 24 496514982 ps
T374 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3115331471 Jan 10 12:23:38 PM PST 24 Jan 10 12:23:41 PM PST 24 424457054 ps
T375 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.533483847 Jan 10 12:27:01 PM PST 24 Jan 10 12:27:22 PM PST 24 8314983513 ps
T376 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1033200300 Jan 10 12:29:52 PM PST 24 Jan 10 12:30:34 PM PST 24 5775690124 ps
T377 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2607554606 Jan 10 12:28:28 PM PST 24 Jan 10 12:28:40 PM PST 24 477005835 ps
T378 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4155613205 Jan 10 12:26:16 PM PST 24 Jan 10 12:26:19 PM PST 24 415536864 ps
T379 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.972605340 Jan 10 12:26:43 PM PST 24 Jan 10 12:26:49 PM PST 24 300325336 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3903911841 Jan 10 12:26:45 PM PST 24 Jan 10 12:26:51 PM PST 24 1842876691 ps
T381 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.796050330 Jan 10 12:26:42 PM PST 24 Jan 10 12:27:03 PM PST 24 8584702165 ps
T71 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3394756181 Jan 10 12:26:32 PM PST 24 Jan 10 12:26:42 PM PST 24 4071622533 ps
T382 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3093332589 Jan 10 12:29:57 PM PST 24 Jan 10 12:30:37 PM PST 24 431794770 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1771921463 Jan 10 12:24:18 PM PST 24 Jan 10 12:24:21 PM PST 24 409724642 ps
T384 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1513187637 Jan 10 12:30:16 PM PST 24 Jan 10 12:30:57 PM PST 24 485873316 ps
T385 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1111763554 Jan 10 12:29:54 PM PST 24 Jan 10 12:30:32 PM PST 24 335398825 ps
T386 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1426888951 Jan 10 12:23:03 PM PST 24 Jan 10 12:23:04 PM PST 24 489557713 ps
T387 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2365233605 Jan 10 12:27:52 PM PST 24 Jan 10 12:28:08 PM PST 24 1208014629 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1113726196 Jan 10 12:29:07 PM PST 24 Jan 10 12:29:39 PM PST 24 9532313311 ps
T389 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4260666273 Jan 10 12:24:15 PM PST 24 Jan 10 12:24:23 PM PST 24 4217033642 ps
T390 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1155580844 Jan 10 12:27:02 PM PST 24 Jan 10 12:27:09 PM PST 24 890452557 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.268929179 Jan 10 12:30:25 PM PST 24 Jan 10 12:31:08 PM PST 24 655604525 ps
T392 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3914376142 Jan 10 12:27:38 PM PST 24 Jan 10 12:27:48 PM PST 24 421994448 ps
T393 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.947897108 Jan 10 12:27:56 PM PST 24 Jan 10 12:28:10 PM PST 24 489578370 ps
T72 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1644803816 Jan 10 12:23:08 PM PST 24 Jan 10 12:23:30 PM PST 24 7517122305 ps
T394 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.457384137 Jan 10 12:28:56 PM PST 24 Jan 10 12:29:16 PM PST 24 509982842 ps
T395 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2576837226 Jan 10 12:29:34 PM PST 24 Jan 10 12:30:12 PM PST 24 8002265890 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.199504317 Jan 10 12:30:13 PM PST 24 Jan 10 12:30:57 PM PST 24 8230087543 ps
T397 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2292638366 Jan 10 12:29:52 PM PST 24 Jan 10 12:30:33 PM PST 24 605218976 ps
T398 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2722858094 Jan 10 12:24:02 PM PST 24 Jan 10 12:24:07 PM PST 24 445089116 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3715512853 Jan 10 12:29:09 PM PST 24 Jan 10 12:29:32 PM PST 24 2533319575 ps
T400 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1917070958 Jan 10 12:25:54 PM PST 24 Jan 10 12:25:57 PM PST 24 564346820 ps
T401 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.984224394 Jan 10 12:30:36 PM PST 24 Jan 10 12:31:20 PM PST 24 1338810068 ps
T402 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1409829308 Jan 10 12:30:34 PM PST 24 Jan 10 12:31:23 PM PST 24 378009531 ps
T403 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3134573402 Jan 10 12:27:07 PM PST 24 Jan 10 12:27:15 PM PST 24 4384088464 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2411403326 Jan 10 12:28:55 PM PST 24 Jan 10 12:29:14 PM PST 24 414825517 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3840509512 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:53 PM PST 24 324698470 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1315759468 Jan 10 12:24:01 PM PST 24 Jan 10 12:24:06 PM PST 24 428195227 ps
T407 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3123659896 Jan 10 12:27:25 PM PST 24 Jan 10 12:27:31 PM PST 24 506623728 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1990197135 Jan 10 12:30:31 PM PST 24 Jan 10 12:31:14 PM PST 24 269302214 ps
T409 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3382894429 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:52 PM PST 24 428110728 ps
T410 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2842211105 Jan 10 12:26:14 PM PST 24 Jan 10 12:26:20 PM PST 24 999233598 ps
T411 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2818952317 Jan 10 12:28:39 PM PST 24 Jan 10 12:28:53 PM PST 24 722461246 ps
T412 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.829192486 Jan 10 12:27:54 PM PST 24 Jan 10 12:28:07 PM PST 24 481359764 ps
T413 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2534426457 Jan 10 12:26:24 PM PST 24 Jan 10 12:26:28 PM PST 24 614953114 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1521286309 Jan 10 12:26:57 PM PST 24 Jan 10 12:27:05 PM PST 24 2265845560 ps
T415 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2279160002 Jan 10 12:27:12 PM PST 24 Jan 10 12:27:18 PM PST 24 632234927 ps
T416 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3643280059 Jan 10 12:30:27 PM PST 24 Jan 10 12:31:10 PM PST 24 1171124303 ps
T417 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2147363671 Jan 10 12:27:57 PM PST 24 Jan 10 12:28:10 PM PST 24 503150777 ps
T418 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.601121065 Jan 10 12:28:08 PM PST 24 Jan 10 12:28:24 PM PST 24 533381189 ps
T419 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.156162185 Jan 10 12:30:02 PM PST 24 Jan 10 12:30:47 PM PST 24 1148418085 ps
T420 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2680718740 Jan 10 12:29:18 PM PST 24 Jan 10 12:29:43 PM PST 24 332984891 ps
T421 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.332541843 Jan 10 12:27:37 PM PST 24 Jan 10 12:27:47 PM PST 24 284702214 ps
T422 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2847378394 Jan 10 12:26:44 PM PST 24 Jan 10 12:26:50 PM PST 24 401777314 ps
T423 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3547453979 Jan 10 12:24:51 PM PST 24 Jan 10 12:24:53 PM PST 24 1030511109 ps
T424 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3940452831 Jan 10 12:22:58 PM PST 24 Jan 10 12:23:00 PM PST 24 619448148 ps
T425 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.578424728 Jan 10 12:29:58 PM PST 24 Jan 10 12:30:41 PM PST 24 318089072 ps
T426 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1476362323 Jan 10 12:26:44 PM PST 24 Jan 10 12:26:50 PM PST 24 384276653 ps
T427 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1720441984 Jan 10 12:28:52 PM PST 24 Jan 10 12:29:17 PM PST 24 4192753545 ps
T428 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3429830373 Jan 10 12:30:25 PM PST 24 Jan 10 12:31:09 PM PST 24 2858978741 ps
T429 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3666017862 Jan 10 12:27:11 PM PST 24 Jan 10 12:27:30 PM PST 24 7654081048 ps
T430 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2821535933 Jan 10 12:28:52 PM PST 24 Jan 10 12:29:11 PM PST 24 424235042 ps

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.271898240
Short name T2
Test name
Test status
Simulation time 4093359844 ps
CPU time 7.3 seconds
Started Jan 10 12:27:13 PM PST 24
Finished Jan 10 12:27:25 PM PST 24
Peak memory 196900 kb
Host smart-858afdc3-3e08-44a7-8979-7fc2d17d81fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271898240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.271898240
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3427962778
Short name T26
Test name
Test status
Simulation time 210031839551 ps
CPU time 748.12 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 01:07:44 PM PST 24
Peak memory 200184 kb
Host smart-863b505a-106b-4f03-8053-c379e3fc842c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427962778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3427962778
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2535780786
Short name T8
Test name
Test status
Simulation time 706587947 ps
CPU time 0.82 seconds
Started Jan 10 12:29:36 PM PST 24
Finished Jan 10 12:30:05 PM PST 24
Peak memory 193548 kb
Host smart-390bd04a-36f8-4949-9ea6-d7452da9d275
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535780786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2535780786
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2495177699
Short name T69
Test name
Test status
Simulation time 104163833275 ps
CPU time 206.64 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 12:58:18 PM PST 24
Peak memory 197660 kb
Host smart-bf8238f3-759f-4058-81c6-61e385afa4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495177699 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2495177699
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2297825003
Short name T13
Test name
Test status
Simulation time 740983429 ps
CPU time 1.98 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:08 PM PST 24
Peak memory 198572 kb
Host smart-0645a3a6-2ecd-45b1-ac42-cf124941be24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297825003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2297825003
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3073761850
Short name T22
Test name
Test status
Simulation time 355243130113 ps
CPU time 253.53 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:59:31 PM PST 24
Peak memory 190916 kb
Host smart-6354772a-adfb-422c-a8d6-1c59bd697984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073761850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3073761850
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1891321383
Short name T41
Test name
Test status
Simulation time 291310347051 ps
CPU time 779.7 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 01:07:48 PM PST 24
Peak memory 201100 kb
Host smart-0c37f85a-a90f-402d-8c7b-22249ba68690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891321383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1891321383
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1047044668
Short name T100
Test name
Test status
Simulation time 252384857676 ps
CPU time 514.86 seconds
Started Jan 10 12:54:00 PM PST 24
Finished Jan 10 01:03:44 PM PST 24
Peak memory 197620 kb
Host smart-6440daf1-dfed-4d19-ae35-76c6a6bc3d3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047044668 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1047044668
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3923768109
Short name T215
Test name
Test status
Simulation time 193029279990 ps
CPU time 544.29 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 01:03:39 PM PST 24
Peak memory 198164 kb
Host smart-c56ac227-8e80-4c70-b882-bbdcc854b93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923768109 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3923768109
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2961167054
Short name T76
Test name
Test status
Simulation time 129667725455 ps
CPU time 99.04 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:56:19 PM PST 24
Peak memory 182676 kb
Host smart-09f481ac-75c3-40ac-b167-d89aaece9dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961167054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2961167054
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3524314660
Short name T33
Test name
Test status
Simulation time 4052295562 ps
CPU time 6.99 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 215044 kb
Host smart-97c0e1fc-28ca-4a4e-bdbc-bbbea0400f45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524314660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3524314660
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3560013459
Short name T84
Test name
Test status
Simulation time 545776762111 ps
CPU time 916.38 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 01:10:05 PM PST 24
Peak memory 201736 kb
Host smart-ed7b56c6-8bb0-4716-b27b-0172a6808b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560013459 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3560013459
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.398651809
Short name T70
Test name
Test status
Simulation time 4063329345 ps
CPU time 7.6 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 194416 kb
Host smart-aa8f2452-9d72-47aa-b513-0f853ceb5a57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398651809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.398651809
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1890299072
Short name T116
Test name
Test status
Simulation time 60502439011 ps
CPU time 250.21 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:58:59 PM PST 24
Peak memory 197680 kb
Host smart-1f20946b-8a00-4cb3-9bec-da60a0e21354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890299072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1890299072
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1644172167
Short name T85
Test name
Test status
Simulation time 122526297709 ps
CPU time 189.32 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 182720 kb
Host smart-0e0183b9-3087-4c65-a4b6-029261c1f437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644172167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1644172167
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1504998053
Short name T67
Test name
Test status
Simulation time 20543687701 ps
CPU time 144.55 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:57:12 PM PST 24
Peak memory 197592 kb
Host smart-f1647f99-9daf-4826-a767-c2b8fe452ccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504998053 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1504998053
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3400413680
Short name T63
Test name
Test status
Simulation time 959491632 ps
CPU time 1.94 seconds
Started Jan 10 12:29:18 PM PST 24
Finished Jan 10 12:29:45 PM PST 24
Peak memory 192964 kb
Host smart-634653f2-588d-4e0d-8806-482b637bfaa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400413680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3400413680
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.165788268
Short name T251
Test name
Test status
Simulation time 28272372297 ps
CPU time 241.51 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:58:43 PM PST 24
Peak memory 197592 kb
Host smart-4b36c14d-89cd-486e-837f-f9076f775137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165788268 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.165788268
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3010174032
Short name T32
Test name
Test status
Simulation time 616961582 ps
CPU time 1.14 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 182648 kb
Host smart-cc1c5b7d-d24a-48b7-afe3-257c54e8a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010174032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3010174032
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1088493444
Short name T312
Test name
Test status
Simulation time 5815369373 ps
CPU time 12.56 seconds
Started Jan 10 12:28:30 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 183908 kb
Host smart-2aef122d-704f-427f-8121-c6181610ff97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088493444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1088493444
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3355910171
Short name T55
Test name
Test status
Simulation time 1185473063 ps
CPU time 2.56 seconds
Started Jan 10 12:26:45 PM PST 24
Finished Jan 10 12:26:52 PM PST 24
Peak memory 183616 kb
Host smart-c5de00e3-63c9-45d1-9501-c39ad19f1442
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355910171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3355910171
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.154446341
Short name T9
Test name
Test status
Simulation time 405749851 ps
CPU time 0.93 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 197824 kb
Host smart-94f7d6ae-d0b5-46de-a7a3-34301299a9a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154446341 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.154446341
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2548623088
Short name T361
Test name
Test status
Simulation time 400675699 ps
CPU time 0.76 seconds
Started Jan 10 12:27:53 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 183696 kb
Host smart-ebd5aeb6-6b0d-40f2-8369-5993c9180f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548623088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2548623088
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1527395689
Short name T14
Test name
Test status
Simulation time 426835710 ps
CPU time 0.82 seconds
Started Jan 10 12:26:35 PM PST 24
Finished Jan 10 12:26:39 PM PST 24
Peak memory 182572 kb
Host smart-aa0bcf94-189b-4477-ad32-e993cfa8b42d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527395689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1527395689
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2847378394
Short name T422
Test name
Test status
Simulation time 401777314 ps
CPU time 1.13 seconds
Started Jan 10 12:26:44 PM PST 24
Finished Jan 10 12:26:50 PM PST 24
Peak memory 183604 kb
Host smart-bbef76d1-62cb-4075-9f84-75aabfed6c8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847378394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2847378394
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1831973636
Short name T125
Test name
Test status
Simulation time 420500550 ps
CPU time 0.71 seconds
Started Jan 10 12:26:34 PM PST 24
Finished Jan 10 12:26:38 PM PST 24
Peak memory 183492 kb
Host smart-812863d9-41dd-407e-b29c-7377388cce04
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831973636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1831973636
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3903911841
Short name T380
Test name
Test status
Simulation time 1842876691 ps
CPU time 1.57 seconds
Started Jan 10 12:26:45 PM PST 24
Finished Jan 10 12:26:51 PM PST 24
Peak memory 195120 kb
Host smart-090ebb8c-b2f0-4d1e-b9fa-80241eed012c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903911841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3903911841
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1771921463
Short name T383
Test name
Test status
Simulation time 409724642 ps
CPU time 2.2 seconds
Started Jan 10 12:24:18 PM PST 24
Finished Jan 10 12:24:21 PM PST 24
Peak memory 198524 kb
Host smart-8919dd64-63e6-4631-b6de-01a787392ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771921463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1771921463
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.961668044
Short name T73
Test name
Test status
Simulation time 8029775793 ps
CPU time 11.94 seconds
Started Jan 10 12:28:13 PM PST 24
Finished Jan 10 12:28:39 PM PST 24
Peak memory 195916 kb
Host smart-4a68760c-4966-41d3-a568-684c571429cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961668044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.961668044
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.455539250
Short name T304
Test name
Test status
Simulation time 502515033 ps
CPU time 1.34 seconds
Started Jan 10 12:27:35 PM PST 24
Finished Jan 10 12:27:43 PM PST 24
Peak memory 183736 kb
Host smart-5c2be784-d4c5-418a-ac17-b6d3287ceecf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455539250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.455539250
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1113726196
Short name T388
Test name
Test status
Simulation time 9532313311 ps
CPU time 10.93 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:39 PM PST 24
Peak memory 193316 kb
Host smart-0120f48f-499f-4df1-af90-71f3e93ba011
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113726196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1113726196
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.268929179
Short name T391
Test name
Test status
Simulation time 655604525 ps
CPU time 1.62 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 183476 kb
Host smart-f91632f5-63a0-4ebd-9dca-3b3a39fe7a2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268929179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.268929179
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3552134217
Short name T334
Test name
Test status
Simulation time 404522956 ps
CPU time 0.92 seconds
Started Jan 10 12:29:37 PM PST 24
Finished Jan 10 12:30:07 PM PST 24
Peak memory 194672 kb
Host smart-e13d091d-311b-48ac-9bc7-d94fbdc98ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552134217 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3552134217
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3536278649
Short name T46
Test name
Test status
Simulation time 501664406 ps
CPU time 1.24 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:29 PM PST 24
Peak memory 182784 kb
Host smart-bf4e3708-ebd4-407a-9efe-a93ffea94edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536278649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3536278649
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.30251957
Short name T309
Test name
Test status
Simulation time 363662023 ps
CPU time 0.82 seconds
Started Jan 10 12:27:30 PM PST 24
Finished Jan 10 12:27:36 PM PST 24
Peak memory 183868 kb
Host smart-2c092f5e-c977-47d2-8b3f-3943ff5fa937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.30251957
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3010875733
Short name T338
Test name
Test status
Simulation time 346850079 ps
CPU time 0.82 seconds
Started Jan 10 12:26:36 PM PST 24
Finished Jan 10 12:26:40 PM PST 24
Peak memory 183816 kb
Host smart-aefbfc70-4850-48ce-97b7-4997ddd52225
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010875733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3010875733
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.3914376142
Short name T392
Test name
Test status
Simulation time 421994448 ps
CPU time 0.77 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:27:48 PM PST 24
Peak memory 183652 kb
Host smart-27de77bf-8862-49c5-9a61-ae0fce4899ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914376142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.3914376142
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.77412609
Short name T48
Test name
Test status
Simulation time 553881143 ps
CPU time 1.48 seconds
Started Jan 10 12:26:36 PM PST 24
Finished Jan 10 12:26:42 PM PST 24
Peak memory 198868 kb
Host smart-dbb79a4c-1550-407e-b413-ede8e50050b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77412609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.77412609
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.256843411
Short name T356
Test name
Test status
Simulation time 4781092278 ps
CPU time 1.74 seconds
Started Jan 10 12:26:20 PM PST 24
Finished Jan 10 12:26:24 PM PST 24
Peak memory 194604 kb
Host smart-2f991093-f91b-4cfc-9579-f650674fec1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256843411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.256843411
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1164933670
Short name T324
Test name
Test status
Simulation time 346020886 ps
CPU time 1.11 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 195196 kb
Host smart-b67f72fc-41cb-41e8-963f-05a14a91980f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164933670 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1164933670
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.578424728
Short name T425
Test name
Test status
Simulation time 318089072 ps
CPU time 1 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:41 PM PST 24
Peak memory 182652 kb
Host smart-05bb2805-9f96-46f9-a29e-e9d0a2f43ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578424728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.578424728
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3694030188
Short name T25
Test name
Test status
Simulation time 504426118 ps
CPU time 1.33 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 183652 kb
Host smart-6ec5ed42-861d-4c86-9161-01a889ca492f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694030188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3694030188
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1644776189
Short name T3
Test name
Test status
Simulation time 2270268535 ps
CPU time 1.83 seconds
Started Jan 10 12:29:11 PM PST 24
Finished Jan 10 12:29:35 PM PST 24
Peak memory 194884 kb
Host smart-d2c61806-867c-4712-81f8-5467b1a997f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644776189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1644776189
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2438922039
Short name T349
Test name
Test status
Simulation time 1168246903 ps
CPU time 2.6 seconds
Started Jan 10 12:24:52 PM PST 24
Finished Jan 10 12:24:56 PM PST 24
Peak memory 198588 kb
Host smart-1777c243-06b5-4895-9ca0-fdf4c1ff36db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438922039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2438922039
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.688642843
Short name T357
Test name
Test status
Simulation time 4313241215 ps
CPU time 3.72 seconds
Started Jan 10 12:29:59 PM PST 24
Finished Jan 10 12:30:44 PM PST 24
Peak memory 195880 kb
Host smart-ad9ede28-1496-498a-ba84-204ee1939b85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688642843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.688642843
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.138245769
Short name T45
Test name
Test status
Simulation time 501837669 ps
CPU time 0.75 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 194500 kb
Host smart-f5b7fae9-ce37-4a1f-8d32-941d13e8f5ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138245769 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.138245769
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.4205356218
Short name T60
Test name
Test status
Simulation time 506101361 ps
CPU time 0.93 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:02 PM PST 24
Peak memory 183540 kb
Host smart-b711ffe9-64c4-4d25-82cd-eda19db8dcf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205356218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.4205356218
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2956492123
Short name T367
Test name
Test status
Simulation time 280578365 ps
CPU time 0.93 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 183260 kb
Host smart-d196cb51-95de-4c7a-a289-e320abdb1ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956492123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2956492123
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.141930337
Short name T340
Test name
Test status
Simulation time 1066529406 ps
CPU time 1.95 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 192700 kb
Host smart-b16dae18-b058-4035-a939-e0f9f08afb8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141930337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.141930337
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2292638366
Short name T397
Test name
Test status
Simulation time 605218976 ps
CPU time 2.28 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:33 PM PST 24
Peak memory 197672 kb
Host smart-6e7b0ebb-a799-447f-b3a4-a5d5a599b180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292638366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2292638366
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2576837226
Short name T395
Test name
Test status
Simulation time 8002265890 ps
CPU time 12.1 seconds
Started Jan 10 12:29:34 PM PST 24
Finished Jan 10 12:30:12 PM PST 24
Peak memory 197156 kb
Host smart-e0fe339d-b832-4c82-b3de-676685175b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576837226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2576837226
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.833933520
Short name T359
Test name
Test status
Simulation time 397564147 ps
CPU time 1.26 seconds
Started Jan 10 12:29:31 PM PST 24
Finished Jan 10 12:29:58 PM PST 24
Peak memory 194516 kb
Host smart-60943772-3dc5-498c-b584-6acaa3b55340
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833933520 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.833933520
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3552639926
Short name T311
Test name
Test status
Simulation time 442799386 ps
CPU time 0.67 seconds
Started Jan 10 12:28:51 PM PST 24
Finished Jan 10 12:29:09 PM PST 24
Peak memory 183712 kb
Host smart-84c73b72-b81c-48a2-9b84-892c3475b848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552639926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3552639926
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3743072719
Short name T331
Test name
Test status
Simulation time 446357842 ps
CPU time 0.61 seconds
Started Jan 10 12:28:29 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 183436 kb
Host smart-2b1f18e2-339c-4f4a-8b7c-02949dab5d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743072719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3743072719
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.984224394
Short name T401
Test name
Test status
Simulation time 1338810068 ps
CPU time 1.1 seconds
Started Jan 10 12:30:36 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 193712 kb
Host smart-774a404b-509c-453a-b085-1e4ca703836d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984224394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.984224394
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1932723706
Short name T17
Test name
Test status
Simulation time 631827397 ps
CPU time 1.87 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:29:28 PM PST 24
Peak memory 197424 kb
Host smart-b25adf00-7423-4be2-bdeb-378ee0397b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932723706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1932723706
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1644803816
Short name T72
Test name
Test status
Simulation time 7517122305 ps
CPU time 13.88 seconds
Started Jan 10 12:23:08 PM PST 24
Finished Jan 10 12:23:30 PM PST 24
Peak memory 197792 kb
Host smart-e4377f3b-0f08-457f-b9dd-0e89acc24558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644803816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1644803816
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2279160002
Short name T415
Test name
Test status
Simulation time 632234927 ps
CPU time 0.89 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:18 PM PST 24
Peak memory 195788 kb
Host smart-63f73e90-70b0-4d46-b21e-ec8a9f133c12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279160002 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2279160002
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1602845547
Short name T358
Test name
Test status
Simulation time 483148338 ps
CPU time 1.35 seconds
Started Jan 10 12:28:51 PM PST 24
Finished Jan 10 12:29:10 PM PST 24
Peak memory 183708 kb
Host smart-03c8825b-3bc7-4602-9908-d5ca2b770431
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602845547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1602845547
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.4262475658
Short name T333
Test name
Test status
Simulation time 303122230 ps
CPU time 0.61 seconds
Started Jan 10 12:29:07 PM PST 24
Finished Jan 10 12:29:29 PM PST 24
Peak memory 183464 kb
Host smart-b4501f11-ee04-455e-a861-febb7cdfe728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262475658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.4262475658
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3912279211
Short name T350
Test name
Test status
Simulation time 1772154316 ps
CPU time 1.36 seconds
Started Jan 10 12:26:56 PM PST 24
Finished Jan 10 12:27:05 PM PST 24
Peak memory 195500 kb
Host smart-ad7139ed-c982-4fdd-9285-eaa2ea3d45a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912279211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3912279211
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3860009890
Short name T47
Test name
Test status
Simulation time 491862806 ps
CPU time 1.68 seconds
Started Jan 10 12:30:37 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 198392 kb
Host smart-f8d1629f-e7f3-4b57-a45b-49f4f20a0a25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860009890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3860009890
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3394756181
Short name T71
Test name
Test status
Simulation time 4071622533 ps
CPU time 7.4 seconds
Started Jan 10 12:26:32 PM PST 24
Finished Jan 10 12:26:42 PM PST 24
Peak memory 197356 kb
Host smart-6142e1b1-cf41-4d67-b020-481ccdf94b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394756181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3394756181
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3486189123
Short name T345
Test name
Test status
Simulation time 588052727 ps
CPU time 0.86 seconds
Started Jan 10 12:26:29 PM PST 24
Finished Jan 10 12:26:32 PM PST 24
Peak memory 195736 kb
Host smart-b0b9be21-c597-4d4d-ac8b-5dad704beb43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486189123 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3486189123
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2722858094
Short name T398
Test name
Test status
Simulation time 445089116 ps
CPU time 1.21 seconds
Started Jan 10 12:24:02 PM PST 24
Finished Jan 10 12:24:07 PM PST 24
Peak memory 183656 kb
Host smart-52bd16f5-8c23-4df3-8de5-19194e86accf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722858094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2722858094
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.332541843
Short name T421
Test name
Test status
Simulation time 284702214 ps
CPU time 0.75 seconds
Started Jan 10 12:27:37 PM PST 24
Finished Jan 10 12:27:47 PM PST 24
Peak memory 183524 kb
Host smart-323a69ad-0272-480b-b1b3-5f3907d62cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332541843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.332541843
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3715512853
Short name T399
Test name
Test status
Simulation time 2533319575 ps
CPU time 0.99 seconds
Started Jan 10 12:29:09 PM PST 24
Finished Jan 10 12:29:32 PM PST 24
Peak memory 194456 kb
Host smart-c8411a20-55ea-453d-b6e5-3556c49cc2f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715512853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3715512853
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3115331471
Short name T374
Test name
Test status
Simulation time 424457054 ps
CPU time 2.29 seconds
Started Jan 10 12:23:38 PM PST 24
Finished Jan 10 12:23:41 PM PST 24
Peak memory 198572 kb
Host smart-f9fc1137-1451-493d-bd0b-f4cee1b315b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115331471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3115331471
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4010063067
Short name T337
Test name
Test status
Simulation time 7907360106 ps
CPU time 6.08 seconds
Started Jan 10 12:28:11 PM PST 24
Finished Jan 10 12:28:31 PM PST 24
Peak memory 197416 kb
Host smart-3be44edc-6911-4ea3-b6b6-a6d9792c3819
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010063067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4010063067
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1917070958
Short name T400
Test name
Test status
Simulation time 564346820 ps
CPU time 1.49 seconds
Started Jan 10 12:25:54 PM PST 24
Finished Jan 10 12:25:57 PM PST 24
Peak memory 195536 kb
Host smart-dca7d513-c6c5-4353-bb61-df627b95271f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917070958 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1917070958
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2493112245
Short name T52
Test name
Test status
Simulation time 376023820 ps
CPU time 1.2 seconds
Started Jan 10 12:23:14 PM PST 24
Finished Jan 10 12:23:19 PM PST 24
Peak memory 193040 kb
Host smart-a4be2703-9ddd-447d-abc4-f16411cf00f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493112245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2493112245
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2607554606
Short name T377
Test name
Test status
Simulation time 477005835 ps
CPU time 0.69 seconds
Started Jan 10 12:28:28 PM PST 24
Finished Jan 10 12:28:40 PM PST 24
Peak memory 183512 kb
Host smart-45a9b452-1145-4369-b19c-c2ee1c0891d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607554606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2607554606
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3675680513
Short name T326
Test name
Test status
Simulation time 1967622362 ps
CPU time 5.54 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:46 PM PST 24
Peak memory 192680 kb
Host smart-3ff42099-bfe9-4095-ab7b-dd7b977cd9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675680513 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3675680513
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2152624884
Short name T322
Test name
Test status
Simulation time 509057938 ps
CPU time 2.71 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 198312 kb
Host smart-a501a57f-3ba0-4cc5-94e0-b069657214d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152624884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2152624884
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1529099941
Short name T335
Test name
Test status
Simulation time 410397019 ps
CPU time 1.18 seconds
Started Jan 10 12:26:45 PM PST 24
Finished Jan 10 12:26:51 PM PST 24
Peak memory 195304 kb
Host smart-1d8a035d-ab90-4567-a760-17cfbe80cfdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529099941 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1529099941
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2934766541
Short name T12
Test name
Test status
Simulation time 332551960 ps
CPU time 1.08 seconds
Started Jan 10 12:28:13 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 181948 kb
Host smart-361e131e-444c-448f-8a39-f8dd490476c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934766541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2934766541
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1315759468
Short name T406
Test name
Test status
Simulation time 428195227 ps
CPU time 0.75 seconds
Started Jan 10 12:24:01 PM PST 24
Finished Jan 10 12:24:06 PM PST 24
Peak memory 183804 kb
Host smart-49eb64db-8d55-4bde-8408-9686bc7dbe3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315759468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1315759468
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1521286309
Short name T414
Test name
Test status
Simulation time 2265845560 ps
CPU time 1.54 seconds
Started Jan 10 12:26:57 PM PST 24
Finished Jan 10 12:27:05 PM PST 24
Peak memory 192308 kb
Host smart-fef760ad-d7d5-45a6-a620-6d6ad623c72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521286309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1521286309
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2034729940
Short name T18
Test name
Test status
Simulation time 447409895 ps
CPU time 1.93 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:25 PM PST 24
Peak memory 198232 kb
Host smart-99ea4c7a-0d8a-404d-b0dd-fed89011190f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034729940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2034729940
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1720441984
Short name T427
Test name
Test status
Simulation time 4192753545 ps
CPU time 7.85 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 194264 kb
Host smart-851eb460-98dc-4898-a1bd-4893099e0bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720441984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1720441984
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3420556047
Short name T330
Test name
Test status
Simulation time 414125144 ps
CPU time 1.22 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:06 PM PST 24
Peak memory 194580 kb
Host smart-d46d8987-6935-4cb9-bea0-6bf087cabaad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420556047 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3420556047
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3027872242
Short name T57
Test name
Test status
Simulation time 469374897 ps
CPU time 0.93 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 184028 kb
Host smart-49f9e69f-01b3-4684-b572-02fd61a0c268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027872242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3027872242
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.661009877
Short name T362
Test name
Test status
Simulation time 428057229 ps
CPU time 0.66 seconds
Started Jan 10 12:28:02 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 183192 kb
Host smart-6cd53d03-c857-4755-b438-964f93f6bedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661009877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.661009877
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2365233605
Short name T387
Test name
Test status
Simulation time 1208014629 ps
CPU time 1.58 seconds
Started Jan 10 12:27:52 PM PST 24
Finished Jan 10 12:28:08 PM PST 24
Peak memory 193228 kb
Host smart-653811ed-6b33-49d1-872a-f7831bf22d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365233605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2365233605
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3093332589
Short name T382
Test name
Test status
Simulation time 431794770 ps
CPU time 1.29 seconds
Started Jan 10 12:29:57 PM PST 24
Finished Jan 10 12:30:37 PM PST 24
Peak memory 198244 kb
Host smart-2d915ed9-a69d-4964-809d-90a38cf005c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093332589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3093332589
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3666017862
Short name T429
Test name
Test status
Simulation time 7654081048 ps
CPU time 13.14 seconds
Started Jan 10 12:27:11 PM PST 24
Finished Jan 10 12:27:30 PM PST 24
Peak memory 197260 kb
Host smart-171194a4-784b-40d8-997d-e69656cfbf6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666017862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3666017862
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2411403326
Short name T404
Test name
Test status
Simulation time 414825517 ps
CPU time 1.04 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:29:14 PM PST 24
Peak memory 198396 kb
Host smart-1adf4096-e66f-45b5-b193-975728b7375b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411403326 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2411403326
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3916540475
Short name T1
Test name
Test status
Simulation time 336456865 ps
CPU time 1.16 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 181076 kb
Host smart-263a05eb-6376-4f34-a3b1-0c943001085b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916540475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3916540475
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2821535933
Short name T430
Test name
Test status
Simulation time 424235042 ps
CPU time 1.31 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 180944 kb
Host smart-a8944849-889a-4315-9adc-a519c4a5c969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821535933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2821535933
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.227038944
Short name T351
Test name
Test status
Simulation time 2345896236 ps
CPU time 4.26 seconds
Started Jan 10 12:28:49 PM PST 24
Finished Jan 10 12:29:09 PM PST 24
Peak memory 193000 kb
Host smart-ed4964a0-d3a3-4b30-8e5a-d8cde5b71832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227038944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.227038944
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.612259783
Short name T323
Test name
Test status
Simulation time 479852611 ps
CPU time 2.1 seconds
Started Jan 10 12:25:11 PM PST 24
Finished Jan 10 12:25:14 PM PST 24
Peak memory 198528 kb
Host smart-380d1068-d878-4000-9853-03d1c4d180aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612259783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.612259783
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2285419173
Short name T342
Test name
Test status
Simulation time 461617230 ps
CPU time 1.28 seconds
Started Jan 10 12:23:47 PM PST 24
Finished Jan 10 12:23:49 PM PST 24
Peak memory 194736 kb
Host smart-fc6c786a-50ab-4086-a182-1a02e3b33af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285419173 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2285419173
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1409829308
Short name T402
Test name
Test status
Simulation time 378009531 ps
CPU time 0.66 seconds
Started Jan 10 12:30:34 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 183468 kb
Host smart-aa482879-65a2-4eea-83ab-8124268f931d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409829308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1409829308
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1639912558
Short name T329
Test name
Test status
Simulation time 319292734 ps
CPU time 0.98 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 183608 kb
Host smart-c108748e-b8a8-464e-9cdd-81e6e2c867d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639912558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1639912558
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3547453979
Short name T423
Test name
Test status
Simulation time 1030511109 ps
CPU time 1.43 seconds
Started Jan 10 12:24:51 PM PST 24
Finished Jan 10 12:24:53 PM PST 24
Peak memory 194036 kb
Host smart-e0597b4f-d558-48dd-b363-8559114d288c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547453979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3547453979
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1760809922
Short name T314
Test name
Test status
Simulation time 4497287662 ps
CPU time 4.81 seconds
Started Jan 10 12:24:59 PM PST 24
Finished Jan 10 12:25:05 PM PST 24
Peak memory 196420 kb
Host smart-e3951cf7-6020-4e18-b94d-264f519bf392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760809922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1760809922
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3940452831
Short name T424
Test name
Test status
Simulation time 619448148 ps
CPU time 1.02 seconds
Started Jan 10 12:22:58 PM PST 24
Finished Jan 10 12:23:00 PM PST 24
Peak memory 183784 kb
Host smart-68fc649b-fc18-4764-96ce-db4c6b333066
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940452831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3940452831
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2958681802
Short name T16
Test name
Test status
Simulation time 11175782529 ps
CPU time 6.71 seconds
Started Jan 10 12:28:25 PM PST 24
Finished Jan 10 12:28:43 PM PST 24
Peak memory 192104 kb
Host smart-7986ad57-912c-4dd5-8e9d-449d0c1b7dfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958681802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2958681802
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2460485075
Short name T59
Test name
Test status
Simulation time 742998431 ps
CPU time 1.79 seconds
Started Jan 10 12:27:52 PM PST 24
Finished Jan 10 12:28:08 PM PST 24
Peak memory 183708 kb
Host smart-fe018f05-5f53-4df2-a2fb-4036c853a603
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460485075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2460485075
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3707879022
Short name T15
Test name
Test status
Simulation time 372610631 ps
CPU time 1.14 seconds
Started Jan 10 12:23:03 PM PST 24
Finished Jan 10 12:23:05 PM PST 24
Peak memory 196368 kb
Host smart-c066bcd8-9443-4b2d-bdf3-b1e02f0cd677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707879022 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3707879022
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.947897108
Short name T393
Test name
Test status
Simulation time 489578370 ps
CPU time 1.43 seconds
Started Jan 10 12:27:56 PM PST 24
Finished Jan 10 12:28:10 PM PST 24
Peak memory 182512 kb
Host smart-3e4c59de-2008-4bab-ab67-ce3a46baac5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947897108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.947897108
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1426888951
Short name T386
Test name
Test status
Simulation time 489557713 ps
CPU time 0.72 seconds
Started Jan 10 12:23:03 PM PST 24
Finished Jan 10 12:23:04 PM PST 24
Peak memory 183540 kb
Host smart-86dce808-17fe-464b-87e5-5c793cb6c70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426888951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1426888951
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2147363671
Short name T417
Test name
Test status
Simulation time 503150777 ps
CPU time 1.35 seconds
Started Jan 10 12:27:57 PM PST 24
Finished Jan 10 12:28:10 PM PST 24
Peak memory 182524 kb
Host smart-746f365a-c00d-40ff-a74d-c4aa1443ef18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147363671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2147363671
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.829192486
Short name T412
Test name
Test status
Simulation time 481359764 ps
CPU time 0.66 seconds
Started Jan 10 12:27:54 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 183756 kb
Host smart-ce805364-e6f4-4105-a7a4-5ba667eb2020
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829192486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.829192486
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.42609980
Short name T320
Test name
Test status
Simulation time 2010479724 ps
CPU time 3.22 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:38 PM PST 24
Peak memory 191880 kb
Host smart-140ed8af-3947-4777-b4a6-b73f41a384b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42609980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_same_csr_outstanding.42609980
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2796805253
Short name T363
Test name
Test status
Simulation time 322762051 ps
CPU time 1.69 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:30:36 PM PST 24
Peak memory 196428 kb
Host smart-d46bae17-0fb2-4995-9c56-bb8e1bcf9106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796805253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2796805253
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.690027780
Short name T7
Test name
Test status
Simulation time 4206497578 ps
CPU time 7.65 seconds
Started Jan 10 12:26:54 PM PST 24
Finished Jan 10 12:27:07 PM PST 24
Peak memory 197464 kb
Host smart-3f02255f-a803-4bbf-9c71-366e60018711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690027780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.690027780
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3389539909
Short name T126
Test name
Test status
Simulation time 517745764 ps
CPU time 1.36 seconds
Started Jan 10 12:28:52 PM PST 24
Finished Jan 10 12:29:11 PM PST 24
Peak memory 180744 kb
Host smart-be93859e-284d-48be-be7e-1ef7cf12cb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389539909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3389539909
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1293002380
Short name T369
Test name
Test status
Simulation time 334748940 ps
CPU time 0.96 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 183456 kb
Host smart-267965a7-86e3-4dde-97da-f77d243d84ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293002380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1293002380
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.1964455101
Short name T368
Test name
Test status
Simulation time 516977056 ps
CPU time 0.73 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 183584 kb
Host smart-722ecd59-db4b-4599-9935-046404e40a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964455101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.1964455101
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3169302288
Short name T336
Test name
Test status
Simulation time 646558900 ps
CPU time 0.56 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 183456 kb
Host smart-948671ba-0e04-4b4b-89ce-9aad6f89e50f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169302288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3169302288
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2352455015
Short name T6
Test name
Test status
Simulation time 470611554 ps
CPU time 1.34 seconds
Started Jan 10 12:26:29 PM PST 24
Finished Jan 10 12:26:32 PM PST 24
Peak memory 183512 kb
Host smart-f5aa881b-bd55-4a16-be95-c3267353572e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352455015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2352455015
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3851542722
Short name T65
Test name
Test status
Simulation time 338558009 ps
CPU time 1.09 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 183360 kb
Host smart-c821867a-f8cb-4b8b-bfd1-8cf481669895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851542722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3851542722
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2363059938
Short name T316
Test name
Test status
Simulation time 296334827 ps
CPU time 0.87 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 183216 kb
Host smart-84ff1c1c-ad35-4c74-a12c-244fd0ee2ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363059938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2363059938
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.894470104
Short name T64
Test name
Test status
Simulation time 363184824 ps
CPU time 1.03 seconds
Started Jan 10 12:25:34 PM PST 24
Finished Jan 10 12:25:35 PM PST 24
Peak memory 183740 kb
Host smart-e3c83723-f29f-49af-a951-f4f506a1627d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894470104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.894470104
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3302345824
Short name T360
Test name
Test status
Simulation time 454074396 ps
CPU time 1.23 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 183216 kb
Host smart-df020a9b-11be-421b-8a81-4a1e10515e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302345824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3302345824
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.457384137
Short name T394
Test name
Test status
Simulation time 509982842 ps
CPU time 0.85 seconds
Started Jan 10 12:28:56 PM PST 24
Finished Jan 10 12:29:16 PM PST 24
Peak memory 183176 kb
Host smart-a1c69dd9-33ee-471e-8f1c-5099707543ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457384137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.457384137
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.891219750
Short name T366
Test name
Test status
Simulation time 595168343 ps
CPU time 1.03 seconds
Started Jan 10 12:25:00 PM PST 24
Finished Jan 10 12:25:02 PM PST 24
Peak memory 193788 kb
Host smart-55790c79-de1f-4b67-a9a5-0458ba33001c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891219750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.891219750
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1033200300
Short name T376
Test name
Test status
Simulation time 5775690124 ps
CPU time 6.06 seconds
Started Jan 10 12:29:52 PM PST 24
Finished Jan 10 12:30:34 PM PST 24
Peak memory 193944 kb
Host smart-af266fde-77b9-486d-9c6a-d77b03e118d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033200300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1033200300
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2842211105
Short name T410
Test name
Test status
Simulation time 999233598 ps
CPU time 1.97 seconds
Started Jan 10 12:26:14 PM PST 24
Finished Jan 10 12:26:20 PM PST 24
Peak memory 183748 kb
Host smart-0c7c911a-9e5a-425d-8a36-284c259b47e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842211105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2842211105
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.268777518
Short name T346
Test name
Test status
Simulation time 576058920 ps
CPU time 1.39 seconds
Started Jan 10 12:27:04 PM PST 24
Finished Jan 10 12:27:11 PM PST 24
Peak memory 195292 kb
Host smart-db9e853d-6a26-4d68-be8d-094074c1a57c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268777518 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.268777518
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4155613205
Short name T378
Test name
Test status
Simulation time 415536864 ps
CPU time 0.73 seconds
Started Jan 10 12:26:16 PM PST 24
Finished Jan 10 12:26:19 PM PST 24
Peak memory 183704 kb
Host smart-8c0af189-580a-4011-b5b1-28bd9769f466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155613205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4155613205
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3840509512
Short name T405
Test name
Test status
Simulation time 324698470 ps
CPU time 1 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 182764 kb
Host smart-6fe5dfd3-061f-4e70-a05c-b374459d2aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840509512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3840509512
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1892612276
Short name T310
Test name
Test status
Simulation time 414539816 ps
CPU time 1.15 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 183304 kb
Host smart-30d93c67-b09a-41eb-9663-a23778bf1e9e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892612276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1892612276
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2170070444
Short name T308
Test name
Test status
Simulation time 463079309 ps
CPU time 1.29 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 183344 kb
Host smart-971cacf6-a83b-4f31-945d-27ae103bc741
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170070444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2170070444
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1799732485
Short name T10
Test name
Test status
Simulation time 1103542524 ps
CPU time 0.99 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:03 PM PST 24
Peak memory 192428 kb
Host smart-aa4eabef-0233-4232-aa6b-0603819b2f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799732485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1799732485
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.236926733
Short name T341
Test name
Test status
Simulation time 435814132 ps
CPU time 2.13 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 198488 kb
Host smart-2c74df00-b3fe-4540-aab5-dbf8b5d17255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236926733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.236926733
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1039939827
Short name T74
Test name
Test status
Simulation time 8504182171 ps
CPU time 4.04 seconds
Started Jan 10 12:25:36 PM PST 24
Finished Jan 10 12:25:41 PM PST 24
Peak memory 198048 kb
Host smart-66fdbe1d-d3d9-4693-aa6a-bb7cc3b3f041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039939827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1039939827
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3901554959
Short name T332
Test name
Test status
Simulation time 298747081 ps
CPU time 0.87 seconds
Started Jan 10 12:29:15 PM PST 24
Finished Jan 10 12:29:39 PM PST 24
Peak memory 183432 kb
Host smart-8dc1c32c-469d-4af7-be1e-df57f8564c31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901554959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3901554959
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2538086532
Short name T306
Test name
Test status
Simulation time 381039263 ps
CPU time 0.82 seconds
Started Jan 10 12:28:55 PM PST 24
Finished Jan 10 12:29:15 PM PST 24
Peak memory 182464 kb
Host smart-3f2fd0d3-e7db-49b9-8af6-4a50d68c70c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538086532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2538086532
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2172491639
Short name T315
Test name
Test status
Simulation time 409987455 ps
CPU time 0.71 seconds
Started Jan 10 12:28:41 PM PST 24
Finished Jan 10 12:28:55 PM PST 24
Peak memory 182352 kb
Host smart-0f8a50e0-ba2e-453b-9b5f-a54e3745fd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172491639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2172491639
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1076851410
Short name T372
Test name
Test status
Simulation time 313943144 ps
CPU time 0.6 seconds
Started Jan 10 12:26:50 PM PST 24
Finished Jan 10 12:26:55 PM PST 24
Peak memory 183516 kb
Host smart-ef1d0233-f170-49f3-aa12-ff14bab3bf47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076851410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1076851410
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1373039571
Short name T339
Test name
Test status
Simulation time 456491339 ps
CPU time 1.2 seconds
Started Jan 10 12:30:21 PM PST 24
Finished Jan 10 12:31:03 PM PST 24
Peak memory 183392 kb
Host smart-8d645592-9015-491c-937a-99f67b8deaf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373039571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1373039571
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.601121065
Short name T418
Test name
Test status
Simulation time 533381189 ps
CPU time 0.72 seconds
Started Jan 10 12:28:08 PM PST 24
Finished Jan 10 12:28:24 PM PST 24
Peak memory 183608 kb
Host smart-7279135e-86c0-41aa-9f0d-7672da05f095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601121065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.601121065
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1938226069
Short name T343
Test name
Test status
Simulation time 410248514 ps
CPU time 0.83 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:31:15 PM PST 24
Peak memory 183196 kb
Host smart-9f0e9ef4-7675-4938-8577-f71d7ec978f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938226069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1938226069
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1586458440
Short name T328
Test name
Test status
Simulation time 335824850 ps
CPU time 0.98 seconds
Started Jan 10 12:24:46 PM PST 24
Finished Jan 10 12:24:48 PM PST 24
Peak memory 183800 kb
Host smart-59dc7019-8f50-4ab9-9d7a-0fb1015c4594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586458440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1586458440
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.4283046149
Short name T370
Test name
Test status
Simulation time 279307634 ps
CPU time 0.9 seconds
Started Jan 10 12:26:32 PM PST 24
Finished Jan 10 12:26:36 PM PST 24
Peak memory 183216 kb
Host smart-5fb83a22-c3ff-448f-9ce8-1207c32c5f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283046149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.4283046149
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1476362323
Short name T426
Test name
Test status
Simulation time 384276653 ps
CPU time 1.2 seconds
Started Jan 10 12:26:44 PM PST 24
Finished Jan 10 12:26:50 PM PST 24
Peak memory 183524 kb
Host smart-d8f3c00f-e3e5-4e40-9281-3cb676326e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476362323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1476362323
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4158142979
Short name T53
Test name
Test status
Simulation time 641524983 ps
CPU time 1.16 seconds
Started Jan 10 12:29:56 PM PST 24
Finished Jan 10 12:30:36 PM PST 24
Peak memory 182596 kb
Host smart-19c3a4f2-e5ae-4313-89ce-8e5bd0c7d311
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158142979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4158142979
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2520510993
Short name T58
Test name
Test status
Simulation time 1618394739 ps
CPU time 2.79 seconds
Started Jan 10 12:22:40 PM PST 24
Finished Jan 10 12:22:43 PM PST 24
Peak memory 183916 kb
Host smart-17c7eb4d-20b4-4f6d-9c97-3357600b65d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520510993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2520510993
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3297809234
Short name T347
Test name
Test status
Simulation time 1352898902 ps
CPU time 0.74 seconds
Started Jan 10 12:29:58 PM PST 24
Finished Jan 10 12:30:39 PM PST 24
Peak memory 183688 kb
Host smart-6a368003-00bf-497c-8e08-be4113d4fd5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297809234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3297809234
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.2295439370
Short name T365
Test name
Test status
Simulation time 453465094 ps
CPU time 1.24 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 194200 kb
Host smart-9539d5d9-c321-467f-8d55-19923521febc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295439370 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.2295439370
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3382894429
Short name T409
Test name
Test status
Simulation time 428110728 ps
CPU time 0.7 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:52 PM PST 24
Peak memory 183272 kb
Host smart-306e1706-8949-43ef-8c18-7fc67c7b488f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382894429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3382894429
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.2253322411
Short name T305
Test name
Test status
Simulation time 352357064 ps
CPU time 0.78 seconds
Started Jan 10 12:29:38 PM PST 24
Finished Jan 10 12:30:09 PM PST 24
Peak memory 183184 kb
Host smart-3722af07-61a1-441e-b890-a3ede2f6f060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253322411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.2253322411
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2680718740
Short name T420
Test name
Test status
Simulation time 332984891 ps
CPU time 0.77 seconds
Started Jan 10 12:29:18 PM PST 24
Finished Jan 10 12:29:43 PM PST 24
Peak memory 182412 kb
Host smart-c5d831ea-592a-4b89-883d-6b6dc39cd624
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680718740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2680718740
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1985781535
Short name T373
Test name
Test status
Simulation time 496514982 ps
CPU time 0.88 seconds
Started Jan 10 12:26:42 PM PST 24
Finished Jan 10 12:26:49 PM PST 24
Peak memory 182164 kb
Host smart-4c0597a1-2e0c-4029-9769-d4b8a669a1ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985781535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1985781535
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3251669310
Short name T5
Test name
Test status
Simulation time 2464944836 ps
CPU time 1.72 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 194784 kb
Host smart-821d1864-acb4-4b5c-8ee8-909c245a2475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251669310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3251669310
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1513187637
Short name T384
Test name
Test status
Simulation time 485873316 ps
CPU time 1.7 seconds
Started Jan 10 12:30:16 PM PST 24
Finished Jan 10 12:30:57 PM PST 24
Peak memory 198188 kb
Host smart-dec87ea9-2da1-42ee-9dc4-4bc35a96a37b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513187637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1513187637
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.4260666273
Short name T389
Test name
Test status
Simulation time 4217033642 ps
CPU time 7.21 seconds
Started Jan 10 12:24:15 PM PST 24
Finished Jan 10 12:24:23 PM PST 24
Peak memory 197252 kb
Host smart-5f0e8c6c-8ced-4850-9dbe-7b1bfbddc1b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260666273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.4260666273
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2136355068
Short name T364
Test name
Test status
Simulation time 375587087 ps
CPU time 0.83 seconds
Started Jan 10 12:27:11 PM PST 24
Finished Jan 10 12:27:17 PM PST 24
Peak memory 182304 kb
Host smart-384fabe6-7e76-4981-9122-2d5a348f0c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136355068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2136355068
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3630634056
Short name T303
Test name
Test status
Simulation time 434764222 ps
CPU time 1.21 seconds
Started Jan 10 12:27:13 PM PST 24
Finished Jan 10 12:27:19 PM PST 24
Peak memory 183188 kb
Host smart-c2c50d36-26b9-46a3-9f63-c5d0deb002d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630634056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3630634056
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3107977101
Short name T353
Test name
Test status
Simulation time 342178696 ps
CPU time 0.79 seconds
Started Jan 10 12:23:18 PM PST 24
Finished Jan 10 12:23:27 PM PST 24
Peak memory 183708 kb
Host smart-c14195e0-469d-45e4-ba3f-71149cdcfcd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107977101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3107977101
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.1761334574
Short name T371
Test name
Test status
Simulation time 363488158 ps
CPU time 0.64 seconds
Started Jan 10 12:26:32 PM PST 24
Finished Jan 10 12:26:35 PM PST 24
Peak memory 183108 kb
Host smart-0f814375-0276-485f-b458-2fd627137497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761334574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.1761334574
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3217450559
Short name T319
Test name
Test status
Simulation time 298710442 ps
CPU time 1.03 seconds
Started Jan 10 12:27:11 PM PST 24
Finished Jan 10 12:27:17 PM PST 24
Peak memory 181884 kb
Host smart-a21e4fba-d501-43f8-8975-807b8197c93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217450559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3217450559
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.284344341
Short name T317
Test name
Test status
Simulation time 453975543 ps
CPU time 0.86 seconds
Started Jan 10 12:27:11 PM PST 24
Finished Jan 10 12:27:17 PM PST 24
Peak memory 182268 kb
Host smart-79de90d5-e05c-42a7-9842-e755eb0a8941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284344341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.284344341
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3569254382
Short name T321
Test name
Test status
Simulation time 377964942 ps
CPU time 1.03 seconds
Started Jan 10 12:27:12 PM PST 24
Finished Jan 10 12:27:18 PM PST 24
Peak memory 183436 kb
Host smart-11e92677-e108-4132-a001-0845414dcbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569254382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3569254382
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2379488869
Short name T352
Test name
Test status
Simulation time 327159065 ps
CPU time 0.67 seconds
Started Jan 10 12:27:13 PM PST 24
Finished Jan 10 12:27:19 PM PST 24
Peak memory 183192 kb
Host smart-3949ec53-fce8-48ab-90b7-98337ee15540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379488869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2379488869
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.3080820370
Short name T318
Test name
Test status
Simulation time 430178962 ps
CPU time 1.13 seconds
Started Jan 10 12:29:33 PM PST 24
Finished Jan 10 12:30:01 PM PST 24
Peak memory 183364 kb
Host smart-c1284e57-c986-4672-92e3-f03aa0dd3979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080820370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.3080820370
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.314429752
Short name T355
Test name
Test status
Simulation time 425522325 ps
CPU time 1.09 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:27:48 PM PST 24
Peak memory 183404 kb
Host smart-e3145222-fca7-44ea-b8f3-ac0123d14a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314429752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.314429752
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3575014468
Short name T307
Test name
Test status
Simulation time 393107121 ps
CPU time 0.91 seconds
Started Jan 10 12:29:51 PM PST 24
Finished Jan 10 12:30:28 PM PST 24
Peak memory 194580 kb
Host smart-84ad2e93-b152-4ff4-9005-a28846aca7e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575014468 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3575014468
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.420666574
Short name T344
Test name
Test status
Simulation time 333227455 ps
CPU time 0.96 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:52 PM PST 24
Peak memory 183240 kb
Host smart-0879ff5c-5049-49d8-82a9-ec6c9835b909
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420666574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.420666574
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2551884650
Short name T325
Test name
Test status
Simulation time 413050614 ps
CPU time 0.74 seconds
Started Jan 10 12:24:17 PM PST 24
Finished Jan 10 12:24:19 PM PST 24
Peak memory 183512 kb
Host smart-a875e9ef-f744-4482-ad12-1be5f30624c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551884650 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2551884650
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2272051220
Short name T4
Test name
Test status
Simulation time 1207105982 ps
CPU time 1.34 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:52 PM PST 24
Peak memory 192624 kb
Host smart-3958c548-845b-458f-846d-d4a222f18a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272051220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2272051220
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3429830373
Short name T428
Test name
Test status
Simulation time 2858978741 ps
CPU time 2.15 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 198356 kb
Host smart-2a4fcfde-2a4b-43c8-a064-fd3c94db9ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429830373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3429830373
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.796050330
Short name T381
Test name
Test status
Simulation time 8584702165 ps
CPU time 14.6 seconds
Started Jan 10 12:26:42 PM PST 24
Finished Jan 10 12:27:03 PM PST 24
Peak memory 196124 kb
Host smart-481201ba-8835-4677-b538-8d152c931636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796050330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.796050330
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3398708502
Short name T354
Test name
Test status
Simulation time 567981283 ps
CPU time 1.46 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 195196 kb
Host smart-f65cd69f-d58c-40c1-8b55-0db98c8dae34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398708502 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3398708502
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1567127775
Short name T56
Test name
Test status
Simulation time 386091752 ps
CPU time 0.75 seconds
Started Jan 10 12:23:40 PM PST 24
Finished Jan 10 12:23:41 PM PST 24
Peak memory 183752 kb
Host smart-0ba848d7-26f8-4a1a-af38-c246ae16e115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567127775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1567127775
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.972605340
Short name T379
Test name
Test status
Simulation time 300325336 ps
CPU time 1.02 seconds
Started Jan 10 12:26:43 PM PST 24
Finished Jan 10 12:26:49 PM PST 24
Peak memory 182280 kb
Host smart-27cc93e0-ba1d-47b3-91aa-eb9042b8c5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972605340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.972605340
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.782529635
Short name T19
Test name
Test status
Simulation time 2174074218 ps
CPU time 1.46 seconds
Started Jan 10 12:29:37 PM PST 24
Finished Jan 10 12:30:07 PM PST 24
Peak memory 191716 kb
Host smart-811a6e3d-659a-40b8-8754-6b083cb9c92e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782529635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.782529635
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2607572110
Short name T49
Test name
Test status
Simulation time 470780864 ps
CPU time 1.54 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 198276 kb
Host smart-14d32417-5392-473a-8aa2-078b2d43b685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607572110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2607572110
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3134573402
Short name T403
Test name
Test status
Simulation time 4384088464 ps
CPU time 2.48 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:15 PM PST 24
Peak memory 196044 kb
Host smart-02208872-fcef-4a7c-ad26-0d33501f65e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134573402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3134573402
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2440973608
Short name T327
Test name
Test status
Simulation time 479295024 ps
CPU time 1.46 seconds
Started Jan 10 12:27:01 PM PST 24
Finished Jan 10 12:27:09 PM PST 24
Peak memory 195016 kb
Host smart-531aa3b0-1238-4134-9c2e-53b251932dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440973608 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2440973608
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1111763554
Short name T385
Test name
Test status
Simulation time 335398825 ps
CPU time 0.72 seconds
Started Jan 10 12:29:54 PM PST 24
Finished Jan 10 12:30:32 PM PST 24
Peak memory 183332 kb
Host smart-653c85f7-c2be-4f31-bce6-02f59fddd42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111763554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1111763554
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3123659896
Short name T407
Test name
Test status
Simulation time 506623728 ps
CPU time 1.36 seconds
Started Jan 10 12:27:25 PM PST 24
Finished Jan 10 12:27:31 PM PST 24
Peak memory 183460 kb
Host smart-47ac5112-5387-4000-b7f7-e0850a69946f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123659896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3123659896
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1673672059
Short name T62
Test name
Test status
Simulation time 1516597022 ps
CPU time 1.05 seconds
Started Jan 10 12:27:01 PM PST 24
Finished Jan 10 12:27:09 PM PST 24
Peak memory 193764 kb
Host smart-0cdc56fc-784c-413c-ac27-4560ca8e4146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673672059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1673672059
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2534426457
Short name T413
Test name
Test status
Simulation time 614953114 ps
CPU time 2.25 seconds
Started Jan 10 12:26:24 PM PST 24
Finished Jan 10 12:26:28 PM PST 24
Peak memory 198568 kb
Host smart-3bddae7f-4199-434b-843e-4916dea48679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534426457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2534426457
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3031776278
Short name T11
Test name
Test status
Simulation time 8487157906 ps
CPU time 6.24 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:57 PM PST 24
Peak memory 196036 kb
Host smart-8d14197d-46bf-4c38-97f7-a4f4610e4bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031776278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3031776278
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3475463076
Short name T348
Test name
Test status
Simulation time 493650035 ps
CPU time 0.72 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:31:05 PM PST 24
Peak memory 196096 kb
Host smart-954a4e0d-3a6e-4ef8-bf0c-acab8e68cd34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475463076 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3475463076
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.759462256
Short name T61
Test name
Test status
Simulation time 359136602 ps
CPU time 0.96 seconds
Started Jan 10 12:24:50 PM PST 24
Finished Jan 10 12:24:51 PM PST 24
Peak memory 183736 kb
Host smart-a3eabe6a-ea53-4386-84ab-e4e50c068a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759462256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.759462256
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1990197135
Short name T408
Test name
Test status
Simulation time 269302214 ps
CPU time 0.9 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:31:14 PM PST 24
Peak memory 183184 kb
Host smart-48b3ab8e-49e3-401b-92c5-2be36b41d695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990197135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1990197135
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1155580844
Short name T390
Test name
Test status
Simulation time 890452557 ps
CPU time 1.12 seconds
Started Jan 10 12:27:02 PM PST 24
Finished Jan 10 12:27:09 PM PST 24
Peak memory 193584 kb
Host smart-fe92cb95-99e6-4a41-a4b2-be606e191338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155580844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1155580844
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.2818952317
Short name T411
Test name
Test status
Simulation time 722461246 ps
CPU time 1.48 seconds
Started Jan 10 12:28:39 PM PST 24
Finished Jan 10 12:28:53 PM PST 24
Peak memory 198020 kb
Host smart-e5a73844-c520-4a2c-8eec-ebb6563d862e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818952317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.2818952317
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.199504317
Short name T396
Test name
Test status
Simulation time 8230087543 ps
CPU time 3.98 seconds
Started Jan 10 12:30:13 PM PST 24
Finished Jan 10 12:30:57 PM PST 24
Peak memory 197196 kb
Host smart-bf13fb1a-e23e-4cc2-aa1c-22ea2c85bff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199504317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.199504317
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2234478714
Short name T28
Test name
Test status
Simulation time 428223673 ps
CPU time 1.01 seconds
Started Jan 10 12:28:22 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 198252 kb
Host smart-5a93b198-c725-46f1-9bee-cad03aa796ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234478714 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2234478714
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.306339721
Short name T54
Test name
Test status
Simulation time 398835816 ps
CPU time 0.67 seconds
Started Jan 10 12:28:23 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 183640 kb
Host smart-1c112898-ea23-4ffb-8158-23e34403c1c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306339721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.306339721
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1808361860
Short name T313
Test name
Test status
Simulation time 356777228 ps
CPU time 0.89 seconds
Started Jan 10 12:28:24 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 183408 kb
Host smart-6c32b0d7-49f5-4f48-8617-7de293353b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808361860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1808361860
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.156162185
Short name T419
Test name
Test status
Simulation time 1148418085 ps
CPU time 3.15 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 192984 kb
Host smart-adb4364c-2943-4fa5-a6b9-a6b02aa8965d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156162185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.156162185
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3643280059
Short name T416
Test name
Test status
Simulation time 1171124303 ps
CPU time 2.08 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:10 PM PST 24
Peak memory 198224 kb
Host smart-9c7922ca-69c8-44f0-bfc7-fb43b839f39d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643280059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3643280059
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.533483847
Short name T375
Test name
Test status
Simulation time 8314983513 ps
CPU time 14.25 seconds
Started Jan 10 12:27:01 PM PST 24
Finished Jan 10 12:27:22 PM PST 24
Peak memory 197448 kb
Host smart-c5acfb00-9b83-4dc2-9fc6-bf78ed72609c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533483847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.533483847
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3876832214
Short name T187
Test name
Test status
Simulation time 470471949 ps
CPU time 0.71 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:29 PM PST 24
Peak memory 182716 kb
Host smart-fceb4f80-0734-43d3-bae5-402509b39d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876832214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3876832214
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.557584567
Short name T238
Test name
Test status
Simulation time 16158438369 ps
CPU time 6.27 seconds
Started Jan 10 12:53:12 PM PST 24
Finished Jan 10 12:54:31 PM PST 24
Peak memory 182680 kb
Host smart-627af747-d84b-4dbf-83ef-e5599d749e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557584567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.557584567
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.1264599724
Short name T20
Test name
Test status
Simulation time 495427616 ps
CPU time 0.79 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:29 PM PST 24
Peak memory 182584 kb
Host smart-b885dba1-02ae-4e45-8ac1-cb93eabb53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264599724 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.1264599724
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1945786193
Short name T225
Test name
Test status
Simulation time 42248243220 ps
CPU time 30.86 seconds
Started Jan 10 12:53:15 PM PST 24
Finished Jan 10 12:54:59 PM PST 24
Peak memory 182756 kb
Host smart-a9cc53d1-a22e-43d1-8f16-d9fb799fc5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945786193 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1945786193
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2237778661
Short name T226
Test name
Test status
Simulation time 120293061899 ps
CPU time 220.09 seconds
Started Jan 10 12:53:19 PM PST 24
Finished Jan 10 12:58:12 PM PST 24
Peak memory 197620 kb
Host smart-5f74128f-fad9-4096-a063-348c0756e679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237778661 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2237778661
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3167579889
Short name T88
Test name
Test status
Simulation time 533595805 ps
CPU time 1.38 seconds
Started Jan 10 12:53:26 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182656 kb
Host smart-576eb4f9-08c3-4006-9294-bf24e72329f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167579889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3167579889
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2723649730
Short name T177
Test name
Test status
Simulation time 14167962935 ps
CPU time 11.16 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:46 PM PST 24
Peak memory 182676 kb
Host smart-68ea7e71-df6a-45a3-aece-dbba6b4b774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723649730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2723649730
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.615357478
Short name T30
Test name
Test status
Simulation time 8042278120 ps
CPU time 2.29 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:35 PM PST 24
Peak memory 215004 kb
Host smart-40a4d26b-86a4-442c-a7b2-5437cf3cef10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615357478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.615357478
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.643820236
Short name T264
Test name
Test status
Simulation time 497851971 ps
CPU time 0.61 seconds
Started Jan 10 12:53:21 PM PST 24
Finished Jan 10 12:54:34 PM PST 24
Peak memory 182584 kb
Host smart-4b08d1f4-7815-445a-96a3-f0f43f30f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643820236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.643820236
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4152041529
Short name T246
Test name
Test status
Simulation time 87329565354 ps
CPU time 31.03 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:55:06 PM PST 24
Peak memory 193144 kb
Host smart-f6e7b991-bd08-4d15-aba7-4e27f6005c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152041529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4152041529
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.319751619
Short name T43
Test name
Test status
Simulation time 18173860284 ps
CPU time 147.81 seconds
Started Jan 10 12:53:24 PM PST 24
Finished Jan 10 12:57:04 PM PST 24
Peak memory 197700 kb
Host smart-420f8392-cca4-44e0-8772-708c909f25eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319751619 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.319751619
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.668492162
Short name T173
Test name
Test status
Simulation time 525951962 ps
CPU time 0.77 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182708 kb
Host smart-1dd16be0-7d1f-4e71-979b-71129daeb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668492162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.668492162
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2516216648
Short name T280
Test name
Test status
Simulation time 8292927796 ps
CPU time 12.59 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:53 PM PST 24
Peak memory 182696 kb
Host smart-9dd916c4-513d-4e32-aaba-8925eeff569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516216648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2516216648
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1200358046
Short name T288
Test name
Test status
Simulation time 421965965 ps
CPU time 0.69 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:42 PM PST 24
Peak memory 182676 kb
Host smart-6f063654-52bf-4013-9272-e71f46a48ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200358046 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1200358046
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.801012139
Short name T89
Test name
Test status
Simulation time 4247575144 ps
CPU time 7.47 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:48 PM PST 24
Peak memory 193092 kb
Host smart-4cbc82dc-fce1-4d05-8d0c-c5f13e95b155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801012139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.801012139
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.2886013164
Short name T91
Test name
Test status
Simulation time 505155250 ps
CPU time 1.36 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 182696 kb
Host smart-4f9488cd-a945-40d6-85ec-f45ca182678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886013164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.2886013164
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.4081177647
Short name T138
Test name
Test status
Simulation time 40792836786 ps
CPU time 69.95 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:55:52 PM PST 24
Peak memory 182740 kb
Host smart-4ce01c10-8e9f-43c4-8a35-84481ae4666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081177647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.4081177647
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1233423738
Short name T295
Test name
Test status
Simulation time 584192872 ps
CPU time 0.74 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182628 kb
Host smart-e73f41c8-8cfe-4e9f-9abb-722559e23def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233423738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1233423738
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3865347914
Short name T186
Test name
Test status
Simulation time 120709027620 ps
CPU time 193.22 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:58:01 PM PST 24
Peak memory 182752 kb
Host smart-42f01763-64b6-4f6f-b59c-49d135c051c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865347914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3865347914
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.195003248
Short name T289
Test name
Test status
Simulation time 618673559 ps
CPU time 0.8 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182708 kb
Host smart-679a10ca-3fb7-4f7e-a455-c9511c1e3276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195003248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.195003248
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2228295699
Short name T134
Test name
Test status
Simulation time 20545309942 ps
CPU time 28.64 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:55:10 PM PST 24
Peak memory 182656 kb
Host smart-136bc280-6e02-4ef4-899a-557878ed22eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228295699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2228295699
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2149299868
Short name T128
Test name
Test status
Simulation time 599714160 ps
CPU time 0.8 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182584 kb
Host smart-bd7c57f7-ce97-46c2-9816-6b67f2b578fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149299868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2149299868
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3021018022
Short name T229
Test name
Test status
Simulation time 318609252402 ps
CPU time 38.36 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:55:20 PM PST 24
Peak memory 182716 kb
Host smart-8608b676-5e44-4cb2-bcc0-d41c0fd54ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021018022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3021018022
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3376273667
Short name T290
Test name
Test status
Simulation time 62984769252 ps
CPU time 187.88 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:57:50 PM PST 24
Peak memory 197680 kb
Host smart-4d7c76d1-a03d-4977-96f9-96ce92204ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376273667 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3376273667
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3345782759
Short name T112
Test name
Test status
Simulation time 464267789 ps
CPU time 1.23 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:41 PM PST 24
Peak memory 182744 kb
Host smart-3c7e7003-6a54-4522-abce-b3b722a10f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345782759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3345782759
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4211782518
Short name T147
Test name
Test status
Simulation time 61888287157 ps
CPU time 105.37 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:56:25 PM PST 24
Peak memory 182832 kb
Host smart-2fae681d-03d4-4f98-89b2-f29ff399c1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211782518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4211782518
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2027128445
Short name T274
Test name
Test status
Simulation time 422110813 ps
CPU time 0.62 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:41 PM PST 24
Peak memory 182544 kb
Host smart-6c5c99ef-9e0b-4b30-a162-9f952dcebc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027128445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2027128445
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1354169000
Short name T282
Test name
Test status
Simulation time 292664553265 ps
CPU time 62.97 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:55:52 PM PST 24
Peak memory 192944 kb
Host smart-c332505d-dca0-407d-9c16-870215d18329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354169000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1354169000
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2604586114
Short name T68
Test name
Test status
Simulation time 738960366722 ps
CPU time 426.6 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 01:01:55 PM PST 24
Peak memory 197600 kb
Host smart-b101d951-9263-4f5e-9069-e6337f2c31e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604586114 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2604586114
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2425897613
Short name T117
Test name
Test status
Simulation time 388245240 ps
CPU time 1.12 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:54:50 PM PST 24
Peak memory 182632 kb
Host smart-f82bc098-6555-4532-b712-19cfd2ba4e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425897613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2425897613
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1534685052
Short name T183
Test name
Test status
Simulation time 41895610381 ps
CPU time 14.82 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:55:03 PM PST 24
Peak memory 182732 kb
Host smart-ba174fd2-f5cb-42ff-8c0d-f6a5868e1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534685052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1534685052
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.1063730974
Short name T233
Test name
Test status
Simulation time 429163726 ps
CPU time 0.68 seconds
Started Jan 10 12:53:39 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182640 kb
Host smart-59b381c0-5beb-4b27-8cb6-2466b446547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063730974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.1063730974
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2988850574
Short name T283
Test name
Test status
Simulation time 139722651384 ps
CPU time 203.25 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:58:16 PM PST 24
Peak memory 182692 kb
Host smart-c4553fe1-41da-46ec-9e52-3002bdc89120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988850574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2988850574
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.2999094844
Short name T122
Test name
Test status
Simulation time 31382054299 ps
CPU time 13.69 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:55:03 PM PST 24
Peak memory 182684 kb
Host smart-33ffc780-1dd1-4af2-b4ad-6515725ab5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999094844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.2999094844
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1888080872
Short name T133
Test name
Test status
Simulation time 350412252 ps
CPU time 0.77 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:54:54 PM PST 24
Peak memory 182596 kb
Host smart-3a5ba154-55a2-4fb5-adca-551adc056e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888080872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1888080872
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.868411745
Short name T255
Test name
Test status
Simulation time 146938381374 ps
CPU time 55.53 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:55:43 PM PST 24
Peak memory 182704 kb
Host smart-636d106f-23bc-451d-9575-82cbd85c7405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868411745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.868411745
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1247366360
Short name T216
Test name
Test status
Simulation time 48401493586 ps
CPU time 378.66 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 01:01:07 PM PST 24
Peak memory 197352 kb
Host smart-cd3b571a-41aa-4603-8bf0-13e3ce1d7fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247366360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1247366360
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1205131020
Short name T174
Test name
Test status
Simulation time 567538946 ps
CPU time 0.6 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:54:48 PM PST 24
Peak memory 182600 kb
Host smart-1c82ca55-fb90-439b-821c-f9d7d2b9437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205131020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1205131020
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2655968061
Short name T161
Test name
Test status
Simulation time 24747893436 ps
CPU time 18.43 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:55:08 PM PST 24
Peak memory 182632 kb
Host smart-0fe60231-27c7-423f-b8df-519f5e798eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655968061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2655968061
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3045965211
Short name T159
Test name
Test status
Simulation time 536038382 ps
CPU time 0.74 seconds
Started Jan 10 12:53:34 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 182512 kb
Host smart-9b88d1ce-ca04-4b43-a3a8-7003646d9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045965211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3045965211
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2515712348
Short name T86
Test name
Test status
Simulation time 221318850707 ps
CPU time 72.05 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 12:56:03 PM PST 24
Peak memory 182740 kb
Host smart-977f1195-52aa-4f29-8683-ebbcd3c1eb37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515712348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2515712348
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3052843495
Short name T39
Test name
Test status
Simulation time 14129852777 ps
CPU time 102.74 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 12:56:31 PM PST 24
Peak memory 197460 kb
Host smart-5c97895d-5b14-4d48-89da-30cc680c5818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052843495 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3052843495
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1527901119
Short name T101
Test name
Test status
Simulation time 551189648 ps
CPU time 0.76 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:54:50 PM PST 24
Peak memory 182652 kb
Host smart-7dfd1921-acf7-408f-b111-c0469682fb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527901119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1527901119
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1864526807
Short name T139
Test name
Test status
Simulation time 40811406609 ps
CPU time 24.37 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 12:55:15 PM PST 24
Peak memory 182728 kb
Host smart-21202907-08dc-4add-bab1-0878da3b42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864526807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1864526807
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.884757049
Short name T249
Test name
Test status
Simulation time 529851709 ps
CPU time 0.75 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:54:48 PM PST 24
Peak memory 182544 kb
Host smart-4d3ed72c-1d30-4cbf-93ff-38455ab657ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884757049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.884757049
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.680974632
Short name T292
Test name
Test status
Simulation time 171565997718 ps
CPU time 142.99 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 12:57:14 PM PST 24
Peak memory 182776 kb
Host smart-3c938581-803b-4806-a4c6-4b360707414a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680974632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.680974632
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3972613596
Short name T108
Test name
Test status
Simulation time 165675875485 ps
CPU time 392.49 seconds
Started Jan 10 12:53:33 PM PST 24
Finished Jan 10 01:01:18 PM PST 24
Peak memory 197580 kb
Host smart-54cb4edb-846e-4731-8a56-a59345753915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972613596 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3972613596
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.444082794
Short name T223
Test name
Test status
Simulation time 529333151 ps
CPU time 1.39 seconds
Started Jan 10 12:53:34 PM PST 24
Finished Jan 10 12:54:48 PM PST 24
Peak memory 182672 kb
Host smart-9c869db1-36d2-432e-841b-276c158da39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444082794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.444082794
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.3443794569
Short name T137
Test name
Test status
Simulation time 52551846136 ps
CPU time 13.03 seconds
Started Jan 10 12:53:34 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 182688 kb
Host smart-5bed8294-83fe-47ee-b70f-961d4b6ffd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443794569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.3443794569
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2594671744
Short name T291
Test name
Test status
Simulation time 461281936 ps
CPU time 1.21 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182548 kb
Host smart-d9f603f5-d4cd-4719-9c2f-1b2b1fb886fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594671744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2594671744
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.726377542
Short name T87
Test name
Test status
Simulation time 55862641039 ps
CPU time 94.69 seconds
Started Jan 10 12:53:35 PM PST 24
Finished Jan 10 12:56:23 PM PST 24
Peak memory 192968 kb
Host smart-6f1f4431-ebe6-4736-b7cf-c504e9f5db80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726377542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.726377542
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.822227219
Short name T242
Test name
Test status
Simulation time 620026438 ps
CPU time 1.51 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182664 kb
Host smart-97953157-1128-4552-a72c-e8c242f70944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822227219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.822227219
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1105348785
Short name T193
Test name
Test status
Simulation time 37354931999 ps
CPU time 28.34 seconds
Started Jan 10 12:53:34 PM PST 24
Finished Jan 10 12:55:16 PM PST 24
Peak memory 182748 kb
Host smart-017161fb-5c49-4286-8798-db6da4deee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105348785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1105348785
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1167138379
Short name T220
Test name
Test status
Simulation time 392648794 ps
CPU time 1.11 seconds
Started Jan 10 12:53:33 PM PST 24
Finished Jan 10 12:54:47 PM PST 24
Peak memory 182644 kb
Host smart-ecb383b0-f60e-4e97-a4e1-6fb58aaefd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167138379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1167138379
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1953506075
Short name T231
Test name
Test status
Simulation time 58655488486 ps
CPU time 70.42 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:56:00 PM PST 24
Peak memory 192920 kb
Host smart-dc09f626-10cd-482a-8ef8-18a099e02937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953506075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1953506075
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2986724599
Short name T217
Test name
Test status
Simulation time 26674962366 ps
CPU time 194.82 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 12:58:03 PM PST 24
Peak memory 197592 kb
Host smart-87967ea8-6106-4c2d-9403-c66a1695f5ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986724599 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2986724599
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2953086986
Short name T124
Test name
Test status
Simulation time 561216312 ps
CPU time 1.28 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:33 PM PST 24
Peak memory 182664 kb
Host smart-b03c3a88-cc32-418b-967e-6fbf3917ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953086986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2953086986
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2817104726
Short name T151
Test name
Test status
Simulation time 20381226913 ps
CPU time 31.53 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:55:04 PM PST 24
Peak memory 182732 kb
Host smart-917209c6-3f51-4c48-b4c4-158932b3c4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817104726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2817104726
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2834822737
Short name T34
Test name
Test status
Simulation time 8177999314 ps
CPU time 3.99 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:39 PM PST 24
Peak memory 214868 kb
Host smart-2bdd66b9-5a6e-404f-852b-411033183dbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834822737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2834822737
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3093145735
Short name T199
Test name
Test status
Simulation time 565990522 ps
CPU time 0.74 seconds
Started Jan 10 12:53:21 PM PST 24
Finished Jan 10 12:54:34 PM PST 24
Peak memory 182528 kb
Host smart-1d935dd2-b2ad-47f9-9ca3-3ec28679f407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093145735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3093145735
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3198213402
Short name T107
Test name
Test status
Simulation time 575850565 ps
CPU time 1.45 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182652 kb
Host smart-51f937de-d92f-483d-94b2-08ebaa3c7e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198213402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3198213402
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4048236685
Short name T293
Test name
Test status
Simulation time 37442911041 ps
CPU time 58.76 seconds
Started Jan 10 12:53:41 PM PST 24
Finished Jan 10 12:55:51 PM PST 24
Peak memory 182728 kb
Host smart-76fbd59b-5904-45ea-a109-e9f0cbcf9923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048236685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4048236685
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2169085922
Short name T130
Test name
Test status
Simulation time 412239349 ps
CPU time 0.66 seconds
Started Jan 10 12:53:39 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182500 kb
Host smart-7d6aca91-c507-4699-9dee-b54c72ba0d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169085922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2169085922
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.667849854
Short name T294
Test name
Test status
Simulation time 118705348946 ps
CPU time 150.43 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:57:20 PM PST 24
Peak memory 192712 kb
Host smart-d768a341-4141-49d6-9c7a-76b7f8ca1e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667849854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.667849854
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1841446127
Short name T192
Test name
Test status
Simulation time 138624983196 ps
CPU time 529.83 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 01:03:39 PM PST 24
Peak memory 197792 kb
Host smart-df77e913-6ef0-4956-8853-7997e94f727b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841446127 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1841446127
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3709764863
Short name T113
Test name
Test status
Simulation time 451582658 ps
CPU time 1.29 seconds
Started Jan 10 12:55:06 PM PST 24
Finished Jan 10 12:56:13 PM PST 24
Peak memory 182344 kb
Host smart-a84a5b12-f8eb-4c86-8fd1-e0c6fb314b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709764863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3709764863
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.417707511
Short name T179
Test name
Test status
Simulation time 17226219219 ps
CPU time 7.06 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 12:54:56 PM PST 24
Peak memory 182988 kb
Host smart-90dbb547-ce9e-4b69-9689-3c8f37526a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417707511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.417707511
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.142560296
Short name T127
Test name
Test status
Simulation time 588655582 ps
CPU time 1.47 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 12:54:50 PM PST 24
Peak memory 182600 kb
Host smart-fe32ab72-a1c1-4b44-9969-e47521a85d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142560296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.142560296
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3780896432
Short name T96
Test name
Test status
Simulation time 34163250283 ps
CPU time 48.92 seconds
Started Jan 10 12:53:33 PM PST 24
Finished Jan 10 12:55:35 PM PST 24
Peak memory 182652 kb
Host smart-45d1965e-79e2-4663-bb03-7b8193d5e38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780896432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3780896432
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3591716751
Short name T261
Test name
Test status
Simulation time 634718132 ps
CPU time 0.76 seconds
Started Jan 10 12:53:39 PM PST 24
Finished Jan 10 12:54:51 PM PST 24
Peak memory 182660 kb
Host smart-b65f6e07-fba7-4428-8d5d-eee170b47cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591716751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3591716751
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2995454797
Short name T169
Test name
Test status
Simulation time 51426499271 ps
CPU time 37.13 seconds
Started Jan 10 12:53:38 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 182772 kb
Host smart-2a21529a-fadb-41e9-bf94-fa250216d395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995454797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2995454797
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3273075429
Short name T178
Test name
Test status
Simulation time 443680686 ps
CPU time 0.87 seconds
Started Jan 10 12:53:34 PM PST 24
Finished Jan 10 12:54:47 PM PST 24
Peak memory 182752 kb
Host smart-a5c50e04-fd5a-4cc8-9f3b-114e4e035883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273075429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3273075429
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1998633986
Short name T219
Test name
Test status
Simulation time 200437079812 ps
CPU time 85.81 seconds
Started Jan 10 12:53:37 PM PST 24
Finished Jan 10 12:56:14 PM PST 24
Peak memory 193048 kb
Host smart-85ba7736-ac7b-4d60-85e4-36ae88a3c0f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998633986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1998633986
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3447320177
Short name T66
Test name
Test status
Simulation time 150155268653 ps
CPU time 206.47 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:58:19 PM PST 24
Peak memory 197568 kb
Host smart-528fac68-599b-4f1d-b6cf-6a63a713a565
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447320177 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3447320177
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2645537711
Short name T221
Test name
Test status
Simulation time 503798464 ps
CPU time 0.65 seconds
Started Jan 10 12:53:43 PM PST 24
Finished Jan 10 12:54:54 PM PST 24
Peak memory 182704 kb
Host smart-1206e07c-d5f8-442b-9ed6-2b0ca6e562bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645537711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2645537711
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.246459042
Short name T244
Test name
Test status
Simulation time 42172870866 ps
CPU time 65.06 seconds
Started Jan 10 12:53:44 PM PST 24
Finished Jan 10 12:55:59 PM PST 24
Peak memory 182672 kb
Host smart-c0da2078-a4e3-4422-8fa6-3c208b0b853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246459042 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.246459042
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1138542258
Short name T203
Test name
Test status
Simulation time 435098282 ps
CPU time 0.7 seconds
Started Jan 10 12:53:36 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 182488 kb
Host smart-f33ec023-b1d6-43c0-9efe-284c22f19c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138542258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1138542258
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2141976673
Short name T297
Test name
Test status
Simulation time 234123950751 ps
CPU time 170.1 seconds
Started Jan 10 12:53:46 PM PST 24
Finished Jan 10 12:57:46 PM PST 24
Peak memory 192876 kb
Host smart-6b55bb98-00ce-4f1b-83ff-d953682a2dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141976673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2141976673
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.4246978688
Short name T82
Test name
Test status
Simulation time 310308510181 ps
CPU time 360.06 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 01:00:51 PM PST 24
Peak memory 197608 kb
Host smart-4ead3a4d-47db-48cc-a68d-644d22b39a7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246978688 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.4246978688
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2572246125
Short name T172
Test name
Test status
Simulation time 347931851 ps
CPU time 1 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:54:53 PM PST 24
Peak memory 182680 kb
Host smart-52ba73e1-36bb-4d05-927d-721404033378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572246125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2572246125
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.238411486
Short name T152
Test name
Test status
Simulation time 22829346717 ps
CPU time 3.14 seconds
Started Jan 10 12:53:41 PM PST 24
Finished Jan 10 12:54:55 PM PST 24
Peak memory 182744 kb
Host smart-134e1b8e-eef4-4eb6-9533-e0fb4d451e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238411486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.238411486
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2920519595
Short name T131
Test name
Test status
Simulation time 436662724 ps
CPU time 0.7 seconds
Started Jan 10 12:53:44 PM PST 24
Finished Jan 10 12:54:55 PM PST 24
Peak memory 182544 kb
Host smart-9face610-ce42-49f4-aa30-b38ae184a14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920519595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2920519595
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.298154447
Short name T235
Test name
Test status
Simulation time 164016836977 ps
CPU time 21.81 seconds
Started Jan 10 12:53:48 PM PST 24
Finished Jan 10 12:55:20 PM PST 24
Peak memory 192828 kb
Host smart-35fffcd4-b2b5-476c-a79a-40331c80f028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298154447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.298154447
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1986359135
Short name T118
Test name
Test status
Simulation time 495560046 ps
CPU time 0.78 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:54:57 PM PST 24
Peak memory 182708 kb
Host smart-75d23e21-e8fa-4dce-9cd8-c9a3ddcf69d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986359135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1986359135
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3483428436
Short name T227
Test name
Test status
Simulation time 23753584837 ps
CPU time 8.76 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 182644 kb
Host smart-6e9e5bb5-2176-4563-b309-e865313661cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483428436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3483428436
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2463211072
Short name T145
Test name
Test status
Simulation time 431051914 ps
CPU time 0.69 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:54:53 PM PST 24
Peak memory 182476 kb
Host smart-7478a073-cf98-4bdf-ab7a-6f5a66a27dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463211072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2463211072
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1386440788
Short name T245
Test name
Test status
Simulation time 4727425977 ps
CPU time 2.29 seconds
Started Jan 10 12:53:45 PM PST 24
Finished Jan 10 12:54:57 PM PST 24
Peak memory 182704 kb
Host smart-effc316f-14cc-4010-b14e-a6d376b1b016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386440788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1386440788
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2270596082
Short name T286
Test name
Test status
Simulation time 367800253384 ps
CPU time 582.81 seconds
Started Jan 10 12:53:44 PM PST 24
Finished Jan 10 01:04:37 PM PST 24
Peak memory 197868 kb
Host smart-aedd35a7-15a3-4aa8-a27a-3cdead944197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270596082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2270596082
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.3470164923
Short name T81
Test name
Test status
Simulation time 440777007 ps
CPU time 0.89 seconds
Started Jan 10 12:53:46 PM PST 24
Finished Jan 10 12:54:59 PM PST 24
Peak memory 182680 kb
Host smart-6261676c-284c-4863-b4a6-324f96bd4dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470164923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.3470164923
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3173859934
Short name T163
Test name
Test status
Simulation time 5036514204 ps
CPU time 8.12 seconds
Started Jan 10 12:53:42 PM PST 24
Finished Jan 10 12:55:01 PM PST 24
Peak memory 182728 kb
Host smart-d9adde76-c8cc-4fd1-9caa-6dad5091de25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173859934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3173859934
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4159836535
Short name T241
Test name
Test status
Simulation time 442445105 ps
CPU time 1.17 seconds
Started Jan 10 12:53:45 PM PST 24
Finished Jan 10 12:54:57 PM PST 24
Peak memory 182616 kb
Host smart-6a88811a-3172-4632-89d0-c33759d23a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159836535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4159836535
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.84670714
Short name T77
Test name
Test status
Simulation time 217725016871 ps
CPU time 173.19 seconds
Started Jan 10 12:53:41 PM PST 24
Finished Jan 10 12:57:45 PM PST 24
Peak memory 182708 kb
Host smart-8d7de0d8-bfa8-4f7b-8e94-a7aa29475067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84670714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_al
l.84670714
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1780995406
Short name T267
Test name
Test status
Simulation time 26097691492 ps
CPU time 206.73 seconds
Started Jan 10 12:53:51 PM PST 24
Finished Jan 10 12:58:26 PM PST 24
Peak memory 197644 kb
Host smart-b4b27801-856e-4ed3-838d-5d49c29ce0b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780995406 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1780995406
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1334395182
Short name T106
Test name
Test status
Simulation time 498177038 ps
CPU time 1.4 seconds
Started Jan 10 12:53:41 PM PST 24
Finished Jan 10 12:54:53 PM PST 24
Peak memory 182680 kb
Host smart-fb854642-581e-4692-b788-4ec8da470591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334395182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1334395182
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2447275554
Short name T176
Test name
Test status
Simulation time 16451721250 ps
CPU time 3.74 seconds
Started Jan 10 12:53:40 PM PST 24
Finished Jan 10 12:54:55 PM PST 24
Peak memory 182608 kb
Host smart-c2602731-4c4c-4666-966c-4892866c6201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447275554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2447275554
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.2309327973
Short name T140
Test name
Test status
Simulation time 458834202 ps
CPU time 1.21 seconds
Started Jan 10 12:53:43 PM PST 24
Finished Jan 10 12:54:55 PM PST 24
Peak memory 182568 kb
Host smart-226fd67f-3b8e-4ced-9135-f9db38990596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309327973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.2309327973
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.231872720
Short name T103
Test name
Test status
Simulation time 383139636247 ps
CPU time 124.72 seconds
Started Jan 10 12:53:48 PM PST 24
Finished Jan 10 12:57:03 PM PST 24
Peak memory 182716 kb
Host smart-1c851d70-9b64-438d-bd5f-684c808dea67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231872720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.231872720
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.955267673
Short name T258
Test name
Test status
Simulation time 18613619756 ps
CPU time 143.36 seconds
Started Jan 10 12:53:43 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 197684 kb
Host smart-430b99a5-f592-40c5-b77a-0288c0479e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955267673 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.955267673
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2035545289
Short name T240
Test name
Test status
Simulation time 547768226 ps
CPU time 1.22 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:54:58 PM PST 24
Peak memory 182708 kb
Host smart-39ca2020-3a94-4dad-88f5-54cbafc05d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035545289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2035545289
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1657311648
Short name T284
Test name
Test status
Simulation time 12788952720 ps
CPU time 4.69 seconds
Started Jan 10 12:53:49 PM PST 24
Finished Jan 10 12:55:03 PM PST 24
Peak memory 182744 kb
Host smart-e6e8dfbc-b642-415e-97da-1cb6a9092a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657311648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1657311648
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.821433176
Short name T141
Test name
Test status
Simulation time 443203454 ps
CPU time 1.16 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:54:58 PM PST 24
Peak memory 182480 kb
Host smart-7c0895c6-0731-4e12-b6da-36a633ce7206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821433176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.821433176
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2294193305
Short name T78
Test name
Test status
Simulation time 123868199430 ps
CPU time 44.69 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:49 PM PST 24
Peak memory 192208 kb
Host smart-5011b91b-0bb7-4546-9032-184d3f245e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294193305 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2294193305
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2827927943
Short name T201
Test name
Test status
Simulation time 88319224378 ps
CPU time 607.55 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 01:05:12 PM PST 24
Peak memory 198148 kb
Host smart-0deab1db-e3ac-4539-8e10-614969fb8847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827927943 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2827927943
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2275596645
Short name T160
Test name
Test status
Simulation time 595502456 ps
CPU time 1.54 seconds
Started Jan 10 12:53:55 PM PST 24
Finished Jan 10 12:55:06 PM PST 24
Peak memory 182296 kb
Host smart-71123eaa-4b3b-4f0b-b807-e25627729d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275596645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2275596645
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.361543015
Short name T23
Test name
Test status
Simulation time 42924405620 ps
CPU time 17.42 seconds
Started Jan 10 12:53:45 PM PST 24
Finished Jan 10 12:55:13 PM PST 24
Peak memory 182716 kb
Host smart-a58be9d1-6bd2-4bef-bbd2-d228b3e7b004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361543015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.361543015
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1712457733
Short name T158
Test name
Test status
Simulation time 531222774 ps
CPU time 0.94 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:05 PM PST 24
Peak memory 182136 kb
Host smart-739122f3-9fbf-4d08-a966-b360ad0aeabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712457733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1712457733
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2392650391
Short name T111
Test name
Test status
Simulation time 103977428070 ps
CPU time 70.41 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:56:08 PM PST 24
Peak memory 193016 kb
Host smart-f73047c4-c13c-487f-b3b3-8b545c40436f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392650391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2392650391
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1675905423
Short name T266
Test name
Test status
Simulation time 19974919114 ps
CPU time 162.35 seconds
Started Jan 10 12:53:49 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 197672 kb
Host smart-5d095cd4-d9cd-40d7-ae67-18d7e07817b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675905423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1675905423
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.180748599
Short name T250
Test name
Test status
Simulation time 380148790 ps
CPU time 0.7 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:36 PM PST 24
Peak memory 182736 kb
Host smart-f4fef33c-bcac-46c6-8e54-0da76c4253b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180748599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.180748599
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3697301728
Short name T132
Test name
Test status
Simulation time 61866901766 ps
CPU time 94.74 seconds
Started Jan 10 12:53:21 PM PST 24
Finished Jan 10 12:56:08 PM PST 24
Peak memory 182628 kb
Host smart-c6d57fd4-bb5e-407f-a291-e9f7840d9b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697301728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3697301728
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3982149078
Short name T36
Test name
Test status
Simulation time 8385968718 ps
CPU time 13.73 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 215032 kb
Host smart-68f2d90b-7c6a-417b-b6e3-f5870fe64531
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982149078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3982149078
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.556112677
Short name T263
Test name
Test status
Simulation time 421162431 ps
CPU time 0.79 seconds
Started Jan 10 12:53:25 PM PST 24
Finished Jan 10 12:54:38 PM PST 24
Peak memory 182544 kb
Host smart-d6131a27-883b-448f-8428-cc657d1b0662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556112677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.556112677
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.3470873577
Short name T97
Test name
Test status
Simulation time 434340694943 ps
CPU time 456.38 seconds
Started Jan 10 12:53:19 PM PST 24
Finished Jan 10 01:02:08 PM PST 24
Peak memory 192716 kb
Host smart-df47bf11-0924-441a-803d-6ad52a477f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470873577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.3470873577
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1162702577
Short name T272
Test name
Test status
Simulation time 395787322336 ps
CPU time 446.26 seconds
Started Jan 10 12:53:21 PM PST 24
Finished Jan 10 01:01:59 PM PST 24
Peak memory 197656 kb
Host smart-8ba15530-379b-42f2-b74f-5b1fd02e6103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162702577 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1162702577
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2579637612
Short name T218
Test name
Test status
Simulation time 387500034 ps
CPU time 0.83 seconds
Started Jan 10 12:53:52 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 182720 kb
Host smart-9830c1b8-c932-4eb8-be88-39e98f3f24e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579637612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2579637612
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2209840464
Short name T254
Test name
Test status
Simulation time 35456830207 ps
CPU time 14.46 seconds
Started Jan 10 12:53:44 PM PST 24
Finished Jan 10 12:55:09 PM PST 24
Peak memory 182644 kb
Host smart-640d522d-2544-472f-9cab-d4e580e660a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209840464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2209840464
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1148665645
Short name T210
Test name
Test status
Simulation time 562948802 ps
CPU time 1.02 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:54:58 PM PST 24
Peak memory 182664 kb
Host smart-376490e5-a0ac-4f07-87b2-b4e9f3856426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148665645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1148665645
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.763637247
Short name T252
Test name
Test status
Simulation time 185964209717 ps
CPU time 299.68 seconds
Started Jan 10 12:53:48 PM PST 24
Finished Jan 10 12:59:57 PM PST 24
Peak memory 194232 kb
Host smart-7995fee8-8286-4232-b5ec-935c4cb1bf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763637247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.763637247
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2328900504
Short name T281
Test name
Test status
Simulation time 22853803569 ps
CPU time 160.93 seconds
Started Jan 10 12:53:51 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 197612 kb
Host smart-a5f7cc0c-62dc-4931-921a-66b1ba9624fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328900504 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2328900504
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.519691954
Short name T115
Test name
Test status
Simulation time 439150868 ps
CPU time 1.22 seconds
Started Jan 10 12:53:51 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 182712 kb
Host smart-80da75e1-3ce4-4a2d-ba38-6f4a66e6dc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519691954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.519691954
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3444548377
Short name T120
Test name
Test status
Simulation time 18570717185 ps
CPU time 27.72 seconds
Started Jan 10 12:53:46 PM PST 24
Finished Jan 10 12:55:24 PM PST 24
Peak memory 182744 kb
Host smart-02c1b739-288c-4cfd-9a5e-781c502b11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444548377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3444548377
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.872532704
Short name T21
Test name
Test status
Simulation time 539988968 ps
CPU time 0.74 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:05 PM PST 24
Peak memory 181952 kb
Host smart-125e3d81-fdfd-495f-93ca-6b5278d2b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872532704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.872532704
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.68299552
Short name T212
Test name
Test status
Simulation time 55919836956 ps
CPU time 9.72 seconds
Started Jan 10 12:53:45 PM PST 24
Finished Jan 10 12:55:05 PM PST 24
Peak memory 182644 kb
Host smart-0a5417b6-7d95-4239-9e06-8c7c4fb78c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68299552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_al
l.68299552
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1000952690
Short name T184
Test name
Test status
Simulation time 51981064904 ps
CPU time 372.56 seconds
Started Jan 10 12:53:48 PM PST 24
Finished Jan 10 01:01:10 PM PST 24
Peak memory 197592 kb
Host smart-1337d543-cacf-4b3e-ac44-590191d52241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000952690 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1000952690
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.678274047
Short name T239
Test name
Test status
Simulation time 604155736 ps
CPU time 0.67 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:08 PM PST 24
Peak memory 182656 kb
Host smart-51dbbdbf-f18d-42c5-af05-db8a6dae5895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678274047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.678274047
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1262262773
Short name T202
Test name
Test status
Simulation time 41181953139 ps
CPU time 31.14 seconds
Started Jan 10 12:53:49 PM PST 24
Finished Jan 10 12:55:30 PM PST 24
Peak memory 182680 kb
Host smart-a9067cf6-b809-44de-9633-23fd1700e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262262773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1262262773
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1922999498
Short name T197
Test name
Test status
Simulation time 388251811 ps
CPU time 1.07 seconds
Started Jan 10 12:53:47 PM PST 24
Finished Jan 10 12:54:58 PM PST 24
Peak memory 182588 kb
Host smart-cec89c20-8d5d-4a08-b7b3-2279e31512a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922999498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1922999498
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.1093390812
Short name T94
Test name
Test status
Simulation time 182340895394 ps
CPU time 17.9 seconds
Started Jan 10 12:53:53 PM PST 24
Finished Jan 10 12:55:21 PM PST 24
Peak memory 182696 kb
Host smart-359ee9a5-5105-4cde-bb68-256ee9c63c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093390812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.1093390812
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1795218949
Short name T276
Test name
Test status
Simulation time 757165019667 ps
CPU time 476.57 seconds
Started Jan 10 12:53:58 PM PST 24
Finished Jan 10 01:03:04 PM PST 24
Peak memory 197676 kb
Host smart-f9fa1f96-a3ec-4dd1-8c3d-a58eca25c128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795218949 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1795218949
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1591093879
Short name T83
Test name
Test status
Simulation time 501898008 ps
CPU time 0.69 seconds
Started Jan 10 12:53:52 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 182628 kb
Host smart-dbce03a4-4e18-4427-a918-77464edb1337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591093879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1591093879
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2320893216
Short name T150
Test name
Test status
Simulation time 12198501043 ps
CPU time 9.24 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:16 PM PST 24
Peak memory 182648 kb
Host smart-0e03a951-24a2-4eb5-bca0-96b3ea7c2860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320893216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2320893216
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1002594189
Short name T247
Test name
Test status
Simulation time 359520884 ps
CPU time 1.1 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:04 PM PST 24
Peak memory 182560 kb
Host smart-26673ccd-bdf0-4ede-bb76-11ff2e96c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002594189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1002594189
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1695218455
Short name T185
Test name
Test status
Simulation time 145588728986 ps
CPU time 236.58 seconds
Started Jan 10 12:53:52 PM PST 24
Finished Jan 10 12:58:57 PM PST 24
Peak memory 190964 kb
Host smart-b10235d2-ac57-4cf1-9b08-bc0efde7eedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695218455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1695218455
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1930023839
Short name T211
Test name
Test status
Simulation time 53641670517 ps
CPU time 598.49 seconds
Started Jan 10 12:53:59 PM PST 24
Finished Jan 10 01:05:07 PM PST 24
Peak memory 197604 kb
Host smart-54962552-c8dc-4a13-9564-08ee4ebe5f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930023839 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1930023839
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1074675169
Short name T102
Test name
Test status
Simulation time 364472733 ps
CPU time 0.67 seconds
Started Jan 10 12:53:53 PM PST 24
Finished Jan 10 12:55:03 PM PST 24
Peak memory 182712 kb
Host smart-521fff0c-d83e-438a-a153-f517227b0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074675169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1074675169
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1767110855
Short name T135
Test name
Test status
Simulation time 20239929592 ps
CPU time 8.86 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:16 PM PST 24
Peak memory 182668 kb
Host smart-d2855938-75ff-4575-89f9-7e30ab2d811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767110855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1767110855
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1362291024
Short name T269
Test name
Test status
Simulation time 433053490 ps
CPU time 1.22 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:05 PM PST 24
Peak memory 182500 kb
Host smart-65abdea6-9df4-447d-91ac-fce15d4c822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362291024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1362291024
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.340286715
Short name T109
Test name
Test status
Simulation time 45282296340 ps
CPU time 66.46 seconds
Started Jan 10 12:53:59 PM PST 24
Finished Jan 10 12:56:15 PM PST 24
Peak memory 194196 kb
Host smart-073f8e08-b213-480a-8e6f-350ebed30777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340286715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.340286715
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.4076955261
Short name T248
Test name
Test status
Simulation time 141826729229 ps
CPU time 370.36 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 01:01:14 PM PST 24
Peak memory 197504 kb
Host smart-291eba6c-f656-4274-9347-f5a25d813a90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076955261 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.4076955261
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3288379161
Short name T93
Test name
Test status
Simulation time 436653027 ps
CPU time 0.65 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:04 PM PST 24
Peak memory 182660 kb
Host smart-8b7ab2eb-37ac-4c71-8445-4906cecbb2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288379161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3288379161
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.462494459
Short name T279
Test name
Test status
Simulation time 42239223869 ps
CPU time 48.38 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:55 PM PST 24
Peak memory 182680 kb
Host smart-3397bd82-ba0c-4ef9-a1ea-1536aa89fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462494459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.462494459
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3633981617
Short name T191
Test name
Test status
Simulation time 422493396 ps
CPU time 0.83 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:08 PM PST 24
Peak memory 182476 kb
Host smart-2da604e1-67df-4cc9-a882-8cd04caf882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633981617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3633981617
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1323944752
Short name T90
Test name
Test status
Simulation time 308698690138 ps
CPU time 509.28 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 01:03:33 PM PST 24
Peak memory 193048 kb
Host smart-d950575a-2eda-4bca-ada7-b8c37d70aef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323944752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1323944752
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1082158429
Short name T296
Test name
Test status
Simulation time 53131585766 ps
CPU time 462.58 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 01:02:46 PM PST 24
Peak memory 197636 kb
Host smart-c4c71c12-67db-46bb-81df-c6b25505b454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082158429 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1082158429
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1050470202
Short name T257
Test name
Test status
Simulation time 447864752 ps
CPU time 0.73 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:05 PM PST 24
Peak memory 182700 kb
Host smart-66814dc4-46d5-4593-935a-f5603219f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050470202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1050470202
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3489751775
Short name T123
Test name
Test status
Simulation time 49460403975 ps
CPU time 17.87 seconds
Started Jan 10 12:53:51 PM PST 24
Finished Jan 10 12:55:18 PM PST 24
Peak memory 182608 kb
Host smart-d92a4f78-dfbd-478e-b44f-449a0f7e77ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489751775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3489751775
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.2256853312
Short name T224
Test name
Test status
Simulation time 444409309 ps
CPU time 0.99 seconds
Started Jan 10 12:53:59 PM PST 24
Finished Jan 10 12:55:09 PM PST 24
Peak memory 182540 kb
Host smart-722af57c-4e9d-422e-ae11-a685dbfb75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256853312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.2256853312
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2640648405
Short name T228
Test name
Test status
Simulation time 303080464648 ps
CPU time 137.24 seconds
Started Jan 10 12:54:04 PM PST 24
Finished Jan 10 12:57:29 PM PST 24
Peak memory 192832 kb
Host smart-464d8adc-4387-4b77-a739-c35ea22569ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640648405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2640648405
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.4194617058
Short name T198
Test name
Test status
Simulation time 147603817095 ps
CPU time 310.31 seconds
Started Jan 10 12:53:56 PM PST 24
Finished Jan 10 01:00:16 PM PST 24
Peak memory 197872 kb
Host smart-34907219-ed2f-492f-bc97-83e8f141fbf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194617058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.4194617058
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4045554587
Short name T262
Test name
Test status
Simulation time 570868777 ps
CPU time 0.98 seconds
Started Jan 10 12:54:02 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 182680 kb
Host smart-f067bb1f-f798-4660-8d4b-1a6724b7b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045554587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4045554587
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2719644606
Short name T153
Test name
Test status
Simulation time 7918222721 ps
CPU time 12.39 seconds
Started Jan 10 12:53:54 PM PST 24
Finished Jan 10 12:55:16 PM PST 24
Peak memory 182716 kb
Host smart-b62ced0c-170d-490b-be56-52a45b926da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719644606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2719644606
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1492978010
Short name T207
Test name
Test status
Simulation time 397639337 ps
CPU time 0.68 seconds
Started Jan 10 12:53:57 PM PST 24
Finished Jan 10 12:55:07 PM PST 24
Peak memory 182628 kb
Host smart-f7f26f56-5042-4e49-b209-4c7de28551f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492978010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1492978010
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2302925153
Short name T95
Test name
Test status
Simulation time 32955950299 ps
CPU time 52.39 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:56:03 PM PST 24
Peak memory 182632 kb
Host smart-86ec9c10-d3ff-4dd8-9ea8-c035a7fa5e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302925153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2302925153
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.606113699
Short name T234
Test name
Test status
Simulation time 89263565626 ps
CPU time 121.7 seconds
Started Jan 10 12:54:02 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 197580 kb
Host smart-1fbcec82-6310-43c5-96d1-801cd53e807e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606113699 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.606113699
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1348987751
Short name T105
Test name
Test status
Simulation time 544656232 ps
CPU time 0.99 seconds
Started Jan 10 12:54:06 PM PST 24
Finished Jan 10 12:55:14 PM PST 24
Peak memory 182704 kb
Host smart-b1b592ee-3ebf-49f9-b850-c6a5935d25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348987751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1348987751
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.446666920
Short name T302
Test name
Test status
Simulation time 10659382668 ps
CPU time 17.02 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 182748 kb
Host smart-2281da93-f772-4a8f-8e45-fb5b0b60d077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446666920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.446666920
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3156330269
Short name T129
Test name
Test status
Simulation time 394657066 ps
CPU time 1.03 seconds
Started Jan 10 12:54:03 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 182536 kb
Host smart-c5ed5968-8c22-4fb9-9274-a3437ee5df76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156330269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3156330269
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2099457714
Short name T27
Test name
Test status
Simulation time 195142588019 ps
CPU time 75.94 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:56:25 PM PST 24
Peak memory 192908 kb
Host smart-2513425b-de87-41c1-bc25-d89b4fa9a501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099457714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2099457714
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.209959353
Short name T50
Test name
Test status
Simulation time 93594408868 ps
CPU time 736.2 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 01:07:26 PM PST 24
Peak memory 205816 kb
Host smart-42c607d4-159c-4313-b61e-5efdf99a6633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209959353 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.209959353
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3356947589
Short name T42
Test name
Test status
Simulation time 624955006 ps
CPU time 0.79 seconds
Started Jan 10 12:54:03 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 182612 kb
Host smart-b38c027d-c5b5-4ce0-886e-e2016df194ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356947589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3356947589
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3601225739
Short name T181
Test name
Test status
Simulation time 45491190091 ps
CPU time 62.91 seconds
Started Jan 10 12:54:13 PM PST 24
Finished Jan 10 12:56:22 PM PST 24
Peak memory 182020 kb
Host smart-fd4127a7-7674-4c3c-b623-ca1b9bfacdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601225739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3601225739
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1379180723
Short name T253
Test name
Test status
Simulation time 379395715 ps
CPU time 1.07 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:55:11 PM PST 24
Peak memory 182476 kb
Host smart-17490e0d-7639-441a-b676-bc930312f8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379180723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1379180723
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.1322555520
Short name T208
Test name
Test status
Simulation time 149875002758 ps
CPU time 218.21 seconds
Started Jan 10 12:53:59 PM PST 24
Finished Jan 10 12:58:47 PM PST 24
Peak memory 182700 kb
Host smart-995a200f-d297-436b-886d-1eff5bc88f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322555520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.1322555520
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_jump.3924413556
Short name T119
Test name
Test status
Simulation time 561774171 ps
CPU time 1.36 seconds
Started Jan 10 12:53:26 PM PST 24
Finished Jan 10 12:54:40 PM PST 24
Peak memory 182660 kb
Host smart-ef581dc5-2acf-472f-a9f8-4f4940381c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924413556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.3924413556
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1065174339
Short name T142
Test name
Test status
Simulation time 8374179001 ps
CPU time 3.7 seconds
Started Jan 10 12:53:25 PM PST 24
Finished Jan 10 12:54:42 PM PST 24
Peak memory 182628 kb
Host smart-85834681-3b13-4b81-b816-9afae57c5217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065174339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1065174339
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4273255634
Short name T35
Test name
Test status
Simulation time 8162397207 ps
CPU time 1.71 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:34 PM PST 24
Peak memory 214956 kb
Host smart-fb3a2b3b-4006-48da-ac41-2eaffc9c992d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273255634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4273255634
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.934868773
Short name T146
Test name
Test status
Simulation time 395347815 ps
CPU time 1.17 seconds
Started Jan 10 12:53:22 PM PST 24
Finished Jan 10 12:54:35 PM PST 24
Peak memory 182720 kb
Host smart-0ab64976-b8e4-47b7-8783-53e2f3eb2682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934868773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.934868773
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2596072821
Short name T200
Test name
Test status
Simulation time 233466689086 ps
CPU time 86.35 seconds
Started Jan 10 12:53:24 PM PST 24
Finished Jan 10 12:56:03 PM PST 24
Peak memory 182764 kb
Host smart-4174ee30-4376-41e9-a87c-beddbd0ac0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596072821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2596072821
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2035020308
Short name T51
Test name
Test status
Simulation time 26835406892 ps
CPU time 286.42 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:59:21 PM PST 24
Peak memory 197640 kb
Host smart-16ae0c41-4a73-45df-ac5f-559d655617b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035020308 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2035020308
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2181897697
Short name T209
Test name
Test status
Simulation time 524586955 ps
CPU time 1.33 seconds
Started Jan 10 12:54:03 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 182704 kb
Host smart-e6cb9124-b1ec-47d7-85fa-3f6154424905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181897697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2181897697
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3840494182
Short name T154
Test name
Test status
Simulation time 8244948622 ps
CPU time 11.62 seconds
Started Jan 10 12:54:03 PM PST 24
Finished Jan 10 12:55:23 PM PST 24
Peak memory 182660 kb
Host smart-8627281b-0909-4728-a313-ba42908d1639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840494182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3840494182
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3330406447
Short name T171
Test name
Test status
Simulation time 490786204 ps
CPU time 0.76 seconds
Started Jan 10 12:54:04 PM PST 24
Finished Jan 10 12:55:12 PM PST 24
Peak memory 182856 kb
Host smart-4fddca5e-6243-460f-82bf-46aadf2a223a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330406447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3330406447
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.273953660
Short name T175
Test name
Test status
Simulation time 292731964941 ps
CPU time 237.12 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:59:06 PM PST 24
Peak memory 192988 kb
Host smart-ab0b5b9c-0298-40e9-bd4c-b83af85b3814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273953660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.273953660
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3277625947
Short name T243
Test name
Test status
Simulation time 276622703580 ps
CPU time 261.79 seconds
Started Jan 10 12:54:02 PM PST 24
Finished Jan 10 12:59:33 PM PST 24
Peak memory 197636 kb
Host smart-cc6f13f5-6767-46f5-94d1-7f9ec69adf86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277625947 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3277625947
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3442981183
Short name T143
Test name
Test status
Simulation time 375260119 ps
CPU time 0.68 seconds
Started Jan 10 12:54:08 PM PST 24
Finished Jan 10 12:55:15 PM PST 24
Peak memory 182636 kb
Host smart-3a660cd6-b544-4770-95a9-d26cb0ead898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442981183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3442981183
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1231334977
Short name T165
Test name
Test status
Simulation time 37806771940 ps
CPU time 57.52 seconds
Started Jan 10 12:54:01 PM PST 24
Finished Jan 10 12:56:07 PM PST 24
Peak memory 182672 kb
Host smart-ba9f9846-e503-424a-acb5-4b8e2bc3e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231334977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1231334977
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2591106502
Short name T156
Test name
Test status
Simulation time 591280128 ps
CPU time 0.91 seconds
Started Jan 10 12:54:13 PM PST 24
Finished Jan 10 12:55:20 PM PST 24
Peak memory 181860 kb
Host smart-13bdf080-123f-4220-a19d-ab80e39c6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591106502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2591106502
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1678902336
Short name T275
Test name
Test status
Simulation time 261228028343 ps
CPU time 391.27 seconds
Started Jan 10 12:54:11 PM PST 24
Finished Jan 10 01:01:49 PM PST 24
Peak memory 182760 kb
Host smart-aee49078-f6c4-4496-ba78-111d3249cf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678902336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1678902336
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.3564816801
Short name T79
Test name
Test status
Simulation time 58125870313 ps
CPU time 639.99 seconds
Started Jan 10 12:54:08 PM PST 24
Finished Jan 10 01:05:54 PM PST 24
Peak memory 197600 kb
Host smart-4086ebd3-41f2-4c78-bb53-d5e9927d79e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564816801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.3564816801
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.4275980703
Short name T204
Test name
Test status
Simulation time 417242421 ps
CPU time 1.24 seconds
Started Jan 10 12:54:09 PM PST 24
Finished Jan 10 12:55:16 PM PST 24
Peak memory 182712 kb
Host smart-53df22a6-69ef-421e-9c6a-3dbc07dc0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275980703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.4275980703
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3843733785
Short name T144
Test name
Test status
Simulation time 24599866403 ps
CPU time 39.49 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:55:57 PM PST 24
Peak memory 182724 kb
Host smart-5b0cb13a-8761-47ac-aab7-445a069db5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843733785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3843733785
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.414492897
Short name T237
Test name
Test status
Simulation time 537568055 ps
CPU time 1.39 seconds
Started Jan 10 12:54:09 PM PST 24
Finished Jan 10 12:55:17 PM PST 24
Peak memory 182544 kb
Host smart-7931f1db-7215-455b-9985-5abeb8573092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414492897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.414492897
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3445403806
Short name T92
Test name
Test status
Simulation time 83697882336 ps
CPU time 257.43 seconds
Started Jan 10 12:54:09 PM PST 24
Finished Jan 10 12:59:33 PM PST 24
Peak memory 197636 kb
Host smart-08d97125-34a7-412f-947f-59c37bc52204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445403806 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3445403806
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.959801559
Short name T38
Test name
Test status
Simulation time 511223225 ps
CPU time 0.91 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:55:17 PM PST 24
Peak memory 182668 kb
Host smart-ad311c04-9c0e-44d5-81c4-68faf65429be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959801559 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.959801559
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3829771094
Short name T300
Test name
Test status
Simulation time 31517467141 ps
CPU time 11.4 seconds
Started Jan 10 12:54:11 PM PST 24
Finished Jan 10 12:55:28 PM PST 24
Peak memory 182732 kb
Host smart-aeea65f2-5cfb-4c7a-aa4f-8020ece9bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829771094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3829771094
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1793018562
Short name T194
Test name
Test status
Simulation time 409717268 ps
CPU time 0.6 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:55:19 PM PST 24
Peak memory 182592 kb
Host smart-cc9a1bf1-adca-45e6-90b9-68ce757ef613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793018562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1793018562
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3320062136
Short name T24
Test name
Test status
Simulation time 12994121306 ps
CPU time 9.19 seconds
Started Jan 10 12:54:11 PM PST 24
Finished Jan 10 12:55:26 PM PST 24
Peak memory 194168 kb
Host smart-0f5a1f15-7ab2-4736-99cc-dad18e14fda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320062136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3320062136
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3227172298
Short name T98
Test name
Test status
Simulation time 64588103630 ps
CPU time 179.47 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:58:16 PM PST 24
Peak memory 197512 kb
Host smart-25900543-708e-4f96-877c-8b6dd7d4010d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227172298 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3227172298
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.625131348
Short name T298
Test name
Test status
Simulation time 454080305 ps
CPU time 0.7 seconds
Started Jan 10 12:54:07 PM PST 24
Finished Jan 10 12:55:15 PM PST 24
Peak memory 182664 kb
Host smart-f7cf394b-40a0-4743-847f-298b9fa5fb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625131348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.625131348
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.800641613
Short name T287
Test name
Test status
Simulation time 20341496986 ps
CPU time 4.42 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:55:22 PM PST 24
Peak memory 182772 kb
Host smart-7b331b28-4ef0-41e5-84ef-337cf13a8eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800641613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.800641613
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.291811475
Short name T157
Test name
Test status
Simulation time 541022780 ps
CPU time 1.41 seconds
Started Jan 10 12:54:07 PM PST 24
Finished Jan 10 12:55:15 PM PST 24
Peak memory 182448 kb
Host smart-39d26b70-7c54-4bcb-ae45-be817f28821c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291811475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.291811475
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.3278440444
Short name T80
Test name
Test status
Simulation time 152615966551 ps
CPU time 239.73 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:59:16 PM PST 24
Peak memory 182676 kb
Host smart-475c35b6-45d2-4c38-8550-9fe84dd5fa0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278440444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.3278440444
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2910446175
Short name T285
Test name
Test status
Simulation time 439284474 ps
CPU time 0.78 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:55:17 PM PST 24
Peak memory 182612 kb
Host smart-ae1f8eab-3670-4a41-86f9-55f7a903b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910446175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2910446175
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1955588175
Short name T230
Test name
Test status
Simulation time 22744850329 ps
CPU time 36.28 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:55:54 PM PST 24
Peak memory 182724 kb
Host smart-91033f56-5e37-4640-8feb-1afee6383fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955588175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1955588175
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3954562316
Short name T278
Test name
Test status
Simulation time 387701779 ps
CPU time 1.04 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:55:19 PM PST 24
Peak memory 182484 kb
Host smart-fe83a18c-e52a-47c0-ad55-09e8b80c3e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954562316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3954562316
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.3269321267
Short name T162
Test name
Test status
Simulation time 29337751956 ps
CPU time 23.96 seconds
Started Jan 10 12:54:11 PM PST 24
Finished Jan 10 12:55:40 PM PST 24
Peak memory 182740 kb
Host smart-3b103b34-c640-4248-85ad-1b5583c49316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269321267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.3269321267
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.1989340659
Short name T222
Test name
Test status
Simulation time 55098033409 ps
CPU time 85.56 seconds
Started Jan 10 12:54:09 PM PST 24
Finished Jan 10 12:56:40 PM PST 24
Peak memory 197644 kb
Host smart-80b5c5f4-ec33-4ca7-8b10-e53ffce80eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989340659 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.1989340659
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.556968192
Short name T301
Test name
Test status
Simulation time 501578468 ps
CPU time 1.34 seconds
Started Jan 10 12:54:11 PM PST 24
Finished Jan 10 12:55:18 PM PST 24
Peak memory 182724 kb
Host smart-8d340af4-77af-4856-bf7c-82458d63373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556968192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.556968192
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2682955
Short name T136
Test name
Test status
Simulation time 7047076806 ps
CPU time 2.2 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:55:18 PM PST 24
Peak memory 182660 kb
Host smart-8d7d266c-a70e-4e3c-8a84-ea0a7a662156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2682955
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.2942238462
Short name T188
Test name
Test status
Simulation time 422207622 ps
CPU time 0.65 seconds
Started Jan 10 12:54:09 PM PST 24
Finished Jan 10 12:55:15 PM PST 24
Peak memory 182568 kb
Host smart-283972cd-21c1-4a76-8654-078ae4c8893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942238462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.2942238462
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1610212628
Short name T110
Test name
Test status
Simulation time 210511407675 ps
CPU time 86.35 seconds
Started Jan 10 12:54:10 PM PST 24
Finished Jan 10 12:56:42 PM PST 24
Peak memory 182792 kb
Host smart-697c8477-6585-4eeb-8494-29f9cff0e9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610212628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1610212628
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4080986752
Short name T164
Test name
Test status
Simulation time 53339478089 ps
CPU time 333.52 seconds
Started Jan 10 12:54:16 PM PST 24
Finished Jan 10 01:00:55 PM PST 24
Peak memory 197624 kb
Host smart-adbda4b9-7588-4710-8da2-183b92225d56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080986752 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4080986752
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3301123556
Short name T182
Test name
Test status
Simulation time 345748582 ps
CPU time 1.11 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 182644 kb
Host smart-c4432bee-441b-49f4-9e92-f9f616c17eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301123556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3301123556
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2664601728
Short name T180
Test name
Test status
Simulation time 59095674934 ps
CPU time 88.23 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:56:54 PM PST 24
Peak memory 182708 kb
Host smart-2346516a-e9c6-4e9c-b755-94b3ab52a0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664601728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2664601728
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4137211074
Short name T277
Test name
Test status
Simulation time 526052553 ps
CPU time 1.39 seconds
Started Jan 10 12:54:17 PM PST 24
Finished Jan 10 12:55:24 PM PST 24
Peak memory 182580 kb
Host smart-3d09c41c-5246-40d7-8b23-8c27f2c818d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137211074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4137211074
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.816373888
Short name T271
Test name
Test status
Simulation time 78474448739 ps
CPU time 115.87 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:57:21 PM PST 24
Peak memory 193008 kb
Host smart-2f15971a-1389-41f9-97b3-c76c10fa1077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816373888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_a
ll.816373888
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2404575304
Short name T206
Test name
Test status
Simulation time 23250376105 ps
CPU time 71.67 seconds
Started Jan 10 12:54:18 PM PST 24
Finished Jan 10 12:56:37 PM PST 24
Peak memory 197604 kb
Host smart-94ab75d2-cd82-49b8-8106-06bb5c6acf95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404575304 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2404575304
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1375054040
Short name T170
Test name
Test status
Simulation time 571133085 ps
CPU time 0.68 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:26 PM PST 24
Peak memory 182680 kb
Host smart-b0444acf-3fb5-46a7-bc88-9c40453e01a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375054040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1375054040
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.535320389
Short name T299
Test name
Test status
Simulation time 33222438673 ps
CPU time 15.61 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:42 PM PST 24
Peak memory 182744 kb
Host smart-f61ea5ba-f6a8-4f73-8e65-8ed9f6e4ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535320389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.535320389
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.792731552
Short name T40
Test name
Test status
Simulation time 471137330 ps
CPU time 0.93 seconds
Started Jan 10 12:54:21 PM PST 24
Finished Jan 10 12:55:28 PM PST 24
Peak memory 182596 kb
Host smart-b209be7e-e828-4944-a291-03ef824f6c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792731552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.792731552
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3310759416
Short name T190
Test name
Test status
Simulation time 33976537509 ps
CPU time 30.1 seconds
Started Jan 10 12:54:30 PM PST 24
Finished Jan 10 12:56:04 PM PST 24
Peak memory 192936 kb
Host smart-faaca704-3f17-43b8-a460-7bb7cfd6deb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310759416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3310759416
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1720150227
Short name T273
Test name
Test status
Simulation time 3241323262 ps
CPU time 24.88 seconds
Started Jan 10 12:54:20 PM PST 24
Finished Jan 10 12:55:51 PM PST 24
Peak memory 197524 kb
Host smart-8f514d5b-a7e5-405c-92d1-c51fa08bcc96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720150227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1720150227
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2774128330
Short name T99
Test name
Test status
Simulation time 587454588 ps
CPU time 0.67 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:26 PM PST 24
Peak memory 182704 kb
Host smart-b0e2da35-2dcd-4d47-bea1-2a4fa0eb5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774128330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2774128330
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1351552189
Short name T121
Test name
Test status
Simulation time 22769354222 ps
CPU time 2.76 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 12:55:28 PM PST 24
Peak memory 182724 kb
Host smart-cbd02175-bef8-4902-a45c-6e697308ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351552189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1351552189
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.48632449
Short name T155
Test name
Test status
Simulation time 525292439 ps
CPU time 0.66 seconds
Started Jan 10 12:54:20 PM PST 24
Finished Jan 10 12:55:27 PM PST 24
Peak memory 182644 kb
Host smart-a1c26035-a292-49d8-a0fd-cdcf9fd7e7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48632449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.48632449
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.1001082757
Short name T270
Test name
Test status
Simulation time 116996454277 ps
CPU time 158.78 seconds
Started Jan 10 12:54:18 PM PST 24
Finished Jan 10 12:58:03 PM PST 24
Peak memory 182692 kb
Host smart-d295c76d-3d04-4106-88cf-49aa0b5cf588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001082757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.1001082757
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2226618115
Short name T213
Test name
Test status
Simulation time 230429559521 ps
CPU time 841.09 seconds
Started Jan 10 12:54:19 PM PST 24
Finished Jan 10 01:09:26 PM PST 24
Peak memory 205820 kb
Host smart-32c1148c-317f-408b-a09d-893fe2b1c85e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226618115 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2226618115
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.4186004181
Short name T148
Test name
Test status
Simulation time 595833839 ps
CPU time 1.05 seconds
Started Jan 10 12:53:25 PM PST 24
Finished Jan 10 12:54:38 PM PST 24
Peak memory 182640 kb
Host smart-1d45cba2-614b-41ad-a74a-e96ad1ca512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186004181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.4186004181
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3714982634
Short name T232
Test name
Test status
Simulation time 19293524105 ps
CPU time 27.24 seconds
Started Jan 10 12:53:22 PM PST 24
Finished Jan 10 12:55:01 PM PST 24
Peak memory 182716 kb
Host smart-22faab64-d092-465a-b87d-423bbd481741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714982634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3714982634
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3548876198
Short name T265
Test name
Test status
Simulation time 583756488 ps
CPU time 0.99 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:36 PM PST 24
Peak memory 182516 kb
Host smart-5b61f2ca-052a-419d-b392-c388f8246d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548876198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3548876198
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2571280183
Short name T166
Test name
Test status
Simulation time 150548817646 ps
CPU time 251.5 seconds
Started Jan 10 12:53:26 PM PST 24
Finished Jan 10 12:58:50 PM PST 24
Peak memory 182696 kb
Host smart-c806eda1-b794-41a1-9d33-3c08409d1b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571280183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2571280183
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.19103010
Short name T75
Test name
Test status
Simulation time 46828946715 ps
CPU time 296.66 seconds
Started Jan 10 12:53:22 PM PST 24
Finished Jan 10 12:59:31 PM PST 24
Peak memory 197648 kb
Host smart-df9b5a53-dc69-4ea3-9ba3-8532672bc6cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103010 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.19103010
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4022108200
Short name T195
Test name
Test status
Simulation time 517120539 ps
CPU time 1.22 seconds
Started Jan 10 12:53:23 PM PST 24
Finished Jan 10 12:54:36 PM PST 24
Peak memory 182752 kb
Host smart-37e5d7e7-ca32-4d6d-bf0a-32eff5d00150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022108200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4022108200
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.619905665
Short name T205
Test name
Test status
Simulation time 10066275977 ps
CPU time 4.57 seconds
Started Jan 10 12:53:20 PM PST 24
Finished Jan 10 12:54:37 PM PST 24
Peak memory 182728 kb
Host smart-c0767409-67ee-4e31-92d3-c8bf8dff27fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619905665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.619905665
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2167203715
Short name T29
Test name
Test status
Simulation time 587867271 ps
CPU time 1.02 seconds
Started Jan 10 12:53:22 PM PST 24
Finished Jan 10 12:54:35 PM PST 24
Peak memory 182520 kb
Host smart-d548b3fe-d1f5-412a-948e-e49ad65da97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167203715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2167203715
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.2770333032
Short name T104
Test name
Test status
Simulation time 3290948128 ps
CPU time 5.51 seconds
Started Jan 10 12:53:30 PM PST 24
Finished Jan 10 12:54:49 PM PST 24
Peak memory 192804 kb
Host smart-d7777c21-1dc3-4f2c-9dee-2edfb808e82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770333032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.2770333032
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2358757722
Short name T44
Test name
Test status
Simulation time 64529854612 ps
CPU time 206.96 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:58:09 PM PST 24
Peak memory 197636 kb
Host smart-3dccd46f-d3b6-465d-819f-cd81a70f3704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358757722 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2358757722
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3842326477
Short name T149
Test name
Test status
Simulation time 449011297 ps
CPU time 0.71 seconds
Started Jan 10 12:53:33 PM PST 24
Finished Jan 10 12:54:47 PM PST 24
Peak memory 182644 kb
Host smart-f2de8d7f-d7b5-4621-bd4e-cc4865c5a3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842326477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3842326477
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3151476653
Short name T214
Test name
Test status
Simulation time 3723300004 ps
CPU time 1.75 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:54:41 PM PST 24
Peak memory 182724 kb
Host smart-e9efb88c-11a3-4f3e-844f-a40e090cbec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151476653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3151476653
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.112795239
Short name T37
Test name
Test status
Simulation time 421145825 ps
CPU time 0.66 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:54:43 PM PST 24
Peak memory 182716 kb
Host smart-5fa9c8c6-cdf7-4a4e-8a7d-7bfb06c59fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112795239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.112795239
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.932013328
Short name T167
Test name
Test status
Simulation time 64054894992 ps
CPU time 259.59 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:59:02 PM PST 24
Peak memory 205852 kb
Host smart-79a8fa2d-5a83-49a3-b39a-4c7fcacd8d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932013328 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.932013328
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3095413805
Short name T168
Test name
Test status
Simulation time 416737328 ps
CPU time 0.68 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:54:43 PM PST 24
Peak memory 182640 kb
Host smart-4bbe447b-0bd1-4739-9618-e7a9b53cb007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095413805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3095413805
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3047116028
Short name T31
Test name
Test status
Simulation time 10790195223 ps
CPU time 4.39 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:54:46 PM PST 24
Peak memory 182680 kb
Host smart-359377f3-0b99-4010-b259-b3352276dee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047116028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3047116028
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1569037310
Short name T260
Test name
Test status
Simulation time 524251176 ps
CPU time 0.91 seconds
Started Jan 10 12:53:41 PM PST 24
Finished Jan 10 12:54:52 PM PST 24
Peak memory 182548 kb
Host smart-25ae9bf4-22bf-407b-ad67-c55522dc61e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569037310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1569037310
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1137178904
Short name T196
Test name
Test status
Simulation time 6553002352 ps
CPU time 10.82 seconds
Started Jan 10 12:53:30 PM PST 24
Finished Jan 10 12:54:54 PM PST 24
Peak memory 182620 kb
Host smart-dabed698-5858-4120-97e1-8e915b4faae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137178904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1137178904
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.986814461
Short name T114
Test name
Test status
Simulation time 1776225221863 ps
CPU time 838.19 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 01:08:40 PM PST 24
Peak memory 201572 kb
Host smart-255bf350-de12-4a13-8af1-fdd966d38fbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986814461 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.986814461
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1709073915
Short name T189
Test name
Test status
Simulation time 425549302 ps
CPU time 1.11 seconds
Started Jan 10 12:53:30 PM PST 24
Finished Jan 10 12:54:44 PM PST 24
Peak memory 182720 kb
Host smart-d155fb7c-20ac-4722-af15-b39c0dc9e02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709073915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1709073915
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.759249794
Short name T256
Test name
Test status
Simulation time 18319278970 ps
CPU time 1.87 seconds
Started Jan 10 12:53:28 PM PST 24
Finished Jan 10 12:54:42 PM PST 24
Peak memory 182660 kb
Host smart-a0f10dd9-4493-457d-96ea-47faf118f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759249794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.759249794
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1370044789
Short name T259
Test name
Test status
Simulation time 508650064 ps
CPU time 1.3 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:54:43 PM PST 24
Peak memory 182608 kb
Host smart-c8e247de-49c2-4da7-9df9-e3f9d2c77075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370044789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1370044789
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.756867629
Short name T268
Test name
Test status
Simulation time 107871714813 ps
CPU time 47.67 seconds
Started Jan 10 12:53:29 PM PST 24
Finished Jan 10 12:55:30 PM PST 24
Peak memory 192776 kb
Host smart-4add7091-03fc-4349-98d9-45fddfc8104b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756867629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.756867629
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1258561289
Short name T236
Test name
Test status
Simulation time 91276830549 ps
CPU time 392.4 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 01:01:12 PM PST 24
Peak memory 197660 kb
Host smart-c0e940e8-cf7f-434c-94d0-2179f19d3f89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258561289 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1258561289
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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