Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
97.16 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 4 137 97.16


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 0 34 100.00 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 27128 1 T16 10 T17 564 T19 11
bark[1] 339 1 T26 16 T81 22 T82 26
bark[2] 500 1 T27 16 T83 206 T84 16
bark[3] 119 1 T51 21 T77 37 T85 45
bark[4] 254 1 T86 16 T87 16 T88 26
bark[5] 422 1 T17 243 T20 6 T89 13
bark[6] 507 1 T22 114 T51 16 T90 39
bark[7] 1006 1 T20 79 T41 16 T91 16
bark[8] 191 1 T83 17 T69 17 T92 31
bark[9] 301 1 T17 20 T93 12 T94 12
bark[10] 294 1 T95 21 T96 104 T97 27
bark[11] 600 1 T98 16 T78 16 T99 16
bark[12] 522 1 T100 16 T101 31 T98 27
bark[13] 407 1 T17 35 T102 16 T95 16
bark[14] 218 1 T26 45 T27 16 T103 12
bark[15] 337 1 T75 17 T104 12 T105 12
bark[16] 413 1 T106 33 T101 16 T86 169
bark[17] 1281 1 T37 16 T46 72 T75 6
bark[18] 697 1 T107 12 T108 105 T28 60
bark[19] 692 1 T46 23 T86 16 T69 65
bark[20] 349 1 T22 17 T27 12 T68 16
bark[21] 60 1 T109 12 T77 16 T110 16
bark[22] 789 1 T26 47 T68 16 T111 58
bark[23] 201 1 T27 16 T112 12 T91 42
bark[24] 523 1 T17 16 T22 5 T40 13
bark[25] 810 1 T17 16 T20 88 T98 22
bark[26] 880 1 T26 13 T108 16 T113 12
bark[27] 1077 1 T18 12 T68 58 T91 16
bark[28] 570 1 T36 12 T100 16 T83 136
bark[29] 284 1 T100 66 T28 22 T81 32
bark[30] 758 1 T22 302 T46 27 T68 16
bark[31] 453 1 T38 66 T84 30 T50 112
bark_0 3460 1 T15 6 T70 9 T71 5


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 26868 1 T16 9 T17 575 T19 10
bite[1] 239 1 T27 11 T28 51 T111 17
bite[2] 578 1 T68 16 T91 32 T76 190
bite[3] 624 1 T17 19 T22 113 T83 16
bite[4] 399 1 T83 16 T69 48 T114 31
bite[5] 745 1 T101 127 T91 16 T98 22
bite[6] 564 1 T26 16 T27 16 T69 428
bite[7] 1011 1 T17 242 T18 11 T26 12
bite[8] 333 1 T91 16 T92 16 T102 26
bite[9] 192 1 T22 17 T115 11 T113 16
bite[10] 469 1 T27 16 T93 11 T91 16
bite[11] 273 1 T22 4 T84 30 T77 16
bite[12] 1292 1 T22 301 T116 27 T78 169
bite[13] 453 1 T100 65 T117 11 T76 17
bite[14] 301 1 T81 22 T78 16 T102 21
bite[15] 522 1 T68 36 T101 30 T83 135
bite[16] 505 1 T113 11 T98 16 T118 20
bite[17] 163 1 T109 11 T75 5 T78 16
bite[18] 503 1 T37 16 T27 16 T68 76
bite[19] 287 1 T26 45 T107 11 T99 32
bite[20] 1107 1 T20 87 T38 65 T108 32
bite[21] 338 1 T75 17 T106 16 T50 25
bite[22] 221 1 T111 57 T119 11 T120 16
bite[23] 615 1 T41 16 T46 27 T83 205
bite[24] 606 1 T40 12 T68 16 T91 26
bite[25] 296 1 T28 60 T83 17 T113 16
bite[26] 320 1 T82 26 T121 17 T122 11
bite[27] 511 1 T20 78 T36 11 T26 16
bite[28] 603 1 T17 34 T100 16 T83 16
bite[29] 407 1 T26 31 T89 12 T46 76
bite[30] 888 1 T17 16 T103 11 T68 57
bite[31] 231 1 T46 23 T28 22 T98 26
bite_0 3978 1 T15 6 T70 9 T71 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 46442 1 T15 6 T70 9 T71 5


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 0 34 100.00


User Defined Bins for prescale_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale_max 8 1 T123 8 - - - -
prescale[0] 1159 1 T17 15 T22 196 T41 31
prescale[1] 672 1 T20 18 T26 47 T75 40
prescale[2] 1004 1 T17 15 T20 2 T38 2
prescale[3] 1059 1 T17 30 T38 33 T108 18
prescale[4] 1053 1 T22 72 T37 41 T41 2
prescale[5] 799 1 T91 22 T83 30 T84 31
prescale[6] 689 1 T17 29 T68 67 T81 47
prescale[7] 774 1 T17 32 T26 18 T100 21
prescale[8] 589 1 T17 59 T22 31 T38 41
prescale[9] 513 1 T17 15 T22 2 T37 2
prescale[10] 730 1 T17 2 T20 40 T37 2
prescale[11] 560 1 T22 15 T38 24 T27 18
prescale[12] 862 1 T26 23 T108 22 T68 168
prescale[13] 869 1 T17 31 T46 2 T68 24
prescale[14] 790 1 T17 49 T38 17 T27 18
prescale[15] 694 1 T17 29 T22 43 T26 15
prescale[16] 783 1 T17 31 T27 18 T75 2
prescale[17] 326 1 T17 2 T26 28 T46 16
prescale[18] 902 1 T17 83 T38 22 T46 140
prescale[19] 684 1 T17 8 T19 8 T20 2
prescale[20] 760 1 T31 8 T124 8 T68 77
prescale[21] 494 1 T101 98 T86 15 T83 47
prescale[22] 820 1 T108 2 T68 24 T118 2
prescale[23] 717 1 T17 7 T22 2 T37 2
prescale[24] 604 1 T17 2 T21 8 T100 78
prescale[25] 401 1 T100 30 T75 29 T68 21
prescale[26] 497 1 T69 134 T92 15 T51 2
prescale[27] 613 1 T17 31 T29 8 T27 15
prescale[28] 707 1 T22 15 T39 8 T100 59
prescale[29] 619 1 T17 29 T22 2 T75 2
prescale[30] 937 1 T17 29 T22 4 T38 57
prescale[31] 907 1 T17 16 T20 2 T46 25
prescale_0 22855 1 T15 6 T70 9 T71 5


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35354 1 T15 6 T70 9 T71 5
auto[1] 11088 1 T16 8 T17 222 T18 10


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 46442 1 T15 6 T70 9 T71 5


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28007 1 T16 11 T17 600 T19 12
wkup[1] 402 1 T26 16 T100 16 T83 16
wkup[2] 543 1 T22 16 T100 13 T111 16
wkup[3] 351 1 T17 32 T22 17 T93 13
wkup[4] 490 1 T20 7 T26 14 T100 31
wkup[5] 587 1 T27 16 T115 13 T28 16
wkup[6] 438 1 T17 16 T20 16 T22 33
wkup[7] 593 1 T22 33 T68 32 T113 16
wkup[8] 365 1 T17 38 T68 26 T111 26
wkup[9] 274 1 T38 7 T103 13 T108 42
wkup[10] 450 1 T17 16 T37 16 T41 7
wkup[11] 566 1 T20 34 T22 16 T38 16
wkup[12] 384 1 T22 16 T38 16 T108 7
wkup[13] 390 1 T17 22 T20 17 T22 16
wkup[14] 334 1 T17 16 T22 6 T68 16
wkup[15] 493 1 T22 21 T26 16 T38 25
wkup[16] 506 1 T20 16 T26 16 T37 16
wkup[17] 634 1 T37 16 T100 28 T75 17
wkup[18] 697 1 T17 33 T22 16 T46 26
wkup[19] 592 1 T17 16 T40 14 T41 16
wkup[20] 393 1 T22 16 T37 22 T101 16
wkup[21] 510 1 T17 16 T108 16 T28 16
wkup[22] 585 1 T17 16 T22 16 T68 32
wkup[23] 412 1 T68 26 T83 16 T119 13
wkup[24] 407 1 T22 45 T37 16 T46 27
wkup[25] 706 1 T22 16 T46 23 T108 32
wkup[26] 563 1 T17 16 T22 16 T89 14
wkup[27] 469 1 T46 7 T100 16 T28 16
wkup[28] 554 1 T17 16 T22 16 T26 16
wkup[29] 581 1 T17 16 T18 13 T68 48
wkup[30] 586 1 T17 33 T108 26 T81 38
wkup[31] 593 1 T22 16 T46 41 T75 7
wkup_0 2987 1 T15 6 T70 9 T71 5

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