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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.61 99.82 95.32 100.00 99.35 100.00 97.16


Total test records in report: 429
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T270 /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1586674852 Jan 14 01:09:36 PM PST 24 Jan 14 01:17:11 PM PST 24 56470293547 ps
T271 /workspace/coverage/default/23.aon_timer_smoke.907967471 Jan 14 01:09:07 PM PST 24 Jan 14 01:09:09 PM PST 24 525177766 ps
T272 /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1136101799 Jan 14 01:09:26 PM PST 24 Jan 14 01:12:34 PM PST 24 65451792239 ps
T273 /workspace/coverage/default/5.aon_timer_stress_all.3630394855 Jan 14 01:08:45 PM PST 24 Jan 14 01:09:58 PM PST 24 245481721473 ps
T274 /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.896090184 Jan 14 01:09:33 PM PST 24 Jan 14 01:17:40 PM PST 24 64207971441 ps
T275 /workspace/coverage/default/25.aon_timer_smoke.1117191807 Jan 14 01:09:17 PM PST 24 Jan 14 01:09:19 PM PST 24 406119718 ps
T276 /workspace/coverage/default/49.aon_timer_prescaler.1003201871 Jan 14 01:09:36 PM PST 24 Jan 14 01:10:07 PM PST 24 37851249431 ps
T277 /workspace/coverage/default/29.aon_timer_smoke.3243837953 Jan 14 01:09:16 PM PST 24 Jan 14 01:09:17 PM PST 24 678297953 ps
T278 /workspace/coverage/default/11.aon_timer_stress_all.2003615522 Jan 14 01:09:03 PM PST 24 Jan 14 01:10:44 PM PST 24 145231109326 ps
T279 /workspace/coverage/default/40.aon_timer_jump.3325136969 Jan 14 01:09:31 PM PST 24 Jan 14 01:09:33 PM PST 24 600702794 ps
T280 /workspace/coverage/default/20.aon_timer_prescaler.1407780673 Jan 14 01:09:03 PM PST 24 Jan 14 01:09:08 PM PST 24 19873200240 ps
T281 /workspace/coverage/default/26.aon_timer_jump.2070498983 Jan 14 01:09:19 PM PST 24 Jan 14 01:09:21 PM PST 24 569491925 ps
T282 /workspace/coverage/default/30.aon_timer_prescaler.268853431 Jan 14 01:09:25 PM PST 24 Jan 14 01:09:30 PM PST 24 2723916554 ps
T283 /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1816911205 Jan 14 01:09:00 PM PST 24 Jan 14 01:16:55 PM PST 24 47606167540 ps
T284 /workspace/coverage/default/19.aon_timer_jump.390690153 Jan 14 01:09:05 PM PST 24 Jan 14 01:09:07 PM PST 24 549566895 ps
T285 /workspace/coverage/default/33.aon_timer_prescaler.1308436031 Jan 14 01:09:15 PM PST 24 Jan 14 01:09:28 PM PST 24 28567951838 ps
T35 /workspace/coverage/default/3.aon_timer_sec_cm.3890035836 Jan 14 01:08:35 PM PST 24 Jan 14 01:08:38 PM PST 24 4444860703 ps
T286 /workspace/coverage/default/19.aon_timer_stress_all.1979761953 Jan 14 01:09:01 PM PST 24 Jan 14 01:09:14 PM PST 24 45586154006 ps
T287 /workspace/coverage/default/5.aon_timer_smoke.797266504 Jan 14 01:08:49 PM PST 24 Jan 14 01:08:50 PM PST 24 561990588 ps
T288 /workspace/coverage/default/13.aon_timer_smoke.26563074 Jan 14 01:09:02 PM PST 24 Jan 14 01:09:04 PM PST 24 399741699 ps
T289 /workspace/coverage/default/41.aon_timer_smoke.1486434954 Jan 14 01:09:34 PM PST 24 Jan 14 01:09:36 PM PST 24 437149962 ps
T290 /workspace/coverage/default/49.aon_timer_stress_all.4239349531 Jan 14 01:09:35 PM PST 24 Jan 14 01:10:52 PM PST 24 187932413937 ps
T291 /workspace/coverage/default/36.aon_timer_prescaler.727602643 Jan 14 01:09:32 PM PST 24 Jan 14 01:10:16 PM PST 24 55081960487 ps
T292 /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.603711767 Jan 14 01:09:08 PM PST 24 Jan 14 01:24:40 PM PST 24 178764725232 ps
T293 /workspace/coverage/default/26.aon_timer_stress_all.3707448774 Jan 14 01:09:10 PM PST 24 Jan 14 01:09:36 PM PST 24 73087749821 ps
T294 /workspace/coverage/default/37.aon_timer_stress_all.3254785055 Jan 14 01:09:27 PM PST 24 Jan 14 01:12:20 PM PST 24 204036973177 ps
T295 /workspace/coverage/default/44.aon_timer_stress_all.561602419 Jan 14 01:09:33 PM PST 24 Jan 14 01:13:48 PM PST 24 152500233616 ps
T296 /workspace/coverage/default/31.aon_timer_jump.1133702562 Jan 14 01:09:29 PM PST 24 Jan 14 01:09:31 PM PST 24 433273860 ps
T297 /workspace/coverage/default/38.aon_timer_stress_all.1627867140 Jan 14 01:09:30 PM PST 24 Jan 14 01:10:29 PM PST 24 171384600677 ps
T298 /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2452272219 Jan 14 01:08:46 PM PST 24 Jan 14 01:17:50 PM PST 24 53534529108 ps
T299 /workspace/coverage/default/8.aon_timer_jump.1137586879 Jan 14 01:09:04 PM PST 24 Jan 14 01:09:05 PM PST 24 464492815 ps
T300 /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4100623617 Jan 14 01:08:39 PM PST 24 Jan 14 01:16:57 PM PST 24 45715126522 ps
T301 /workspace/coverage/default/15.aon_timer_prescaler.3321697299 Jan 14 01:09:11 PM PST 24 Jan 14 01:09:52 PM PST 24 23845279579 ps
T302 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1831263214 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:54 PM PST 24 384724813 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1634073743 Jan 14 01:03:08 PM PST 24 Jan 14 01:03:10 PM PST 24 479279050 ps
T304 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3455298735 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 382645501 ps
T52 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2365219444 Jan 14 01:03:13 PM PST 24 Jan 14 01:03:15 PM PST 24 515622886 ps
T79 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4261194237 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:55 PM PST 24 8310159389 ps
T305 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.394606950 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:52 PM PST 24 4100398176 ps
T306 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.403594648 Jan 14 01:03:16 PM PST 24 Jan 14 01:03:19 PM PST 24 947842394 ps
T307 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2374584662 Jan 14 01:03:43 PM PST 24 Jan 14 01:03:47 PM PST 24 467532816 ps
T308 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3684528530 Jan 14 01:03:13 PM PST 24 Jan 14 01:03:15 PM PST 24 667726528 ps
T309 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3073680278 Jan 14 01:03:39 PM PST 24 Jan 14 01:03:45 PM PST 24 620869159 ps
T310 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.891000571 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:50 PM PST 24 518987318 ps
T53 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1395586536 Jan 14 01:03:38 PM PST 24 Jan 14 01:03:44 PM PST 24 442415737 ps
T311 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2048738467 Jan 14 01:03:22 PM PST 24 Jan 14 01:03:23 PM PST 24 547829911 ps
T312 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1814804360 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:58 PM PST 24 457737165 ps
T313 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.929137560 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 416936686 ps
T314 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1631826627 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 395823517 ps
T315 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2160693761 Jan 14 01:03:54 PM PST 24 Jan 14 01:03:56 PM PST 24 438526914 ps
T316 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2394348681 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:52 PM PST 24 312139371 ps
T54 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.428255703 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:48 PM PST 24 313333618 ps
T317 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3463268716 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:50 PM PST 24 4502626399 ps
T318 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4254660642 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:54 PM PST 24 359303201 ps
T319 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3918900700 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:55 PM PST 24 1058081314 ps
T80 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.560087963 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:54 PM PST 24 4188470104 ps
T320 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2044184334 Jan 14 01:03:54 PM PST 24 Jan 14 01:04:02 PM PST 24 4415317567 ps
T63 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3015431673 Jan 14 01:03:50 PM PST 24 Jan 14 01:03:52 PM PST 24 518131695 ps
T321 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.437891212 Jan 14 01:03:18 PM PST 24 Jan 14 01:03:20 PM PST 24 852286044 ps
T322 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3264497162 Jan 14 01:03:20 PM PST 24 Jan 14 01:03:21 PM PST 24 350783716 ps
T323 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4102630823 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:51 PM PST 24 533566086 ps
T324 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.155248165 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:49 PM PST 24 511087794 ps
T64 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1274894372 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:51 PM PST 24 995894136 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4155650958 Jan 14 01:03:11 PM PST 24 Jan 14 01:03:12 PM PST 24 372226389 ps
T65 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1902700211 Jan 14 01:03:19 PM PST 24 Jan 14 01:03:20 PM PST 24 1289813357 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1858911246 Jan 14 01:03:15 PM PST 24 Jan 14 01:03:16 PM PST 24 382018690 ps
T326 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1828176794 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:51 PM PST 24 407196339 ps
T327 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2813869178 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:54 PM PST 24 454083695 ps
T67 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1670546842 Jan 14 01:03:37 PM PST 24 Jan 14 01:03:39 PM PST 24 1265505324 ps
T328 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2183192688 Jan 14 01:03:24 PM PST 24 Jan 14 01:03:35 PM PST 24 4159397285 ps
T329 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1004518109 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 491896255 ps
T330 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4218591597 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:49 PM PST 24 735958975 ps
T331 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4067291430 Jan 14 01:03:08 PM PST 24 Jan 14 01:03:10 PM PST 24 2733766932 ps
T332 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3757574869 Jan 14 01:03:50 PM PST 24 Jan 14 01:03:52 PM PST 24 368620969 ps
T333 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.628226025 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:49 PM PST 24 504265604 ps
T334 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4098063791 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 2320365564 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4228829869 Jan 14 01:03:20 PM PST 24 Jan 14 01:03:23 PM PST 24 710903696 ps
T336 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2561494756 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:50 PM PST 24 373596833 ps
T337 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2234879045 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:52 PM PST 24 568420089 ps
T338 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2366216768 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 339845803 ps
T339 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.733787398 Jan 14 01:03:42 PM PST 24 Jan 14 01:03:44 PM PST 24 457742248 ps
T340 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1454580629 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:48 PM PST 24 524700004 ps
T55 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1615497800 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 463576159 ps
T56 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4161733353 Jan 14 01:03:26 PM PST 24 Jan 14 01:03:39 PM PST 24 4200051096 ps
T341 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.763875742 Jan 14 01:03:43 PM PST 24 Jan 14 01:03:48 PM PST 24 378925011 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1411705048 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:47 PM PST 24 546535068 ps
T343 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1610035416 Jan 14 01:03:17 PM PST 24 Jan 14 01:03:19 PM PST 24 491128700 ps
T344 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2016607351 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:54 PM PST 24 330127583 ps
T57 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3152114125 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:49 PM PST 24 354573244 ps
T345 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.754011014 Jan 14 01:03:55 PM PST 24 Jan 14 01:03:56 PM PST 24 418473507 ps
T346 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4245973129 Jan 14 01:03:40 PM PST 24 Jan 14 01:03:46 PM PST 24 1873078073 ps
T347 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.442688064 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:54 PM PST 24 437826225 ps
T348 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3192922606 Jan 14 01:03:24 PM PST 24 Jan 14 01:03:28 PM PST 24 475985597 ps
T349 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3193599894 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:58 PM PST 24 527747389 ps
T58 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.236693966 Jan 14 01:03:13 PM PST 24 Jan 14 01:03:14 PM PST 24 503411006 ps
T350 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2463615839 Jan 14 01:03:20 PM PST 24 Jan 14 01:03:21 PM PST 24 390327609 ps
T351 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1351047090 Jan 14 01:03:48 PM PST 24 Jan 14 01:03:51 PM PST 24 366528986 ps
T352 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1148350286 Jan 14 01:03:39 PM PST 24 Jan 14 01:03:45 PM PST 24 375842253 ps
T353 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4281061605 Jan 14 01:04:03 PM PST 24 Jan 14 01:04:05 PM PST 24 375309562 ps
T354 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3827449374 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:48 PM PST 24 480231074 ps
T355 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.708934912 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:50 PM PST 24 492989198 ps
T356 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.652733348 Jan 14 01:03:58 PM PST 24 Jan 14 01:04:00 PM PST 24 498019644 ps
T357 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.286777890 Jan 14 01:03:25 PM PST 24 Jan 14 01:03:29 PM PST 24 514952386 ps
T358 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1342678369 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:50 PM PST 24 1127074566 ps
T359 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2460491781 Jan 14 01:04:00 PM PST 24 Jan 14 01:04:01 PM PST 24 472015867 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3402742555 Jan 14 01:03:17 PM PST 24 Jan 14 01:03:19 PM PST 24 1033854147 ps
T360 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2914281343 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:51 PM PST 24 412843105 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.904688837 Jan 14 01:03:26 PM PST 24 Jan 14 01:03:29 PM PST 24 914829628 ps
T362 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1227495703 Jan 14 01:03:48 PM PST 24 Jan 14 01:03:52 PM PST 24 1198858815 ps
T363 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.821232398 Jan 14 01:03:59 PM PST 24 Jan 14 01:04:01 PM PST 24 481614052 ps
T60 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1700196511 Jan 14 01:03:12 PM PST 24 Jan 14 01:03:13 PM PST 24 1145533814 ps
T364 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2792680087 Jan 14 01:03:41 PM PST 24 Jan 14 01:03:45 PM PST 24 436059488 ps
T365 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3257703255 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:48 PM PST 24 537680143 ps
T366 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2903674560 Jan 14 01:03:48 PM PST 24 Jan 14 01:03:51 PM PST 24 523445113 ps
T367 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.141745940 Jan 14 01:04:01 PM PST 24 Jan 14 01:04:02 PM PST 24 523417346 ps
T368 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.757296086 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:49 PM PST 24 383120096 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.778543498 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:55 PM PST 24 8720239960 ps
T370 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.608291536 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:48 PM PST 24 398209614 ps
T371 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3897798443 Jan 14 01:03:23 PM PST 24 Jan 14 01:03:29 PM PST 24 1098433659 ps
T372 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4225893404 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:49 PM PST 24 369764879 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3319248054 Jan 14 01:03:12 PM PST 24 Jan 14 01:03:14 PM PST 24 399577826 ps
T374 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4224062505 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 329985216 ps
T375 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4097074373 Jan 14 01:03:16 PM PST 24 Jan 14 01:03:19 PM PST 24 6177084152 ps
T376 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1796194027 Jan 14 01:03:36 PM PST 24 Jan 14 01:03:38 PM PST 24 1098356651 ps
T377 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1320043297 Jan 14 01:03:58 PM PST 24 Jan 14 01:04:00 PM PST 24 402837224 ps
T378 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1724187851 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:59 PM PST 24 365138586 ps
T379 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1111564574 Jan 14 01:03:40 PM PST 24 Jan 14 01:03:44 PM PST 24 519847413 ps
T380 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2530736998 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:49 PM PST 24 1544843666 ps
T381 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3708825376 Jan 14 01:03:57 PM PST 24 Jan 14 01:03:58 PM PST 24 414865626 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3123907041 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:49 PM PST 24 2698442987 ps
T383 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1062175434 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 1346436633 ps
T384 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.25886249 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:48 PM PST 24 355432538 ps
T61 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4293678867 Jan 14 01:03:54 PM PST 24 Jan 14 01:03:55 PM PST 24 342997318 ps
T385 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2107726263 Jan 14 01:03:47 PM PST 24 Jan 14 01:03:50 PM PST 24 554581084 ps
T386 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1317516440 Jan 14 01:03:59 PM PST 24 Jan 14 01:04:01 PM PST 24 400740240 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2312502168 Jan 14 01:03:18 PM PST 24 Jan 14 01:03:19 PM PST 24 307491126 ps
T388 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4183808713 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:50 PM PST 24 875208392 ps
T389 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1441282640 Jan 14 01:03:20 PM PST 24 Jan 14 01:03:22 PM PST 24 475467037 ps
T62 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2864415623 Jan 14 01:03:10 PM PST 24 Jan 14 01:03:11 PM PST 24 621266153 ps
T390 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3237702704 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:48 PM PST 24 508538807 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3002492780 Jan 14 01:03:45 PM PST 24 Jan 14 01:03:52 PM PST 24 8781639931 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1129248549 Jan 14 01:03:22 PM PST 24 Jan 14 01:03:24 PM PST 24 512138814 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3038948863 Jan 14 01:03:17 PM PST 24 Jan 14 01:03:20 PM PST 24 3690341064 ps
T394 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2710209435 Jan 14 01:03:12 PM PST 24 Jan 14 01:03:13 PM PST 24 403951823 ps
T395 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1109957553 Jan 14 01:03:44 PM PST 24 Jan 14 01:03:48 PM PST 24 331507500 ps
T396 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3308908530 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:53 PM PST 24 4035107405 ps
T397 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2291200608 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 385082616 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3568495003 Jan 14 01:03:24 PM PST 24 Jan 14 01:03:28 PM PST 24 490766279 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4039539154 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:52 PM PST 24 4476758481 ps
T400 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3455109754 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:55 PM PST 24 332507008 ps
T401 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3930673466 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:50 PM PST 24 4294531113 ps
T402 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2964399333 Jan 14 01:03:07 PM PST 24 Jan 14 01:03:09 PM PST 24 979879233 ps
T403 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.498739891 Jan 14 01:03:07 PM PST 24 Jan 14 01:03:08 PM PST 24 539320606 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1908027683 Jan 14 01:03:53 PM PST 24 Jan 14 01:03:55 PM PST 24 581784256 ps
T405 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1535006323 Jan 14 01:03:10 PM PST 24 Jan 14 01:03:13 PM PST 24 517118512 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3861941258 Jan 14 01:03:43 PM PST 24 Jan 14 01:03:48 PM PST 24 523643096 ps
T407 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.651371954 Jan 14 01:03:12 PM PST 24 Jan 14 01:03:13 PM PST 24 312161503 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.531880632 Jan 14 01:03:39 PM PST 24 Jan 14 01:03:44 PM PST 24 401596626 ps
T409 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2894558737 Jan 14 01:03:59 PM PST 24 Jan 14 01:04:00 PM PST 24 391192276 ps
T410 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.933513422 Jan 14 01:03:56 PM PST 24 Jan 14 01:03:57 PM PST 24 511071168 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.739799145 Jan 14 01:03:07 PM PST 24 Jan 14 01:03:09 PM PST 24 516732576 ps
T412 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1484485516 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:48 PM PST 24 402272790 ps
T413 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1857255875 Jan 14 01:03:46 PM PST 24 Jan 14 01:03:52 PM PST 24 8204807047 ps
T414 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2251403708 Jan 14 01:03:08 PM PST 24 Jan 14 01:03:13 PM PST 24 8989401745 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3827545441 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:52 PM PST 24 828841122 ps
T416 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.438174884 Jan 14 01:03:17 PM PST 24 Jan 14 01:03:20 PM PST 24 8550846444 ps
T417 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2735359893 Jan 14 01:04:03 PM PST 24 Jan 14 01:04:05 PM PST 24 458690139 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4085415445 Jan 14 01:03:07 PM PST 24 Jan 14 01:03:09 PM PST 24 541121813 ps
T419 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1765982542 Jan 14 01:03:41 PM PST 24 Jan 14 01:03:44 PM PST 24 510662333 ps
T420 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2494808635 Jan 14 01:03:16 PM PST 24 Jan 14 01:03:18 PM PST 24 464294928 ps
T421 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3648368813 Jan 14 01:03:51 PM PST 24 Jan 14 01:03:53 PM PST 24 562041687 ps
T422 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1009369238 Jan 14 01:03:59 PM PST 24 Jan 14 01:04:01 PM PST 24 448471748 ps
T423 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3661608012 Jan 14 01:03:52 PM PST 24 Jan 14 01:03:55 PM PST 24 436737915 ps
T424 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.134542135 Jan 14 01:03:19 PM PST 24 Jan 14 01:03:33 PM PST 24 8274046564 ps
T425 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1717974075 Jan 14 01:03:26 PM PST 24 Jan 14 01:03:29 PM PST 24 1173571486 ps
T426 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1465706769 Jan 14 01:03:25 PM PST 24 Jan 14 01:03:28 PM PST 24 342367660 ps
T427 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4148238110 Jan 14 01:03:49 PM PST 24 Jan 14 01:03:55 PM PST 24 2038832677 ps
T428 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.678049283 Jan 14 01:03:43 PM PST 24 Jan 14 01:03:48 PM PST 24 957645080 ps
T429 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2488505844 Jan 14 01:03:25 PM PST 24 Jan 14 01:03:29 PM PST 24 492157606 ps

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.3441083031
Short name T8
Test name
Test status
Simulation time 7994883174 ps
CPU time 7.34 seconds
Started Jan 14 01:03:40 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 197672 kb
Host smart-8a0c8e17-42fb-4caf-8ff6-0b9582e511ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441083031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.3441083031
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.865918575
Short name T17
Test name
Test status
Simulation time 287801605378 ps
CPU time 324.31 seconds
Started Jan 14 01:09:05 PM PST 24
Finished Jan 14 01:14:30 PM PST 24
Peak memory 197596 kb
Host smart-0c1b5791-c2a0-4b41-8cbe-e7353fb4b868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865918575 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.865918575
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2716270678
Short name T68
Test name
Test status
Simulation time 419674893427 ps
CPU time 868.82 seconds
Started Jan 14 01:08:39 PM PST 24
Finished Jan 14 01:23:08 PM PST 24
Peak memory 201724 kb
Host smart-41eeb0e9-b994-4bfd-9d0f-1da349670edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716270678 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2716270678
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3954832945
Short name T78
Test name
Test status
Simulation time 121223796740 ps
CPU time 803.8 seconds
Started Jan 14 01:09:27 PM PST 24
Finished Jan 14 01:22:51 PM PST 24
Peak memory 199936 kb
Host smart-3ad8b647-ecc0-4ed2-a601-fabfb638034c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954832945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3954832945
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1653455855
Short name T73
Test name
Test status
Simulation time 517049785 ps
CPU time 1.3 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 183736 kb
Host smart-4750e535-bcbd-4d51-8822-f0fc871cbe56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653455855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1653455855
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2316747311
Short name T26
Test name
Test status
Simulation time 62751354560 ps
CPU time 24.9 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182812 kb
Host smart-97d967e8-57f0-446a-9432-029d7e627f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316747311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2316747311
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.14767783
Short name T46
Test name
Test status
Simulation time 134175512440 ps
CPU time 189.02 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:12:12 PM PST 24
Peak memory 197664 kb
Host smart-25fd85bd-7b65-4b70-b249-ada5582fb0a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14767783 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.14767783
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1621781280
Short name T227
Test name
Test status
Simulation time 211823659525 ps
CPU time 418.7 seconds
Started Jan 14 01:09:09 PM PST 24
Finished Jan 14 01:16:08 PM PST 24
Peak memory 197656 kb
Host smart-422093ae-efaf-46ab-98fb-66db25d7581d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621781280 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1621781280
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.719871774
Short name T85
Test name
Test status
Simulation time 79067137554 ps
CPU time 633.58 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:19:52 PM PST 24
Peak memory 198432 kb
Host smart-d20709f7-ba78-4c73-a3f1-3675cc00ce0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719871774 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.719871774
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3697872784
Short name T34
Test name
Test status
Simulation time 8030767384 ps
CPU time 3.63 seconds
Started Jan 14 01:08:47 PM PST 24
Finished Jan 14 01:08:51 PM PST 24
Peak memory 214988 kb
Host smart-983af986-1983-4613-b593-637fed8caa89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697872784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3697872784
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.693922341
Short name T92
Test name
Test status
Simulation time 224529067139 ps
CPU time 83.34 seconds
Started Jan 14 01:09:22 PM PST 24
Finished Jan 14 01:10:45 PM PST 24
Peak memory 182752 kb
Host smart-3b2c35e4-5ed5-4092-888c-c189c1df55d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693922341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.693922341
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.279740547
Short name T188
Test name
Test status
Simulation time 55418475888 ps
CPU time 41.59 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:52 PM PST 24
Peak memory 193040 kb
Host smart-3e814662-5938-4874-a4c1-f9461019e1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279740547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.279740547
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2441304454
Short name T250
Test name
Test status
Simulation time 46336692673 ps
CPU time 350.53 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:14:58 PM PST 24
Peak memory 197692 kb
Host smart-09faadf9-f5d9-4af4-ac25-2a96e2991b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441304454 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2441304454
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2251403708
Short name T414
Test name
Test status
Simulation time 8989401745 ps
CPU time 4.46 seconds
Started Jan 14 01:03:08 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 197452 kb
Host smart-5e583049-4eca-470f-8efb-c3526921ff2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251403708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2251403708
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1871362815
Short name T24
Test name
Test status
Simulation time 397439550 ps
CPU time 0.76 seconds
Started Jan 14 01:03:39 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 193044 kb
Host smart-c4ae9342-0234-41c9-af07-6e80f2a4600c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871362815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1871362815
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.2003615522
Short name T278
Test name
Test status
Simulation time 145231109326 ps
CPU time 100.9 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:10:44 PM PST 24
Peak memory 192956 kb
Host smart-58bb9b8c-cb75-4e32-a744-3d1860d470d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003615522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.2003615522
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.4100623617
Short name T300
Test name
Test status
Simulation time 45715126522 ps
CPU time 497.79 seconds
Started Jan 14 01:08:39 PM PST 24
Finished Jan 14 01:16:57 PM PST 24
Peak memory 197640 kb
Host smart-99574f3a-1e56-4118-9e0f-9ae446e88c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100623617 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.4100623617
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3110886572
Short name T27
Test name
Test status
Simulation time 132341915803 ps
CPU time 220.46 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:12:56 PM PST 24
Peak memory 182760 kb
Host smart-8f15f36a-af8a-4af1-ae84-729134acaf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110886572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3110886572
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.918651394
Short name T77
Test name
Test status
Simulation time 290407832000 ps
CPU time 424.33 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:16:17 PM PST 24
Peak memory 197676 kb
Host smart-67f42b5d-860b-4ff7-87d2-229868ec8100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918651394 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.918651394
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1177859000
Short name T123
Test name
Test status
Simulation time 41440358532 ps
CPU time 15.77 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:09:18 PM PST 24
Peak memory 182760 kb
Host smart-df23472b-bcec-4c67-82a8-421eb72170aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177859000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1177859000
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1222428606
Short name T23
Test name
Test status
Simulation time 640070177 ps
CPU time 2.13 seconds
Started Jan 14 01:03:12 PM PST 24
Finished Jan 14 01:03:15 PM PST 24
Peak memory 198612 kb
Host smart-a2d4be99-5c97-4039-8829-dd1aea9bc857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222428606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1222428606
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.498739891
Short name T403
Test name
Test status
Simulation time 539320606 ps
CPU time 0.89 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:08 PM PST 24
Peak memory 183832 kb
Host smart-5e1a03a8-9933-4fef-9c83-04c766503acc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498739891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.498739891
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.739799145
Short name T411
Test name
Test status
Simulation time 516732576 ps
CPU time 1.93 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:09 PM PST 24
Peak memory 192184 kb
Host smart-42cb23ea-e02d-4e10-8ffd-7ef47fa9606c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739799145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.739799145
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1700196511
Short name T60
Test name
Test status
Simulation time 1145533814 ps
CPU time 0.93 seconds
Started Jan 14 01:03:12 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 183712 kb
Host smart-ae7ae33d-1fca-47c4-b6bd-c068800e4318
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700196511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1700196511
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.4085415445
Short name T418
Test name
Test status
Simulation time 541121813 ps
CPU time 1.46 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:09 PM PST 24
Peak memory 195340 kb
Host smart-f9cda462-5dcd-46a2-96cd-339d96e159f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085415445 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.4085415445
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2365219444
Short name T52
Test name
Test status
Simulation time 515622886 ps
CPU time 0.98 seconds
Started Jan 14 01:03:13 PM PST 24
Finished Jan 14 01:03:15 PM PST 24
Peak memory 183732 kb
Host smart-9dbe6e05-877d-4d73-9abf-7efdbf1c729c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365219444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2365219444
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3319248054
Short name T373
Test name
Test status
Simulation time 399577826 ps
CPU time 1.09 seconds
Started Jan 14 01:03:12 PM PST 24
Finished Jan 14 01:03:14 PM PST 24
Peak memory 183452 kb
Host smart-e8b036cf-fbd3-454e-a66a-02c19f47c148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319248054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3319248054
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3325708
Short name T49
Test name
Test status
Simulation time 297060140 ps
CPU time 0.95 seconds
Started Jan 14 01:03:13 PM PST 24
Finished Jan 14 01:03:15 PM PST 24
Peak memory 183436 kb
Host smart-6bdc5299-5780-44c9-ab84-d17d13ca7e1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_time
r_mem_partial_access.3325708
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1634073743
Short name T303
Test name
Test status
Simulation time 479279050 ps
CPU time 1.31 seconds
Started Jan 14 01:03:08 PM PST 24
Finished Jan 14 01:03:10 PM PST 24
Peak memory 183480 kb
Host smart-c1e9301f-bed1-4f07-8311-4579e1fcb681
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634073743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1634073743
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.4067291430
Short name T331
Test name
Test status
Simulation time 2733766932 ps
CPU time 1.96 seconds
Started Jan 14 01:03:08 PM PST 24
Finished Jan 14 01:03:10 PM PST 24
Peak memory 192076 kb
Host smart-8aeacdba-9752-4132-b87c-c8b283c1aef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067291430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.4067291430
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2864415623
Short name T62
Test name
Test status
Simulation time 621266153 ps
CPU time 1.01 seconds
Started Jan 14 01:03:10 PM PST 24
Finished Jan 14 01:03:11 PM PST 24
Peak memory 183804 kb
Host smart-bb280990-969b-44dd-a3f9-626f3753b986
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864415623 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2864415623
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1301816448
Short name T12
Test name
Test status
Simulation time 2804139634 ps
CPU time 6.25 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:14 PM PST 24
Peak memory 192272 kb
Host smart-25cb7a0c-3340-4bc7-8f07-38f6d7c29389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301816448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1301816448
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3684528530
Short name T308
Test name
Test status
Simulation time 667726528 ps
CPU time 1.12 seconds
Started Jan 14 01:03:13 PM PST 24
Finished Jan 14 01:03:15 PM PST 24
Peak memory 183712 kb
Host smart-9c07012d-ab00-4d65-823a-be514b364fe1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684528530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3684528530
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1610037093
Short name T44
Test name
Test status
Simulation time 572007721 ps
CPU time 1.12 seconds
Started Jan 14 01:03:09 PM PST 24
Finished Jan 14 01:03:10 PM PST 24
Peak memory 195564 kb
Host smart-a712609a-87df-4e3a-887d-e2abacc7dab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610037093 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1610037093
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.236693966
Short name T58
Test name
Test status
Simulation time 503411006 ps
CPU time 0.95 seconds
Started Jan 14 01:03:13 PM PST 24
Finished Jan 14 01:03:14 PM PST 24
Peak memory 183764 kb
Host smart-d1072901-19fd-4fa9-aae0-6044dfab1d77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236693966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.236693966
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4155650958
Short name T325
Test name
Test status
Simulation time 372226389 ps
CPU time 0.66 seconds
Started Jan 14 01:03:11 PM PST 24
Finished Jan 14 01:03:12 PM PST 24
Peak memory 183840 kb
Host smart-751ee14a-23d7-4705-af22-1513901f25d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155650958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4155650958
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2710209435
Short name T394
Test name
Test status
Simulation time 403951823 ps
CPU time 0.67 seconds
Started Jan 14 01:03:12 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 183560 kb
Host smart-e381263f-1bd1-4432-b4e7-31ddb8d9a5aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710209435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2710209435
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.651371954
Short name T407
Test name
Test status
Simulation time 312161503 ps
CPU time 0.66 seconds
Started Jan 14 01:03:12 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 183504 kb
Host smart-29d4813e-5ec0-4204-85ad-e02e71e0ec5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651371954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.651371954
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.2964399333
Short name T402
Test name
Test status
Simulation time 979879233 ps
CPU time 1 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:09 PM PST 24
Peak memory 194292 kb
Host smart-229ad405-2508-43cd-9e03-9b484652076f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964399333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.2964399333
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1535006323
Short name T405
Test name
Test status
Simulation time 517118512 ps
CPU time 2.26 seconds
Started Jan 14 01:03:10 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 198600 kb
Host smart-0e129c5e-9216-4759-948e-f9637c5702e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535006323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1535006323
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3528387935
Short name T11
Test name
Test status
Simulation time 8638471748 ps
CPU time 4.71 seconds
Started Jan 14 01:03:07 PM PST 24
Finished Jan 14 01:03:13 PM PST 24
Peak memory 197684 kb
Host smart-d39087fc-3066-4238-848b-f64238bceff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528387935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3528387935
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.891000571
Short name T310
Test name
Test status
Simulation time 518987318 ps
CPU time 1.29 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 195308 kb
Host smart-d94dbef3-ed7c-4fca-843a-67371db1a382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891000571 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.891000571
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3237702704
Short name T390
Test name
Test status
Simulation time 508538807 ps
CPU time 0.64 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 193144 kb
Host smart-98095de3-7a92-4753-afca-2cde05f39ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237702704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3237702704
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.4225893404
Short name T372
Test name
Test status
Simulation time 369764879 ps
CPU time 1.12 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 183568 kb
Host smart-73f2e565-25fa-4ba2-a6ff-1795eda7586b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225893404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.4225893404
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.678049283
Short name T428
Test name
Test status
Simulation time 957645080 ps
CPU time 1.84 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 194224 kb
Host smart-b1521aaa-1e15-4036-9061-85971ba72d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678049283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon
_timer_same_csr_outstanding.678049283
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1148350286
Short name T352
Test name
Test status
Simulation time 375842253 ps
CPU time 2.01 seconds
Started Jan 14 01:03:39 PM PST 24
Finished Jan 14 01:03:45 PM PST 24
Peak memory 198632 kb
Host smart-3aae6295-9f9b-44d3-bfbd-b362e2092d6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148350286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1148350286
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.560087963
Short name T80
Test name
Test status
Simulation time 4188470104 ps
CPU time 6.78 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 197172 kb
Host smart-54845c7d-802e-4601-a27b-e1449cd8fa59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560087963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl
_intg_err.560087963
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1109957553
Short name T395
Test name
Test status
Simulation time 331507500 ps
CPU time 1.08 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 195596 kb
Host smart-293f4f3a-0dd3-460c-89c4-543b1c1b5a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109957553 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1109957553
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2107726263
Short name T385
Test name
Test status
Simulation time 554581084 ps
CPU time 0.63 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 183844 kb
Host smart-fde24072-5c5a-4990-adad-2a6240f4a95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107726263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2107726263
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3123907041
Short name T382
Test name
Test status
Simulation time 2698442987 ps
CPU time 2.09 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 195376 kb
Host smart-50248dce-d815-4e7a-a472-188d262397d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123907041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3123907041
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.4183808713
Short name T388
Test name
Test status
Simulation time 875208392 ps
CPU time 2.65 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 198652 kb
Host smart-005c0cd4-640d-49ad-9beb-2b4cc3ec1fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183808713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.4183808713
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3002492780
Short name T391
Test name
Test status
Simulation time 8781639931 ps
CPU time 4.79 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 197588 kb
Host smart-0a4edb68-ffd2-40d6-8f67-fac206f5bc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002492780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3002492780
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.628226025
Short name T333
Test name
Test status
Simulation time 504265604 ps
CPU time 1.04 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 196436 kb
Host smart-d2ad9efe-cd84-430d-8a88-d0381207467b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628226025 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.628226025
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3257703255
Short name T365
Test name
Test status
Simulation time 537680143 ps
CPU time 0.6 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183792 kb
Host smart-e64581b3-4a95-476e-9ff5-95e7175f41f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257703255 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3257703255
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.155248165
Short name T324
Test name
Test status
Simulation time 511087794 ps
CPU time 0.7 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 183516 kb
Host smart-7c5a7e49-5686-44f7-be31-9ba0096f977f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155248165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.155248165
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1342678369
Short name T358
Test name
Test status
Simulation time 1127074566 ps
CPU time 1.84 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 193288 kb
Host smart-cf67c78f-9d6b-4d36-99c4-7df164c88e5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342678369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1342678369
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2665652499
Short name T45
Test name
Test status
Simulation time 560964195 ps
CPU time 2.57 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 198628 kb
Host smart-37ccdb28-0620-4ad3-ba32-9355d6decd2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665652499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2665652499
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1857255875
Short name T413
Test name
Test status
Simulation time 8204807047 ps
CPU time 4.24 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 197472 kb
Host smart-151501c6-dbc5-48eb-85c6-1ff6341fa55a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857255875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1857255875
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.2903674560
Short name T366
Test name
Test status
Simulation time 523445113 ps
CPU time 1.42 seconds
Started Jan 14 01:03:48 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 195492 kb
Host smart-37e6961e-62a2-4597-a908-f09bbd10c3a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903674560 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.2903674560
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.25886249
Short name T384
Test name
Test status
Simulation time 355432538 ps
CPU time 0.7 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183788 kb
Host smart-55225c34-4364-4b74-a0bc-552c5ec48a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.25886249
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1454580629
Short name T340
Test name
Test status
Simulation time 524700004 ps
CPU time 0.76 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183584 kb
Host smart-243f3c17-5d4c-4cf5-8fb9-ea0ad791eb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454580629 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1454580629
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2530736998
Short name T380
Test name
Test status
Simulation time 1544843666 ps
CPU time 1.4 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 194160 kb
Host smart-70b348da-53da-416f-95e1-150402b939eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530736998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2530736998
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.234401543
Short name T13
Test name
Test status
Simulation time 707097744 ps
CPU time 2.22 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 198604 kb
Host smart-85c18d00-3aba-4d14-aedf-59fa95e3c53a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234401543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.234401543
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.394606950
Short name T305
Test name
Test status
Simulation time 4100398176 ps
CPU time 2.54 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 197200 kb
Host smart-d24ef7d7-9c4a-406d-95e1-4ec327ce8219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394606950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.394606950
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2291200608
Short name T397
Test name
Test status
Simulation time 385082616 ps
CPU time 0.93 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 195144 kb
Host smart-72b03d83-20aa-4aa4-bde2-c035bcd78dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291200608 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2291200608
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3152114125
Short name T57
Test name
Test status
Simulation time 354573244 ps
CPU time 1.17 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 183880 kb
Host smart-50ded14f-f087-477b-8d03-0c7d581927f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152114125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3152114125
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2914281343
Short name T360
Test name
Test status
Simulation time 412843105 ps
CPU time 0.86 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 183144 kb
Host smart-e9e8cb56-5013-4fcf-824c-df1547be5589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914281343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2914281343
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3827545441
Short name T415
Test name
Test status
Simulation time 828841122 ps
CPU time 1.02 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 194148 kb
Host smart-65866149-47ab-4374-b05c-a5af0fbfe287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827545441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3827545441
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2234879045
Short name T337
Test name
Test status
Simulation time 568420089 ps
CPU time 1.71 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 198124 kb
Host smart-a2f48abc-3b38-4b5c-a239-9925de306479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234879045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2234879045
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4039539154
Short name T399
Test name
Test status
Simulation time 4476758481 ps
CPU time 4.43 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 196128 kb
Host smart-c864a0c6-5300-43e6-acfd-e841b0b8cd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039539154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4039539154
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.4102630823
Short name T323
Test name
Test status
Simulation time 533566086 ps
CPU time 0.82 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 194356 kb
Host smart-50758e57-1da6-4e39-968c-f6dbd79b537d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102630823 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.4102630823
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1615497800
Short name T55
Test name
Test status
Simulation time 463576159 ps
CPU time 0.73 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 183808 kb
Host smart-d6a96453-54cc-486d-98db-55b04c70ad91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615497800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1615497800
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3757574869
Short name T332
Test name
Test status
Simulation time 368620969 ps
CPU time 0.86 seconds
Started Jan 14 01:03:50 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 183848 kb
Host smart-3c5bfe80-d0bc-4b55-8d54-d800469b4a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757574869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3757574869
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.4098063791
Short name T334
Test name
Test status
Simulation time 2320365564 ps
CPU time 1.52 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 194624 kb
Host smart-d9eda318-29e2-4d4a-b835-deb9bb15bac4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098063791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.4098063791
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.1227495703
Short name T362
Test name
Test status
Simulation time 1198858815 ps
CPU time 2.32 seconds
Started Jan 14 01:03:48 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 198704 kb
Host smart-15e09f54-6032-4a39-8c95-ce8871f728cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227495703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.1227495703
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3930673466
Short name T401
Test name
Test status
Simulation time 4294531113 ps
CPU time 2.37 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 197372 kb
Host smart-aa408562-dab5-4f01-b40a-beeddfe7069a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930673466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3930673466
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1828176794
Short name T326
Test name
Test status
Simulation time 407196339 ps
CPU time 0.77 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 195796 kb
Host smart-6fb2a0c8-e903-4706-9bdb-e3455414dbcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828176794 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1828176794
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1351047090
Short name T351
Test name
Test status
Simulation time 366528986 ps
CPU time 1.06 seconds
Started Jan 14 01:03:48 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 193040 kb
Host smart-729873f1-2afc-4221-b54a-9f0dcb8b79c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351047090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1351047090
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.1004518109
Short name T329
Test name
Test status
Simulation time 491896255 ps
CPU time 0.93 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 183552 kb
Host smart-f5e788a2-c956-47a9-8a63-5fa14203893d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004518109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.1004518109
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.851009484
Short name T6
Test name
Test status
Simulation time 1069124227 ps
CPU time 1.03 seconds
Started Jan 14 01:03:48 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 194112 kb
Host smart-6a4b18fd-492f-42ed-9bc2-fe39d7cb503d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851009484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.851009484
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.708934912
Short name T355
Test name
Test status
Simulation time 492989198 ps
CPU time 1.5 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 198652 kb
Host smart-35b9d99d-e2ba-44a9-a6a1-738520efc060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708934912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.708934912
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3308908530
Short name T396
Test name
Test status
Simulation time 4035107405 ps
CPU time 2.44 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 196304 kb
Host smart-1239b908-f52f-4e56-928f-b7988fe16648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308908530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3308908530
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3661608012
Short name T423
Test name
Test status
Simulation time 436737915 ps
CPU time 1.04 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 196288 kb
Host smart-6d723857-8a08-4acb-9cee-8c07e839551e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661608012 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3661608012
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1031729983
Short name T3
Test name
Test status
Simulation time 527047164 ps
CPU time 1.42 seconds
Started Jan 14 01:03:48 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 183752 kb
Host smart-5088cf77-dc86-4d05-9c5c-9a49d743833b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031729983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1031729983
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2561494756
Short name T336
Test name
Test status
Simulation time 373596833 ps
CPU time 0.66 seconds
Started Jan 14 01:03:47 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 183540 kb
Host smart-f13271b2-b223-4fab-90a8-b6a808b0498b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561494756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2561494756
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.4148238110
Short name T427
Test name
Test status
Simulation time 2038832677 ps
CPU time 4.42 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 194044 kb
Host smart-5354f7d9-ee8f-470a-bedc-cfd3ec132582
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148238110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.4148238110
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3918900700
Short name T319
Test name
Test status
Simulation time 1058081314 ps
CPU time 2.42 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 198628 kb
Host smart-5a0b6871-46ad-46b8-a8d4-17a54b851fb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918900700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3918900700
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4261194237
Short name T79
Test name
Test status
Simulation time 8310159389 ps
CPU time 4.15 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 197596 kb
Host smart-24543407-4cad-49c4-ba2c-60cb21cb8fae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261194237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4261194237
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1908027683
Short name T404
Test name
Test status
Simulation time 581784256 ps
CPU time 0.8 seconds
Started Jan 14 01:03:53 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 194780 kb
Host smart-a6556557-cd9b-4cd7-b07f-e57ff9f4ecd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908027683 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1908027683
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3015431673
Short name T63
Test name
Test status
Simulation time 518131695 ps
CPU time 0.86 seconds
Started Jan 14 01:03:50 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 183848 kb
Host smart-e2907fa6-aa89-4d76-af12-ef3bb2a9b67b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015431673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3015431673
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2160693761
Short name T315
Test name
Test status
Simulation time 438526914 ps
CPU time 0.69 seconds
Started Jan 14 01:03:54 PM PST 24
Finished Jan 14 01:03:56 PM PST 24
Peak memory 183596 kb
Host smart-06a01d9b-a2a8-461b-99df-1517affbbfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160693761 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2160693761
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1274894372
Short name T64
Test name
Test status
Simulation time 995894136 ps
CPU time 0.68 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 193472 kb
Host smart-49512538-2daa-450b-a5c2-8ae0e9b64f8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274894372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1274894372
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.4254660642
Short name T318
Test name
Test status
Simulation time 359303201 ps
CPU time 1.37 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 198456 kb
Host smart-f7447535-ac0d-44e0-9843-1e3196fdd4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254660642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.4254660642
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.778543498
Short name T369
Test name
Test status
Simulation time 8720239960 ps
CPU time 2.66 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 197520 kb
Host smart-485b4c49-ae5e-4b2b-9461-9d0d7348352d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778543498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.778543498
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3648368813
Short name T421
Test name
Test status
Simulation time 562041687 ps
CPU time 1.13 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 198420 kb
Host smart-0c40911f-ac5b-4da9-ae9a-cab6a887b2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648368813 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3648368813
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.4293678867
Short name T61
Test name
Test status
Simulation time 342997318 ps
CPU time 0.66 seconds
Started Jan 14 01:03:54 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 183816 kb
Host smart-b8838b09-c513-4bc4-8869-cd9441df90a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293678867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.4293678867
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1831263214
Short name T302
Test name
Test status
Simulation time 384724813 ps
CPU time 1.15 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 183488 kb
Host smart-e2c3e788-c147-44e9-b9cc-2c99f634853e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831263214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1831263214
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1062175434
Short name T383
Test name
Test status
Simulation time 1346436633 ps
CPU time 1.24 seconds
Started Jan 14 01:03:51 PM PST 24
Finished Jan 14 01:03:53 PM PST 24
Peak memory 192796 kb
Host smart-6dba5162-6ca1-4264-9fa8-3a2b28d01212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062175434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1062175434
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3455109754
Short name T400
Test name
Test status
Simulation time 332507008 ps
CPU time 1.58 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:55 PM PST 24
Peak memory 198528 kb
Host smart-3f0e2925-e135-46f6-9ae2-6326a57b6223
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455109754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3455109754
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2044184334
Short name T320
Test name
Test status
Simulation time 4415317567 ps
CPU time 6.8 seconds
Started Jan 14 01:03:54 PM PST 24
Finished Jan 14 01:04:02 PM PST 24
Peak memory 195748 kb
Host smart-5a6d640c-8f37-4845-bcec-df77b93dd0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044184334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2044184334
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1441282640
Short name T389
Test name
Test status
Simulation time 475467037 ps
CPU time 1.25 seconds
Started Jan 14 01:03:20 PM PST 24
Finished Jan 14 01:03:22 PM PST 24
Peak memory 183756 kb
Host smart-d051832b-e676-43b3-9866-445659f61ca1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441282640 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1441282640
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4097074373
Short name T375
Test name
Test status
Simulation time 6177084152 ps
CPU time 3.43 seconds
Started Jan 14 01:03:16 PM PST 24
Finished Jan 14 01:03:19 PM PST 24
Peak memory 192204 kb
Host smart-b551a0a4-5054-4693-8e47-279c08b324f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097074373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4097074373
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3402742555
Short name T59
Test name
Test status
Simulation time 1033854147 ps
CPU time 0.81 seconds
Started Jan 14 01:03:17 PM PST 24
Finished Jan 14 01:03:19 PM PST 24
Peak memory 183820 kb
Host smart-cf44f069-4f98-4d4f-b021-2e3c549cf1a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402742555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3402742555
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.2019401454
Short name T47
Test name
Test status
Simulation time 485760029 ps
CPU time 1 seconds
Started Jan 14 01:03:20 PM PST 24
Finished Jan 14 01:03:21 PM PST 24
Peak memory 194604 kb
Host smart-8efa0fd6-097c-4147-9777-1f7378cdff21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019401454 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.2019401454
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1858911246
Short name T66
Test name
Test status
Simulation time 382018690 ps
CPU time 0.8 seconds
Started Jan 14 01:03:15 PM PST 24
Finished Jan 14 01:03:16 PM PST 24
Peak memory 192984 kb
Host smart-ec54abb7-64e0-45ce-9827-667419d793ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858911246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1858911246
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3264497162
Short name T322
Test name
Test status
Simulation time 350783716 ps
CPU time 0.65 seconds
Started Jan 14 01:03:20 PM PST 24
Finished Jan 14 01:03:21 PM PST 24
Peak memory 183532 kb
Host smart-13aa3045-feba-4577-9b3f-d5c83e7ad843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264497162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3264497162
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2494808635
Short name T420
Test name
Test status
Simulation time 464294928 ps
CPU time 0.91 seconds
Started Jan 14 01:03:16 PM PST 24
Finished Jan 14 01:03:18 PM PST 24
Peak memory 183732 kb
Host smart-291c8fee-42df-4ffe-a512-906c42d090cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494808635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2494808635
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2822881246
Short name T42
Test name
Test status
Simulation time 408031561 ps
CPU time 0.7 seconds
Started Jan 14 01:03:14 PM PST 24
Finished Jan 14 01:03:15 PM PST 24
Peak memory 183452 kb
Host smart-2918b092-42cf-43ee-8310-97d241e3b3a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822881246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2822881246
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3897798443
Short name T371
Test name
Test status
Simulation time 1098433659 ps
CPU time 2.18 seconds
Started Jan 14 01:03:23 PM PST 24
Finished Jan 14 01:03:29 PM PST 24
Peak memory 192772 kb
Host smart-b324070f-7bed-4741-af69-08998e25458b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897798443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3897798443
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.403594648
Short name T306
Test name
Test status
Simulation time 947842394 ps
CPU time 2.9 seconds
Started Jan 14 01:03:16 PM PST 24
Finished Jan 14 01:03:19 PM PST 24
Peak memory 198596 kb
Host smart-adfb0495-efbc-40ed-981a-318bbcebf3fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403594648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.403594648
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.438174884
Short name T416
Test name
Test status
Simulation time 8550846444 ps
CPU time 2.1 seconds
Started Jan 14 01:03:17 PM PST 24
Finished Jan 14 01:03:20 PM PST 24
Peak memory 197736 kb
Host smart-ae287fee-30bd-488c-ba32-9253041f4478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438174884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.438174884
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2394348681
Short name T316
Test name
Test status
Simulation time 312139371 ps
CPU time 1.01 seconds
Started Jan 14 01:03:49 PM PST 24
Finished Jan 14 01:03:52 PM PST 24
Peak memory 183564 kb
Host smart-f9165793-7ac8-4e41-aa53-1fbef50ef1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394348681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2394348681
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.442688064
Short name T347
Test name
Test status
Simulation time 437826225 ps
CPU time 0.56 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 183556 kb
Host smart-9e3b2f37-3b5c-4150-9671-dadf1895989a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442688064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.442688064
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2016607351
Short name T344
Test name
Test status
Simulation time 330127583 ps
CPU time 1.04 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 183572 kb
Host smart-e92d7be3-8a23-4e22-8016-9d0bf372c6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016607351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2016607351
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2813869178
Short name T327
Test name
Test status
Simulation time 454083695 ps
CPU time 0.72 seconds
Started Jan 14 01:03:52 PM PST 24
Finished Jan 14 01:03:54 PM PST 24
Peak memory 183488 kb
Host smart-e5f116d5-2bee-4a74-a863-b4e3c9199710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813869178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2813869178
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2440335609
Short name T70
Test name
Test status
Simulation time 295534817 ps
CPU time 0.76 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:58 PM PST 24
Peak memory 183504 kb
Host smart-2af5340d-6a8c-4570-a7bf-10ae60d69a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440335609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2440335609
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2460491781
Short name T359
Test name
Test status
Simulation time 472015867 ps
CPU time 0.84 seconds
Started Jan 14 01:04:00 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 183612 kb
Host smart-0560ca6c-d92f-421e-9214-b82038fa6182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460491781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2460491781
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.2946315359
Short name T72
Test name
Test status
Simulation time 453008753 ps
CPU time 0.69 seconds
Started Jan 14 01:03:56 PM PST 24
Finished Jan 14 01:03:58 PM PST 24
Peak memory 183512 kb
Host smart-b6c936af-a78a-4eab-80fc-7ecde5cba66d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946315359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.2946315359
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.754011014
Short name T345
Test name
Test status
Simulation time 418473507 ps
CPU time 0.69 seconds
Started Jan 14 01:03:55 PM PST 24
Finished Jan 14 01:03:56 PM PST 24
Peak memory 183844 kb
Host smart-063016e2-10e3-4cd0-b51e-03868019af8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754011014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.754011014
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.3193599894
Short name T349
Test name
Test status
Simulation time 527747389 ps
CPU time 0.73 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:58 PM PST 24
Peak memory 183516 kb
Host smart-de1347fd-8df3-46f6-9de0-41cbf9242360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193599894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.3193599894
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4281061605
Short name T353
Test name
Test status
Simulation time 375309562 ps
CPU time 0.81 seconds
Started Jan 14 01:04:03 PM PST 24
Finished Jan 14 01:04:05 PM PST 24
Peak memory 183488 kb
Host smart-289219df-dd7c-456f-8336-920307e46b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281061605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4281061605
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1157106933
Short name T10
Test name
Test status
Simulation time 554492801 ps
CPU time 1.55 seconds
Started Jan 14 01:03:18 PM PST 24
Finished Jan 14 01:03:20 PM PST 24
Peak memory 183864 kb
Host smart-d286ec9c-7747-4796-8399-bcb60fe592d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157106933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1157106933
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3038948863
Short name T393
Test name
Test status
Simulation time 3690341064 ps
CPU time 3.09 seconds
Started Jan 14 01:03:17 PM PST 24
Finished Jan 14 01:03:20 PM PST 24
Peak memory 192176 kb
Host smart-f2e6cd34-76e6-48d7-a121-316ed33da20a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038948863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3038948863
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.437891212
Short name T321
Test name
Test status
Simulation time 852286044 ps
CPU time 1.73 seconds
Started Jan 14 01:03:18 PM PST 24
Finished Jan 14 01:03:20 PM PST 24
Peak memory 183704 kb
Host smart-5c96b9bb-d807-4a31-9cf6-57405a795afd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437891212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.437891212
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2048738467
Short name T311
Test name
Test status
Simulation time 547829911 ps
CPU time 0.79 seconds
Started Jan 14 01:03:22 PM PST 24
Finished Jan 14 01:03:23 PM PST 24
Peak memory 196092 kb
Host smart-fa3d71ec-386a-42fb-935b-be93ff696c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048738467 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2048738467
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2463615839
Short name T350
Test name
Test status
Simulation time 390327609 ps
CPU time 0.74 seconds
Started Jan 14 01:03:20 PM PST 24
Finished Jan 14 01:03:21 PM PST 24
Peak memory 183880 kb
Host smart-1f6e5820-6604-4026-952e-eb968d34b68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463615839 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2463615839
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1610035416
Short name T343
Test name
Test status
Simulation time 491128700 ps
CPU time 1.24 seconds
Started Jan 14 01:03:17 PM PST 24
Finished Jan 14 01:03:19 PM PST 24
Peak memory 183836 kb
Host smart-7ec13aa5-2b0f-4795-bde1-c6be7c64e1d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610035416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1610035416
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2312502168
Short name T387
Test name
Test status
Simulation time 307491126 ps
CPU time 1.06 seconds
Started Jan 14 01:03:18 PM PST 24
Finished Jan 14 01:03:19 PM PST 24
Peak memory 183872 kb
Host smart-f8c66447-90f7-4419-9aa4-631fcfa5abba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312502168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2312502168
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1465706769
Short name T426
Test name
Test status
Simulation time 342367660 ps
CPU time 1.02 seconds
Started Jan 14 01:03:25 PM PST 24
Finished Jan 14 01:03:28 PM PST 24
Peak memory 183608 kb
Host smart-d7a5442a-e725-4184-822a-5eb16b4ab9d5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465706769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1465706769
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1902700211
Short name T65
Test name
Test status
Simulation time 1289813357 ps
CPU time 1.01 seconds
Started Jan 14 01:03:19 PM PST 24
Finished Jan 14 01:03:20 PM PST 24
Peak memory 194216 kb
Host smart-77c43d5e-dd5f-43f2-9f61-c5038ab499fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902700211 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1902700211
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4228829869
Short name T335
Test name
Test status
Simulation time 710903696 ps
CPU time 2.07 seconds
Started Jan 14 01:03:20 PM PST 24
Finished Jan 14 01:03:23 PM PST 24
Peak memory 198672 kb
Host smart-ba6353c1-2717-4af0-a2f5-2330163525e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228829869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4228829869
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.134542135
Short name T424
Test name
Test status
Simulation time 8274046564 ps
CPU time 13.16 seconds
Started Jan 14 01:03:19 PM PST 24
Finished Jan 14 01:03:33 PM PST 24
Peak memory 197492 kb
Host smart-de4f34e3-d5c0-4dfb-b063-c62b642ce11a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134542135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.134542135
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2735359893
Short name T417
Test name
Test status
Simulation time 458690139 ps
CPU time 0.93 seconds
Started Jan 14 01:04:03 PM PST 24
Finished Jan 14 01:04:05 PM PST 24
Peak memory 183488 kb
Host smart-1cbe2f30-9b08-46b6-ae3e-4558ec6ff5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735359893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2735359893
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3973517311
Short name T71
Test name
Test status
Simulation time 432836768 ps
CPU time 0.69 seconds
Started Jan 14 01:04:03 PM PST 24
Finished Jan 14 01:04:05 PM PST 24
Peak memory 183488 kb
Host smart-19692706-1af2-4edc-a233-75c0946a80e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973517311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3973517311
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.141745940
Short name T367
Test name
Test status
Simulation time 523417346 ps
CPU time 0.6 seconds
Started Jan 14 01:04:01 PM PST 24
Finished Jan 14 01:04:02 PM PST 24
Peak memory 183556 kb
Host smart-74021184-dc54-4ad5-96bc-10670b76bffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141745940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.141745940
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3708825376
Short name T381
Test name
Test status
Simulation time 414865626 ps
CPU time 0.57 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:58 PM PST 24
Peak memory 183612 kb
Host smart-31f51e12-f0d3-459e-a7ad-a0a351f801aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708825376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3708825376
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2894558737
Short name T409
Test name
Test status
Simulation time 391192276 ps
CPU time 0.86 seconds
Started Jan 14 01:03:59 PM PST 24
Finished Jan 14 01:04:00 PM PST 24
Peak memory 183696 kb
Host smart-4f26b511-4ade-4438-a149-7b89f3be339b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894558737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2894558737
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.929137560
Short name T313
Test name
Test status
Simulation time 416936686 ps
CPU time 0.69 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183544 kb
Host smart-7d1f3276-9608-43a5-abe8-7ef3d5763cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929137560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.929137560
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2366216768
Short name T338
Test name
Test status
Simulation time 339845803 ps
CPU time 1 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183540 kb
Host smart-8abcd2d9-4a71-4fee-8943-b01f8c1ecca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366216768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2366216768
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.821232398
Short name T363
Test name
Test status
Simulation time 481614052 ps
CPU time 1.18 seconds
Started Jan 14 01:03:59 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 183688 kb
Host smart-4f79ef48-6f1e-4582-a288-ff40c5a36c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821232398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.821232398
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.652733348
Short name T356
Test name
Test status
Simulation time 498019644 ps
CPU time 1.26 seconds
Started Jan 14 01:03:58 PM PST 24
Finished Jan 14 01:04:00 PM PST 24
Peak memory 183584 kb
Host smart-fba27d2a-a548-4b4c-a7dd-4727314e82f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652733348 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.652733348
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.4224062505
Short name T374
Test name
Test status
Simulation time 329985216 ps
CPU time 0.76 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183792 kb
Host smart-1b9a93d9-88c9-49ac-9c1a-cb4053ba1adf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224062505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.4224062505
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.3568495003
Short name T398
Test name
Test status
Simulation time 490766279 ps
CPU time 0.96 seconds
Started Jan 14 01:03:24 PM PST 24
Finished Jan 14 01:03:28 PM PST 24
Peak memory 193796 kb
Host smart-c0f4cae1-89c5-494f-b1f1-64fe59b06bb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568495003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.3568495003
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4161733353
Short name T56
Test name
Test status
Simulation time 4200051096 ps
CPU time 11.44 seconds
Started Jan 14 01:03:26 PM PST 24
Finished Jan 14 01:03:39 PM PST 24
Peak memory 184036 kb
Host smart-2e67fdfa-254c-4507-9712-f7ff52376b18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161733353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4161733353
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1717974075
Short name T425
Test name
Test status
Simulation time 1173571486 ps
CPU time 1.47 seconds
Started Jan 14 01:03:26 PM PST 24
Finished Jan 14 01:03:29 PM PST 24
Peak memory 183800 kb
Host smart-e0cdc8c3-a65c-487a-91d3-6940d1302a01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717974075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1717974075
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3827449374
Short name T354
Test name
Test status
Simulation time 480231074 ps
CPU time 0.88 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 196352 kb
Host smart-a8ec6a1d-964d-4d72-8d1d-2193b2a1f1ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827449374 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3827449374
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.286777890
Short name T357
Test name
Test status
Simulation time 514952386 ps
CPU time 1.42 seconds
Started Jan 14 01:03:25 PM PST 24
Finished Jan 14 01:03:29 PM PST 24
Peak memory 183772 kb
Host smart-63e1f8ce-ce94-4d2b-af1f-23075c26694b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286777890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.286777890
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1129248549
Short name T392
Test name
Test status
Simulation time 512138814 ps
CPU time 0.72 seconds
Started Jan 14 01:03:22 PM PST 24
Finished Jan 14 01:03:24 PM PST 24
Peak memory 183788 kb
Host smart-8d53af84-e930-47d9-8e61-6ca01671122a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129248549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1129248549
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3192922606
Short name T348
Test name
Test status
Simulation time 475985597 ps
CPU time 0.67 seconds
Started Jan 14 01:03:24 PM PST 24
Finished Jan 14 01:03:28 PM PST 24
Peak memory 183576 kb
Host smart-a93c6be0-f6dc-40fd-a34e-cb1ac7a5c514
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192922606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3192922606
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.2488505844
Short name T429
Test name
Test status
Simulation time 492157606 ps
CPU time 1.29 seconds
Started Jan 14 01:03:25 PM PST 24
Finished Jan 14 01:03:29 PM PST 24
Peak memory 183788 kb
Host smart-1cd97ed3-5986-4b97-8622-26dd4bfcf51c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488505844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.2488505844
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.904688837
Short name T361
Test name
Test status
Simulation time 914829628 ps
CPU time 1.83 seconds
Started Jan 14 01:03:26 PM PST 24
Finished Jan 14 01:03:29 PM PST 24
Peak memory 193380 kb
Host smart-2472707c-5a4b-4e1b-b0be-6513cc321eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904688837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_
timer_same_csr_outstanding.904688837
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2412478233
Short name T14
Test name
Test status
Simulation time 513096805 ps
CPU time 1.75 seconds
Started Jan 14 01:03:21 PM PST 24
Finished Jan 14 01:03:24 PM PST 24
Peak memory 198648 kb
Host smart-5802c994-f648-44c5-af0c-95dc9db388b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412478233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2412478233
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.2183192688
Short name T328
Test name
Test status
Simulation time 4159397285 ps
CPU time 7.93 seconds
Started Jan 14 01:03:24 PM PST 24
Finished Jan 14 01:03:35 PM PST 24
Peak memory 197384 kb
Host smart-605d471e-9e41-4403-8481-af7cde285bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183192688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.2183192688
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1320043297
Short name T377
Test name
Test status
Simulation time 402837224 ps
CPU time 0.61 seconds
Started Jan 14 01:03:58 PM PST 24
Finished Jan 14 01:04:00 PM PST 24
Peak memory 183548 kb
Host smart-7990b7a4-656a-4561-9d4d-032cbf6f363a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320043297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1320043297
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1724187851
Short name T378
Test name
Test status
Simulation time 365138586 ps
CPU time 1.03 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183756 kb
Host smart-41926184-a412-4b08-b7f5-1f0d787839f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724187851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1724187851
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1631826627
Short name T314
Test name
Test status
Simulation time 395823517 ps
CPU time 0.74 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183584 kb
Host smart-12def5ff-ea52-4147-af4c-1cc1d0640fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631826627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1631826627
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3244777963
Short name T15
Test name
Test status
Simulation time 290310860 ps
CPU time 0.62 seconds
Started Jan 14 01:04:00 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 183456 kb
Host smart-9d035dca-029a-4419-a323-d5a8c4da4989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244777963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3244777963
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1009369238
Short name T422
Test name
Test status
Simulation time 448471748 ps
CPU time 0.9 seconds
Started Jan 14 01:03:59 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 183696 kb
Host smart-1937f083-38b8-47e8-9355-116f130c54a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009369238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1009369238
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.933513422
Short name T410
Test name
Test status
Simulation time 511071168 ps
CPU time 0.88 seconds
Started Jan 14 01:03:56 PM PST 24
Finished Jan 14 01:03:57 PM PST 24
Peak memory 183504 kb
Host smart-fec1ec6b-974f-4c90-a99d-5f197f95e362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933513422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.933513422
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3455298735
Short name T304
Test name
Test status
Simulation time 382645501 ps
CPU time 0.67 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 183608 kb
Host smart-a8bfa5dd-6497-456d-a64c-68a61cb90841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455298735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3455298735
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.9286607
Short name T74
Test name
Test status
Simulation time 286729170 ps
CPU time 0.66 seconds
Started Jan 14 01:03:58 PM PST 24
Finished Jan 14 01:04:00 PM PST 24
Peak memory 183552 kb
Host smart-d63049b2-459f-4de7-9712-c7c0f61e61ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9286607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.9286607
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1317516440
Short name T386
Test name
Test status
Simulation time 400740240 ps
CPU time 1.1 seconds
Started Jan 14 01:03:59 PM PST 24
Finished Jan 14 01:04:01 PM PST 24
Peak memory 183652 kb
Host smart-bb9f0910-a3f5-453c-8fe4-ecae0cf2508a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317516440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1317516440
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1814804360
Short name T312
Test name
Test status
Simulation time 457737165 ps
CPU time 1.13 seconds
Started Jan 14 01:03:57 PM PST 24
Finished Jan 14 01:03:58 PM PST 24
Peak memory 183524 kb
Host smart-ba4a5b2d-b5dd-45b2-a010-f207b6481e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814804360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1814804360
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.733787398
Short name T339
Test name
Test status
Simulation time 457742248 ps
CPU time 0.92 seconds
Started Jan 14 01:03:42 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 195256 kb
Host smart-86f89c3d-087b-4793-9057-1e6739d4370c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733787398 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.733787398
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.608291536
Short name T370
Test name
Test status
Simulation time 398209614 ps
CPU time 0.83 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183524 kb
Host smart-b1ce7f69-9ee9-4033-84a9-36495e35eaf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608291536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.608291536
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1796194027
Short name T376
Test name
Test status
Simulation time 1098356651 ps
CPU time 1.19 seconds
Started Jan 14 01:03:36 PM PST 24
Finished Jan 14 01:03:38 PM PST 24
Peak memory 194248 kb
Host smart-5de495db-afd5-4d44-bef2-7aac4f6f9db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796194027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1796194027
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.4218591597
Short name T330
Test name
Test status
Simulation time 735958975 ps
CPU time 1.91 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 198544 kb
Host smart-3b88209f-3b69-4324-be94-c5ee67440947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218591597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.4218591597
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.570398437
Short name T1
Test name
Test status
Simulation time 8316145964 ps
CPU time 13.86 seconds
Started Jan 14 01:03:34 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 197840 kb
Host smart-b445ad2c-89a8-41e7-b242-80c288c519b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570398437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.570398437
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2374584662
Short name T307
Test name
Test status
Simulation time 467532816 ps
CPU time 0.93 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:47 PM PST 24
Peak memory 196348 kb
Host smart-cf207ad7-5a4a-4e45-8e0c-c4861ada26d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374584662 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2374584662
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1395586536
Short name T53
Test name
Test status
Simulation time 442415737 ps
CPU time 0.73 seconds
Started Jan 14 01:03:38 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 183876 kb
Host smart-91b23ef2-d862-4b8d-81df-5ecd8638deee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395586536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1395586536
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1765982542
Short name T419
Test name
Test status
Simulation time 510662333 ps
CPU time 1.26 seconds
Started Jan 14 01:03:41 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 183776 kb
Host smart-7eb55008-9713-48a1-8572-273f15c11b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765982542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1765982542
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.150635983
Short name T2
Test name
Test status
Simulation time 2063232062 ps
CPU time 7.63 seconds
Started Jan 14 01:03:40 PM PST 24
Finished Jan 14 01:03:51 PM PST 24
Peak memory 195236 kb
Host smart-9b840e43-ce7e-4815-b5d0-284278d2cd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150635983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.150635983
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3073680278
Short name T309
Test name
Test status
Simulation time 620869159 ps
CPU time 1.74 seconds
Started Jan 14 01:03:39 PM PST 24
Finished Jan 14 01:03:45 PM PST 24
Peak memory 198648 kb
Host smart-b70a282f-f92b-48e9-8056-bef6bdff4d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073680278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3073680278
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1768312995
Short name T9
Test name
Test status
Simulation time 8186665997 ps
CPU time 14.23 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:59 PM PST 24
Peak memory 197584 kb
Host smart-1052377d-ab99-4f03-a859-abf7c6c45928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768312995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1768312995
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.3136585676
Short name T7
Test name
Test status
Simulation time 470117281 ps
CPU time 1.32 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 194620 kb
Host smart-7dbbf657-1863-4187-8c18-fb1fbc7e901f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136585676 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.3136585676
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1484485516
Short name T412
Test name
Test status
Simulation time 402272790 ps
CPU time 0.58 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183860 kb
Host smart-89cc02a9-9e9b-40ca-9652-e4a7a72e2a35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484485516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1484485516
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.531880632
Short name T408
Test name
Test status
Simulation time 401596626 ps
CPU time 0.87 seconds
Started Jan 14 01:03:39 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 183560 kb
Host smart-8f35c76a-b10d-4f73-a40b-5a7d4022fb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531880632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.531880632
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.4245973129
Short name T346
Test name
Test status
Simulation time 1873078073 ps
CPU time 3.17 seconds
Started Jan 14 01:03:40 PM PST 24
Finished Jan 14 01:03:46 PM PST 24
Peak memory 195224 kb
Host smart-a9904929-f345-42a1-8988-4fb2f0a89ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245973129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.4245973129
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2555215613
Short name T48
Test name
Test status
Simulation time 324474004 ps
CPU time 1.69 seconds
Started Jan 14 01:03:37 PM PST 24
Finished Jan 14 01:03:39 PM PST 24
Peak memory 198532 kb
Host smart-1d557e5e-c081-42ae-b18b-99511f809cee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555215613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2555215613
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1111564574
Short name T379
Test name
Test status
Simulation time 519847413 ps
CPU time 1.32 seconds
Started Jan 14 01:03:40 PM PST 24
Finished Jan 14 01:03:44 PM PST 24
Peak memory 194604 kb
Host smart-c6b32145-ba9b-4d0c-a991-095e0a8c3fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111564574 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1111564574
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2792680087
Short name T364
Test name
Test status
Simulation time 436059488 ps
CPU time 1.33 seconds
Started Jan 14 01:03:41 PM PST 24
Finished Jan 14 01:03:45 PM PST 24
Peak memory 183792 kb
Host smart-507cbfa8-a62e-465b-8dd4-db89262a09bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792680087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2792680087
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.4113653012
Short name T43
Test name
Test status
Simulation time 514087500 ps
CPU time 1.31 seconds
Started Jan 14 01:03:40 PM PST 24
Finished Jan 14 01:03:45 PM PST 24
Peak memory 183548 kb
Host smart-10f1ff67-b7b4-451c-92d8-d38d3d606dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113653012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.4113653012
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1670546842
Short name T67
Test name
Test status
Simulation time 1265505324 ps
CPU time 1.27 seconds
Started Jan 14 01:03:37 PM PST 24
Finished Jan 14 01:03:39 PM PST 24
Peak memory 194324 kb
Host smart-5955615e-e4e5-4976-b9d0-39ac19a0defa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670546842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1670546842
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.763875742
Short name T341
Test name
Test status
Simulation time 378925011 ps
CPU time 1.99 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 198576 kb
Host smart-97e11445-18b0-4a58-b726-23c309cf5c42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763875742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.763875742
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3463268716
Short name T317
Test name
Test status
Simulation time 4502626399 ps
CPU time 2.13 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:50 PM PST 24
Peak memory 195992 kb
Host smart-9f7ccd2d-5c03-482b-90aa-2fbeeca06e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463268716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3463268716
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.757296086
Short name T368
Test name
Test status
Simulation time 383120096 ps
CPU time 0.78 seconds
Started Jan 14 01:03:46 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 196100 kb
Host smart-0117084d-3258-45a6-803b-1157708aa3b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757296086 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.757296086
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.428255703
Short name T54
Test name
Test status
Simulation time 313333618 ps
CPU time 0.88 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 183768 kb
Host smart-2a9ff79f-df49-420c-9d4f-973e86227957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428255703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.428255703
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1411705048
Short name T342
Test name
Test status
Simulation time 546535068 ps
CPU time 0.62 seconds
Started Jan 14 01:03:44 PM PST 24
Finished Jan 14 01:03:47 PM PST 24
Peak memory 183572 kb
Host smart-e2dac403-b768-4e10-8c13-27870dab7c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411705048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1411705048
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.932626903
Short name T5
Test name
Test status
Simulation time 1158706713 ps
CPU time 1.66 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 193296 kb
Host smart-3598219a-b45a-46dd-8c1a-7483822cb0c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932626903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.932626903
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3861941258
Short name T406
Test name
Test status
Simulation time 523643096 ps
CPU time 1.78 seconds
Started Jan 14 01:03:43 PM PST 24
Finished Jan 14 01:03:48 PM PST 24
Peak memory 198440 kb
Host smart-a3b5a3fe-a47d-49c4-b6a9-c86bbc0f6004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861941258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3861941258
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.368182801
Short name T4
Test name
Test status
Simulation time 4446532680 ps
CPU time 1.5 seconds
Started Jan 14 01:03:45 PM PST 24
Finished Jan 14 01:03:49 PM PST 24
Peak memory 196224 kb
Host smart-2047d949-7466-4017-8406-fbb8e52a1ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368182801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.368182801
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4156000729
Short name T221
Test name
Test status
Simulation time 529853369 ps
CPU time 1.25 seconds
Started Jan 14 01:08:41 PM PST 24
Finished Jan 14 01:08:42 PM PST 24
Peak memory 182664 kb
Host smart-f9ae342b-77d0-4922-bfcf-f76fbe420461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156000729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4156000729
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1202899171
Short name T211
Test name
Test status
Simulation time 19652966269 ps
CPU time 6.56 seconds
Started Jan 14 01:08:42 PM PST 24
Finished Jan 14 01:08:49 PM PST 24
Peak memory 182716 kb
Host smart-7e648cb3-5012-47d1-817b-a93694f347bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202899171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1202899171
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3776193986
Short name T231
Test name
Test status
Simulation time 500690903 ps
CPU time 0.78 seconds
Started Jan 14 01:08:49 PM PST 24
Finished Jan 14 01:08:50 PM PST 24
Peak memory 182616 kb
Host smart-7ef4f7b6-11e4-4e07-a58f-4b3cf5e4acb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776193986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3776193986
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2707327712
Short name T207
Test name
Test status
Simulation time 75031388200 ps
CPU time 66.87 seconds
Started Jan 14 01:08:41 PM PST 24
Finished Jan 14 01:09:48 PM PST 24
Peak memory 182716 kb
Host smart-da55ef88-b323-4692-92c7-8e18819a65ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707327712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2707327712
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1190581472
Short name T118
Test name
Test status
Simulation time 19939700808 ps
CPU time 189.65 seconds
Started Jan 14 01:08:43 PM PST 24
Finished Jan 14 01:11:53 PM PST 24
Peak memory 197664 kb
Host smart-abb72a0f-3665-413a-930c-524705e69c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190581472 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1190581472
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3887955673
Short name T89
Test name
Test status
Simulation time 459095880 ps
CPU time 0.94 seconds
Started Jan 14 01:08:49 PM PST 24
Finished Jan 14 01:08:50 PM PST 24
Peak memory 182700 kb
Host smart-b26b49a9-fc9d-4f32-9f49-a7448df3e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887955673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3887955673
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.157645162
Short name T143
Test name
Test status
Simulation time 34990102189 ps
CPU time 24.97 seconds
Started Jan 14 01:08:39 PM PST 24
Finished Jan 14 01:09:04 PM PST 24
Peak memory 182760 kb
Host smart-22274f9e-9d99-47e7-bd50-a3111f016855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157645162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.157645162
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2102946354
Short name T30
Test name
Test status
Simulation time 8454353778 ps
CPU time 6.81 seconds
Started Jan 14 01:08:45 PM PST 24
Finished Jan 14 01:08:52 PM PST 24
Peak memory 214800 kb
Host smart-b68023b0-0d74-49ce-94a7-6477850656e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102946354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2102946354
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2453063302
Short name T182
Test name
Test status
Simulation time 349972124 ps
CPU time 1.02 seconds
Started Jan 14 01:08:36 PM PST 24
Finished Jan 14 01:08:38 PM PST 24
Peak memory 182632 kb
Host smart-1d9db4b6-5c6a-48d9-ada4-22c85ce8015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453063302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2453063302
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1094438868
Short name T106
Test name
Test status
Simulation time 33425435674 ps
CPU time 29.45 seconds
Started Jan 14 01:08:48 PM PST 24
Finished Jan 14 01:09:18 PM PST 24
Peak memory 182716 kb
Host smart-dd92582e-2a17-4e0f-ae0d-5620ad78b121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094438868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1094438868
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.3068521264
Short name T179
Test name
Test status
Simulation time 505843366 ps
CPU time 1.23 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:09:14 PM PST 24
Peak memory 182592 kb
Host smart-b1205f55-f0ed-45b9-b7e1-9a9638d8b430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068521264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.3068521264
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.215499840
Short name T230
Test name
Test status
Simulation time 39730138778 ps
CPU time 14.45 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 182688 kb
Host smart-15190f98-5fb3-4ab9-a9d8-797480e8ef7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215499840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.215499840
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2609127807
Short name T125
Test name
Test status
Simulation time 465412568 ps
CPU time 0.71 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:09:09 PM PST 24
Peak memory 182576 kb
Host smart-4e240f9c-a29a-4bf5-948d-b9b288ea222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609127807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2609127807
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2912469428
Short name T264
Test name
Test status
Simulation time 158331554123 ps
CPU time 55.59 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:10:04 PM PST 24
Peak memory 193004 kb
Host smart-8e8de304-8b42-45c2-9118-0d5cf48fdc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912469428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2912469428
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3359374736
Short name T268
Test name
Test status
Simulation time 518900163 ps
CPU time 0.93 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:05 PM PST 24
Peak memory 182632 kb
Host smart-5de10439-ba5d-4a51-b677-f2e648ca4c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359374736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3359374736
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.2861709307
Short name T220
Test name
Test status
Simulation time 13979934791 ps
CPU time 9.77 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:09:11 PM PST 24
Peak memory 182752 kb
Host smart-34bee6f3-22be-4252-aa30-9befceaf407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861709307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.2861709307
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4197095998
Short name T237
Test name
Test status
Simulation time 427181064 ps
CPU time 0.68 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:05 PM PST 24
Peak memory 182572 kb
Host smart-a1997f65-f1c2-4401-bccb-be501129761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197095998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4197095998
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3684244202
Short name T99
Test name
Test status
Simulation time 819612891569 ps
CPU time 304.18 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:14:06 PM PST 24
Peak memory 197664 kb
Host smart-b721a037-675f-404a-aade-bc65747275e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684244202 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3684244202
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1251958610
Short name T197
Test name
Test status
Simulation time 460777608 ps
CPU time 0.61 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 182696 kb
Host smart-c0361884-e060-41d7-82a0-2d8f6a8c2916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251958610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1251958610
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2365904223
Short name T257
Test name
Test status
Simulation time 56401265861 ps
CPU time 46.29 seconds
Started Jan 14 01:09:06 PM PST 24
Finished Jan 14 01:09:53 PM PST 24
Peak memory 182688 kb
Host smart-d595a59f-d4c9-424c-88c4-6f30b63b20dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365904223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2365904223
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2103689156
Short name T127
Test name
Test status
Simulation time 430202933 ps
CPU time 1.15 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:06 PM PST 24
Peak memory 182632 kb
Host smart-03956abf-8c61-40d3-998a-7f3d2fd28f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103689156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2103689156
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2440930842
Short name T223
Test name
Test status
Simulation time 66527002388 ps
CPU time 490.79 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:17:26 PM PST 24
Peak memory 197656 kb
Host smart-00df34cd-2403-41d9-9ddf-758827b2cfa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440930842 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2440930842
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1739286048
Short name T40
Test name
Test status
Simulation time 588291151 ps
CPU time 0.6 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:12 PM PST 24
Peak memory 182812 kb
Host smart-56fb96f5-375d-4bfc-8d98-6904ea9edbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739286048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1739286048
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1242298992
Short name T196
Test name
Test status
Simulation time 29988415882 ps
CPU time 12.08 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182748 kb
Host smart-7d4af9a0-24a9-4be2-b425-e19fd16fd94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242298992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1242298992
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.26563074
Short name T288
Test name
Test status
Simulation time 399741699 ps
CPU time 0.75 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:09:04 PM PST 24
Peak memory 182640 kb
Host smart-dfc59ffc-1372-4207-a96e-a2aa041b238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26563074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.26563074
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3491255965
Short name T117
Test name
Test status
Simulation time 77889171038 ps
CPU time 63.41 seconds
Started Jan 14 01:09:09 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 192956 kb
Host smart-5a1fb52a-a4e5-4080-8b0b-f82d319778c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491255965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3491255965
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1900808177
Short name T75
Test name
Test status
Simulation time 58148739837 ps
CPU time 452.87 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:16:45 PM PST 24
Peak memory 197708 kb
Host smart-4976bfa5-0176-4ab3-8460-b4f4201c0665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900808177 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1900808177
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3757772047
Short name T169
Test name
Test status
Simulation time 539722265 ps
CPU time 0.75 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:09:08 PM PST 24
Peak memory 182680 kb
Host smart-ebd33c55-c148-489c-8903-b3b8c4dcd924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757772047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3757772047
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.769374606
Short name T137
Test name
Test status
Simulation time 38028558378 ps
CPU time 56.74 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:10:09 PM PST 24
Peak memory 182888 kb
Host smart-e3a2cd1b-20fb-451f-b555-bb010c124ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769374606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.769374606
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.503886719
Short name T234
Test name
Test status
Simulation time 427202686 ps
CPU time 0.7 seconds
Started Jan 14 01:09:06 PM PST 24
Finished Jan 14 01:09:07 PM PST 24
Peak memory 182692 kb
Host smart-f53cdb50-2c56-4097-93c1-488382a15764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503886719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.503886719
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2159261419
Short name T120
Test name
Test status
Simulation time 205425299176 ps
CPU time 175.17 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:12:00 PM PST 24
Peak memory 182752 kb
Host smart-755bb408-2d5a-48c9-b90e-38547673eb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159261419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2159261419
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.888008871
Short name T90
Test name
Test status
Simulation time 38896821166 ps
CPU time 406.34 seconds
Started Jan 14 01:09:05 PM PST 24
Finished Jan 14 01:15:52 PM PST 24
Peak memory 197676 kb
Host smart-8c2cc717-2cfa-405e-bbd7-c134232a3d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888008871 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.888008871
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.88671387
Short name T226
Test name
Test status
Simulation time 444754284 ps
CPU time 1.29 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182704 kb
Host smart-cce659b0-fd7c-40c0-878b-bd61ff80e63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88671387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.88671387
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3321697299
Short name T301
Test name
Test status
Simulation time 23845279579 ps
CPU time 40.02 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:52 PM PST 24
Peak memory 182732 kb
Host smart-f0765880-3027-436c-bd85-4b59c40acc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321697299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3321697299
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.984062681
Short name T164
Test name
Test status
Simulation time 402003081 ps
CPU time 0.78 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182572 kb
Host smart-90164742-4326-4f41-921c-6bfe502aafef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984062681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.984062681
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.4057911230
Short name T190
Test name
Test status
Simulation time 154762193965 ps
CPU time 257.55 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:13:26 PM PST 24
Peak memory 182664 kb
Host smart-8b9f7b76-afee-4d19-ac8e-4bb7b8fd9904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057911230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.4057911230
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1101703609
Short name T18
Test name
Test status
Simulation time 585188929 ps
CPU time 0.72 seconds
Started Jan 14 01:09:09 PM PST 24
Finished Jan 14 01:09:11 PM PST 24
Peak memory 182680 kb
Host smart-f3955eff-ed76-4fce-8534-1dcbf437e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101703609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1101703609
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1484066041
Short name T208
Test name
Test status
Simulation time 28923438184 ps
CPU time 17 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:09:25 PM PST 24
Peak memory 182624 kb
Host smart-027f25ab-7669-4978-b26e-6f026c16140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484066041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1484066041
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3983143810
Short name T239
Test name
Test status
Simulation time 573468468 ps
CPU time 1.49 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:12 PM PST 24
Peak memory 182660 kb
Host smart-de2e8b2e-3535-42be-9e81-8ac5e5d61862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983143810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3983143810
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1716898872
Short name T206
Test name
Test status
Simulation time 162802886690 ps
CPU time 132.25 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:11:24 PM PST 24
Peak memory 190952 kb
Host smart-4ae33fa0-9754-4951-a849-23e9a0b07c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716898872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1716898872
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1822240678
Short name T101
Test name
Test status
Simulation time 56058544680 ps
CPU time 156.5 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:11:41 PM PST 24
Peak memory 197640 kb
Host smart-bdd8deb1-bd69-4415-996c-d47222237e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822240678 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1822240678
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3947633418
Short name T93
Test name
Test status
Simulation time 431921516 ps
CPU time 0.92 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182736 kb
Host smart-3525b2fc-972d-4300-8f21-735b5c71d63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947633418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3947633418
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2936289486
Short name T31
Test name
Test status
Simulation time 25958361195 ps
CPU time 9.93 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:09:19 PM PST 24
Peak memory 182628 kb
Host smart-27233459-97c3-442d-a428-a390df0a3c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936289486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2936289486
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4067910730
Short name T16
Test name
Test status
Simulation time 412432582 ps
CPU time 0.86 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182624 kb
Host smart-c2d6fcbe-d23a-4339-8280-3d30eb98dffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067910730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4067910730
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1254851601
Short name T98
Test name
Test status
Simulation time 257603730873 ps
CPU time 425.74 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:16:21 PM PST 24
Peak memory 182808 kb
Host smart-b6617e3a-397b-4165-a084-d779df674d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254851601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1254851601
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3391720209
Short name T186
Test name
Test status
Simulation time 16037181651 ps
CPU time 168.79 seconds
Started Jan 14 01:09:13 PM PST 24
Finished Jan 14 01:12:03 PM PST 24
Peak memory 197612 kb
Host smart-9d674bca-55d6-4e98-9b5d-e073a9ca2d31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391720209 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3391720209
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1727243458
Short name T252
Test name
Test status
Simulation time 601321059 ps
CPU time 0.96 seconds
Started Jan 14 01:09:06 PM PST 24
Finished Jan 14 01:09:07 PM PST 24
Peak memory 182624 kb
Host smart-5269fdf2-0946-411c-b503-c6b4717e9d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727243458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1727243458
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2074342862
Short name T249
Test name
Test status
Simulation time 27984870774 ps
CPU time 18.61 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:34 PM PST 24
Peak memory 182796 kb
Host smart-261a664b-9ca7-4bec-a683-59e66df597f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074342862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2074342862
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2483156160
Short name T146
Test name
Test status
Simulation time 338143337 ps
CPU time 1.08 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:09:09 PM PST 24
Peak memory 182588 kb
Host smart-67c9f13d-d837-4f7f-b835-e090d9ce5c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483156160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2483156160
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.195038187
Short name T241
Test name
Test status
Simulation time 175734862729 ps
CPU time 70.28 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:10:12 PM PST 24
Peak memory 182760 kb
Host smart-e9303b3f-04dd-4b74-a1e4-896954c713b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195038187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.195038187
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.390690153
Short name T284
Test name
Test status
Simulation time 549566895 ps
CPU time 1.52 seconds
Started Jan 14 01:09:05 PM PST 24
Finished Jan 14 01:09:07 PM PST 24
Peak memory 182708 kb
Host smart-8db95c80-b14d-4f05-a8f2-fded64ef1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390690153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.390690153
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1319999380
Short name T266
Test name
Test status
Simulation time 44588470781 ps
CPU time 54.65 seconds
Started Jan 14 01:09:06 PM PST 24
Finished Jan 14 01:10:01 PM PST 24
Peak memory 182816 kb
Host smart-5e52d5c9-1d3d-409a-b951-d5e77266c319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319999380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1319999380
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2437970147
Short name T25
Test name
Test status
Simulation time 482415747 ps
CPU time 0.8 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:09:03 PM PST 24
Peak memory 182516 kb
Host smart-4c760404-041d-4ba9-ba9b-68f8ce8ae88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437970147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2437970147
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1979761953
Short name T286
Test name
Test status
Simulation time 45586154006 ps
CPU time 12.08 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:09:14 PM PST 24
Peak memory 182760 kb
Host smart-168775a5-f870-425c-a5d2-92f715940779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979761953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1979761953
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1093863010
Short name T88
Test name
Test status
Simulation time 899479622196 ps
CPU time 342.5 seconds
Started Jan 14 01:09:00 PM PST 24
Finished Jan 14 01:14:43 PM PST 24
Peak memory 197640 kb
Host smart-90ef7083-b8d1-4c45-87f6-4a9194009a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093863010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1093863010
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3206565071
Short name T246
Test name
Test status
Simulation time 725572268 ps
CPU time 0.6 seconds
Started Jan 14 01:08:41 PM PST 24
Finished Jan 14 01:08:42 PM PST 24
Peak memory 182700 kb
Host smart-f595e536-64ce-460f-9da9-9ea5fdb3a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206565071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3206565071
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1526191025
Short name T173
Test name
Test status
Simulation time 19133962037 ps
CPU time 8.15 seconds
Started Jan 14 01:08:45 PM PST 24
Finished Jan 14 01:08:54 PM PST 24
Peak memory 182740 kb
Host smart-162f604e-0b5c-42d2-8c76-b3856012c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526191025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1526191025
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1103031803
Short name T32
Test name
Test status
Simulation time 4395322552 ps
CPU time 7.29 seconds
Started Jan 14 01:08:44 PM PST 24
Finished Jan 14 01:08:51 PM PST 24
Peak memory 214796 kb
Host smart-54d56bf3-f258-4c35-8986-43d592caad31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103031803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1103031803
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.779783328
Short name T175
Test name
Test status
Simulation time 418014881 ps
CPU time 1.06 seconds
Started Jan 14 01:08:48 PM PST 24
Finished Jan 14 01:08:49 PM PST 24
Peak memory 182540 kb
Host smart-77c75459-f202-4dde-a20f-edcab7c04762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779783328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.779783328
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1625048730
Short name T236
Test name
Test status
Simulation time 169672962252 ps
CPU time 57.64 seconds
Started Jan 14 01:08:38 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 182736 kb
Host smart-f66da05d-36a1-46de-8c93-1030b657959f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625048730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1625048730
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1438698930
Short name T243
Test name
Test status
Simulation time 447563271 ps
CPU time 1.25 seconds
Started Jan 14 01:09:06 PM PST 24
Finished Jan 14 01:09:07 PM PST 24
Peak memory 182664 kb
Host smart-62461b60-0f57-428f-abbf-740505cb93e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438698930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1438698930
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1407780673
Short name T280
Test name
Test status
Simulation time 19873200240 ps
CPU time 3.36 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:08 PM PST 24
Peak memory 182676 kb
Host smart-fa810a97-9a9a-4f16-8a28-048e123dc5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407780673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1407780673
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3496732350
Short name T144
Test name
Test status
Simulation time 577119946 ps
CPU time 1.41 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182612 kb
Host smart-7b7af829-97c2-4381-a439-d76e04a0c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496732350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3496732350
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1820087516
Short name T261
Test name
Test status
Simulation time 86968672994 ps
CPU time 41.38 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:09:44 PM PST 24
Peak memory 182696 kb
Host smart-47c1acfd-2954-495a-b8fb-11a4ced442e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820087516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1820087516
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3233160985
Short name T203
Test name
Test status
Simulation time 216159365305 ps
CPU time 86.7 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:10:31 PM PST 24
Peak memory 205904 kb
Host smart-40a2facf-26d6-4ea0-b38b-09626acba2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233160985 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3233160985
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.187869926
Short name T107
Test name
Test status
Simulation time 469116287 ps
CPU time 1.32 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182732 kb
Host smart-5e99fdbb-caca-4f2a-a439-6a93fc03d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187869926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.187869926
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1422549412
Short name T124
Test name
Test status
Simulation time 26433296078 ps
CPU time 11.55 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182716 kb
Host smart-617cbb2b-9648-454c-ad96-0722daf226b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422549412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1422549412
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2122938689
Short name T171
Test name
Test status
Simulation time 473930598 ps
CPU time 0.77 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:05 PM PST 24
Peak memory 182532 kb
Host smart-1368d473-747d-41bf-a871-168c0fe583e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122938689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2122938689
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3095616375
Short name T191
Test name
Test status
Simulation time 64863217182 ps
CPU time 11.74 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 194260 kb
Host smart-0251000d-313f-4ae6-a8f7-befce5f55e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095616375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3095616375
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.348770393
Short name T76
Test name
Test status
Simulation time 36543871950 ps
CPU time 136.2 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:11:21 PM PST 24
Peak memory 197668 kb
Host smart-43524a23-bec7-48e5-86b8-9901104309b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348770393 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.348770393
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1063939980
Short name T212
Test name
Test status
Simulation time 540942870 ps
CPU time 0.74 seconds
Started Jan 14 01:09:05 PM PST 24
Finished Jan 14 01:09:06 PM PST 24
Peak memory 182728 kb
Host smart-c4f3e520-324e-40e1-aff0-fea2ec037d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063939980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1063939980
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.715971941
Short name T180
Test name
Test status
Simulation time 6751930925 ps
CPU time 5.92 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:11 PM PST 24
Peak memory 182672 kb
Host smart-a9e08646-7fb3-4788-bcb6-89c63c949724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715971941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.715971941
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1756972039
Short name T152
Test name
Test status
Simulation time 674563488 ps
CPU time 0.57 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:12 PM PST 24
Peak memory 182612 kb
Host smart-bd9150a0-1f8f-48bd-8ad6-d92db311c4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756972039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1756972039
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.603711767
Short name T292
Test name
Test status
Simulation time 178764725232 ps
CPU time 930.5 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:24:40 PM PST 24
Peak memory 203580 kb
Host smart-87675ac2-6413-40b3-8dbc-b3dacc91e91f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603711767 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.603711767
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2173418867
Short name T157
Test name
Test status
Simulation time 609534400 ps
CPU time 1.52 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:09:09 PM PST 24
Peak memory 182732 kb
Host smart-9dd2d374-c89a-40c9-9ad6-94fcd8827b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173418867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2173418867
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.769429983
Short name T168
Test name
Test status
Simulation time 27881160383 ps
CPU time 37.73 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:09:42 PM PST 24
Peak memory 182796 kb
Host smart-01eb54b7-b1c1-4d53-85df-ea738242b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769429983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.769429983
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.907967471
Short name T271
Test name
Test status
Simulation time 525177766 ps
CPU time 1.35 seconds
Started Jan 14 01:09:07 PM PST 24
Finished Jan 14 01:09:09 PM PST 24
Peak memory 182568 kb
Host smart-57a37186-0c2d-4113-baf2-8a6fb12f5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907967471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.907967471
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.558673745
Short name T244
Test name
Test status
Simulation time 22221705302 ps
CPU time 8.97 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:14 PM PST 24
Peak memory 192804 kb
Host smart-b10b95ee-9159-4902-8e6a-d09bdb1892ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558673745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.558673745
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.676361816
Short name T36
Test name
Test status
Simulation time 462600346 ps
CPU time 0.76 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182712 kb
Host smart-b998f88c-bfc7-4492-a401-1c4b1ad66606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676361816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.676361816
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.3283855052
Short name T240
Test name
Test status
Simulation time 39060684561 ps
CPU time 5.15 seconds
Started Jan 14 01:09:11 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182696 kb
Host smart-5a34a701-0bd2-4c26-aa02-7fbceba1abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283855052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.3283855052
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2948662717
Short name T140
Test name
Test status
Simulation time 412958576 ps
CPU time 0.85 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:06 PM PST 24
Peak memory 182580 kb
Host smart-b74615b1-ea7d-4194-8add-03c98193aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948662717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2948662717
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1897569801
Short name T94
Test name
Test status
Simulation time 421957113 ps
CPU time 1 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:19 PM PST 24
Peak memory 182732 kb
Host smart-32204975-96a6-4bda-8d60-a7ae78bb12b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897569801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1897569801
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.559210849
Short name T216
Test name
Test status
Simulation time 41265288018 ps
CPU time 71.16 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:10:24 PM PST 24
Peak memory 182732 kb
Host smart-3f072041-ef96-4ae0-bb0d-0431444f42d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559210849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.559210849
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1117191807
Short name T275
Test name
Test status
Simulation time 406119718 ps
CPU time 0.64 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:19 PM PST 24
Peak memory 182392 kb
Host smart-d8071f2c-b1df-4909-b3a0-6134c40574e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117191807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1117191807
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.421462100
Short name T91
Test name
Test status
Simulation time 219496501973 ps
CPU time 79.01 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:10:34 PM PST 24
Peak memory 182812 kb
Host smart-f8816187-6cdf-49bc-9ce2-0b98e024fbc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421462100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.421462100
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.532281238
Short name T41
Test name
Test status
Simulation time 20388867430 ps
CPU time 179.42 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:12:17 PM PST 24
Peak memory 197380 kb
Host smart-a3ba474a-1a85-4602-9759-c708f7bb2f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532281238 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.532281238
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2070498983
Short name T281
Test name
Test status
Simulation time 569491925 ps
CPU time 1.33 seconds
Started Jan 14 01:09:19 PM PST 24
Finished Jan 14 01:09:21 PM PST 24
Peak memory 182692 kb
Host smart-efd3e22e-a6f0-4451-96bf-4aeef85257ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070498983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2070498983
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1486927569
Short name T136
Test name
Test status
Simulation time 11827941334 ps
CPU time 8.2 seconds
Started Jan 14 01:09:09 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182660 kb
Host smart-c7eb9d37-ce48-41e5-a763-354172b27322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486927569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1486927569
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1498557805
Short name T259
Test name
Test status
Simulation time 349739283 ps
CPU time 1.01 seconds
Started Jan 14 01:09:18 PM PST 24
Finished Jan 14 01:09:20 PM PST 24
Peak memory 182660 kb
Host smart-3784eba8-f116-456f-8611-98d294cf9602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498557805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1498557805
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3707448774
Short name T293
Test name
Test status
Simulation time 73087749821 ps
CPU time 25.83 seconds
Started Jan 14 01:09:10 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 193108 kb
Host smart-283b0a5e-8bc2-4c6b-b5ad-378c4ad10605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707448774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3707448774
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_jump.536825565
Short name T229
Test name
Test status
Simulation time 537853798 ps
CPU time 1.38 seconds
Started Jan 14 01:09:18 PM PST 24
Finished Jan 14 01:09:20 PM PST 24
Peak memory 182652 kb
Host smart-b90bb913-f624-4873-8c14-b6003c427b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536825565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.536825565
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3153783892
Short name T148
Test name
Test status
Simulation time 60166469395 ps
CPU time 12.83 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:31 PM PST 24
Peak memory 182692 kb
Host smart-b7a695f4-30cf-4193-85f1-6758fc25bd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153783892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3153783892
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.118926089
Short name T185
Test name
Test status
Simulation time 556569763 ps
CPU time 0.75 seconds
Started Jan 14 01:09:20 PM PST 24
Finished Jan 14 01:09:21 PM PST 24
Peak memory 182696 kb
Host smart-91f20c10-128c-4a06-bc0e-a55d60aec39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118926089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.118926089
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3990087918
Short name T233
Test name
Test status
Simulation time 505025486790 ps
CPU time 186.24 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 182736 kb
Host smart-42e5f8a0-528e-4f2a-9e98-0f06dc5b1b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990087918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3990087918
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.498039289
Short name T265
Test name
Test status
Simulation time 24678963069 ps
CPU time 258.04 seconds
Started Jan 14 01:09:14 PM PST 24
Finished Jan 14 01:13:32 PM PST 24
Peak memory 197624 kb
Host smart-2b84ef99-5de7-4e4e-98f9-24efe12cf1c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498039289 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.498039289
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3110945016
Short name T109
Test name
Test status
Simulation time 372578302 ps
CPU time 1.11 seconds
Started Jan 14 01:09:14 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 182676 kb
Host smart-9eada4f6-5e91-4f86-9a50-fe459eb81676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110945016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3110945016
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.455729609
Short name T147
Test name
Test status
Simulation time 32239922295 ps
CPU time 13.52 seconds
Started Jan 14 01:09:14 PM PST 24
Finished Jan 14 01:09:28 PM PST 24
Peak memory 182740 kb
Host smart-9083cb8f-bd62-45f5-9825-02904c7acaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455729609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.455729609
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3105905457
Short name T214
Test name
Test status
Simulation time 449871083 ps
CPU time 0.7 seconds
Started Jan 14 01:09:19 PM PST 24
Finished Jan 14 01:09:20 PM PST 24
Peak memory 182520 kb
Host smart-1ce139e0-85d5-4270-b242-fea8c60df71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105905457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3105905457
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1120041333
Short name T51
Test name
Test status
Simulation time 63638938794 ps
CPU time 584.88 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:19:03 PM PST 24
Peak memory 205832 kb
Host smart-ee131f39-f427-48b1-b8b5-4dc71b122c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120041333 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1120041333
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2620053962
Short name T105
Test name
Test status
Simulation time 416239856 ps
CPU time 1.28 seconds
Started Jan 14 01:09:10 PM PST 24
Finished Jan 14 01:09:11 PM PST 24
Peak memory 182692 kb
Host smart-ecaa49d6-a69b-4227-8911-65caa3351778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620053962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2620053962
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3959364406
Short name T225
Test name
Test status
Simulation time 24527707547 ps
CPU time 10.74 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:28 PM PST 24
Peak memory 182760 kb
Host smart-da9b507a-b5ec-4541-838a-0f6bae8c0368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959364406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3959364406
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3243837953
Short name T277
Test name
Test status
Simulation time 678297953 ps
CPU time 0.58 seconds
Started Jan 14 01:09:16 PM PST 24
Finished Jan 14 01:09:17 PM PST 24
Peak memory 182632 kb
Host smart-6f1f56b3-e97a-41ca-b583-fba4025bde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243837953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3243837953
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.3385186661
Short name T181
Test name
Test status
Simulation time 68981219602 ps
CPU time 102.49 seconds
Started Jan 14 01:09:21 PM PST 24
Finished Jan 14 01:11:04 PM PST 24
Peak memory 182720 kb
Host smart-0beaac35-3255-46e1-9c66-bc02cf2b96ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385186661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.3385186661
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.217287526
Short name T20
Test name
Test status
Simulation time 54649024092 ps
CPU time 154.96 seconds
Started Jan 14 01:09:29 PM PST 24
Finished Jan 14 01:12:05 PM PST 24
Peak memory 197612 kb
Host smart-fa59e100-7210-4929-aded-4f6f2e124d8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217287526 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.217287526
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.3788172685
Short name T122
Test name
Test status
Simulation time 435205508 ps
CPU time 1.24 seconds
Started Jan 14 01:08:33 PM PST 24
Finished Jan 14 01:08:35 PM PST 24
Peak memory 182660 kb
Host smart-766772ff-d6e6-4252-99fc-dd0d6e465a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788172685 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.3788172685
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2045022320
Short name T217
Test name
Test status
Simulation time 4554550861 ps
CPU time 8.11 seconds
Started Jan 14 01:08:34 PM PST 24
Finished Jan 14 01:08:43 PM PST 24
Peak memory 182752 kb
Host smart-5ba7bab1-cac4-4f67-a7d4-f9c4f83f0f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045022320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2045022320
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3890035836
Short name T35
Test name
Test status
Simulation time 4444860703 ps
CPU time 2.4 seconds
Started Jan 14 01:08:35 PM PST 24
Finished Jan 14 01:08:38 PM PST 24
Peak memory 214932 kb
Host smart-aedd01a4-e0d3-404f-8bfb-70eacbc838e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890035836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3890035836
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2897624441
Short name T267
Test name
Test status
Simulation time 459070472 ps
CPU time 0.65 seconds
Started Jan 14 01:08:39 PM PST 24
Finished Jan 14 01:08:40 PM PST 24
Peak memory 182596 kb
Host smart-2b8d072b-7f90-4fd0-a949-10e350ce605a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897624441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2897624441
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.2519251993
Short name T183
Test name
Test status
Simulation time 27553985571 ps
CPU time 23.8 seconds
Started Jan 14 01:08:38 PM PST 24
Finished Jan 14 01:09:02 PM PST 24
Peak memory 192864 kb
Host smart-eda9c8ed-02e3-4bff-bb35-17c0f6904141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519251993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.2519251993
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.572356514
Short name T258
Test name
Test status
Simulation time 244725678007 ps
CPU time 650.09 seconds
Started Jan 14 01:08:39 PM PST 24
Finished Jan 14 01:19:29 PM PST 24
Peak memory 199372 kb
Host smart-d1537998-0492-454e-bf21-f9a1b56e59da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572356514 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.572356514
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1245335675
Short name T155
Test name
Test status
Simulation time 488032294 ps
CPU time 0.73 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 182648 kb
Host smart-5bd444be-0cc4-4e96-ab18-f3f76efdad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245335675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1245335675
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.268853431
Short name T282
Test name
Test status
Simulation time 2723916554 ps
CPU time 4.84 seconds
Started Jan 14 01:09:25 PM PST 24
Finished Jan 14 01:09:30 PM PST 24
Peak memory 182668 kb
Host smart-bfde3d1e-0ddd-4758-bacd-7cf1ef6bd705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268853431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.268853431
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.743718957
Short name T160
Test name
Test status
Simulation time 398585522 ps
CPU time 0.62 seconds
Started Jan 14 01:09:24 PM PST 24
Finished Jan 14 01:09:25 PM PST 24
Peak memory 182556 kb
Host smart-23bba69c-8ddc-415c-bcc5-ee351b20e17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743718957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.743718957
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1418506182
Short name T205
Test name
Test status
Simulation time 22878633689 ps
CPU time 17.86 seconds
Started Jan 14 01:09:29 PM PST 24
Finished Jan 14 01:09:47 PM PST 24
Peak memory 192884 kb
Host smart-11d61b9c-11b2-4f45-b747-e7bd6812b31e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418506182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1418506182
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.4058211837
Short name T97
Test name
Test status
Simulation time 311655942612 ps
CPU time 652.05 seconds
Started Jan 14 01:09:21 PM PST 24
Finished Jan 14 01:20:14 PM PST 24
Peak memory 198772 kb
Host smart-077d5dbd-2e39-46ca-930d-2313fec207b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058211837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.4058211837
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1133702562
Short name T296
Test name
Test status
Simulation time 433273860 ps
CPU time 0.93 seconds
Started Jan 14 01:09:29 PM PST 24
Finished Jan 14 01:09:31 PM PST 24
Peak memory 182648 kb
Host smart-94476c1e-78b2-47b4-9892-846b87544d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133702562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1133702562
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2008101774
Short name T204
Test name
Test status
Simulation time 38353405697 ps
CPU time 52.21 seconds
Started Jan 14 01:09:26 PM PST 24
Finished Jan 14 01:10:19 PM PST 24
Peak memory 182744 kb
Host smart-19309d8e-ced8-4340-85f5-4fbfc4f30d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008101774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2008101774
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1845072143
Short name T126
Test name
Test status
Simulation time 428375946 ps
CPU time 0.7 seconds
Started Jan 14 01:09:26 PM PST 24
Finished Jan 14 01:09:27 PM PST 24
Peak memory 182516 kb
Host smart-114aaf25-0316-4622-b03c-6d62f8eeb125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845072143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1845072143
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2787633443
Short name T198
Test name
Test status
Simulation time 132164682753 ps
CPU time 180.9 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:12:35 PM PST 24
Peak memory 193208 kb
Host smart-5fc0e1ad-3f26-4ec4-babb-376d96d2c235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787633443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2787633443
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.892334837
Short name T170
Test name
Test status
Simulation time 83948740275 ps
CPU time 480.51 seconds
Started Jan 14 01:09:28 PM PST 24
Finished Jan 14 01:17:29 PM PST 24
Peak memory 197652 kb
Host smart-edc2ced9-d63f-4297-a4b1-dabf0fdd110e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892334837 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.892334837
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3846058480
Short name T115
Test name
Test status
Simulation time 440838780 ps
CPU time 0.72 seconds
Started Jan 14 01:09:29 PM PST 24
Finished Jan 14 01:09:30 PM PST 24
Peak memory 182648 kb
Host smart-bd0dbb22-9124-4c87-ba9e-35cae26d64f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846058480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3846058480
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1920817980
Short name T149
Test name
Test status
Simulation time 12289639334 ps
CPU time 5.34 seconds
Started Jan 14 01:09:28 PM PST 24
Finished Jan 14 01:09:34 PM PST 24
Peak memory 182756 kb
Host smart-5c8596bc-6a8c-4fe5-a5c1-e9c6fd1b5838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920817980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1920817980
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.263041594
Short name T165
Test name
Test status
Simulation time 583377947 ps
CPU time 1.32 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182548 kb
Host smart-2b73f386-e5e8-49a1-918c-5ef6b713c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263041594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.263041594
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2073184554
Short name T84
Test name
Test status
Simulation time 140856234155 ps
CPU time 93.5 seconds
Started Jan 14 01:09:18 PM PST 24
Finished Jan 14 01:10:52 PM PST 24
Peak memory 193020 kb
Host smart-42bb5549-6a8e-4d9d-8b6e-d16269549822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073184554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2073184554
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3013273962
Short name T38
Test name
Test status
Simulation time 192805634426 ps
CPU time 402.32 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:16:15 PM PST 24
Peak memory 197676 kb
Host smart-8e464d2e-4a21-42c0-ac14-b642e012102f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013273962 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3013273962
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2802084445
Short name T138
Test name
Test status
Simulation time 574126049 ps
CPU time 1.46 seconds
Started Jan 14 01:09:19 PM PST 24
Finished Jan 14 01:09:21 PM PST 24
Peak memory 182632 kb
Host smart-0227a793-7652-4e2d-9692-bc0fccf502e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802084445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2802084445
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1308436031
Short name T285
Test name
Test status
Simulation time 28567951838 ps
CPU time 12.02 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:28 PM PST 24
Peak memory 182676 kb
Host smart-1e39e8a8-52ba-4e73-bada-ef7d09115062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308436031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1308436031
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1160898529
Short name T192
Test name
Test status
Simulation time 401165621 ps
CPU time 0.68 seconds
Started Jan 14 01:09:27 PM PST 24
Finished Jan 14 01:09:28 PM PST 24
Peak memory 182520 kb
Host smart-c8e176d6-88d2-4fb4-a0d3-89dbe04dc370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160898529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1160898529
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3635325989
Short name T242
Test name
Test status
Simulation time 224410651431 ps
CPU time 85.74 seconds
Started Jan 14 01:09:19 PM PST 24
Finished Jan 14 01:10:45 PM PST 24
Peak memory 182696 kb
Host smart-b2d9af6b-b6de-4db1-9b21-fbee2b6c2177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635325989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3635325989
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3759217140
Short name T172
Test name
Test status
Simulation time 820385326780 ps
CPU time 556.82 seconds
Started Jan 14 01:09:14 PM PST 24
Finished Jan 14 01:18:31 PM PST 24
Peak memory 197792 kb
Host smart-347c73b7-df01-417d-b52b-6d22b6b98bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759217140 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3759217140
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1461811126
Short name T228
Test name
Test status
Simulation time 545003803 ps
CPU time 0.88 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:18 PM PST 24
Peak memory 182728 kb
Host smart-c67cd448-a43e-4566-ad6d-07da3e1b6889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461811126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1461811126
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3561137941
Short name T39
Test name
Test status
Simulation time 54362034022 ps
CPU time 19.33 seconds
Started Jan 14 01:09:20 PM PST 24
Finished Jan 14 01:09:39 PM PST 24
Peak memory 182656 kb
Host smart-1dbdb9bd-3dcb-4e2a-ab84-fd145cdd2bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561137941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3561137941
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1740661325
Short name T130
Test name
Test status
Simulation time 527482640 ps
CPU time 0.72 seconds
Started Jan 14 01:09:12 PM PST 24
Finished Jan 14 01:09:13 PM PST 24
Peak memory 182628 kb
Host smart-cb32fb42-276e-46c4-9e47-2c2876ba8b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740661325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1740661325
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.124938743
Short name T202
Test name
Test status
Simulation time 206764190734 ps
CPU time 308.81 seconds
Started Jan 14 01:09:19 PM PST 24
Finished Jan 14 01:14:29 PM PST 24
Peak memory 197576 kb
Host smart-325c177f-d607-4761-a13b-4a59810301b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124938743 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.124938743
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3635866590
Short name T178
Test name
Test status
Simulation time 527787696 ps
CPU time 1.48 seconds
Started Jan 14 01:09:17 PM PST 24
Finished Jan 14 01:09:19 PM PST 24
Peak memory 182660 kb
Host smart-8a6ebbfa-32cd-44be-ab23-b78e3ee7ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635866590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3635866590
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2482445349
Short name T135
Test name
Test status
Simulation time 40254402955 ps
CPU time 30.77 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:46 PM PST 24
Peak memory 182724 kb
Host smart-c6f1ed2c-19a1-442e-8abd-718384d4ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482445349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2482445349
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.424699586
Short name T166
Test name
Test status
Simulation time 480367924 ps
CPU time 0.74 seconds
Started Jan 14 01:09:15 PM PST 24
Finished Jan 14 01:09:16 PM PST 24
Peak memory 182536 kb
Host smart-678e7c8b-d05a-4ba6-bac6-e122035d5b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424699586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.424699586
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2876068919
Short name T176
Test name
Test status
Simulation time 272207939814 ps
CPU time 306.62 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:14:38 PM PST 24
Peak memory 192816 kb
Host smart-a519afcd-4ec8-4814-b3ec-3d6f90f1b991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876068919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2876068919
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3923662328
Short name T121
Test name
Test status
Simulation time 29207953889 ps
CPU time 230.49 seconds
Started Jan 14 01:09:22 PM PST 24
Finished Jan 14 01:13:13 PM PST 24
Peak memory 197648 kb
Host smart-586a905c-2e13-4d6f-a114-f15ce28d133e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923662328 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3923662328
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2546991730
Short name T269
Test name
Test status
Simulation time 389932436 ps
CPU time 0.74 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182700 kb
Host smart-462ab3a3-4db3-4656-8ba9-aa45c209579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546991730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2546991730
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.727602643
Short name T291
Test name
Test status
Simulation time 55081960487 ps
CPU time 42.84 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:10:16 PM PST 24
Peak memory 182764 kb
Host smart-a5fa3984-a167-4eca-8fdf-9ecebcb7b268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727602643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.727602643
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.644723732
Short name T150
Test name
Test status
Simulation time 423870799 ps
CPU time 1.01 seconds
Started Jan 14 01:09:26 PM PST 24
Finished Jan 14 01:09:27 PM PST 24
Peak memory 182560 kb
Host smart-a541943b-3e0f-44e2-8850-92cdbd1ec988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644723732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.644723732
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.3364376437
Short name T87
Test name
Test status
Simulation time 4331635356 ps
CPU time 2.46 seconds
Started Jan 14 01:09:29 PM PST 24
Finished Jan 14 01:09:32 PM PST 24
Peak memory 182716 kb
Host smart-378cef82-db52-408f-a5cb-07868a5b0e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364376437 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.3364376437
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1136101799
Short name T272
Test name
Test status
Simulation time 65451792239 ps
CPU time 187.26 seconds
Started Jan 14 01:09:26 PM PST 24
Finished Jan 14 01:12:34 PM PST 24
Peak memory 205832 kb
Host smart-c070fcc9-1319-4850-abaf-18f7b1193ea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136101799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1136101799
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1927827328
Short name T245
Test name
Test status
Simulation time 454280012 ps
CPU time 1.21 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182668 kb
Host smart-764f4edf-c0c5-4548-95be-20b49cbb3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927827328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1927827328
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.164320111
Short name T153
Test name
Test status
Simulation time 40267763796 ps
CPU time 25.62 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:57 PM PST 24
Peak memory 182696 kb
Host smart-22fec987-ae37-4ffa-80fe-43cedc541a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164320111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.164320111
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.1848851
Short name T128
Test name
Test status
Simulation time 388153865 ps
CPU time 0.71 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182628 kb
Host smart-4e7671f8-397a-4b79-960d-877593a486fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.1848851
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3254785055
Short name T294
Test name
Test status
Simulation time 204036973177 ps
CPU time 172.45 seconds
Started Jan 14 01:09:27 PM PST 24
Finished Jan 14 01:12:20 PM PST 24
Peak memory 182772 kb
Host smart-dff5a32c-fc6f-422e-848b-067135d15b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254785055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3254785055
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.660690533
Short name T251
Test name
Test status
Simulation time 591721404 ps
CPU time 1.27 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182736 kb
Host smart-cfbeb1e6-b92a-4d04-b8e7-aef21cb1916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660690533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.660690533
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1195386503
Short name T145
Test name
Test status
Simulation time 21772710764 ps
CPU time 33.47 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:10:07 PM PST 24
Peak memory 182760 kb
Host smart-c983787e-db8f-41ff-9cfe-85a04a4ea241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195386503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1195386503
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2387639682
Short name T162
Test name
Test status
Simulation time 366450980 ps
CPU time 1.08 seconds
Started Jan 14 01:09:28 PM PST 24
Finished Jan 14 01:09:30 PM PST 24
Peak memory 182600 kb
Host smart-e4c391e5-1512-4e11-953c-069250f7f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387639682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2387639682
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1627867140
Short name T297
Test name
Test status
Simulation time 171384600677 ps
CPU time 58.27 seconds
Started Jan 14 01:09:30 PM PST 24
Finished Jan 14 01:10:29 PM PST 24
Peak memory 193056 kb
Host smart-2c2ec60a-fd28-40a4-87eb-1b8619bc9adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627867140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1627867140
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.896090184
Short name T274
Test name
Test status
Simulation time 64207971441 ps
CPU time 486.42 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:17:40 PM PST 24
Peak memory 197664 kb
Host smart-dd163325-e15a-4bf1-b90f-2cdb4183a65a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896090184 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.896090184
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.4051577260
Short name T210
Test name
Test status
Simulation time 369915516 ps
CPU time 1.14 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:32 PM PST 24
Peak memory 182728 kb
Host smart-3bf6d8f5-a0e1-46bb-a90d-a473de7dfe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051577260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.4051577260
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1922855527
Short name T29
Test name
Test status
Simulation time 52231426004 ps
CPU time 23.43 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:55 PM PST 24
Peak memory 182732 kb
Host smart-447fdfbd-8984-4fbc-9964-967857a534e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922855527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1922855527
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3393287948
Short name T142
Test name
Test status
Simulation time 503885422 ps
CPU time 1.35 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182616 kb
Host smart-450e368c-1582-4754-a346-71249b99d603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393287948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3393287948
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2432482866
Short name T235
Test name
Test status
Simulation time 10804378810 ps
CPU time 9.48 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 182428 kb
Host smart-f6e0307c-7019-469b-b681-345117f5dcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432482866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2432482866
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.244689269
Short name T100
Test name
Test status
Simulation time 124095964076 ps
CPU time 271.15 seconds
Started Jan 14 01:09:37 PM PST 24
Finished Jan 14 01:14:08 PM PST 24
Peak memory 197628 kb
Host smart-8ead2b6b-af66-40bc-a448-d43d5609f204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244689269 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.244689269
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2023060957
Short name T187
Test name
Test status
Simulation time 488825347 ps
CPU time 1.34 seconds
Started Jan 14 01:08:38 PM PST 24
Finished Jan 14 01:08:40 PM PST 24
Peak memory 182620 kb
Host smart-683976c3-9c45-488a-8362-9c96b3be18d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023060957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2023060957
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3124023188
Short name T218
Test name
Test status
Simulation time 23135530589 ps
CPU time 9.06 seconds
Started Jan 14 01:08:38 PM PST 24
Finished Jan 14 01:08:48 PM PST 24
Peak memory 182724 kb
Host smart-f104b9bd-14b5-4fff-9dd6-f234f88d5cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124023188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3124023188
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.748596731
Short name T33
Test name
Test status
Simulation time 7906672217 ps
CPU time 13.04 seconds
Started Jan 14 01:08:38 PM PST 24
Finished Jan 14 01:08:51 PM PST 24
Peak memory 214824 kb
Host smart-e99b0753-2bbf-4ff3-aca7-e3d0af3828ba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748596731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.748596731
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.733010567
Short name T158
Test name
Test status
Simulation time 374013552 ps
CPU time 0.79 seconds
Started Jan 14 01:08:35 PM PST 24
Finished Jan 14 01:08:37 PM PST 24
Peak memory 182720 kb
Host smart-8a8c8b33-7d39-4e3e-856a-42d90167616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733010567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.733010567
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1239403829
Short name T82
Test name
Test status
Simulation time 386222734278 ps
CPU time 645.99 seconds
Started Jan 14 01:08:40 PM PST 24
Finished Jan 14 01:19:26 PM PST 24
Peak memory 182704 kb
Host smart-0b088e71-66b6-448d-b329-b8f27e107835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239403829 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1239403829
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3461508928
Short name T108
Test name
Test status
Simulation time 97189662780 ps
CPU time 206.5 seconds
Started Jan 14 01:08:48 PM PST 24
Finished Jan 14 01:12:15 PM PST 24
Peak memory 197596 kb
Host smart-51dbfba8-bc8a-40e4-ba9c-ff360057ddf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461508928 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3461508928
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3325136969
Short name T279
Test name
Test status
Simulation time 600702794 ps
CPU time 0.63 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182628 kb
Host smart-c9f21ae4-4202-43d5-ac23-3c97eda1ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325136969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3325136969
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2924123390
Short name T21
Test name
Test status
Simulation time 47835759571 ps
CPU time 4.83 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182852 kb
Host smart-53b08809-3c26-41c2-978a-d10983bb2753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924123390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2924123390
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1107609232
Short name T159
Test name
Test status
Simulation time 455490956 ps
CPU time 0.59 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182576 kb
Host smart-b92b7e7e-35d8-4c5b-a8b4-fd69226a3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107609232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1107609232
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3801875174
Short name T193
Test name
Test status
Simulation time 124912361294 ps
CPU time 199.37 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:12:52 PM PST 24
Peak memory 182692 kb
Host smart-aef85523-1a7e-401e-9f32-9cb855920aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801875174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3801875174
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.209330095
Short name T83
Test name
Test status
Simulation time 54931912325 ps
CPU time 236.6 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:13:29 PM PST 24
Peak memory 197704 kb
Host smart-a23ca655-ae26-4bee-b60b-ddaa0263f53b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209330095 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.209330095
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1012039263
Short name T194
Test name
Test status
Simulation time 592409898 ps
CPU time 0.87 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:09:35 PM PST 24
Peak memory 182700 kb
Host smart-e70c203a-0763-4d1a-aba2-2e37735c0b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012039263 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1012039263
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2796773616
Short name T139
Test name
Test status
Simulation time 16679555989 ps
CPU time 27.14 seconds
Started Jan 14 01:09:37 PM PST 24
Finished Jan 14 01:10:04 PM PST 24
Peak memory 182752 kb
Host smart-a5535c45-4dad-466a-befa-0c44068da76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796773616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2796773616
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1486434954
Short name T289
Test name
Test status
Simulation time 437149962 ps
CPU time 1.21 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 182692 kb
Host smart-e33461c3-ef8f-4c7a-8e07-3d9613d1edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486434954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1486434954
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3089300695
Short name T113
Test name
Test status
Simulation time 234224469654 ps
CPU time 362.21 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:15:37 PM PST 24
Peak memory 182728 kb
Host smart-34e31a5c-a637-4f77-bdb7-1dfed02797a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089300695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3089300695
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1241819058
Short name T22
Test name
Test status
Simulation time 323114165811 ps
CPU time 313.47 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:14:50 PM PST 24
Peak memory 197628 kb
Host smart-d3086ae5-af4d-4f33-8c5b-ce31b9cdb4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241819058 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1241819058
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.492824788
Short name T103
Test name
Test status
Simulation time 402194340 ps
CPU time 0.69 seconds
Started Jan 14 01:09:32 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182636 kb
Host smart-ca19c6fc-6f43-4c4b-8b1b-e5cf92911fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492824788 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.492824788
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.609206357
Short name T209
Test name
Test status
Simulation time 18687537125 ps
CPU time 28.46 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:10:02 PM PST 24
Peak memory 182736 kb
Host smart-efd3d2b6-c207-4124-9a74-4f11f08f4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609206357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.609206357
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3958178423
Short name T134
Test name
Test status
Simulation time 552270406 ps
CPU time 0.76 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 182692 kb
Host smart-35addb3d-2a56-4887-88b2-cfe9c51f5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958178423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3958178423
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3960643356
Short name T111
Test name
Test status
Simulation time 4300685495 ps
CPU time 7.24 seconds
Started Jan 14 01:09:42 PM PST 24
Finished Jan 14 01:09:50 PM PST 24
Peak memory 193216 kb
Host smart-fb5a6c77-fd57-44d4-9392-4ff577f7539d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960643356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3960643356
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1731562588
Short name T174
Test name
Test status
Simulation time 105951717595 ps
CPU time 291.2 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:14:26 PM PST 24
Peak memory 197636 kb
Host smart-ca377bc9-2ad8-4d1a-b5af-df50ebe3e4e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731562588 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1731562588
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1028275696
Short name T260
Test name
Test status
Simulation time 386248712 ps
CPU time 1.13 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:38 PM PST 24
Peak memory 182644 kb
Host smart-6a597308-7c6a-40c8-bfe8-14c01f3be67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028275696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1028275696
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3986610891
Short name T163
Test name
Test status
Simulation time 50262018301 ps
CPU time 73.6 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:10:48 PM PST 24
Peak memory 182688 kb
Host smart-50ad0dd4-d947-450c-a932-a0ac0acf741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986610891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3986610891
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.4011665377
Short name T131
Test name
Test status
Simulation time 383657565 ps
CPU time 0.64 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:37 PM PST 24
Peak memory 182532 kb
Host smart-aa393527-c622-4c10-b630-6ec938475cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011665377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.4011665377
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.3945572245
Short name T116
Test name
Test status
Simulation time 95858150356 ps
CPU time 145.33 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:12:00 PM PST 24
Peak memory 182768 kb
Host smart-ac7111c0-27fb-443d-8577-16f76aed7865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945572245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.3945572245
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3463890653
Short name T69
Test name
Test status
Simulation time 121961847717 ps
CPU time 1020.7 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:26:39 PM PST 24
Peak memory 202260 kb
Host smart-9d54456d-d951-4fb1-b45e-58da684cdc2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463890653 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3463890653
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.2428356917
Short name T151
Test name
Test status
Simulation time 405824667 ps
CPU time 0.8 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:09:35 PM PST 24
Peak memory 182672 kb
Host smart-31d69767-6e35-4d51-b04d-b9e63ab47080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428356917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.2428356917
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.27533398
Short name T215
Test name
Test status
Simulation time 8571522154 ps
CPU time 4.01 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182680 kb
Host smart-464e8c3d-efb4-46b0-808a-9fd4a28f2816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27533398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.27533398
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2993591194
Short name T132
Test name
Test status
Simulation time 506726601 ps
CPU time 1.08 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 182596 kb
Host smart-d7854b51-f0e1-4a9c-8f67-39718db611e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993591194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2993591194
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.561602419
Short name T295
Test name
Test status
Simulation time 152500233616 ps
CPU time 253.81 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:13:48 PM PST 24
Peak memory 182656 kb
Host smart-ba008b96-a488-4178-b6cc-9d80bdcdf799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561602419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.561602419
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2720524042
Short name T222
Test name
Test status
Simulation time 43234322719 ps
CPU time 165.72 seconds
Started Jan 14 01:09:35 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 197588 kb
Host smart-5f65f18d-2299-4d5b-92dd-abe84a4a9cc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720524042 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2720524042
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.287444420
Short name T119
Test name
Test status
Simulation time 529105480 ps
CPU time 1.46 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:09:33 PM PST 24
Peak memory 182708 kb
Host smart-9355dff8-1dbd-4013-9578-58e3c58bb19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287444420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.287444420
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4163201301
Short name T219
Test name
Test status
Simulation time 20377861871 ps
CPU time 6.89 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:42 PM PST 24
Peak memory 182692 kb
Host smart-7eddd680-bf2b-43a9-909d-e878aece84be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163201301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4163201301
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1834346129
Short name T154
Test name
Test status
Simulation time 408635791 ps
CPU time 0.69 seconds
Started Jan 14 01:09:41 PM PST 24
Finished Jan 14 01:09:42 PM PST 24
Peak memory 182720 kb
Host smart-fcbbd406-d746-4128-ba6b-32bd70aa94ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834346129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1834346129
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2247265342
Short name T114
Test name
Test status
Simulation time 14386753626 ps
CPU time 6.28 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:09:47 PM PST 24
Peak memory 182712 kb
Host smart-6f7cc6fd-9a8b-4324-977d-c40dd299fe15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247265342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2247265342
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.843759761
Short name T37
Test name
Test status
Simulation time 20542459393 ps
CPU time 105.49 seconds
Started Jan 14 01:09:42 PM PST 24
Finished Jan 14 01:11:29 PM PST 24
Peak memory 196808 kb
Host smart-52c37695-fa4f-4336-84b3-898712e738d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843759761 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.843759761
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1144096260
Short name T262
Test name
Test status
Simulation time 530204826 ps
CPU time 1.37 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:09:36 PM PST 24
Peak memory 182500 kb
Host smart-07e0512b-6823-4624-9401-05daf8474f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144096260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1144096260
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2322755550
Short name T19
Test name
Test status
Simulation time 25474183621 ps
CPU time 10.66 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 182652 kb
Host smart-87f714ff-b81d-4244-a516-6256b95eeca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322755550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2322755550
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1289848022
Short name T248
Test name
Test status
Simulation time 518675937 ps
CPU time 0.62 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182536 kb
Host smart-867b2814-694a-4200-a3ee-d4e346141388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289848022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1289848022
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.3132102512
Short name T81
Test name
Test status
Simulation time 83827031289 ps
CPU time 117.56 seconds
Started Jan 14 01:09:39 PM PST 24
Finished Jan 14 01:11:38 PM PST 24
Peak memory 192884 kb
Host smart-f9f5689e-d49d-4b3a-bcac-1c7bff1a4cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132102512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.3132102512
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.496787868
Short name T213
Test name
Test status
Simulation time 114131700919 ps
CPU time 328.38 seconds
Started Jan 14 01:09:37 PM PST 24
Finished Jan 14 01:15:06 PM PST 24
Peak memory 197628 kb
Host smart-2715788e-6d63-4a0b-818c-75d5d18bfd8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496787868 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.496787868
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2239588809
Short name T112
Test name
Test status
Simulation time 444198942 ps
CPU time 0.71 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 182704 kb
Host smart-b5def1b2-30ef-4769-85c6-a9aadf43a7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239588809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2239588809
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2529523935
Short name T189
Test name
Test status
Simulation time 9088615717 ps
CPU time 2.7 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:47 PM PST 24
Peak memory 182728 kb
Host smart-9e0f2037-4ace-43d5-8511-49537bdfb714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529523935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2529523935
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.980853775
Short name T253
Test name
Test status
Simulation time 470229584 ps
CPU time 0.72 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:09:40 PM PST 24
Peak memory 182644 kb
Host smart-10297453-6f3a-45e6-a398-db63c62c5fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980853775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.980853775
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1140483806
Short name T95
Test name
Test status
Simulation time 120112966837 ps
CPU time 47.58 seconds
Started Jan 14 01:09:38 PM PST 24
Finished Jan 14 01:10:26 PM PST 24
Peak memory 182708 kb
Host smart-3da7fac6-03d8-4aab-83d3-65ad528b51e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140483806 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1140483806
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.448514479
Short name T86
Test name
Test status
Simulation time 178230225111 ps
CPU time 492.68 seconds
Started Jan 14 01:09:33 PM PST 24
Finished Jan 14 01:17:47 PM PST 24
Peak memory 197640 kb
Host smart-192be809-a776-467d-9127-7ee497e694d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448514479 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.448514479
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3641672653
Short name T104
Test name
Test status
Simulation time 499488203 ps
CPU time 0.98 seconds
Started Jan 14 01:09:43 PM PST 24
Finished Jan 14 01:09:45 PM PST 24
Peak memory 182700 kb
Host smart-5792d38c-cf84-4c7f-bc09-08d3ac6e80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641672653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3641672653
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.162435024
Short name T199
Test name
Test status
Simulation time 19604596328 ps
CPU time 33.31 seconds
Started Jan 14 01:09:31 PM PST 24
Finished Jan 14 01:10:05 PM PST 24
Peak memory 182664 kb
Host smart-c6b734d2-4564-462b-b50c-7eab199067cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162435024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.162435024
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.4138687654
Short name T129
Test name
Test status
Simulation time 506590491 ps
CPU time 0.65 seconds
Started Jan 14 01:09:35 PM PST 24
Finished Jan 14 01:09:37 PM PST 24
Peak memory 182540 kb
Host smart-032b3875-a746-4e30-846d-29c93d95bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138687654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.4138687654
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.3952064907
Short name T254
Test name
Test status
Simulation time 68989151351 ps
CPU time 106.87 seconds
Started Jan 14 01:09:34 PM PST 24
Finished Jan 14 01:11:22 PM PST 24
Peak memory 182740 kb
Host smart-450b7eef-776d-40d8-9c84-4c45becaad57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952064907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.3952064907
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1586674852
Short name T270
Test name
Test status
Simulation time 56470293547 ps
CPU time 453.71 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:17:11 PM PST 24
Peak memory 197616 kb
Host smart-7a2ac48c-d945-41d6-a06a-18b01c82db7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586674852 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1586674852
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.1261104851
Short name T247
Test name
Test status
Simulation time 549581189 ps
CPU time 0.77 seconds
Started Jan 14 01:09:45 PM PST 24
Finished Jan 14 01:09:53 PM PST 24
Peak memory 182600 kb
Host smart-8d01dd08-dcb2-4b8e-9854-8e948dcfdb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261104851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.1261104851
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1003201871
Short name T276
Test name
Test status
Simulation time 37851249431 ps
CPU time 29.66 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:10:07 PM PST 24
Peak memory 182720 kb
Host smart-3aeb2113-1c80-4872-9020-0c6b7f4addf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003201871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1003201871
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1536654854
Short name T238
Test name
Test status
Simulation time 394683458 ps
CPU time 1.12 seconds
Started Jan 14 01:09:36 PM PST 24
Finished Jan 14 01:09:37 PM PST 24
Peak memory 182540 kb
Host smart-43c0c401-eda1-42cd-a838-ebd6e25c8d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536654854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1536654854
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.4239349531
Short name T290
Test name
Test status
Simulation time 187932413937 ps
CPU time 76.35 seconds
Started Jan 14 01:09:35 PM PST 24
Finished Jan 14 01:10:52 PM PST 24
Peak memory 182688 kb
Host smart-caa6c891-957f-46d7-bccc-8a2dc3e3402e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239349531 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.4239349531
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.95893913
Short name T102
Test name
Test status
Simulation time 36746547654 ps
CPU time 197.27 seconds
Started Jan 14 01:09:37 PM PST 24
Finished Jan 14 01:12:55 PM PST 24
Peak memory 197656 kb
Host smart-26b0cf64-119c-4af6-9dc8-4ada63288b69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95893913 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.95893913
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2117765208
Short name T141
Test name
Test status
Simulation time 447770588 ps
CPU time 0.76 seconds
Started Jan 14 01:08:46 PM PST 24
Finished Jan 14 01:08:47 PM PST 24
Peak memory 182600 kb
Host smart-ddc618ea-6754-4711-b94d-216bf276f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117765208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2117765208
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2914007454
Short name T255
Test name
Test status
Simulation time 7698714156 ps
CPU time 12.68 seconds
Started Jan 14 01:08:49 PM PST 24
Finished Jan 14 01:09:02 PM PST 24
Peak memory 182728 kb
Host smart-df6426a3-2601-4d9c-badb-4dcc9cacc2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914007454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2914007454
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.797266504
Short name T287
Test name
Test status
Simulation time 561990588 ps
CPU time 0.97 seconds
Started Jan 14 01:08:49 PM PST 24
Finished Jan 14 01:08:50 PM PST 24
Peak memory 182696 kb
Host smart-b61ed6f2-62b8-4e45-b539-201428957f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797266504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.797266504
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3630394855
Short name T273
Test name
Test status
Simulation time 245481721473 ps
CPU time 72.78 seconds
Started Jan 14 01:08:45 PM PST 24
Finished Jan 14 01:09:58 PM PST 24
Peak memory 182660 kb
Host smart-5046fda4-e6c0-4200-85b1-6d3b503fc291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630394855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3630394855
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2452272219
Short name T298
Test name
Test status
Simulation time 53534529108 ps
CPU time 542.92 seconds
Started Jan 14 01:08:46 PM PST 24
Finished Jan 14 01:17:50 PM PST 24
Peak memory 197556 kb
Host smart-1e80dcb9-e859-4818-9a44-20b2521c0c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452272219 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2452272219
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4077171877
Short name T224
Test name
Test status
Simulation time 508630910 ps
CPU time 0.85 seconds
Started Jan 14 01:08:49 PM PST 24
Finished Jan 14 01:08:50 PM PST 24
Peak memory 182704 kb
Host smart-7c0d67e2-938d-4f3b-b6c6-d9ee9a5994cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077171877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4077171877
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.741778712
Short name T200
Test name
Test status
Simulation time 20460767801 ps
CPU time 6.89 seconds
Started Jan 14 01:08:41 PM PST 24
Finished Jan 14 01:08:49 PM PST 24
Peak memory 182728 kb
Host smart-bbd937d2-c55f-4a70-93d5-bd5486046e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741778712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.741778712
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.897493282
Short name T133
Test name
Test status
Simulation time 470462636 ps
CPU time 1.35 seconds
Started Jan 14 01:08:46 PM PST 24
Finished Jan 14 01:08:48 PM PST 24
Peak memory 182492 kb
Host smart-4d4a32cc-b78f-4ed3-800a-c37b3c4c7ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897493282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.897493282
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1962038011
Short name T256
Test name
Test status
Simulation time 169009622700 ps
CPU time 33.59 seconds
Started Jan 14 01:08:48 PM PST 24
Finished Jan 14 01:09:22 PM PST 24
Peak memory 192800 kb
Host smart-dd67169d-65ac-4889-a6f4-817313974911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962038011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1962038011
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3854766457
Short name T96
Test name
Test status
Simulation time 20005721164 ps
CPU time 138.91 seconds
Started Jan 14 01:08:47 PM PST 24
Finished Jan 14 01:11:06 PM PST 24
Peak memory 197572 kb
Host smart-6a82568b-84a3-493b-999b-86ae45a44f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854766457 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3854766457
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3141011987
Short name T161
Test name
Test status
Simulation time 605329742 ps
CPU time 0.76 seconds
Started Jan 14 01:08:40 PM PST 24
Finished Jan 14 01:08:41 PM PST 24
Peak memory 182696 kb
Host smart-d8079e84-034e-4f71-b5dd-b0c5f7ddb4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141011987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3141011987
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1789889768
Short name T184
Test name
Test status
Simulation time 18204604911 ps
CPU time 12.17 seconds
Started Jan 14 01:08:43 PM PST 24
Finished Jan 14 01:08:55 PM PST 24
Peak memory 182708 kb
Host smart-e267cc8c-eee6-4a83-9d2b-b9244dd0e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789889768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1789889768
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1218709346
Short name T177
Test name
Test status
Simulation time 453698807 ps
CPU time 0.91 seconds
Started Jan 14 01:08:48 PM PST 24
Finished Jan 14 01:08:50 PM PST 24
Peak memory 182564 kb
Host smart-d58a084b-53bb-400a-8b9d-f23399e64aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218709346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1218709346
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3727892938
Short name T28
Test name
Test status
Simulation time 182940259164 ps
CPU time 65.64 seconds
Started Jan 14 01:08:45 PM PST 24
Finished Jan 14 01:09:51 PM PST 24
Peak memory 182716 kb
Host smart-d8b0570e-13aa-46db-b4d9-e282324c6de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727892938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3727892938
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.630060124
Short name T50
Test name
Test status
Simulation time 23974202454 ps
CPU time 222.35 seconds
Started Jan 14 01:08:43 PM PST 24
Finished Jan 14 01:12:26 PM PST 24
Peak memory 197632 kb
Host smart-47e62593-4e3e-44dc-b43d-eaa85f836f26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630060124 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.630060124
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1137586879
Short name T299
Test name
Test status
Simulation time 464492815 ps
CPU time 0.72 seconds
Started Jan 14 01:09:04 PM PST 24
Finished Jan 14 01:09:05 PM PST 24
Peak memory 182676 kb
Host smart-e89cf01a-072c-4e11-bea9-d5455190be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137586879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1137586879
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3612752144
Short name T201
Test name
Test status
Simulation time 21182768156 ps
CPU time 35.26 seconds
Started Jan 14 01:08:45 PM PST 24
Finished Jan 14 01:09:21 PM PST 24
Peak memory 182692 kb
Host smart-c25a06cb-b7d0-4753-adc9-ae68752aa16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612752144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3612752144
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.158224032
Short name T156
Test name
Test status
Simulation time 484561066 ps
CPU time 0.77 seconds
Started Jan 14 01:08:46 PM PST 24
Finished Jan 14 01:08:47 PM PST 24
Peak memory 182640 kb
Host smart-1951ca53-441e-4de7-b69f-aa4a86b13166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158224032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.158224032
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.803210859
Short name T110
Test name
Test status
Simulation time 59363895426 ps
CPU time 22.44 seconds
Started Jan 14 01:09:02 PM PST 24
Finished Jan 14 01:09:25 PM PST 24
Peak memory 182804 kb
Host smart-429ec7c5-8ba7-4505-84f7-90a40d15abc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803210859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.803210859
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1816911205
Short name T283
Test name
Test status
Simulation time 47606167540 ps
CPU time 474.41 seconds
Started Jan 14 01:09:00 PM PST 24
Finished Jan 14 01:16:55 PM PST 24
Peak memory 197672 kb
Host smart-c74193ae-68ce-4c86-9c5a-24a432186884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816911205 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1816911205
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3750132066
Short name T167
Test name
Test status
Simulation time 536355596 ps
CPU time 0.78 seconds
Started Jan 14 01:09:08 PM PST 24
Finished Jan 14 01:09:09 PM PST 24
Peak memory 182636 kb
Host smart-d0f4c831-d9ec-4f7d-b4de-ef2d8518b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750132066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3750132066
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3726812106
Short name T232
Test name
Test status
Simulation time 476371852 ps
CPU time 0.76 seconds
Started Jan 14 01:08:58 PM PST 24
Finished Jan 14 01:08:59 PM PST 24
Peak memory 182528 kb
Host smart-d621574d-607b-47ce-bca5-f63dd3c3c591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726812106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3726812106
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1143785441
Short name T195
Test name
Test status
Simulation time 339729041386 ps
CPU time 266.49 seconds
Started Jan 14 01:09:01 PM PST 24
Finished Jan 14 01:13:28 PM PST 24
Peak memory 192824 kb
Host smart-9613565e-4734-4546-8f4d-d83296bf818c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143785441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1143785441
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3480378944
Short name T263
Test name
Test status
Simulation time 39887345015 ps
CPU time 185.23 seconds
Started Jan 14 01:09:03 PM PST 24
Finished Jan 14 01:12:09 PM PST 24
Peak memory 197592 kb
Host smart-67ce5234-f7e3-419e-a0aa-603bf62d85ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480378944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3480378944
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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