Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 30597 1 T15 120 T17 131 T18 11
bark[1] 599 1 T16 12 T46 16 T86 31
bark[2] 328 1 T87 12 T46 16 T88 66
bark[3] 711 1 T15 36 T44 22 T89 16
bark[4] 499 1 T54 156 T80 27 T76 254
bark[5] 318 1 T20 16 T90 172 T91 12
bark[6] 584 1 T20 16 T89 259 T34 12
bark[7] 481 1 T17 26 T46 16 T92 12
bark[8] 243 1 T40 16 T93 16 T94 16
bark[9] 131 1 T95 16 T96 17 T97 34
bark[10] 744 1 T25 16 T48 17 T54 193
bark[11] 380 1 T36 16 T98 17 T99 12
bark[12] 428 1 T44 23 T54 51 T76 78
bark[13] 773 1 T26 12 T20 16 T100 12
bark[14] 400 1 T46 30 T48 17 T36 41
bark[15] 279 1 T92 17 T101 47 T102 12
bark[16] 343 1 T25 17 T44 13 T86 22
bark[17] 384 1 T19 16 T20 16 T36 12
bark[18] 445 1 T19 16 T53 12 T44 17
bark[19] 734 1 T54 103 T103 16 T101 44
bark[20] 244 1 T46 16 T89 17 T104 21
bark[21] 767 1 T25 23 T45 16 T48 59
bark[22] 517 1 T103 47 T105 12 T106 30
bark[23] 220 1 T15 63 T77 26 T101 21
bark[24] 420 1 T17 26 T93 52 T107 17
bark[25] 358 1 T108 12 T92 32 T89 22
bark[26] 368 1 T45 16 T109 12 T110 12
bark[27] 232 1 T90 90 T111 16 T112 30
bark[28] 513 1 T113 34 T114 36 T101 90
bark[29] 786 1 T19 16 T48 57 T92 16
bark[30] 134 1 T20 49 T115 22 T116 12
bark[31] 608 1 T14 12 T20 56 T54 16
bark_0 3543 1 T12 6 T21 6 T22 5


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 30612 1 T15 117 T17 130 T18 10
bite[1] 342 1 T20 56 T44 16 T80 26
bite[2] 323 1 T16 11 T34 11 T90 16
bite[3] 722 1 T20 32 T25 23 T37 12
bite[4] 760 1 T103 47 T89 16 T36 41
bite[5] 405 1 T44 17 T89 103 T115 22
bite[6] 314 1 T44 12 T104 16 T76 213
bite[7] 477 1 T103 16 T86 21 T88 16
bite[8] 442 1 T115 26 T102 16 T112 57
bite[9] 821 1 T45 16 T117 11 T76 253
bite[10] 435 1 T44 23 T87 11 T48 16
bite[11] 451 1 T19 16 T25 17 T107 33
bite[12] 602 1 T20 49 T105 11 T90 166
bite[13] 468 1 T46 16 T93 26 T107 38
bite[14] 496 1 T20 16 T48 56 T54 43
bite[15] 291 1 T14 11 T19 16 T54 50
bite[16] 377 1 T46 30 T48 163 T93 52
bite[17] 266 1 T44 22 T93 16 T118 42
bite[18] 559 1 T92 11 T103 17 T98 406
bite[19] 402 1 T17 26 T113 17 T99 11
bite[20] 219 1 T46 16 T48 58 T101 68
bite[21] 429 1 T15 36 T19 16 T48 17
bite[22] 430 1 T15 62 T108 11 T54 58
bite[23] 593 1 T89 258 T76 64 T93 16
bite[24] 138 1 T25 16 T92 32 T86 16
bite[25] 426 1 T17 26 T46 16 T54 16
bite[26] 173 1 T46 16 T93 16 T101 16
bite[27] 844 1 T100 11 T89 176 T113 21
bite[28] 158 1 T53 11 T104 21 T81 27
bite[29] 147 1 T45 16 T48 17 T36 11
bite[30] 768 1 T26 11 T54 155 T92 33
bite[31] 174 1 T20 16 T89 22 T119 12
bite_0 4047 1 T12 6 T21 6 T22 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 48111 1 T12 6 T21 6 T22 5


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1135 1 T46 18 T48 228 T103 18
prescale[1] 915 1 T20 15 T42 8 T54 8
prescale[2] 998 1 T25 102 T120 8 T89 67
prescale[3] 875 1 T25 37 T121 8 T54 15
prescale[4] 592 1 T17 22 T54 15 T89 24
prescale[5] 672 1 T20 18 T54 37 T104 39
prescale[6] 918 1 T54 37 T89 30 T36 15
prescale[7] 1065 1 T122 8 T54 51 T89 71
prescale[8] 754 1 T19 15 T48 144 T54 129
prescale[9] 649 1 T54 23 T76 2 T90 70
prescale[10] 595 1 T25 36 T54 2 T103 57
prescale[11] 854 1 T25 15 T46 18 T123 8
prescale[12] 1103 1 T25 15 T50 8 T54 112
prescale[13] 913 1 T25 15 T45 8 T54 24
prescale[14] 739 1 T25 64 T36 15 T113 37
prescale[15] 843 1 T17 24 T18 8 T19 28
prescale[16] 580 1 T25 75 T92 66 T80 2
prescale[17] 874 1 T19 21 T44 25 T54 55
prescale[18] 584 1 T25 15 T36 58 T88 15
prescale[19] 835 1 T113 24 T124 8 T76 66
prescale[20] 721 1 T19 15 T48 2 T54 47
prescale[21] 816 1 T20 21 T45 31 T125 8
prescale[22] 775 1 T20 15 T25 77 T126 8
prescale[23] 637 1 T15 2 T89 109 T90 25
prescale[24] 776 1 T20 15 T25 53 T44 20
prescale[25] 587 1 T15 2 T17 30 T19 18
prescale[26] 812 1 T45 15 T46 15 T54 88
prescale[27] 970 1 T15 2 T48 2 T54 30
prescale[28] 903 1 T15 20 T27 8 T25 55
prescale[29] 751 1 T17 44 T46 15 T54 18
prescale[30] 907 1 T15 18 T20 18 T92 32
prescale[31] 826 1 T127 8 T86 44 T89 49
prescale_0 22137 1 T12 6 T21 6 T22 5


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36964 1 T12 6 T21 6 T22 5
auto[1] 11147 1 T15 92 T17 47 T18 9


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 48111 1 T12 6 T21 6 T22 5


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 29190 1 T15 142 T17 106 T18 12
wkup[1] 561 1 T25 13 T48 16 T89 54
wkup[2] 633 1 T20 16 T89 13 T104 21
wkup[3] 677 1 T15 7 T20 16 T25 16
wkup[4] 505 1 T44 33 T45 16 T48 16
wkup[5] 545 1 T17 26 T92 16 T103 17
wkup[6] 524 1 T20 16 T46 16 T48 16
wkup[7] 381 1 T54 38 T86 16 T36 16
wkup[8] 581 1 T20 16 T48 16 T54 16
wkup[9] 343 1 T14 13 T19 16 T54 16
wkup[10] 286 1 T46 16 T92 17 T86 16
wkup[11] 553 1 T25 16 T87 13 T80 22
wkup[12] 628 1 T15 16 T17 26 T48 17
wkup[13] 446 1 T100 13 T54 22 T81 27
wkup[14] 301 1 T89 33 T76 16 T111 16
wkup[15] 469 1 T46 16 T54 16 T89 16
wkup[16] 653 1 T15 22 T25 16 T48 16
wkup[17] 418 1 T25 16 T44 22 T54 9
wkup[18] 620 1 T25 17 T45 16 T89 25
wkup[19] 477 1 T15 36 T48 32 T54 26
wkup[20] 439 1 T19 16 T53 13 T54 26
wkup[21] 420 1 T16 13 T25 32 T48 54
wkup[22] 619 1 T48 47 T54 48 T89 51
wkup[23] 515 1 T20 16 T44 23 T46 16
wkup[24] 545 1 T48 17 T54 22 T89 32
wkup[25] 732 1 T19 16 T25 39 T89 16
wkup[26] 585 1 T20 16 T48 22 T54 7
wkup[27] 524 1 T46 16 T54 22 T103 47
wkup[28] 427 1 T25 16 T48 17 T54 16
wkup[29] 471 1 T17 26 T45 16 T108 13
wkup[30] 472 1 T44 14 T86 16 T89 17
wkup[31] 585 1 T26 13 T25 26 T54 32
wkup_0 2986 1 T12 6 T21 6 T22 5

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