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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.31 100.00 99.35 100.00 96.90


Total test records in report: 426
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T271 /workspace/coverage/default/49.aon_timer_jump.2644426975 Jan 24 12:54:47 PM PST 24 Jan 24 12:54:56 PM PST 24 589957044 ps
T272 /workspace/coverage/default/6.aon_timer_jump.3868078919 Jan 24 01:22:10 PM PST 24 Jan 24 01:23:10 PM PST 24 604039623 ps
T273 /workspace/coverage/default/4.aon_timer_prescaler.953419089 Jan 24 12:52:38 PM PST 24 Jan 24 12:52:59 PM PST 24 27998469040 ps
T274 /workspace/coverage/default/13.aon_timer_stress_all.3484586359 Jan 24 12:53:16 PM PST 24 Jan 24 12:53:59 PM PST 24 100248316570 ps
T275 /workspace/coverage/default/7.aon_timer_prescaler.1832842399 Jan 24 12:57:20 PM PST 24 Jan 24 12:58:16 PM PST 24 18306916278 ps
T276 /workspace/coverage/default/21.aon_timer_jump.558080143 Jan 24 12:53:33 PM PST 24 Jan 24 12:53:52 PM PST 24 451382094 ps
T277 /workspace/coverage/default/11.aon_timer_jump.3224253654 Jan 24 12:53:16 PM PST 24 Jan 24 12:53:33 PM PST 24 643266302 ps
T278 /workspace/coverage/default/26.aon_timer_jump.2590094496 Jan 24 12:53:31 PM PST 24 Jan 24 12:53:50 PM PST 24 512702886 ps
T279 /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3242233523 Jan 24 12:52:49 PM PST 24 Jan 24 01:01:33 PM PST 24 118852605268 ps
T280 /workspace/coverage/default/0.aon_timer_stress_all.29909264 Jan 24 12:52:23 PM PST 24 Jan 24 12:56:23 PM PST 24 267290117365 ps
T281 /workspace/coverage/default/42.aon_timer_jump.3854758025 Jan 24 12:54:05 PM PST 24 Jan 24 12:54:19 PM PST 24 569455317 ps
T282 /workspace/coverage/default/18.aon_timer_prescaler.652604391 Jan 24 12:53:21 PM PST 24 Jan 24 12:53:42 PM PST 24 4997020605 ps
T283 /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1911747944 Jan 24 01:03:37 PM PST 24 Jan 24 01:06:20 PM PST 24 17344146570 ps
T284 /workspace/coverage/default/32.aon_timer_smoke.1034884894 Jan 24 12:53:40 PM PST 24 Jan 24 12:54:00 PM PST 24 509777337 ps
T285 /workspace/coverage/default/8.aon_timer_stress_all.1904466133 Jan 24 12:52:56 PM PST 24 Jan 24 12:54:35 PM PST 24 118021734275 ps
T286 /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1060056915 Jan 24 12:52:37 PM PST 24 Jan 24 12:56:53 PM PST 24 141641754436 ps
T287 /workspace/coverage/default/19.aon_timer_stress_all.136987040 Jan 24 12:53:30 PM PST 24 Jan 24 01:02:38 PM PST 24 381089022549 ps
T288 /workspace/coverage/default/2.aon_timer_prescaler.1288346215 Jan 24 12:52:35 PM PST 24 Jan 24 12:52:55 PM PST 24 17820329432 ps
T289 /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2301080651 Jan 24 12:53:12 PM PST 24 Jan 24 01:01:18 PM PST 24 59736905180 ps
T290 /workspace/coverage/default/32.aon_timer_jump.2911095347 Jan 24 12:53:40 PM PST 24 Jan 24 12:54:01 PM PST 24 562144549 ps
T291 /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3113729182 Jan 24 12:53:31 PM PST 24 Jan 24 12:58:23 PM PST 24 25960885957 ps
T292 /workspace/coverage/default/36.aon_timer_smoke.3944801167 Jan 24 01:38:59 PM PST 24 Jan 24 01:39:07 PM PST 24 592525903 ps
T293 /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2687225195 Jan 24 12:53:13 PM PST 24 Jan 24 12:55:49 PM PST 24 20018845191 ps
T294 /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.690068626 Jan 24 12:53:24 PM PST 24 Jan 24 12:56:15 PM PST 24 13538180473 ps
T295 /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1403246383 Jan 24 01:12:21 PM PST 24 Jan 24 01:26:07 PM PST 24 443748048647 ps
T296 /workspace/coverage/default/40.aon_timer_smoke.1945774918 Jan 24 12:53:58 PM PST 24 Jan 24 12:54:15 PM PST 24 571472064 ps
T297 /workspace/coverage/default/43.aon_timer_jump.3095358608 Jan 24 12:54:28 PM PST 24 Jan 24 12:54:38 PM PST 24 567869079 ps
T298 /workspace/coverage/default/15.aon_timer_jump.2671099545 Jan 24 12:53:20 PM PST 24 Jan 24 12:53:38 PM PST 24 371812123 ps
T299 /workspace/coverage/default/43.aon_timer_smoke.2156092603 Jan 24 12:54:34 PM PST 24 Jan 24 12:54:43 PM PST 24 529961686 ps
T300 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3471872987 Jan 24 12:48:11 PM PST 24 Jan 24 12:48:14 PM PST 24 346458148 ps
T301 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3269105141 Jan 24 12:48:47 PM PST 24 Jan 24 12:49:29 PM PST 24 691600046 ps
T83 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3417696406 Jan 24 12:48:46 PM PST 24 Jan 24 12:49:34 PM PST 24 4101894748 ps
T59 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2674198237 Jan 24 12:48:23 PM PST 24 Jan 24 12:48:57 PM PST 24 423513359 ps
T302 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2825975338 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 344443272 ps
T303 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3563777783 Jan 24 12:53:12 PM PST 24 Jan 24 12:53:24 PM PST 24 494889195 ps
T304 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.807737273 Jan 24 12:48:14 PM PST 24 Jan 24 12:48:20 PM PST 24 285825751 ps
T71 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2661412684 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 441479301 ps
T60 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2456598340 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 364244607 ps
T305 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.601074900 Jan 24 12:55:49 PM PST 24 Jan 24 12:56:26 PM PST 24 443274140 ps
T306 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3621014228 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 438526613 ps
T72 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2188970729 Jan 24 01:08:10 PM PST 24 Jan 24 01:08:50 PM PST 24 330824134 ps
T61 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3987532449 Jan 24 12:48:20 PM PST 24 Jan 24 12:48:46 PM PST 24 385701132 ps
T307 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1914933624 Jan 24 12:48:29 PM PST 24 Jan 24 12:49:13 PM PST 24 8836306950 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2082374018 Jan 24 12:48:32 PM PST 24 Jan 24 12:49:03 PM PST 24 545257955 ps
T73 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1802022173 Jan 24 12:48:27 PM PST 24 Jan 24 12:49:00 PM PST 24 1611564615 ps
T308 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.739562589 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:44 PM PST 24 517008006 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1314730941 Jan 24 12:48:16 PM PST 24 Jan 24 12:48:34 PM PST 24 5331843148 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3121564273 Jan 24 12:48:27 PM PST 24 Jan 24 12:48:58 PM PST 24 504534914 ps
T311 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1005274518 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:29 PM PST 24 400618892 ps
T312 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1968720656 Jan 24 12:55:47 PM PST 24 Jan 24 12:56:22 PM PST 24 338513965 ps
T74 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4151451276 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:16 PM PST 24 1797793793 ps
T313 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4104819745 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:57 PM PST 24 611285782 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1503220766 Jan 24 12:48:46 PM PST 24 Jan 24 12:49:26 PM PST 24 353997052 ps
T315 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.33222666 Jan 24 01:23:09 PM PST 24 Jan 24 01:24:00 PM PST 24 370021819 ps
T316 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.827421162 Jan 24 12:49:23 PM PST 24 Jan 24 12:49:49 PM PST 24 490265494 ps
T317 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.622180930 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 388904935 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2315288420 Jan 24 12:48:20 PM PST 24 Jan 24 12:48:46 PM PST 24 510184673 ps
T319 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3875935828 Jan 24 12:48:20 PM PST 24 Jan 24 12:48:46 PM PST 24 332845893 ps
T320 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.702946626 Jan 24 12:48:18 PM PST 24 Jan 24 12:48:39 PM PST 24 1027770139 ps
T75 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.413489811 Jan 24 12:48:32 PM PST 24 Jan 24 12:49:03 PM PST 24 1818614055 ps
T321 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3353249948 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:30 PM PST 24 630620613 ps
T322 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2031428853 Jan 24 02:24:30 PM PST 24 Jan 24 02:24:38 PM PST 24 496572278 ps
T323 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.926357458 Jan 24 12:49:14 PM PST 24 Jan 24 12:49:46 PM PST 24 304745546 ps
T324 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.233670287 Jan 24 12:48:38 PM PST 24 Jan 24 12:49:15 PM PST 24 438989426 ps
T325 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2182908187 Jan 24 12:48:42 PM PST 24 Jan 24 12:49:19 PM PST 24 503218179 ps
T326 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2223869898 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:43 PM PST 24 485227541 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3364659213 Jan 24 12:48:25 PM PST 24 Jan 24 12:48:58 PM PST 24 366913410 ps
T328 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4027144589 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:59 PM PST 24 1161222607 ps
T329 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1479107001 Jan 24 12:48:13 PM PST 24 Jan 24 12:48:19 PM PST 24 400990644 ps
T330 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2567444684 Jan 24 12:48:42 PM PST 24 Jan 24 12:49:21 PM PST 24 493562235 ps
T331 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.413514981 Jan 24 12:48:53 PM PST 24 Jan 24 12:49:36 PM PST 24 4126620277 ps
T63 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2970877419 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 566823408 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1211270438 Jan 24 12:48:25 PM PST 24 Jan 24 12:48:57 PM PST 24 604676479 ps
T333 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1439106852 Jan 24 12:48:18 PM PST 24 Jan 24 12:48:38 PM PST 24 642027049 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3656542833 Jan 24 12:48:24 PM PST 24 Jan 24 12:48:57 PM PST 24 329206133 ps
T335 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2743367483 Jan 24 01:03:03 PM PST 24 Jan 24 01:03:23 PM PST 24 561503015 ps
T336 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.46022440 Jan 24 12:48:14 PM PST 24 Jan 24 12:48:21 PM PST 24 487522628 ps
T337 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4014690547 Jan 24 12:48:25 PM PST 24 Jan 24 12:48:57 PM PST 24 384397324 ps
T338 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.449738633 Jan 24 12:48:54 PM PST 24 Jan 24 12:49:35 PM PST 24 277349904 ps
T339 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4094012805 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:57 PM PST 24 469405871 ps
T340 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3224723828 Jan 24 12:48:31 PM PST 24 Jan 24 12:49:01 PM PST 24 294060371 ps
T341 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2216910691 Jan 24 12:48:56 PM PST 24 Jan 24 12:49:36 PM PST 24 356884399 ps
T342 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1047707789 Jan 24 12:48:43 PM PST 24 Jan 24 12:49:23 PM PST 24 708101523 ps
T64 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2100761524 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:29 PM PST 24 470940998 ps
T343 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.581890323 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 503576011 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2602548009 Jan 24 12:48:13 PM PST 24 Jan 24 12:48:26 PM PST 24 5828831364 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4108759117 Jan 24 12:48:25 PM PST 24 Jan 24 12:48:58 PM PST 24 1213415655 ps
T345 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2094572882 Jan 24 12:48:46 PM PST 24 Jan 24 12:49:27 PM PST 24 483671934 ps
T346 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3501241821 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:30 PM PST 24 583259083 ps
T347 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.493728720 Jan 24 12:52:21 PM PST 24 Jan 24 12:52:40 PM PST 24 2898978194 ps
T348 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3842707341 Jan 24 12:48:43 PM PST 24 Jan 24 12:49:25 PM PST 24 4474180469 ps
T66 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2891614167 Jan 24 12:48:20 PM PST 24 Jan 24 12:48:48 PM PST 24 1299393569 ps
T349 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1865260337 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:43 PM PST 24 322156112 ps
T350 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1781668599 Jan 24 12:53:06 PM PST 24 Jan 24 12:53:14 PM PST 24 534164119 ps
T351 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1652084436 Jan 24 12:48:16 PM PST 24 Jan 24 12:48:35 PM PST 24 427323867 ps
T352 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1402013509 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:58 PM PST 24 704194502 ps
T84 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.92357756 Jan 24 12:48:20 PM PST 24 Jan 24 12:48:47 PM PST 24 8796838050 ps
T353 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3873239321 Jan 24 12:48:31 PM PST 24 Jan 24 12:49:01 PM PST 24 580207684 ps
T354 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3440889325 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:43 PM PST 24 569332071 ps
T355 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.889283209 Jan 24 12:48:29 PM PST 24 Jan 24 12:48:59 PM PST 24 655276296 ps
T356 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.76055778 Jan 24 12:48:30 PM PST 24 Jan 24 12:49:07 PM PST 24 4528980194 ps
T357 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1549471420 Jan 24 12:49:20 PM PST 24 Jan 24 12:49:47 PM PST 24 502896035 ps
T85 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2378012088 Jan 24 12:48:26 PM PST 24 Jan 24 12:49:00 PM PST 24 8519062913 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4078121969 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:57 PM PST 24 333540340 ps
T358 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3284720522 Jan 24 12:49:20 PM PST 24 Jan 24 12:49:48 PM PST 24 476129328 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.227248550 Jan 24 12:48:33 PM PST 24 Jan 24 12:49:03 PM PST 24 466514694 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2799697215 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:31 PM PST 24 4378049823 ps
T361 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2817239897 Jan 24 12:48:29 PM PST 24 Jan 24 12:49:00 PM PST 24 448177366 ps
T68 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1269282009 Jan 24 12:48:26 PM PST 24 Jan 24 12:48:58 PM PST 24 319039602 ps
T362 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1878335960 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 1039138386 ps
T363 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.384742830 Jan 24 12:55:25 PM PST 24 Jan 24 12:56:03 PM PST 24 4416822783 ps
T364 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1608170921 Jan 24 12:48:47 PM PST 24 Jan 24 12:49:27 PM PST 24 352492743 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1053239085 Jan 24 12:48:16 PM PST 24 Jan 24 12:48:32 PM PST 24 341112240 ps
T365 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.790033804 Jan 24 01:26:27 PM PST 24 Jan 24 01:27:24 PM PST 24 423299600 ps
T366 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4106272571 Jan 24 12:48:57 PM PST 24 Jan 24 12:49:37 PM PST 24 270678767 ps
T367 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.883377344 Jan 24 12:48:32 PM PST 24 Jan 24 12:49:05 PM PST 24 6056110958 ps
T368 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.377706163 Jan 24 12:48:51 PM PST 24 Jan 24 12:49:34 PM PST 24 640092124 ps
T369 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3515321202 Jan 24 12:48:43 PM PST 24 Jan 24 12:49:24 PM PST 24 2591881807 ps
T70 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1861569688 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:34 PM PST 24 443849999 ps
T370 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.108109167 Jan 24 12:48:33 PM PST 24 Jan 24 12:49:03 PM PST 24 407497529 ps
T371 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1430539660 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:17 PM PST 24 531822556 ps
T372 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2137508780 Jan 24 12:48:18 PM PST 24 Jan 24 12:48:39 PM PST 24 608871502 ps
T373 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.917609313 Jan 24 12:48:32 PM PST 24 Jan 24 12:49:02 PM PST 24 1004196873 ps
T374 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3072096550 Jan 24 12:48:27 PM PST 24 Jan 24 12:48:59 PM PST 24 1554114746 ps
T375 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2105685468 Jan 24 12:48:44 PM PST 24 Jan 24 12:49:23 PM PST 24 291031584 ps
T376 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2425369508 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:30 PM PST 24 472680294 ps
T377 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.244270607 Jan 24 12:48:54 PM PST 24 Jan 24 12:49:36 PM PST 24 500286913 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1113698382 Jan 24 12:48:23 PM PST 24 Jan 24 12:48:55 PM PST 24 4706609272 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1696685974 Jan 24 12:48:31 PM PST 24 Jan 24 12:49:01 PM PST 24 470361147 ps
T380 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.683725024 Jan 24 12:48:13 PM PST 24 Jan 24 12:48:21 PM PST 24 1706481693 ps
T381 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2795321471 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 573519448 ps
T382 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3376621316 Jan 24 12:48:53 PM PST 24 Jan 24 12:49:35 PM PST 24 506918354 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1004872660 Jan 24 12:48:33 PM PST 24 Jan 24 12:49:04 PM PST 24 507609398 ps
T384 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1526346921 Jan 24 12:48:29 PM PST 24 Jan 24 12:49:00 PM PST 24 424050589 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3741079994 Jan 24 12:48:26 PM PST 24 Jan 24 12:49:00 PM PST 24 1182118709 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.599645821 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:16 PM PST 24 566602883 ps
T387 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1193017030 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 516825957 ps
T388 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3650587491 Jan 24 01:03:38 PM PST 24 Jan 24 01:04:17 PM PST 24 4502711819 ps
T389 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.395322712 Jan 24 12:49:07 PM PST 24 Jan 24 12:49:42 PM PST 24 396913123 ps
T390 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2105173095 Jan 24 12:48:46 PM PST 24 Jan 24 12:49:28 PM PST 24 527681886 ps
T391 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.549970325 Jan 24 12:48:31 PM PST 24 Jan 24 12:49:02 PM PST 24 468857843 ps
T392 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2683200374 Jan 24 12:48:43 PM PST 24 Jan 24 12:49:22 PM PST 24 521165742 ps
T393 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.173989615 Jan 24 12:48:11 PM PST 24 Jan 24 12:48:19 PM PST 24 1726638534 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3071541689 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:29 PM PST 24 426455807 ps
T395 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2794670754 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:30 PM PST 24 602249213 ps
T396 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1816492192 Jan 24 12:48:48 PM PST 24 Jan 24 12:49:38 PM PST 24 7775581983 ps
T397 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1151788178 Jan 24 12:59:01 PM PST 24 Jan 24 12:59:27 PM PST 24 441077029 ps
T398 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1505902352 Jan 24 12:48:56 PM PST 24 Jan 24 12:49:42 PM PST 24 2068339608 ps
T399 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3891926877 Jan 24 12:49:09 PM PST 24 Jan 24 12:49:43 PM PST 24 464576206 ps
T400 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3601991819 Jan 24 12:48:25 PM PST 24 Jan 24 12:48:58 PM PST 24 434341389 ps
T401 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.393825400 Jan 24 12:48:29 PM PST 24 Jan 24 12:49:00 PM PST 24 1669131762 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4087162215 Jan 24 12:48:22 PM PST 24 Jan 24 12:49:19 PM PST 24 10690929062 ps
T403 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3487687645 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:43 PM PST 24 337809728 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.52914888 Jan 24 12:48:32 PM PST 24 Jan 24 12:49:02 PM PST 24 336985368 ps
T405 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3709565897 Jan 24 12:48:33 PM PST 24 Jan 24 12:49:06 PM PST 24 1612082321 ps
T406 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.646323565 Jan 24 12:48:16 PM PST 24 Jan 24 12:48:32 PM PST 24 436474359 ps
T407 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3231219949 Jan 24 03:19:31 PM PST 24 Jan 24 03:19:49 PM PST 24 418283976 ps
T408 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3260290439 Jan 24 12:49:10 PM PST 24 Jan 24 12:49:43 PM PST 24 513119678 ps
T409 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1827280702 Jan 24 12:48:27 PM PST 24 Jan 24 12:49:00 PM PST 24 544042784 ps
T410 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1694086562 Jan 24 12:49:05 PM PST 24 Jan 24 12:49:41 PM PST 24 348958938 ps
T411 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3916228716 Jan 24 12:48:14 PM PST 24 Jan 24 12:48:21 PM PST 24 384732145 ps
T412 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2693899734 Jan 24 12:48:54 PM PST 24 Jan 24 12:49:36 PM PST 24 980835474 ps
T413 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3395355213 Jan 24 01:31:03 PM PST 24 Jan 24 01:31:55 PM PST 24 1341792644 ps
T414 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1358019165 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:35 PM PST 24 2069625581 ps
T415 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3092212830 Jan 24 12:48:49 PM PST 24 Jan 24 12:49:37 PM PST 24 4505629925 ps
T416 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1355206221 Jan 24 12:48:12 PM PST 24 Jan 24 12:48:15 PM PST 24 525656366 ps
T417 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4126646059 Jan 24 01:12:34 PM PST 24 Jan 24 01:13:27 PM PST 24 388302940 ps
T418 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.411201100 Jan 24 12:48:57 PM PST 24 Jan 24 12:49:37 PM PST 24 280493587 ps
T419 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.964728134 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:16 PM PST 24 751337015 ps
T420 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3264007376 Jan 24 12:48:52 PM PST 24 Jan 24 12:49:40 PM PST 24 4509439364 ps
T421 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1729213578 Jan 24 01:28:45 PM PST 24 Jan 24 01:29:08 PM PST 24 388889633 ps
T422 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.314246174 Jan 24 12:48:38 PM PST 24 Jan 24 12:49:14 PM PST 24 511701181 ps
T423 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1005748480 Jan 24 12:48:46 PM PST 24 Jan 24 12:49:28 PM PST 24 1632243126 ps
T424 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.815527078 Jan 24 12:48:23 PM PST 24 Jan 24 12:48:55 PM PST 24 6028444333 ps
T425 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1192581953 Jan 24 12:48:47 PM PST 24 Jan 24 12:49:27 PM PST 24 355256004 ps
T426 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.128152758 Jan 24 12:48:39 PM PST 24 Jan 24 12:49:15 PM PST 24 1382220304 ps

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.652061212
Short name T1
Test name
Test status
Simulation time 8454267105 ps
CPU time 13.92 seconds
Started Jan 24 12:48:38 PM PST 24
Finished Jan 24 12:49:28 PM PST 24
Peak memory 197028 kb
Host smart-888a3b1e-6460-4182-83f1-d40c2ddee051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652061212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.652061212
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2841910651
Short name T15
Test name
Test status
Simulation time 108373323206 ps
CPU time 314.33 seconds
Started Jan 24 12:53:37 PM PST 24
Finished Jan 24 12:59:11 PM PST 24
Peak memory 206144 kb
Host smart-c0c15ba2-3f86-4eb0-a0d4-89ad5a3abdfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841910651 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2841910651
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.42173568
Short name T89
Test name
Test status
Simulation time 375957988741 ps
CPU time 724.34 seconds
Started Jan 24 01:02:15 PM PST 24
Finished Jan 24 01:14:21 PM PST 24
Peak memory 208588 kb
Host smart-1724af1b-ff1e-4d1b-a325-7f545c29e2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42173568 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.42173568
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1380958546
Short name T48
Test name
Test status
Simulation time 89842111981 ps
CPU time 175.78 seconds
Started Jan 24 12:53:14 PM PST 24
Finished Jan 24 12:56:22 PM PST 24
Peak memory 197804 kb
Host smart-eb8c3b59-5a7c-4def-acb8-fe8c578dfd38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380958546 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1380958546
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.403809154
Short name T101
Test name
Test status
Simulation time 257356847086 ps
CPU time 537.79 seconds
Started Jan 24 12:53:37 PM PST 24
Finished Jan 24 01:02:54 PM PST 24
Peak memory 197832 kb
Host smart-c7e75121-f02f-4423-90e9-7b022e8e9db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403809154 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.403809154
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.212934183
Short name T44
Test name
Test status
Simulation time 113418542306 ps
CPU time 14.84 seconds
Started Jan 24 12:52:38 PM PST 24
Finished Jan 24 12:53:04 PM PST 24
Peak memory 182940 kb
Host smart-345d7507-bd9b-4d6d-aeee-7612a642dfbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212934183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.212934183
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.2282001030
Short name T12
Test name
Test status
Simulation time 433821096 ps
CPU time 0.93 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 12:53:32 PM PST 24
Peak memory 183356 kb
Host smart-3ac8341a-1cc3-4fae-8c36-e013a2799fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282001030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.2282001030
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3490795544
Short name T185
Test name
Test status
Simulation time 275954786620 ps
CPU time 549.74 seconds
Started Jan 24 01:05:42 PM PST 24
Finished Jan 24 01:15:43 PM PST 24
Peak memory 198016 kb
Host smart-cc98d94a-d9ad-4204-86bc-5b6e66ffe335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490795544 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3490795544
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1448718267
Short name T5
Test name
Test status
Simulation time 541278569 ps
CPU time 1.07 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:46 PM PST 24
Peak memory 183276 kb
Host smart-880a67b0-277c-41f4-b197-d195a86b396d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448718267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1448718267
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2136105446
Short name T90
Test name
Test status
Simulation time 289397574097 ps
CPU time 630.61 seconds
Started Jan 24 12:53:54 PM PST 24
Finished Jan 24 01:04:41 PM PST 24
Peak memory 198292 kb
Host smart-4fe1448b-a5f7-49ea-96af-99f32e07f6ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136105446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2136105446
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2237526455
Short name T29
Test name
Test status
Simulation time 7608400005 ps
CPU time 11.68 seconds
Started Jan 24 12:52:22 PM PST 24
Finished Jan 24 12:52:51 PM PST 24
Peak memory 215132 kb
Host smart-ff1e63fb-c6cb-4712-aae3-2866e0c38a90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237526455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2237526455
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.373543059
Short name T107
Test name
Test status
Simulation time 165693942428 ps
CPU time 245.61 seconds
Started Jan 24 12:54:30 PM PST 24
Finished Jan 24 12:58:45 PM PST 24
Peak memory 183076 kb
Host smart-eec6ffb3-63f0-491d-9d7d-5260789f2a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373543059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_a
ll.373543059
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.189118125
Short name T115
Test name
Test status
Simulation time 11648823860 ps
CPU time 3.66 seconds
Started Jan 24 12:53:36 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 193328 kb
Host smart-9c024708-b4b8-4c4e-9034-f0710dbbb005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189118125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.189118125
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2949791264
Short name T4
Test name
Test status
Simulation time 8760392786 ps
CPU time 2.3 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:22 PM PST 24
Peak memory 197160 kb
Host smart-daa51c7a-8e90-4abb-8e2b-7bd512e6d351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949791264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2949791264
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3408194957
Short name T54
Test name
Test status
Simulation time 267003917145 ps
CPU time 410.11 seconds
Started Jan 24 12:53:22 PM PST 24
Finished Jan 24 01:00:29 PM PST 24
Peak memory 197796 kb
Host smart-42efe4bf-3f16-4ffa-98af-16cc27b5fe07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408194957 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3408194957
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2188970729
Short name T72
Test name
Test status
Simulation time 330824134 ps
CPU time 1.08 seconds
Started Jan 24 01:08:10 PM PST 24
Finished Jan 24 01:08:50 PM PST 24
Peak memory 183504 kb
Host smart-1a7893ee-2c73-43dd-809d-90598e86f93d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188970729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2188970729
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.29909264
Short name T280
Test name
Test status
Simulation time 267290117365 ps
CPU time 222.81 seconds
Started Jan 24 12:52:23 PM PST 24
Finished Jan 24 12:56:23 PM PST 24
Peak memory 183064 kb
Host smart-a914dbe2-4795-4636-99b8-10e4346eb889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all
.29909264
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1701063464
Short name T113
Test name
Test status
Simulation time 116019117740 ps
CPU time 232.96 seconds
Started Jan 24 12:52:39 PM PST 24
Finished Jan 24 12:56:43 PM PST 24
Peak memory 197752 kb
Host smart-363945b4-81bf-402a-a7b5-496bed1649bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701063464 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1701063464
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3484586359
Short name T274
Test name
Test status
Simulation time 100248316570 ps
CPU time 27.97 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 194248 kb
Host smart-d4d6a58d-82b7-471d-85fe-e0057ec55242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484586359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3484586359
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1439106852
Short name T333
Test name
Test status
Simulation time 642027049 ps
CPU time 0.88 seconds
Started Jan 24 12:48:18 PM PST 24
Finished Jan 24 12:48:38 PM PST 24
Peak memory 183280 kb
Host smart-166ce591-f91b-4ab5-9e60-71a028a7a33d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439106852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1439106852
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.104430686
Short name T56
Test name
Test status
Simulation time 2893420623 ps
CPU time 2.54 seconds
Started Jan 24 12:48:16 PM PST 24
Finished Jan 24 12:48:34 PM PST 24
Peak memory 191888 kb
Host smart-ffb09fbb-72d0-4248-9fe9-31f2959c39d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104430686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.104430686
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.702946626
Short name T320
Test name
Test status
Simulation time 1027770139 ps
CPU time 1.86 seconds
Started Jan 24 12:48:18 PM PST 24
Finished Jan 24 12:48:39 PM PST 24
Peak memory 183268 kb
Host smart-55d73832-8ab6-4c69-a75f-df0f091fbb5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702946626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.702946626
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2315288420
Short name T318
Test name
Test status
Simulation time 510184673 ps
CPU time 0.92 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:46 PM PST 24
Peak memory 197244 kb
Host smart-4fdc90f5-ab90-4472-9bb1-843073ca6f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315288420 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2315288420
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1053239085
Short name T69
Test name
Test status
Simulation time 341112240 ps
CPU time 0.66 seconds
Started Jan 24 12:48:16 PM PST 24
Finished Jan 24 12:48:32 PM PST 24
Peak memory 183396 kb
Host smart-f8645cad-adab-4f5e-9110-0b999265404c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053239085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1053239085
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.1355206221
Short name T416
Test name
Test status
Simulation time 525656366 ps
CPU time 0.74 seconds
Started Jan 24 12:48:12 PM PST 24
Finished Jan 24 12:48:15 PM PST 24
Peak memory 183268 kb
Host smart-49a435a4-4d50-4160-9f5c-f38028d9a169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355206221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.1355206221
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.46022440
Short name T336
Test name
Test status
Simulation time 487522628 ps
CPU time 1.28 seconds
Started Jan 24 12:48:14 PM PST 24
Finished Jan 24 12:48:21 PM PST 24
Peak memory 183164 kb
Host smart-f58b19ac-05ff-4eb8-ad7e-d31692087dd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46022440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.46022440
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3471872987
Short name T300
Test name
Test status
Simulation time 346458148 ps
CPU time 0.58 seconds
Started Jan 24 12:48:11 PM PST 24
Finished Jan 24 12:48:14 PM PST 24
Peak memory 182960 kb
Host smart-af746994-d666-47d9-bde3-245094c3278b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471872987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3471872987
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.683725024
Short name T380
Test name
Test status
Simulation time 1706481693 ps
CPU time 2.75 seconds
Started Jan 24 12:48:13 PM PST 24
Finished Jan 24 12:48:21 PM PST 24
Peak memory 192288 kb
Host smart-a138ff3f-7e6a-43f9-839b-bc2ad85a29f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683725024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.683725024
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3916228716
Short name T411
Test name
Test status
Simulation time 384732145 ps
CPU time 2.02 seconds
Started Jan 24 12:48:14 PM PST 24
Finished Jan 24 12:48:21 PM PST 24
Peak memory 198244 kb
Host smart-4420f8af-b318-4490-8982-fdb09fb1a8c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916228716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3916228716
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1314730941
Short name T309
Test name
Test status
Simulation time 5331843148 ps
CPU time 2.42 seconds
Started Jan 24 12:48:16 PM PST 24
Finished Jan 24 12:48:34 PM PST 24
Peak memory 195388 kb
Host smart-f8106ff1-21ec-404c-baab-9c5fbae20208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314730941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1314730941
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2602548009
Short name T344
Test name
Test status
Simulation time 5828831364 ps
CPU time 8.32 seconds
Started Jan 24 12:48:13 PM PST 24
Finished Jan 24 12:48:26 PM PST 24
Peak memory 191912 kb
Host smart-06c9a55f-0a41-40e6-9c4a-6b6b969e027f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602548009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2602548009
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2891614167
Short name T66
Test name
Test status
Simulation time 1299393569 ps
CPU time 2.64 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:48 PM PST 24
Peak memory 183296 kb
Host smart-c1a78ffc-5d6d-4621-ad9b-ca572c9b4784
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891614167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2891614167
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3875935828
Short name T319
Test name
Test status
Simulation time 332845893 ps
CPU time 0.92 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:46 PM PST 24
Peak memory 194156 kb
Host smart-a1a0b69f-39f6-4c0c-a7b2-20ed2c47dbde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875935828 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3875935828
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.3987532449
Short name T61
Test name
Test status
Simulation time 385701132 ps
CPU time 1.19 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:46 PM PST 24
Peak memory 183268 kb
Host smart-692a8630-2e23-4ec8-a982-c78e4c9b3f94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987532449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.3987532449
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.646323565
Short name T406
Test name
Test status
Simulation time 436474359 ps
CPU time 0.79 seconds
Started Jan 24 12:48:16 PM PST 24
Finished Jan 24 12:48:32 PM PST 24
Peak memory 182932 kb
Host smart-e8539e1a-5e30-4969-90cc-91ecc188a0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646323565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.646323565
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.807737273
Short name T304
Test name
Test status
Simulation time 285825751 ps
CPU time 0.92 seconds
Started Jan 24 12:48:14 PM PST 24
Finished Jan 24 12:48:20 PM PST 24
Peak memory 183348 kb
Host smart-7681fcb5-707f-4d75-bcb8-07592a25e09c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807737273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.807737273
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1479107001
Short name T329
Test name
Test status
Simulation time 400990644 ps
CPU time 0.65 seconds
Started Jan 24 12:48:13 PM PST 24
Finished Jan 24 12:48:19 PM PST 24
Peak memory 183128 kb
Host smart-cf486179-d3d2-4a58-b41b-b2960ff50e65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479107001 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1479107001
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.173989615
Short name T393
Test name
Test status
Simulation time 1726638534 ps
CPU time 4.76 seconds
Started Jan 24 12:48:11 PM PST 24
Finished Jan 24 12:48:19 PM PST 24
Peak memory 192680 kb
Host smart-c581117b-f42a-4d22-9045-1edd4dbc33f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173989615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.173989615
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2137508780
Short name T372
Test name
Test status
Simulation time 608871502 ps
CPU time 2.05 seconds
Started Jan 24 12:48:18 PM PST 24
Finished Jan 24 12:48:39 PM PST 24
Peak memory 198076 kb
Host smart-c7f387ba-bdab-402b-a684-37386881a216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137508780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2137508780
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.92357756
Short name T84
Test name
Test status
Simulation time 8796838050 ps
CPU time 2.08 seconds
Started Jan 24 12:48:20 PM PST 24
Finished Jan 24 12:48:47 PM PST 24
Peak memory 196940 kb
Host smart-0094ced4-cfde-4b7c-a0ee-e0b72c97892a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92357756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_i
ntg_err.92357756
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2182908187
Short name T325
Test name
Test status
Simulation time 503218179 ps
CPU time 0.77 seconds
Started Jan 24 12:48:42 PM PST 24
Finished Jan 24 12:49:19 PM PST 24
Peak memory 194144 kb
Host smart-05ff0f81-f553-4e1a-9d18-64f7b8888f0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182908187 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2182908187
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1192581953
Short name T425
Test name
Test status
Simulation time 355256004 ps
CPU time 1.03 seconds
Started Jan 24 12:48:47 PM PST 24
Finished Jan 24 12:49:27 PM PST 24
Peak memory 183448 kb
Host smart-1561fba4-714f-4c46-9500-337e6c1ead97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192581953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1192581953
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.314246174
Short name T422
Test name
Test status
Simulation time 511701181 ps
CPU time 0.91 seconds
Started Jan 24 12:48:38 PM PST 24
Finished Jan 24 12:49:14 PM PST 24
Peak memory 183056 kb
Host smart-0c0c5f7a-2682-4ba9-9b75-b253db9107a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314246174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.314246174
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.3515321202
Short name T369
Test name
Test status
Simulation time 2591881807 ps
CPU time 2.25 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:24 PM PST 24
Peak memory 191620 kb
Host smart-65ee840e-c471-4d3a-8637-0d4b53c0fd7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515321202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.3515321202
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.964728134
Short name T419
Test name
Test status
Simulation time 751337015 ps
CPU time 2.06 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:16 PM PST 24
Peak memory 198176 kb
Host smart-6e1d31da-8374-4799-81c7-51a8d708ed67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964728134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.964728134
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3842707341
Short name T348
Test name
Test status
Simulation time 4474180469 ps
CPU time 3.7 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:25 PM PST 24
Peak memory 195824 kb
Host smart-ff8bc799-32ca-4ef3-ae76-b29db3307ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842707341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3842707341
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2683200374
Short name T392
Test name
Test status
Simulation time 521165742 ps
CPU time 1 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:22 PM PST 24
Peak memory 195064 kb
Host smart-5ea98271-3bc0-4230-9ea8-b91e872a8e05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683200374 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2683200374
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3675315282
Short name T21
Test name
Test status
Simulation time 448822648 ps
CPU time 0.61 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:27 PM PST 24
Peak memory 183132 kb
Host smart-e4081956-90a4-4dde-a312-a3b262d088f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675315282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3675315282
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3709565897
Short name T405
Test name
Test status
Simulation time 1612082321 ps
CPU time 2.3 seconds
Started Jan 24 12:48:33 PM PST 24
Finished Jan 24 12:49:06 PM PST 24
Peak memory 194492 kb
Host smart-7f948af1-9d87-42dd-acdc-f49d75391757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709565897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3709565897
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1430539660
Short name T371
Test name
Test status
Simulation time 531822556 ps
CPU time 2.01 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:17 PM PST 24
Peak memory 198200 kb
Host smart-c7755bf2-f045-4cee-8250-df4427089342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430539660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1430539660
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3092212830
Short name T415
Test name
Test status
Simulation time 4505629925 ps
CPU time 7.77 seconds
Started Jan 24 12:48:49 PM PST 24
Finished Jan 24 12:49:37 PM PST 24
Peak memory 196976 kb
Host smart-7b7af789-621d-49a2-b6fd-afe03ab60bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092212830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3092212830
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1005274518
Short name T311
Test name
Test status
Simulation time 400618892 ps
CPU time 1.27 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:29 PM PST 24
Peak memory 195236 kb
Host smart-cfe9485e-79f1-437a-a3e2-ce3d356d9df2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005274518 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1005274518
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2100761524
Short name T64
Test name
Test status
Simulation time 470940998 ps
CPU time 0.69 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:29 PM PST 24
Peak memory 183460 kb
Host smart-6ac50ad5-8bf9-4e48-95e4-d048352924e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100761524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2100761524
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2567444684
Short name T330
Test name
Test status
Simulation time 493562235 ps
CPU time 1.2 seconds
Started Jan 24 12:48:42 PM PST 24
Finished Jan 24 12:49:21 PM PST 24
Peak memory 183056 kb
Host smart-c846e38e-798f-4b30-b5bd-172409ce039c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567444684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2567444684
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.683629014
Short name T11
Test name
Test status
Simulation time 2480502728 ps
CPU time 1.62 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:22 PM PST 24
Peak memory 193228 kb
Host smart-2d875fb7-3c79-47e1-8a4b-f9a4ea27e1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683629014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.683629014
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3353249948
Short name T321
Test name
Test status
Simulation time 630620613 ps
CPU time 2.23 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:30 PM PST 24
Peak memory 198288 kb
Host smart-0524ae9b-f1bf-4f59-862a-f58fc12d01a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353249948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3353249948
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3563777783
Short name T303
Test name
Test status
Simulation time 494889195 ps
CPU time 0.99 seconds
Started Jan 24 12:53:12 PM PST 24
Finished Jan 24 12:53:24 PM PST 24
Peak memory 194092 kb
Host smart-a930aa2d-9cde-4fa0-9c63-ca5aafaf0d6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563777783 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3563777783
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.2861737502
Short name T7
Test name
Test status
Simulation time 472468955 ps
CPU time 0.92 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183412 kb
Host smart-00884d59-70fe-4609-87fb-434c1a15d19a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861737502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.2861737502
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2825975338
Short name T302
Test name
Test status
Simulation time 344443272 ps
CPU time 0.65 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183112 kb
Host smart-7b688a8f-e6c1-4ffe-95dc-fd73e3c7fcc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825975338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2825975338
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1358019165
Short name T414
Test name
Test status
Simulation time 2069625581 ps
CPU time 2.26 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:35 PM PST 24
Peak memory 192884 kb
Host smart-24aae214-16eb-4db3-ac3a-129d85ee4ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358019165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1358019165
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1047707789
Short name T342
Test name
Test status
Simulation time 708101523 ps
CPU time 1.38 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:23 PM PST 24
Peak memory 198188 kb
Host smart-d33b3891-898b-431d-8108-4fa3ff6e12eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047707789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1047707789
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2799697215
Short name T360
Test name
Test status
Simulation time 4378049823 ps
CPU time 2.34 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:31 PM PST 24
Peak memory 195732 kb
Host smart-02b0ff28-8d88-4336-bb9a-b3ac5348aa7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799697215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2799697215
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2105173095
Short name T390
Test name
Test status
Simulation time 527681886 ps
CPU time 1.4 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:28 PM PST 24
Peak memory 194392 kb
Host smart-71953ed9-ca37-433a-8f2c-41044a660256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105173095 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2105173095
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1861569688
Short name T70
Test name
Test status
Simulation time 443849999 ps
CPU time 1.11 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183248 kb
Host smart-2fdbc7f7-a4b4-4539-b982-9d7aff4cee62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861569688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1861569688
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2425369508
Short name T376
Test name
Test status
Simulation time 472680294 ps
CPU time 1.18 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:30 PM PST 24
Peak memory 183156 kb
Host smart-b9c8c6e2-194f-43c7-a504-f1426d876a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425369508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2425369508
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2693899734
Short name T412
Test name
Test status
Simulation time 980835474 ps
CPU time 1.72 seconds
Started Jan 24 12:48:54 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 192724 kb
Host smart-a6714462-6d05-497b-a42e-d914bf0dcb5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693899734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2693899734
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3085413569
Short name T13
Test name
Test status
Simulation time 886794179 ps
CPU time 1.15 seconds
Started Jan 24 12:48:45 PM PST 24
Finished Jan 24 12:49:26 PM PST 24
Peak memory 198068 kb
Host smart-faba916e-f295-4bbd-a1ef-7c94f9cc55e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085413569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3085413569
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.384742830
Short name T363
Test name
Test status
Simulation time 4416822783 ps
CPU time 8.01 seconds
Started Jan 24 12:55:25 PM PST 24
Finished Jan 24 12:56:03 PM PST 24
Peak memory 197076 kb
Host smart-581d3f65-78fe-42e1-86f0-7deb761880f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384742830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.384742830
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.3621014228
Short name T306
Test name
Test status
Simulation time 438526613 ps
CPU time 0.85 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 195832 kb
Host smart-cab272a2-d2ca-4096-a2fa-a164d3e1cb34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621014228 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.3621014228
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3071541689
Short name T394
Test name
Test status
Simulation time 426455807 ps
CPU time 0.71 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:29 PM PST 24
Peak memory 183448 kb
Host smart-256ec85b-e4dd-4d41-abbe-395a01226174
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071541689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3071541689
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2094572882
Short name T345
Test name
Test status
Simulation time 483671934 ps
CPU time 0.7 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:27 PM PST 24
Peak memory 183056 kb
Host smart-554d6885-c335-4e07-8a62-5cf99e821273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094572882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2094572882
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.493728720
Short name T347
Test name
Test status
Simulation time 2898978194 ps
CPU time 1.68 seconds
Started Jan 24 12:52:21 PM PST 24
Finished Jan 24 12:52:40 PM PST 24
Peak memory 194536 kb
Host smart-5a365a09-8ae1-4560-b319-c708c822a52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493728720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.493728720
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3269105141
Short name T301
Test name
Test status
Simulation time 691600046 ps
CPU time 2.38 seconds
Started Jan 24 12:48:47 PM PST 24
Finished Jan 24 12:49:29 PM PST 24
Peak memory 197936 kb
Host smart-168e62d6-2c85-45d9-91c5-9e3a4b03ba3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269105141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3269105141
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3264007376
Short name T420
Test name
Test status
Simulation time 4509439364 ps
CPU time 7.1 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:40 PM PST 24
Peak memory 196880 kb
Host smart-c5f2fcd8-9da6-430c-9016-4e4749fcb0bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264007376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3264007376
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1608170921
Short name T364
Test name
Test status
Simulation time 352492743 ps
CPU time 0.72 seconds
Started Jan 24 12:48:47 PM PST 24
Finished Jan 24 12:49:27 PM PST 24
Peak memory 194108 kb
Host smart-1fdb1639-88bc-4295-a68a-348e343f1e46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608170921 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1608170921
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1503220766
Short name T314
Test name
Test status
Simulation time 353997052 ps
CPU time 0.69 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:26 PM PST 24
Peak memory 183356 kb
Host smart-f9861a56-604e-4e70-aa2e-919fb66943b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503220766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1503220766
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2105685468
Short name T375
Test name
Test status
Simulation time 291031584 ps
CPU time 0.95 seconds
Started Jan 24 12:48:44 PM PST 24
Finished Jan 24 12:49:23 PM PST 24
Peak memory 183056 kb
Host smart-ed7e761c-ba4c-4aaf-8c58-347024da19d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105685468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2105685468
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1005748480
Short name T423
Test name
Test status
Simulation time 1632243126 ps
CPU time 2.95 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:28 PM PST 24
Peak memory 193880 kb
Host smart-1a147fa2-80b4-4f07-887b-b3951a94dfc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005748480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1005748480
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2794670754
Short name T395
Test name
Test status
Simulation time 602249213 ps
CPU time 1.88 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:30 PM PST 24
Peak memory 198324 kb
Host smart-e2646c5d-a86d-4f5d-8651-a05a145a766c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794670754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2794670754
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1897501111
Short name T10
Test name
Test status
Simulation time 8281085377 ps
CPU time 7.74 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 197196 kb
Host smart-5a465577-b922-4815-9d21-762d783243d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897501111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1897501111
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4126646059
Short name T417
Test name
Test status
Simulation time 388302940 ps
CPU time 1 seconds
Started Jan 24 01:12:34 PM PST 24
Finished Jan 24 01:13:27 PM PST 24
Peak memory 195592 kb
Host smart-31ddb629-d63e-49b0-8a39-c588c1e160b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126646059 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4126646059
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2970877419
Short name T63
Test name
Test status
Simulation time 566823408 ps
CPU time 0.66 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183388 kb
Host smart-81d96a5f-e409-431d-afd1-994e5f631d89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970877419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2970877419
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2031428853
Short name T322
Test name
Test status
Simulation time 496572278 ps
CPU time 0.72 seconds
Started Jan 24 02:24:30 PM PST 24
Finished Jan 24 02:24:38 PM PST 24
Peak memory 183240 kb
Host smart-0586a348-8626-468e-8cc3-be5a0647795a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031428853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2031428853
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1345001454
Short name T6
Test name
Test status
Simulation time 960123397 ps
CPU time 2.82 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:31 PM PST 24
Peak memory 192380 kb
Host smart-f5c11102-fc6d-4a31-9d95-70bb5ebe0bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345001454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1345001454
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3501241821
Short name T346
Test name
Test status
Simulation time 583259083 ps
CPU time 1.62 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:30 PM PST 24
Peak memory 198320 kb
Host smart-4cb066de-1cb9-48e3-9556-9f954a73e33d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501241821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3501241821
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.4019070803
Short name T9
Test name
Test status
Simulation time 9064879894 ps
CPU time 1.88 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:30 PM PST 24
Peak memory 197180 kb
Host smart-977455cd-0247-47e9-910a-41496077c83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019070803 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.4019070803
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2743367483
Short name T335
Test name
Test status
Simulation time 561503015 ps
CPU time 0.88 seconds
Started Jan 24 01:03:03 PM PST 24
Finished Jan 24 01:03:23 PM PST 24
Peak memory 197160 kb
Host smart-c20b21ad-1269-4cb3-bca8-63e8908dab30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743367483 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2743367483
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2661412684
Short name T71
Test name
Test status
Simulation time 441479301 ps
CPU time 1.19 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183384 kb
Host smart-6e00d132-86ee-4c5a-833f-cd2ffe1c8d31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661412684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2661412684
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1878335960
Short name T362
Test name
Test status
Simulation time 1039138386 ps
CPU time 0.85 seconds
Started Jan 24 12:48:52 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 192904 kb
Host smart-496136ae-6100-47f4-83b9-f093c27a1610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878335960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1878335960
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.377706163
Short name T368
Test name
Test status
Simulation time 640092124 ps
CPU time 1.34 seconds
Started Jan 24 12:48:51 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 198136 kb
Host smart-03a35731-fbd0-4850-8834-78b96a494a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377706163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.377706163
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.1816492192
Short name T396
Test name
Test status
Simulation time 7775581983 ps
CPU time 9.62 seconds
Started Jan 24 12:48:48 PM PST 24
Finished Jan 24 12:49:38 PM PST 24
Peak memory 197400 kb
Host smart-2fe894f1-700f-4ad7-a852-8fc1ce59efbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816492192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.1816492192
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3231219949
Short name T407
Test name
Test status
Simulation time 418283976 ps
CPU time 1.01 seconds
Started Jan 24 03:19:31 PM PST 24
Finished Jan 24 03:19:49 PM PST 24
Peak memory 198176 kb
Host smart-80f74b69-6f8a-44e3-8b86-244afaf57704
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231219949 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3231219949
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1729213578
Short name T421
Test name
Test status
Simulation time 388889633 ps
CPU time 0.67 seconds
Started Jan 24 01:28:45 PM PST 24
Finished Jan 24 01:29:08 PM PST 24
Peak memory 183468 kb
Host smart-16673027-53c5-4e3f-aab5-4dfa942b2959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729213578 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1729213578
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.3376621316
Short name T382
Test name
Test status
Simulation time 506918354 ps
CPU time 0.92 seconds
Started Jan 24 12:48:53 PM PST 24
Finished Jan 24 12:49:35 PM PST 24
Peak memory 183352 kb
Host smart-e81262e3-08a1-4baf-a9e4-3101b8ea0991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376621316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.3376621316
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1505902352
Short name T398
Test name
Test status
Simulation time 2068339608 ps
CPU time 6.51 seconds
Started Jan 24 12:48:56 PM PST 24
Finished Jan 24 12:49:42 PM PST 24
Peak memory 193804 kb
Host smart-f6162109-613d-4918-a43b-f582cf9d0370
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505902352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1505902352
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1149524539
Short name T8
Test name
Test status
Simulation time 303987331 ps
CPU time 1.61 seconds
Started Jan 24 01:12:35 PM PST 24
Finished Jan 24 01:13:30 PM PST 24
Peak memory 198340 kb
Host smart-cffc3d7b-35a2-4d69-9f60-c9b585382d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149524539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1149524539
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.413514981
Short name T331
Test name
Test status
Simulation time 4126620277 ps
CPU time 2.16 seconds
Started Jan 24 12:48:53 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 195552 kb
Host smart-9a2cf296-2109-42ae-95db-681b4eb14c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413514981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.413514981
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2674198237
Short name T59
Test name
Test status
Simulation time 423513359 ps
CPU time 0.79 seconds
Started Jan 24 12:48:23 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 192560 kb
Host smart-c2c4891e-ab52-48e3-9c5c-8da00def7145
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674198237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2674198237
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.4087162215
Short name T402
Test name
Test status
Simulation time 10690929062 ps
CPU time 29.42 seconds
Started Jan 24 12:48:22 PM PST 24
Finished Jan 24 12:49:19 PM PST 24
Peak memory 183640 kb
Host smart-e5f52a96-2689-48bf-93b5-7d68d7b91183
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087162215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.4087162215
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4108759117
Short name T65
Test name
Test status
Simulation time 1213415655 ps
CPU time 1.47 seconds
Started Jan 24 12:48:25 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 182960 kb
Host smart-552b49f3-f397-431a-bc39-5d6b524e5b87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108759117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4108759117
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.1034599417
Short name T79
Test name
Test status
Simulation time 497070916 ps
CPU time 1.24 seconds
Started Jan 24 12:48:22 PM PST 24
Finished Jan 24 12:48:50 PM PST 24
Peak memory 194316 kb
Host smart-81488670-0b3b-48c6-937b-a12c889f67aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034599417 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.1034599417
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.4078121969
Short name T67
Test name
Test status
Simulation time 333540340 ps
CPU time 0.67 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 183028 kb
Host smart-a8a0b023-2baf-4d63-ac50-80e8606b0c1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078121969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.4078121969
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.52914888
Short name T404
Test name
Test status
Simulation time 336985368 ps
CPU time 0.97 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:02 PM PST 24
Peak memory 182940 kb
Host smart-d06dc81b-b3db-4bdd-9608-932e34705c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52914888 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.52914888
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1333700865
Short name T129
Test name
Test status
Simulation time 293012855 ps
CPU time 0.72 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:02 PM PST 24
Peak memory 182964 kb
Host smart-9b249cbc-98d8-47ff-a40e-b8b62c70224e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333700865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1333700865
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4094012805
Short name T339
Test name
Test status
Simulation time 469405871 ps
CPU time 0.68 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 183100 kb
Host smart-de802f40-9d82-4225-b4f4-87573fb08d71
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094012805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4094012805
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3072096550
Short name T374
Test name
Test status
Simulation time 1554114746 ps
CPU time 2.59 seconds
Started Jan 24 12:48:27 PM PST 24
Finished Jan 24 12:48:59 PM PST 24
Peak memory 193792 kb
Host smart-734a55b2-00c5-4134-b22f-4e93813f0a05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072096550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3072096550
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1652084436
Short name T351
Test name
Test status
Simulation time 427323867 ps
CPU time 1.98 seconds
Started Jan 24 12:48:16 PM PST 24
Finished Jan 24 12:48:35 PM PST 24
Peak memory 198144 kb
Host smart-14abec09-3405-4061-b354-c2f7c6dca101
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652084436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1652084436
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2378012088
Short name T85
Test name
Test status
Simulation time 8519062913 ps
CPU time 3.35 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 197016 kb
Host smart-4a6a9c53-d59b-4a2f-aaa9-5e243607add1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378012088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2378012088
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.1385492877
Short name T130
Test name
Test status
Simulation time 455119859 ps
CPU time 1.2 seconds
Started Jan 24 12:48:56 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 183076 kb
Host smart-41bbaa69-b2d8-41d6-90ae-624fede47fe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385492877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.1385492877
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.411201100
Short name T418
Test name
Test status
Simulation time 280493587 ps
CPU time 0.91 seconds
Started Jan 24 12:48:57 PM PST 24
Finished Jan 24 12:49:37 PM PST 24
Peak memory 183184 kb
Host smart-e4aabcde-e385-461d-9b8d-d50ed201457c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411201100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.411201100
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.33222666
Short name T315
Test name
Test status
Simulation time 370021819 ps
CPU time 1.02 seconds
Started Jan 24 01:23:09 PM PST 24
Finished Jan 24 01:24:00 PM PST 24
Peak memory 183428 kb
Host smart-b458ead3-5ae7-4662-98ab-f9272cc8e002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33222666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.33222666
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.449738633
Short name T338
Test name
Test status
Simulation time 277349904 ps
CPU time 0.91 seconds
Started Jan 24 12:48:54 PM PST 24
Finished Jan 24 12:49:35 PM PST 24
Peak memory 183048 kb
Host smart-0fa38fe7-9340-4509-b4e9-42b4b5ad029a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449738633 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.449738633
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.4106272571
Short name T366
Test name
Test status
Simulation time 270678767 ps
CPU time 0.96 seconds
Started Jan 24 12:48:57 PM PST 24
Finished Jan 24 12:49:37 PM PST 24
Peak memory 183004 kb
Host smart-22ff20ea-2197-4265-9e25-ad3c8618c37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106272571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.4106272571
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1018362235
Short name T24
Test name
Test status
Simulation time 399179692 ps
CPU time 1.12 seconds
Started Jan 24 12:48:53 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 183048 kb
Host smart-6f6de02d-2b25-457a-9cd7-ae0e78790843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018362235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1018362235
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2216910691
Short name T341
Test name
Test status
Simulation time 356884399 ps
CPU time 0.56 seconds
Started Jan 24 12:48:56 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 183004 kb
Host smart-a3e7ddc1-006f-4ff9-b027-c3f94219af87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216910691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2216910691
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.244270607
Short name T377
Test name
Test status
Simulation time 500286913 ps
CPU time 1.19 seconds
Started Jan 24 12:48:54 PM PST 24
Finished Jan 24 12:49:36 PM PST 24
Peak memory 183048 kb
Host smart-b77cde08-9de2-4cd4-982b-706455c56b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244270607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.244270607
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.3440889325
Short name T354
Test name
Test status
Simulation time 569332071 ps
CPU time 0.65 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 182876 kb
Host smart-ef1bcb93-eaff-4f13-8c71-9917a48180bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440889325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.3440889325
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1269282009
Short name T68
Test name
Test status
Simulation time 319039602 ps
CPU time 1.02 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 183280 kb
Host smart-052e5766-a589-4755-bd9a-69b455ea160a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269282009 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1269282009
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.883377344
Short name T367
Test name
Test status
Simulation time 6056110958 ps
CPU time 4.24 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:05 PM PST 24
Peak memory 183544 kb
Host smart-86804f59-c728-44f4-be06-76d992acc1c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883377344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.883377344
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.4027144589
Short name T328
Test name
Test status
Simulation time 1161222607 ps
CPU time 2.15 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:59 PM PST 24
Peak memory 183412 kb
Host smart-aed9afbc-e818-410f-9685-43d82a29b115
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027144589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.4027144589
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.4104819745
Short name T313
Test name
Test status
Simulation time 611285782 ps
CPU time 0.82 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 196776 kb
Host smart-c8cc87cd-59b2-4ffb-867f-e60a80c061b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104819745 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.4104819745
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3601991819
Short name T400
Test name
Test status
Simulation time 434341389 ps
CPU time 1.21 seconds
Started Jan 24 12:48:25 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 192616 kb
Host smart-9c9d6894-a9b3-4dbe-a235-65209b18feba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601991819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3601991819
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3121564273
Short name T310
Test name
Test status
Simulation time 504534914 ps
CPU time 1.01 seconds
Started Jan 24 12:48:27 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 182940 kb
Host smart-e1febd33-13db-4a2e-81f1-1a22d6ec2400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121564273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3121564273
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3364659213
Short name T327
Test name
Test status
Simulation time 366913410 ps
CPU time 1.08 seconds
Started Jan 24 12:48:25 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 182684 kb
Host smart-4150620b-fca3-4d8b-ac49-fbe8f84c84bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364659213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3364659213
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.4014690547
Short name T337
Test name
Test status
Simulation time 384397324 ps
CPU time 0.67 seconds
Started Jan 24 12:48:25 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 183444 kb
Host smart-e9bcd26f-ad0f-4b36-87db-3252f871bcaa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014690547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.4014690547
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3741079994
Short name T385
Test name
Test status
Simulation time 1182118709 ps
CPU time 3.14 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 192376 kb
Host smart-62f871f6-f49b-4890-9edd-b9ed620799cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741079994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3741079994
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.320315637
Short name T51
Test name
Test status
Simulation time 927312224 ps
CPU time 2.33 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:59 PM PST 24
Peak memory 198052 kb
Host smart-2f76698c-5454-4bd0-91a6-15f3071d880a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320315637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.320315637
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3650587491
Short name T388
Test name
Test status
Simulation time 4502711819 ps
CPU time 2.52 seconds
Started Jan 24 01:03:38 PM PST 24
Finished Jan 24 01:04:17 PM PST 24
Peak memory 197016 kb
Host smart-03b1b412-186c-4684-be87-4134cbc959df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650587491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3650587491
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3260290439
Short name T408
Test name
Test status
Simulation time 513119678 ps
CPU time 0.91 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 182960 kb
Host smart-ef0d646f-6259-4c89-b389-19662631a6e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260290439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3260290439
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2223869898
Short name T326
Test name
Test status
Simulation time 485227541 ps
CPU time 0.93 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 183380 kb
Host smart-453fb26b-4bc6-4cbc-9157-014ef1568a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223869898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2223869898
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3891926877
Short name T399
Test name
Test status
Simulation time 464576206 ps
CPU time 0.73 seconds
Started Jan 24 12:49:09 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 183352 kb
Host smart-5087b346-4eb2-47dd-8a64-64cafafc1e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891926877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3891926877
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.1694086562
Short name T410
Test name
Test status
Simulation time 348958938 ps
CPU time 0.6 seconds
Started Jan 24 12:49:05 PM PST 24
Finished Jan 24 12:49:41 PM PST 24
Peak memory 183052 kb
Host smart-684a2d11-ea56-4cca-b5f2-b8078044eed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694086562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.1694086562
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.739562589
Short name T308
Test name
Test status
Simulation time 517008006 ps
CPU time 1.45 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:44 PM PST 24
Peak memory 183352 kb
Host smart-d18d6f28-8259-44fd-9aef-c0ca6d898e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739562589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.739562589
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1865260337
Short name T349
Test name
Test status
Simulation time 322156112 ps
CPU time 0.82 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 183116 kb
Host smart-439b1278-ef4a-403f-9896-6c2587d8610c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865260337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1865260337
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.1588912484
Short name T128
Test name
Test status
Simulation time 503364243 ps
CPU time 1.21 seconds
Started Jan 24 12:49:04 PM PST 24
Finished Jan 24 12:49:41 PM PST 24
Peak memory 183116 kb
Host smart-54a2958c-7d36-4fb7-89fc-7421570d1152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588912484 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.1588912484
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.395322712
Short name T389
Test name
Test status
Simulation time 396913123 ps
CPU time 0.84 seconds
Started Jan 24 12:49:07 PM PST 24
Finished Jan 24 12:49:42 PM PST 24
Peak memory 183120 kb
Host smart-597ca2e5-e2b5-45fd-a49d-b266c030abea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395322712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.395322712
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3487687645
Short name T403
Test name
Test status
Simulation time 337809728 ps
CPU time 0.65 seconds
Started Jan 24 12:49:10 PM PST 24
Finished Jan 24 12:49:43 PM PST 24
Peak memory 183356 kb
Host smart-03a9ebb7-2dc8-474a-9924-a7a063c53f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487687645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3487687645
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3904620457
Short name T23
Test name
Test status
Simulation time 516194593 ps
CPU time 0.87 seconds
Started Jan 24 12:49:06 PM PST 24
Finished Jan 24 12:49:41 PM PST 24
Peak memory 183120 kb
Host smart-496535cb-0b2d-4ed7-a848-348e80a33582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904620457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3904620457
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2082374018
Short name T62
Test name
Test status
Simulation time 545257955 ps
CPU time 1.51 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:03 PM PST 24
Peak memory 192468 kb
Host smart-392739e0-e42f-45d4-ad3c-498f73aadd13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082374018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2082374018
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.815527078
Short name T424
Test name
Test status
Simulation time 6028444333 ps
CPU time 3.58 seconds
Started Jan 24 12:48:23 PM PST 24
Finished Jan 24 12:48:55 PM PST 24
Peak memory 191912 kb
Host smart-82f7b665-fab5-485b-8585-4de499317d78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815527078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_bi
t_bash.815527078
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.917609313
Short name T373
Test name
Test status
Simulation time 1004196873 ps
CPU time 0.91 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:02 PM PST 24
Peak memory 183248 kb
Host smart-5218d506-686e-4f83-ab09-92ad654bdf87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917609313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.917609313
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.233670287
Short name T324
Test name
Test status
Simulation time 438989426 ps
CPU time 1.15 seconds
Started Jan 24 12:48:38 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 193856 kb
Host smart-33ad22b2-c304-4739-8eb5-ac2830978e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233670287 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.233670287
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2714977399
Short name T55
Test name
Test status
Simulation time 369185829 ps
CPU time 1.08 seconds
Started Jan 24 12:48:38 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 183176 kb
Host smart-272d6aa4-b676-4fe9-959d-e1177e58bc60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714977399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2714977399
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3873239321
Short name T353
Test name
Test status
Simulation time 580207684 ps
CPU time 0.61 seconds
Started Jan 24 12:48:31 PM PST 24
Finished Jan 24 12:49:01 PM PST 24
Peak memory 183188 kb
Host smart-028b0d62-34c3-418a-ac1f-d1764b374179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873239321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3873239321
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3656542833
Short name T334
Test name
Test status
Simulation time 329206133 ps
CPU time 0.7 seconds
Started Jan 24 12:48:24 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 183152 kb
Host smart-4b0a36e4-2bcb-4d36-b5a7-c6ebcb211ad0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656542833 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3656542833
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.581890323
Short name T343
Test name
Test status
Simulation time 503576011 ps
CPU time 1.15 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 182916 kb
Host smart-55d683fe-5db0-4d5d-816a-c1467a2282e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581890323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.581890323
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1802022173
Short name T73
Test name
Test status
Simulation time 1611564615 ps
CPU time 3.22 seconds
Started Jan 24 12:48:27 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 192912 kb
Host smart-df60ce4a-bfc7-4fbb-b82a-3e2633b5ecf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802022173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1802022173
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1402013509
Short name T352
Test name
Test status
Simulation time 704194502 ps
CPU time 1.49 seconds
Started Jan 24 12:48:26 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 198248 kb
Host smart-c2d77b0b-68b5-4058-868a-075fa431d8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402013509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1402013509
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1113698382
Short name T378
Test name
Test status
Simulation time 4706609272 ps
CPU time 2.84 seconds
Started Jan 24 12:48:23 PM PST 24
Finished Jan 24 12:48:55 PM PST 24
Peak memory 196972 kb
Host smart-2d31403e-bb48-45f1-8494-18454e1e8c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113698382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1113698382
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.516039246
Short name T82
Test name
Test status
Simulation time 496978321 ps
CPU time 1.26 seconds
Started Jan 24 02:30:21 PM PST 24
Finished Jan 24 02:30:35 PM PST 24
Peak memory 183436 kb
Host smart-e94442f2-6937-4c1d-ba01-5d36eca792e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516039246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.516039246
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1549471420
Short name T357
Test name
Test status
Simulation time 502896035 ps
CPU time 0.76 seconds
Started Jan 24 12:49:20 PM PST 24
Finished Jan 24 12:49:47 PM PST 24
Peak memory 183116 kb
Host smart-ba7b5d08-c9c3-48da-811b-abd1f9a5260c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549471420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1549471420
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.926357458
Short name T323
Test name
Test status
Simulation time 304745546 ps
CPU time 0.98 seconds
Started Jan 24 12:49:14 PM PST 24
Finished Jan 24 12:49:46 PM PST 24
Peak memory 183144 kb
Host smart-d3df7068-234d-455c-a1a3-40c672b0c324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926357458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.926357458
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.601074900
Short name T305
Test name
Test status
Simulation time 443274140 ps
CPU time 1.1 seconds
Started Jan 24 12:55:49 PM PST 24
Finished Jan 24 12:56:26 PM PST 24
Peak memory 183120 kb
Host smart-6c53a5d8-8a43-48d6-bd68-a75fb497ad87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601074900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.601074900
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.827421162
Short name T316
Test name
Test status
Simulation time 490265494 ps
CPU time 0.84 seconds
Started Jan 24 12:49:23 PM PST 24
Finished Jan 24 12:49:49 PM PST 24
Peak memory 183352 kb
Host smart-229b5dc1-0514-4d74-a11f-340c94371ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827421162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.827421162
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.790033804
Short name T365
Test name
Test status
Simulation time 423299600 ps
CPU time 0.62 seconds
Started Jan 24 01:26:27 PM PST 24
Finished Jan 24 01:27:24 PM PST 24
Peak memory 183444 kb
Host smart-0b8ff565-fa1c-483a-9a57-291c3a19936c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790033804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.790033804
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1151788178
Short name T397
Test name
Test status
Simulation time 441077029 ps
CPU time 0.83 seconds
Started Jan 24 12:59:01 PM PST 24
Finished Jan 24 12:59:27 PM PST 24
Peak memory 183344 kb
Host smart-9a27478f-e5da-43d9-87b8-fb80c9d08bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151788178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1151788178
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1781668599
Short name T350
Test name
Test status
Simulation time 534164119 ps
CPU time 0.69 seconds
Started Jan 24 12:53:06 PM PST 24
Finished Jan 24 12:53:14 PM PST 24
Peak memory 183048 kb
Host smart-dbf190f9-1e32-49b7-8cc7-51b02f10feb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781668599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1781668599
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3284720522
Short name T358
Test name
Test status
Simulation time 476129328 ps
CPU time 1.24 seconds
Started Jan 24 12:49:20 PM PST 24
Finished Jan 24 12:49:48 PM PST 24
Peak memory 183052 kb
Host smart-44d73239-5884-4180-8e0b-37814a66974a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284720522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3284720522
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1211270438
Short name T332
Test name
Test status
Simulation time 604676479 ps
CPU time 0.86 seconds
Started Jan 24 12:48:25 PM PST 24
Finished Jan 24 12:48:57 PM PST 24
Peak memory 195452 kb
Host smart-7f48486f-3b55-463f-bff2-de711f379f73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211270438 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1211270438
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2456598340
Short name T60
Test name
Test status
Simulation time 364244607 ps
CPU time 1.04 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 183224 kb
Host smart-292bc056-799a-4e71-ad63-a0a9ea977229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456598340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2456598340
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3890296852
Short name T22
Test name
Test status
Simulation time 356570458 ps
CPU time 0.92 seconds
Started Jan 24 12:48:28 PM PST 24
Finished Jan 24 12:48:58 PM PST 24
Peak memory 183352 kb
Host smart-5900a09d-7781-4295-9393-4bba09765799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890296852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3890296852
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.128152758
Short name T426
Test name
Test status
Simulation time 1382220304 ps
CPU time 0.99 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 193488 kb
Host smart-da4f319a-c379-4f1c-9ae2-de037b962fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128152758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.128152758
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.1827280702
Short name T409
Test name
Test status
Simulation time 544042784 ps
CPU time 2.8 seconds
Started Jan 24 12:48:27 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 198236 kb
Host smart-d33f9fdd-1b40-43f0-9e86-639d47cebc3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827280702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.1827280702
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2795321471
Short name T381
Test name
Test status
Simulation time 573519448 ps
CPU time 0.74 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 196072 kb
Host smart-b3626644-a699-467d-8e70-903e03aebd45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795321471 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2795321471
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.889283209
Short name T355
Test name
Test status
Simulation time 655276296 ps
CPU time 0.61 seconds
Started Jan 24 12:48:29 PM PST 24
Finished Jan 24 12:48:59 PM PST 24
Peak memory 183392 kb
Host smart-026bd078-07fa-4a32-bfcf-419cf055094c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889283209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.889283209
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3224723828
Short name T340
Test name
Test status
Simulation time 294060371 ps
CPU time 0.63 seconds
Started Jan 24 12:48:31 PM PST 24
Finished Jan 24 12:49:01 PM PST 24
Peak memory 183092 kb
Host smart-e02be723-6209-4e92-9d42-9899341a45f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224723828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3224723828
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.393825400
Short name T401
Test name
Test status
Simulation time 1669131762 ps
CPU time 2.11 seconds
Started Jan 24 12:48:29 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 194916 kb
Host smart-2b1717e7-2018-4674-a57f-32f306139744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393825400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.393825400
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.599645821
Short name T386
Test name
Test status
Simulation time 566602883 ps
CPU time 1.59 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:16 PM PST 24
Peak memory 198068 kb
Host smart-ca30dd4c-4f6e-46f8-8913-1a6a5e657f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599645821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.599645821
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.76055778
Short name T356
Test name
Test status
Simulation time 4528980194 ps
CPU time 7.06 seconds
Started Jan 24 12:48:30 PM PST 24
Finished Jan 24 12:49:07 PM PST 24
Peak memory 195816 kb
Host smart-8f793d50-da78-4977-a489-3d42ae327241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76055778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_i
ntg_err.76055778
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1696685974
Short name T379
Test name
Test status
Simulation time 470361147 ps
CPU time 0.82 seconds
Started Jan 24 12:48:31 PM PST 24
Finished Jan 24 12:49:01 PM PST 24
Peak memory 194876 kb
Host smart-9a3ab666-12dd-47a5-b542-c084a34978c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696685974 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1696685974
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.549970325
Short name T391
Test name
Test status
Simulation time 468857843 ps
CPU time 1.2 seconds
Started Jan 24 12:48:31 PM PST 24
Finished Jan 24 12:49:02 PM PST 24
Peak memory 183372 kb
Host smart-215649eb-f78a-4d02-a937-43110047870f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549970325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.549970325
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1968720656
Short name T312
Test name
Test status
Simulation time 338513965 ps
CPU time 0.79 seconds
Started Jan 24 12:55:47 PM PST 24
Finished Jan 24 12:56:22 PM PST 24
Peak memory 183120 kb
Host smart-a5289cf6-6973-4d79-8563-c0ce28949786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968720656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1968720656
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.413489811
Short name T75
Test name
Test status
Simulation time 1818614055 ps
CPU time 1.29 seconds
Started Jan 24 12:48:32 PM PST 24
Finished Jan 24 12:49:03 PM PST 24
Peak memory 194564 kb
Host smart-418ca17e-a5cd-4907-85f8-c0786a45fdce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413489811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.413489811
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2817239897
Short name T361
Test name
Test status
Simulation time 448177366 ps
CPU time 1.33 seconds
Started Jan 24 12:48:29 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 198204 kb
Host smart-74f4d545-0e56-41a6-b159-e1b449fb412d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817239897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2817239897
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1914933624
Short name T307
Test name
Test status
Simulation time 8836306950 ps
CPU time 14.92 seconds
Started Jan 24 12:48:29 PM PST 24
Finished Jan 24 12:49:13 PM PST 24
Peak memory 197312 kb
Host smart-e0978dfd-f580-4d6c-aeed-9b60ee07aa39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914933624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1914933624
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1526346921
Short name T384
Test name
Test status
Simulation time 424050589 ps
CPU time 1.34 seconds
Started Jan 24 12:48:29 PM PST 24
Finished Jan 24 12:49:00 PM PST 24
Peak memory 195304 kb
Host smart-ab4b17e1-59ce-47a3-8881-f8d9514156c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526346921 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1526346921
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.622180930
Short name T317
Test name
Test status
Simulation time 388904935 ps
CPU time 0.72 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 183300 kb
Host smart-918c9c7f-1b52-4263-8891-d7772beea6c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622180930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.622180930
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.108109167
Short name T370
Test name
Test status
Simulation time 407497529 ps
CPU time 0.68 seconds
Started Jan 24 12:48:33 PM PST 24
Finished Jan 24 12:49:03 PM PST 24
Peak memory 183044 kb
Host smart-871f479d-691a-487d-8b88-c137ae96a18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108109167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.108109167
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1884677845
Short name T2
Test name
Test status
Simulation time 1169013535 ps
CPU time 2.84 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:29 PM PST 24
Peak memory 193776 kb
Host smart-f2cebcf6-0904-4c7a-8301-7af80b12ff62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884677845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1884677845
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3395355213
Short name T413
Test name
Test status
Simulation time 1341792644 ps
CPU time 1.87 seconds
Started Jan 24 01:31:03 PM PST 24
Finished Jan 24 01:31:55 PM PST 24
Peak memory 198352 kb
Host smart-68601c0d-8d17-43b9-9893-773d2454dfc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395355213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3395355213
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3417696406
Short name T83
Test name
Test status
Simulation time 4101894748 ps
CPU time 7.32 seconds
Started Jan 24 12:48:46 PM PST 24
Finished Jan 24 12:49:34 PM PST 24
Peak memory 195584 kb
Host smart-93de7722-707a-4ddf-9b57-91072112f5ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417696406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3417696406
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.227248550
Short name T359
Test name
Test status
Simulation time 466514694 ps
CPU time 0.79 seconds
Started Jan 24 12:48:33 PM PST 24
Finished Jan 24 12:49:03 PM PST 24
Peak memory 194740 kb
Host smart-ee1b91c1-01f3-4a90-8b43-04936b59ae6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227248550 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.227248550
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1004872660
Short name T383
Test name
Test status
Simulation time 507609398 ps
CPU time 1.46 seconds
Started Jan 24 12:48:33 PM PST 24
Finished Jan 24 12:49:04 PM PST 24
Peak memory 192692 kb
Host smart-0f258d71-4220-4712-9475-839d9357e179
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004872660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1004872660
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1193017030
Short name T387
Test name
Test status
Simulation time 516825957 ps
CPU time 0.7 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:15 PM PST 24
Peak memory 182900 kb
Host smart-22544b6d-7116-408e-b472-aa86d47f380f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193017030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1193017030
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4151451276
Short name T74
Test name
Test status
Simulation time 1797793793 ps
CPU time 1.71 seconds
Started Jan 24 12:48:39 PM PST 24
Finished Jan 24 12:49:16 PM PST 24
Peak memory 194788 kb
Host smart-c07ff824-be7c-425d-bd55-a317451da2ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151451276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4151451276
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1088452249
Short name T52
Test name
Test status
Simulation time 481360168 ps
CPU time 1.8 seconds
Started Jan 24 12:48:43 PM PST 24
Finished Jan 24 12:49:22 PM PST 24
Peak memory 197788 kb
Host smart-ec6ebb76-663a-42da-be45-8f73931d03cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088452249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1088452249
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.756549701
Short name T3
Test name
Test status
Simulation time 8071684519 ps
CPU time 13.97 seconds
Started Jan 24 12:48:35 PM PST 24
Finished Jan 24 12:49:23 PM PST 24
Peak memory 197252 kb
Host smart-f1ee38c6-4f17-449e-a207-e2ffded23956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756549701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_
intg_err.756549701
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.2018815754
Short name T26
Test name
Test status
Simulation time 499014019 ps
CPU time 1.18 seconds
Started Jan 24 12:52:24 PM PST 24
Finished Jan 24 12:52:42 PM PST 24
Peak memory 182916 kb
Host smart-8b4b85e2-fa3c-4472-abcc-20057b8f23c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018815754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.2018815754
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.4216533986
Short name T261
Test name
Test status
Simulation time 15143431442 ps
CPU time 24.85 seconds
Started Jan 24 12:52:25 PM PST 24
Finished Jan 24 12:53:06 PM PST 24
Peak memory 182900 kb
Host smart-f36c7112-f01f-484d-88df-bf3c4e19bf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216533986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.4216533986
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2359924047
Short name T49
Test name
Test status
Simulation time 351885285 ps
CPU time 0.7 seconds
Started Jan 24 12:52:23 PM PST 24
Finished Jan 24 12:52:41 PM PST 24
Peak memory 182964 kb
Host smart-cdde2405-265c-4872-b333-12d3a7a5529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359924047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2359924047
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2201938804
Short name T233
Test name
Test status
Simulation time 45384954880 ps
CPU time 481.71 seconds
Started Jan 24 01:09:06 PM PST 24
Finished Jan 24 01:17:42 PM PST 24
Peak memory 197932 kb
Host smart-3d681a8c-d1fe-4ba1-99e5-01be706307fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201938804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2201938804
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2900627472
Short name T16
Test name
Test status
Simulation time 477909346 ps
CPU time 1.3 seconds
Started Jan 24 12:52:35 PM PST 24
Finished Jan 24 12:52:49 PM PST 24
Peak memory 182880 kb
Host smart-8893263d-173c-4897-8545-202d49d3210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900627472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2900627472
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3917560012
Short name T27
Test name
Test status
Simulation time 54783603724 ps
CPU time 21.56 seconds
Started Jan 24 12:52:37 PM PST 24
Finished Jan 24 12:53:10 PM PST 24
Peak memory 183100 kb
Host smart-74a4d7ba-dbb9-4cf2-8551-7a50dc2e7dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917560012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3917560012
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.716049339
Short name T30
Test name
Test status
Simulation time 4402280201 ps
CPU time 3.89 seconds
Started Jan 24 01:03:11 PM PST 24
Finished Jan 24 01:03:39 PM PST 24
Peak memory 214960 kb
Host smart-28ac01ef-d94b-49f5-af9a-9d002a1bd402
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716049339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.716049339
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2016892508
Short name T184
Test name
Test status
Simulation time 568996671 ps
CPU time 1.43 seconds
Started Jan 24 12:52:24 PM PST 24
Finished Jan 24 12:52:42 PM PST 24
Peak memory 182704 kb
Host smart-26342bbb-6c82-4116-bc34-42f441fa0b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016892508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2016892508
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1617639906
Short name T268
Test name
Test status
Simulation time 115756502152 ps
CPU time 146.48 seconds
Started Jan 24 12:52:38 PM PST 24
Finished Jan 24 12:55:16 PM PST 24
Peak memory 182856 kb
Host smart-e446ccc5-2524-495e-932c-082d0eb91a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617639906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1617639906
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.642690095
Short name T225
Test name
Test status
Simulation time 429512099 ps
CPU time 1.26 seconds
Started Jan 24 01:20:05 PM PST 24
Finished Jan 24 01:21:10 PM PST 24
Peak memory 183000 kb
Host smart-9d966950-c3a8-44af-a9ad-4bc3d043b236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642690095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.642690095
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4093249090
Short name T197
Test name
Test status
Simulation time 31011691402 ps
CPU time 14.77 seconds
Started Jan 24 01:02:52 PM PST 24
Finished Jan 24 01:03:28 PM PST 24
Peak memory 183052 kb
Host smart-63779405-b5f0-46c6-b885-cd7d5df9af2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093249090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4093249090
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.889696165
Short name T47
Test name
Test status
Simulation time 452671184 ps
CPU time 0.67 seconds
Started Jan 24 01:03:38 PM PST 24
Finished Jan 24 01:04:14 PM PST 24
Peak memory 182804 kb
Host smart-ae8dfc6e-d080-4f68-8509-f82fe073cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889696165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.889696165
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.294189031
Short name T45
Test name
Test status
Simulation time 232853548971 ps
CPU time 234.94 seconds
Started Jan 24 12:52:57 PM PST 24
Finished Jan 24 12:57:02 PM PST 24
Peak memory 183064 kb
Host smart-947617fe-d64f-4b7f-9c57-96d29715db67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294189031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.294189031
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2012625409
Short name T215
Test name
Test status
Simulation time 104727345137 ps
CPU time 1126.98 seconds
Started Jan 24 01:16:10 PM PST 24
Finished Jan 24 01:35:38 PM PST 24
Peak memory 205212 kb
Host smart-ea40febb-354d-47a7-85c5-d6ef81326f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012625409 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2012625409
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3224253654
Short name T277
Test name
Test status
Simulation time 643266302 ps
CPU time 0.66 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 12:53:33 PM PST 24
Peak memory 182968 kb
Host smart-59faac00-38ed-4bef-bb32-0f3bcee10ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224253654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3224253654
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1973220942
Short name T191
Test name
Test status
Simulation time 35344479437 ps
CPU time 20.44 seconds
Started Jan 24 12:53:10 PM PST 24
Finished Jan 24 12:53:39 PM PST 24
Peak memory 183028 kb
Host smart-30cd703a-bf09-4d2f-8121-021bc80d486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973220942 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1973220942
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3826298398
Short name T192
Test name
Test status
Simulation time 336585917 ps
CPU time 1 seconds
Started Jan 24 12:52:59 PM PST 24
Finished Jan 24 12:53:09 PM PST 24
Peak memory 182904 kb
Host smart-9f26c8c2-237f-47cc-9139-9b79f7847b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826298398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3826298398
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.516777705
Short name T258
Test name
Test status
Simulation time 684351324495 ps
CPU time 256.07 seconds
Started Jan 24 12:53:11 PM PST 24
Finished Jan 24 12:57:36 PM PST 24
Peak memory 193136 kb
Host smart-eea54ea1-9105-4982-b11f-b4fbfa9d09b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516777705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.516777705
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2687225195
Short name T293
Test name
Test status
Simulation time 20018845191 ps
CPU time 142.88 seconds
Started Jan 24 12:53:13 PM PST 24
Finished Jan 24 12:55:49 PM PST 24
Peak memory 197764 kb
Host smart-c4d06e3d-1bcb-44f7-ad5f-631fb98edd2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687225195 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2687225195
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3410925062
Short name T150
Test name
Test status
Simulation time 373781476 ps
CPU time 1.08 seconds
Started Jan 24 12:53:18 PM PST 24
Finished Jan 24 12:53:36 PM PST 24
Peak memory 182852 kb
Host smart-ab472347-5e35-4156-906c-5ad9aa4f01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410925062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3410925062
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1550255828
Short name T241
Test name
Test status
Simulation time 42592839749 ps
CPU time 72.69 seconds
Started Jan 24 12:53:18 PM PST 24
Finished Jan 24 12:54:47 PM PST 24
Peak memory 182924 kb
Host smart-d0b67991-c242-4233-b21b-1e66f5926d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550255828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1550255828
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.863535347
Short name T149
Test name
Test status
Simulation time 574804851 ps
CPU time 0.91 seconds
Started Jan 24 12:53:14 PM PST 24
Finished Jan 24 12:53:27 PM PST 24
Peak memory 182760 kb
Host smart-a6656082-19be-4b52-bbd9-5781fe256522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863535347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.863535347
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2160253428
Short name T178
Test name
Test status
Simulation time 200528504709 ps
CPU time 150.92 seconds
Started Jan 24 01:09:33 PM PST 24
Finished Jan 24 01:12:43 PM PST 24
Peak memory 193412 kb
Host smart-9da3bde8-bf37-4299-9f4b-88f03b76ba7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160253428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2160253428
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.2301080651
Short name T289
Test name
Test status
Simulation time 59736905180 ps
CPU time 475.31 seconds
Started Jan 24 12:53:12 PM PST 24
Finished Jan 24 01:01:18 PM PST 24
Peak memory 197864 kb
Host smart-bbe0b00a-0edc-494e-ba07-46dbdfa64529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301080651 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.2301080651
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.866083269
Short name T229
Test name
Test status
Simulation time 457017690 ps
CPU time 0.74 seconds
Started Jan 24 12:53:18 PM PST 24
Finished Jan 24 12:53:35 PM PST 24
Peak memory 182856 kb
Host smart-9a3418b5-6918-438c-a0bc-533dfb5c67d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866083269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.866083269
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3763506396
Short name T155
Test name
Test status
Simulation time 27443273220 ps
CPU time 42.6 seconds
Started Jan 24 12:53:14 PM PST 24
Finished Jan 24 12:54:09 PM PST 24
Peak memory 183044 kb
Host smart-013cf674-5a86-4693-b263-4214627b2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763506396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3763506396
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.981158922
Short name T39
Test name
Test status
Simulation time 522916694 ps
CPU time 0.72 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 12:53:32 PM PST 24
Peak memory 182612 kb
Host smart-b82661ef-e4c7-482c-97fd-5bc961459a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981158922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.981158922
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3603578323
Short name T57
Test name
Test status
Simulation time 651470739234 ps
CPU time 1396.12 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 01:16:48 PM PST 24
Peak memory 208100 kb
Host smart-77354661-b952-4871-abc9-825f59cd6fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603578323 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3603578323
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1750611778
Short name T247
Test name
Test status
Simulation time 439337442 ps
CPU time 0.94 seconds
Started Jan 24 12:53:12 PM PST 24
Finished Jan 24 12:53:23 PM PST 24
Peak memory 182860 kb
Host smart-63cdf26d-5e47-4816-9fe7-cb083cc48367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750611778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1750611778
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1889238455
Short name T50
Test name
Test status
Simulation time 16453743308 ps
CPU time 13 seconds
Started Jan 24 12:53:12 PM PST 24
Finished Jan 24 12:53:35 PM PST 24
Peak memory 183020 kb
Host smart-7f7c2a5e-ce46-477e-a12b-4a27bd2a060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889238455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1889238455
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.648252370
Short name T246
Test name
Test status
Simulation time 473248296 ps
CPU time 0.69 seconds
Started Jan 24 12:53:16 PM PST 24
Finished Jan 24 12:53:32 PM PST 24
Peak memory 182784 kb
Host smart-4a5bb2a0-a37a-4665-a827-c831f331037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648252370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.648252370
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.778231837
Short name T237
Test name
Test status
Simulation time 49332750348 ps
CPU time 75.55 seconds
Started Jan 24 12:53:26 PM PST 24
Finished Jan 24 12:55:00 PM PST 24
Peak memory 193080 kb
Host smart-3500f65c-7c10-4aab-bc51-76623d9a9096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778231837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.778231837
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2671099545
Short name T298
Test name
Test status
Simulation time 371812123 ps
CPU time 0.61 seconds
Started Jan 24 12:53:20 PM PST 24
Finished Jan 24 12:53:38 PM PST 24
Peak memory 182916 kb
Host smart-f3d49a8f-b14b-4433-acfa-6f49109bba5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671099545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2671099545
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1859901384
Short name T179
Test name
Test status
Simulation time 33309352654 ps
CPU time 11.09 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:53:49 PM PST 24
Peak memory 182948 kb
Host smart-d250c095-d8f0-4fcf-ac7d-c11b1f491912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859901384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1859901384
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2106752288
Short name T231
Test name
Test status
Simulation time 489961192 ps
CPU time 1.22 seconds
Started Jan 24 12:53:18 PM PST 24
Finished Jan 24 12:53:36 PM PST 24
Peak memory 182980 kb
Host smart-71688e26-b0ad-4e6d-af68-0eca80d38f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106752288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2106752288
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3109624785
Short name T40
Test name
Test status
Simulation time 273876089904 ps
CPU time 198.51 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:57:07 PM PST 24
Peak memory 193056 kb
Host smart-7e7a97bb-f9ba-4b0b-acc1-7c5cda61b23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109624785 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3109624785
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3491879423
Short name T77
Test name
Test status
Simulation time 426802099176 ps
CPU time 759.31 seconds
Started Jan 24 12:53:17 PM PST 24
Finished Jan 24 01:06:13 PM PST 24
Peak memory 209280 kb
Host smart-955cc1b1-6a96-4eef-87d5-d28df87978ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491879423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3491879423
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.800900131
Short name T119
Test name
Test status
Simulation time 396853608 ps
CPU time 0.65 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:49 PM PST 24
Peak memory 182952 kb
Host smart-918512e7-a3fc-4abd-891f-1fe809469179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800900131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.800900131
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3593932762
Short name T270
Test name
Test status
Simulation time 38770747352 ps
CPU time 62.55 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:54:41 PM PST 24
Peak memory 182984 kb
Host smart-5f7e2e6d-e0eb-4a31-98f4-01b093d9b299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593932762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3593932762
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2117309668
Short name T217
Test name
Test status
Simulation time 357279649 ps
CPU time 0.65 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:53:39 PM PST 24
Peak memory 182852 kb
Host smart-aa92c320-3733-4601-8fea-55277d340f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117309668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2117309668
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.685548126
Short name T102
Test name
Test status
Simulation time 164513002725 ps
CPU time 54.94 seconds
Started Jan 24 12:53:22 PM PST 24
Finished Jan 24 12:54:34 PM PST 24
Peak memory 193004 kb
Host smart-fa71e622-58a4-45e6-b7a6-298beb84cf07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685548126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.685548126
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.2774909179
Short name T251
Test name
Test status
Simulation time 274116435809 ps
CPU time 428.75 seconds
Started Jan 24 12:53:20 PM PST 24
Finished Jan 24 01:00:45 PM PST 24
Peak memory 197848 kb
Host smart-4c27aa90-8ccb-45c5-b308-f9c7cf53467b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774909179 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.2774909179
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.464592459
Short name T14
Test name
Test status
Simulation time 554655989 ps
CPU time 0.83 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182952 kb
Host smart-42807bda-a10c-4ebb-a71e-764257d16f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464592459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.464592459
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.106248075
Short name T141
Test name
Test status
Simulation time 24398579457 ps
CPU time 2.16 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 12:53:54 PM PST 24
Peak memory 182932 kb
Host smart-7ce09158-10d2-4708-a8f4-9f8cb4860327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106248075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.106248075
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1606116073
Short name T212
Test name
Test status
Simulation time 465404342 ps
CPU time 0.63 seconds
Started Jan 24 12:53:35 PM PST 24
Finished Jan 24 12:53:55 PM PST 24
Peak memory 182600 kb
Host smart-ef107108-80f2-499a-b1c8-3653c9ef45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606116073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1606116073
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1767390028
Short name T210
Test name
Test status
Simulation time 33366979102 ps
CPU time 49.04 seconds
Started Jan 24 12:53:26 PM PST 24
Finished Jan 24 12:54:33 PM PST 24
Peak memory 193376 kb
Host smart-58f842ca-c1a5-4fa7-923c-35be65e77b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767390028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1767390028
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.795793053
Short name T262
Test name
Test status
Simulation time 67004920317 ps
CPU time 560.38 seconds
Started Jan 24 12:53:35 PM PST 24
Finished Jan 24 01:03:15 PM PST 24
Peak memory 206052 kb
Host smart-4829e6ff-21b2-4f4c-937e-114aa028a0ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795793053 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.795793053
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1826621597
Short name T211
Test name
Test status
Simulation time 393848605 ps
CPU time 0.66 seconds
Started Jan 24 12:53:18 PM PST 24
Finished Jan 24 12:53:35 PM PST 24
Peak memory 183000 kb
Host smart-264c8819-11fc-4c75-bb41-10e7049570f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826621597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1826621597
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.652604391
Short name T282
Test name
Test status
Simulation time 4997020605 ps
CPU time 3.34 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:53:42 PM PST 24
Peak memory 182984 kb
Host smart-9719edbf-83a4-451b-81c4-6019efb2508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652604391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.652604391
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.4157870417
Short name T144
Test name
Test status
Simulation time 590907796 ps
CPU time 1.17 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182840 kb
Host smart-6d3346a6-815e-4e40-8b5e-dad1af26d3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157870417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.4157870417
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1378399414
Short name T161
Test name
Test status
Simulation time 195545702758 ps
CPU time 249.31 seconds
Started Jan 24 12:53:26 PM PST 24
Finished Jan 24 12:57:53 PM PST 24
Peak memory 191292 kb
Host smart-3fae32e5-44ce-4149-873c-db38fbedd2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378399414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1378399414
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1676009591
Short name T209
Test name
Test status
Simulation time 419134892 ps
CPU time 0.68 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 12:53:52 PM PST 24
Peak memory 182924 kb
Host smart-f5388507-82b4-4b9a-a04a-a628a45ebb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676009591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1676009591
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1733110601
Short name T175
Test name
Test status
Simulation time 41339502796 ps
CPU time 30.23 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 12:54:18 PM PST 24
Peak memory 183076 kb
Host smart-2f0e5b47-eb83-4f91-8de7-d652dfee64bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733110601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1733110601
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.498419711
Short name T205
Test name
Test status
Simulation time 486053002 ps
CPU time 1.29 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182868 kb
Host smart-3c0cea13-3f19-4299-bb46-6a581602f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498419711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.498419711
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.136987040
Short name T287
Test name
Test status
Simulation time 381089022549 ps
CPU time 529.84 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 01:02:38 PM PST 24
Peak memory 183124 kb
Host smart-15b50b7c-0f6f-4885-9389-c9d180a6059a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136987040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.136987040
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.151965606
Short name T165
Test name
Test status
Simulation time 37876788572 ps
CPU time 284.52 seconds
Started Jan 24 01:02:56 PM PST 24
Finished Jan 24 01:08:01 PM PST 24
Peak memory 197884 kb
Host smart-3465b163-d6e5-4664-ae41-0501c2c74beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151965606 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.151965606
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.158712423
Short name T208
Test name
Test status
Simulation time 593757922 ps
CPU time 1.35 seconds
Started Jan 24 01:13:41 PM PST 24
Finished Jan 24 01:14:06 PM PST 24
Peak memory 183012 kb
Host smart-7633ff65-6a01-4b02-aa82-9e93dfca6791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158712423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.158712423
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1288346215
Short name T288
Test name
Test status
Simulation time 17820329432 ps
CPU time 7.88 seconds
Started Jan 24 12:52:35 PM PST 24
Finished Jan 24 12:52:55 PM PST 24
Peak memory 182948 kb
Host smart-4b0de985-c590-41a6-9c99-79ca5544747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288346215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1288346215
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.554100562
Short name T28
Test name
Test status
Simulation time 7680389954 ps
CPU time 10.98 seconds
Started Jan 24 12:52:45 PM PST 24
Finished Jan 24 12:53:06 PM PST 24
Peak memory 215144 kb
Host smart-e35d1122-0afd-49cc-a0d7-eac40fc1ca8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554100562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.554100562
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3715883261
Short name T131
Test name
Test status
Simulation time 446223851 ps
CPU time 0.82 seconds
Started Jan 24 12:52:34 PM PST 24
Finished Jan 24 12:52:48 PM PST 24
Peak memory 182824 kb
Host smart-83ee2f0d-3c0e-481f-8534-990c920ecb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715883261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3715883261
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2160399309
Short name T17
Test name
Test status
Simulation time 276095155077 ps
CPU time 169.91 seconds
Started Jan 24 01:06:23 PM PST 24
Finished Jan 24 01:10:09 PM PST 24
Peak memory 183160 kb
Host smart-61a4944e-a7a0-46f5-903c-18e91d0d061f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160399309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2160399309
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.1062219783
Short name T81
Test name
Test status
Simulation time 126551155685 ps
CPU time 254.44 seconds
Started Jan 24 12:52:32 PM PST 24
Finished Jan 24 12:57:01 PM PST 24
Peak memory 206088 kb
Host smart-e9256a50-d778-4f91-92d5-81746ba8d441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062219783 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.1062219783
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4034077099
Short name T37
Test name
Test status
Simulation time 526541072 ps
CPU time 1.21 seconds
Started Jan 24 12:53:26 PM PST 24
Finished Jan 24 12:53:45 PM PST 24
Peak memory 182972 kb
Host smart-e8cc34d8-0d9a-423b-9c95-c2bb9a240bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034077099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4034077099
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2610467579
Short name T147
Test name
Test status
Simulation time 31940201681 ps
CPU time 48.59 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 12:54:37 PM PST 24
Peak memory 183060 kb
Host smart-e84fb95f-4e89-4741-a065-ce61ad45b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610467579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2610467579
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.2141931073
Short name T221
Test name
Test status
Simulation time 392836117 ps
CPU time 1.06 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 12:53:49 PM PST 24
Peak memory 182780 kb
Host smart-e49b3d9b-137f-4640-87a4-b3c3de9e7faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141931073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.2141931073
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3185629575
Short name T94
Test name
Test status
Simulation time 136720262168 ps
CPU time 44.21 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:54:23 PM PST 24
Peak memory 183028 kb
Host smart-0eb98ab7-d14b-4597-878d-f38aef2e9883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185629575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3185629575
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4093561745
Short name T76
Test name
Test status
Simulation time 363806914124 ps
CPU time 584.43 seconds
Started Jan 24 01:08:25 PM PST 24
Finished Jan 24 01:18:44 PM PST 24
Peak memory 198364 kb
Host smart-3b0867e5-098b-491d-875a-bdf01e425a62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093561745 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4093561745
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.558080143
Short name T276
Test name
Test status
Simulation time 451382094 ps
CPU time 0.68 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 12:53:52 PM PST 24
Peak memory 182924 kb
Host smart-e2504146-6fb7-468f-8094-2cf4828d1149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558080143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.558080143
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3443294983
Short name T124
Test name
Test status
Simulation time 25904436625 ps
CPU time 38.33 seconds
Started Jan 24 12:53:35 PM PST 24
Finished Jan 24 12:54:33 PM PST 24
Peak memory 182772 kb
Host smart-1f770aae-4533-4892-8628-a682a7fdab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443294983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3443294983
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1102285737
Short name T198
Test name
Test status
Simulation time 343122988 ps
CPU time 1.02 seconds
Started Jan 24 12:53:20 PM PST 24
Finished Jan 24 12:53:37 PM PST 24
Peak memory 182756 kb
Host smart-f6962013-3d96-4b62-9be0-026ef8e69599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102285737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1102285737
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2049129841
Short name T186
Test name
Test status
Simulation time 125940562050 ps
CPU time 147.62 seconds
Started Jan 24 01:25:24 PM PST 24
Finished Jan 24 01:28:41 PM PST 24
Peak memory 183176 kb
Host smart-0fe7f8d2-3841-4c37-9118-adb1e5bf632a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049129841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2049129841
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.690068626
Short name T294
Test name
Test status
Simulation time 13538180473 ps
CPU time 153.42 seconds
Started Jan 24 12:53:24 PM PST 24
Finished Jan 24 12:56:15 PM PST 24
Peak memory 197892 kb
Host smart-e91741b9-4484-4bde-9e79-d12104e80e04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690068626 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.690068626
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2504941603
Short name T164
Test name
Test status
Simulation time 463986961 ps
CPU time 0.6 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:53:39 PM PST 24
Peak memory 182860 kb
Host smart-119a2236-3195-46f9-bc2f-717958113a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504941603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2504941603
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3034844358
Short name T18
Test name
Test status
Simulation time 30191955684 ps
CPU time 20.98 seconds
Started Jan 24 01:09:19 PM PST 24
Finished Jan 24 01:10:19 PM PST 24
Peak memory 183120 kb
Host smart-8ae7850d-ea45-40cd-94b1-d29222476da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034844358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3034844358
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2186362142
Short name T138
Test name
Test status
Simulation time 356318875 ps
CPU time 0.86 seconds
Started Jan 24 01:02:15 PM PST 24
Finished Jan 24 01:02:17 PM PST 24
Peak memory 182844 kb
Host smart-a8e819e2-8a4d-40e6-b206-f08b4e5f126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186362142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2186362142
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3262354133
Short name T93
Test name
Test status
Simulation time 5647592731 ps
CPU time 3.5 seconds
Started Jan 24 01:29:54 PM PST 24
Finished Jan 24 01:30:18 PM PST 24
Peak memory 183092 kb
Host smart-1241315e-e891-4971-b35d-fa75a222a740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262354133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3262354133
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.1028530774
Short name T259
Test name
Test status
Simulation time 134652801085 ps
CPU time 873.35 seconds
Started Jan 24 12:53:27 PM PST 24
Finished Jan 24 01:08:18 PM PST 24
Peak memory 209452 kb
Host smart-fd25aaf0-3545-4508-a51f-34998005701a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028530774 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.1028530774
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1744198940
Short name T100
Test name
Test status
Simulation time 415453383 ps
CPU time 0.68 seconds
Started Jan 24 12:53:34 PM PST 24
Finished Jan 24 12:53:53 PM PST 24
Peak memory 182920 kb
Host smart-b78f8f1a-f132-40e3-a30d-921d1aa12bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744198940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1744198940
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2981155763
Short name T158
Test name
Test status
Simulation time 10782477009 ps
CPU time 3.69 seconds
Started Jan 24 12:53:21 PM PST 24
Finished Jan 24 12:53:41 PM PST 24
Peak memory 183000 kb
Host smart-5481613f-16d7-403c-ac2f-ad6d00315c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981155763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2981155763
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.151141188
Short name T180
Test name
Test status
Simulation time 403699521 ps
CPU time 0.87 seconds
Started Jan 24 12:53:35 PM PST 24
Finished Jan 24 12:53:54 PM PST 24
Peak memory 182796 kb
Host smart-285554da-b3d3-4cd8-b35d-492d25eeeeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151141188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.151141188
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.821208149
Short name T200
Test name
Test status
Simulation time 256990902131 ps
CPU time 102.72 seconds
Started Jan 24 01:10:23 PM PST 24
Finished Jan 24 01:12:46 PM PST 24
Peak memory 194488 kb
Host smart-ff401ce9-8691-4e01-9ec0-fe1c6c753a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821208149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.821208149
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1435883903
Short name T218
Test name
Test status
Simulation time 150366717946 ps
CPU time 323.16 seconds
Started Jan 24 01:06:23 PM PST 24
Finished Jan 24 01:12:43 PM PST 24
Peak memory 197940 kb
Host smart-2db5d0dd-e6d3-47fc-8cfe-10b2fd0eaf48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435883903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1435883903
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1837167832
Short name T234
Test name
Test status
Simulation time 556339675 ps
CPU time 1.34 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 12:53:51 PM PST 24
Peak memory 182948 kb
Host smart-f6f9cf12-f084-44b2-b3ec-271a7dd51421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837167832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1837167832
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1566583464
Short name T166
Test name
Test status
Simulation time 23836762078 ps
CPU time 21.09 seconds
Started Jan 24 01:12:22 PM PST 24
Finished Jan 24 01:13:33 PM PST 24
Peak memory 183080 kb
Host smart-faf20923-8b09-4fa2-8273-c70c2e0d418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566583464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1566583464
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2643241558
Short name T133
Test name
Test status
Simulation time 568851439 ps
CPU time 0.71 seconds
Started Jan 24 01:20:33 PM PST 24
Finished Jan 24 01:21:44 PM PST 24
Peak memory 183028 kb
Host smart-1bb5d1d5-988a-4120-9723-0437bdaa91b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643241558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2643241558
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.967144474
Short name T242
Test name
Test status
Simulation time 198179136712 ps
CPU time 313.74 seconds
Started Jan 24 12:53:30 PM PST 24
Finished Jan 24 12:59:02 PM PST 24
Peak memory 183104 kb
Host smart-5f9fdbde-3ba9-4d77-9075-532643df84e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967144474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_a
ll.967144474
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4213552197
Short name T220
Test name
Test status
Simulation time 57615235847 ps
CPU time 635.67 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 01:04:24 PM PST 24
Peak memory 197992 kb
Host smart-b688ecbf-2658-4a82-9d48-a31880a55fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213552197 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4213552197
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2253780371
Short name T170
Test name
Test status
Simulation time 483729573 ps
CPU time 1.27 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 12:53:51 PM PST 24
Peak memory 182952 kb
Host smart-6505e20e-f617-4d9e-9e47-c55557be2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253780371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2253780371
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.497375230
Short name T136
Test name
Test status
Simulation time 28868444297 ps
CPU time 21.48 seconds
Started Jan 24 01:06:26 PM PST 24
Finished Jan 24 01:07:44 PM PST 24
Peak memory 183060 kb
Host smart-ab0df00c-74a9-422d-a730-2e92329ae81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497375230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.497375230
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2416576017
Short name T206
Test name
Test status
Simulation time 401251936 ps
CPU time 0.74 seconds
Started Jan 24 12:58:59 PM PST 24
Finished Jan 24 12:59:22 PM PST 24
Peak memory 182872 kb
Host smart-460cef84-9188-4d12-b8ac-a3794cb25ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416576017 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2416576017
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.339697191
Short name T46
Test name
Test status
Simulation time 184152825790 ps
CPU time 18.33 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:54:08 PM PST 24
Peak memory 183076 kb
Host smart-f5ffcecc-c2f9-4f79-be59-d9086f53f69e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339697191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.339697191
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.671410457
Short name T106
Test name
Test status
Simulation time 38988582517 ps
CPU time 193.09 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:57:01 PM PST 24
Peak memory 197856 kb
Host smart-c85afa96-a9ea-4aa8-870f-3b67c7afb586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671410457 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.671410457
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2590094496
Short name T278
Test name
Test status
Simulation time 512702886 ps
CPU time 1.37 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182976 kb
Host smart-f199ea68-4cbd-4a42-b5cc-40575ee07c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590094496 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2590094496
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2063213405
Short name T135
Test name
Test status
Simulation time 28682071055 ps
CPU time 3.1 seconds
Started Jan 24 01:40:18 PM PST 24
Finished Jan 24 01:41:18 PM PST 24
Peak memory 183084 kb
Host smart-c540b4d6-eb5e-4a51-b5bf-e865f2637673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063213405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2063213405
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3548499309
Short name T142
Test name
Test status
Simulation time 393622268 ps
CPU time 1.13 seconds
Started Jan 24 01:02:53 PM PST 24
Finished Jan 24 01:03:14 PM PST 24
Peak memory 182840 kb
Host smart-282568d7-83da-46c6-a49b-d927f1027b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548499309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3548499309
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.4257691758
Short name T80
Test name
Test status
Simulation time 16593377408 ps
CPU time 128.84 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:55:58 PM PST 24
Peak memory 197928 kb
Host smart-1ebdef9d-1d9d-4eab-a14b-df8d3dff3dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257691758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.4257691758
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2931003707
Short name T250
Test name
Test status
Simulation time 546924977 ps
CPU time 1.3 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182952 kb
Host smart-0c277719-890d-4bec-8b3f-64006b43b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931003707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2931003707
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3245576056
Short name T253
Test name
Test status
Simulation time 6981281490 ps
CPU time 9.9 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 183028 kb
Host smart-f2b87f55-2a9e-4347-b394-0f8641929dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245576056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3245576056
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3119908012
Short name T132
Test name
Test status
Simulation time 515615390 ps
CPU time 0.71 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182828 kb
Host smart-76ff0b21-de80-4c7c-aba3-d05aab81af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119908012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3119908012
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3541202414
Short name T207
Test name
Test status
Simulation time 67398234742 ps
CPU time 90.74 seconds
Started Jan 24 01:18:04 PM PST 24
Finished Jan 24 01:20:26 PM PST 24
Peak memory 183140 kb
Host smart-ac1471c0-34b7-409d-9b3e-8bf47ab6d7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541202414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3541202414
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3113729182
Short name T291
Test name
Test status
Simulation time 25960885957 ps
CPU time 274.57 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:58:23 PM PST 24
Peak memory 197908 kb
Host smart-44147799-1611-4bbc-ba04-4d7caa1fe5d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113729182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3113729182
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.888915029
Short name T33
Test name
Test status
Simulation time 578239303 ps
CPU time 0.98 seconds
Started Jan 24 12:53:36 PM PST 24
Finished Jan 24 12:53:57 PM PST 24
Peak memory 182972 kb
Host smart-da4885f9-d035-4aa4-adca-3aad0c1e6009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888915029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.888915029
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.3888815110
Short name T269
Test name
Test status
Simulation time 53193228796 ps
CPU time 84.5 seconds
Started Jan 24 12:53:27 PM PST 24
Finished Jan 24 12:55:09 PM PST 24
Peak memory 182948 kb
Host smart-849c7fc3-18a5-4cb6-8fb8-32360a067b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888815110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.3888815110
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2863831834
Short name T143
Test name
Test status
Simulation time 572514124 ps
CPU time 1.44 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:04 PM PST 24
Peak memory 182872 kb
Host smart-a8d3be01-ee30-4be6-9125-39fe431621df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863831834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2863831834
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.71259078
Short name T169
Test name
Test status
Simulation time 92925873616 ps
CPU time 15.76 seconds
Started Jan 24 12:53:37 PM PST 24
Finished Jan 24 12:54:12 PM PST 24
Peak memory 193420 kb
Host smart-30ae43de-e2d1-4e31-9c65-146794351147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71259078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_al
l.71259078
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.4031897491
Short name T110
Test name
Test status
Simulation time 455743093 ps
CPU time 1.19 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:50 PM PST 24
Peak memory 182988 kb
Host smart-94abbcda-2318-4df3-a26f-c6319052a21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031897491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.4031897491
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1615199152
Short name T252
Test name
Test status
Simulation time 31346753820 ps
CPU time 21.86 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:54:11 PM PST 24
Peak memory 183000 kb
Host smart-14c96ce9-ec56-4408-9df4-b23d3612a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615199152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1615199152
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.3172743642
Short name T227
Test name
Test status
Simulation time 375172265 ps
CPU time 0.81 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:49 PM PST 24
Peak memory 182684 kb
Host smart-195af153-ae6c-410d-b065-71717967e4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172743642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.3172743642
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1737653606
Short name T104
Test name
Test status
Simulation time 326487244291 ps
CPU time 466.96 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 01:01:36 PM PST 24
Peak memory 183124 kb
Host smart-e828874b-c3da-4edc-9363-35b2e71048ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737653606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1737653606
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3916218848
Short name T58
Test name
Test status
Simulation time 411852307050 ps
CPU time 381.75 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 01:00:21 PM PST 24
Peak memory 197940 kb
Host smart-5d8035e3-8a30-41d5-b9d0-79f135f5ea95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916218848 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3916218848
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.4175394173
Short name T172
Test name
Test status
Simulation time 475408997 ps
CPU time 0.69 seconds
Started Jan 24 01:04:41 PM PST 24
Finished Jan 24 01:05:20 PM PST 24
Peak memory 183000 kb
Host smart-98325e94-f844-4675-856b-f18bf5c61f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175394173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4175394173
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.719190026
Short name T239
Test name
Test status
Simulation time 26558936487 ps
CPU time 42.69 seconds
Started Jan 24 12:52:36 PM PST 24
Finished Jan 24 12:53:31 PM PST 24
Peak memory 183076 kb
Host smart-75cb8c01-dbec-4208-8b02-a1535296b9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719190026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.719190026
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.924321709
Short name T32
Test name
Test status
Simulation time 8374965955 ps
CPU time 1.8 seconds
Started Jan 24 12:52:43 PM PST 24
Finished Jan 24 12:52:55 PM PST 24
Peak memory 215208 kb
Host smart-d94e56fd-a429-412d-a8f6-906d96563f3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924321709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.924321709
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2834043537
Short name T173
Test name
Test status
Simulation time 465499149 ps
CPU time 0.74 seconds
Started Jan 24 12:52:36 PM PST 24
Finished Jan 24 12:52:49 PM PST 24
Peak memory 182948 kb
Host smart-ac94a3a2-afec-48fe-bacf-dae29a83b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834043537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2834043537
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1060056915
Short name T286
Test name
Test status
Simulation time 141641754436 ps
CPU time 244.47 seconds
Started Jan 24 12:52:37 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 197876 kb
Host smart-569a7c0d-57cb-40c1-a7d1-c17eb1a30ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060056915 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1060056915
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3109292269
Short name T226
Test name
Test status
Simulation time 448932575 ps
CPU time 0.91 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:04 PM PST 24
Peak memory 182996 kb
Host smart-ce9eb890-c3cc-45f6-8655-d4c9aade0dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109292269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3109292269
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2748978530
Short name T154
Test name
Test status
Simulation time 18584831171 ps
CPU time 7.83 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:53:57 PM PST 24
Peak memory 183052 kb
Host smart-4e62aff5-83b3-4144-a8c3-e0b2ef628c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748978530 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2748978530
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3151403569
Short name T199
Test name
Test status
Simulation time 435835334 ps
CPU time 0.69 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 12:54:00 PM PST 24
Peak memory 182864 kb
Host smart-8af38d12-2ade-4fb2-bfc6-59e527fe7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151403569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3151403569
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.35329502
Short name T95
Test name
Test status
Simulation time 158682790002 ps
CPU time 414.4 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 01:00:44 PM PST 24
Peak memory 197892 kb
Host smart-8717b006-218f-40a9-a742-bde9d259d87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35329502 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.35329502
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3118304037
Short name T116
Test name
Test status
Simulation time 414978841 ps
CPU time 0.96 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:04 PM PST 24
Peak memory 182996 kb
Host smart-33481c34-4b01-4a49-b3af-ba999553a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118304037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3118304037
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1663020793
Short name T125
Test name
Test status
Simulation time 41256143420 ps
CPU time 68.29 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:54:57 PM PST 24
Peak memory 182980 kb
Host smart-6fe3765d-5177-453d-95b5-89679daf55fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663020793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1663020793
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1385452922
Short name T181
Test name
Test status
Simulation time 612084374 ps
CPU time 0.79 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 12:53:49 PM PST 24
Peak memory 182800 kb
Host smart-96d42f27-7200-41aa-8f88-02c506640077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385452922 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1385452922
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.634804333
Short name T201
Test name
Test status
Simulation time 152391148012 ps
CPU time 59.12 seconds
Started Jan 24 12:53:36 PM PST 24
Finished Jan 24 12:54:54 PM PST 24
Peak memory 193164 kb
Host smart-73de6e28-ccea-4a0b-b4e3-0112f5763952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634804333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.634804333
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1276732183
Short name T232
Test name
Test status
Simulation time 166546761544 ps
CPU time 624.3 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 01:04:13 PM PST 24
Peak memory 198912 kb
Host smart-08f4f9ff-34e7-4f81-b773-cb68f8cb75a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276732183 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1276732183
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2911095347
Short name T290
Test name
Test status
Simulation time 562144549 ps
CPU time 0.74 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 12:54:01 PM PST 24
Peak memory 182992 kb
Host smart-18d32587-2e0f-4cec-a979-271140065517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911095347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2911095347
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.4002185370
Short name T156
Test name
Test status
Simulation time 52062189388 ps
CPU time 80.13 seconds
Started Jan 24 12:53:32 PM PST 24
Finished Jan 24 12:55:09 PM PST 24
Peak memory 183076 kb
Host smart-dc11dae0-0dac-460c-b855-c20c131ae5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002185370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.4002185370
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1034884894
Short name T284
Test name
Test status
Simulation time 509777337 ps
CPU time 1.31 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 12:54:00 PM PST 24
Peak memory 182988 kb
Host smart-3545d867-c4a5-4cae-9213-e20404896456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034884894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1034884894
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2986597844
Short name T190
Test name
Test status
Simulation time 305298447400 ps
CPU time 233.04 seconds
Started Jan 24 01:00:11 PM PST 24
Finished Jan 24 01:04:24 PM PST 24
Peak memory 193344 kb
Host smart-d405d44d-83a8-4ea6-90dc-ece867cbfdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986597844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2986597844
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.918756488
Short name T203
Test name
Test status
Simulation time 288656552430 ps
CPU time 702 seconds
Started Jan 24 12:53:31 PM PST 24
Finished Jan 24 01:05:31 PM PST 24
Peak memory 200340 kb
Host smart-7dd0d595-69a3-46b2-a672-403c7fffd8ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918756488 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.918756488
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2378163925
Short name T264
Test name
Test status
Simulation time 591387667 ps
CPU time 0.77 seconds
Started Jan 24 12:53:39 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 182976 kb
Host smart-236abeb6-8e9f-4672-89e6-3bb13fd36e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378163925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2378163925
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1902480581
Short name T123
Test name
Test status
Simulation time 23026067727 ps
CPU time 33.13 seconds
Started Jan 24 12:53:37 PM PST 24
Finished Jan 24 12:54:30 PM PST 24
Peak memory 182984 kb
Host smart-5b9b0de9-933f-4bf4-94d5-435dfbc5f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902480581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1902480581
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2355171298
Short name T139
Test name
Test status
Simulation time 537530581 ps
CPU time 1.39 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:04 PM PST 24
Peak memory 182996 kb
Host smart-d88bd3ae-f1be-4cd1-bc79-db7bb7e77c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355171298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2355171298
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.4000935372
Short name T244
Test name
Test status
Simulation time 26065001614 ps
CPU time 19.98 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 12:54:19 PM PST 24
Peak memory 191324 kb
Host smart-6839a22d-706c-47ba-960a-059ec70c1f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000935372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.4000935372
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2799272355
Short name T213
Test name
Test status
Simulation time 1972566415059 ps
CPU time 834.35 seconds
Started Jan 24 12:53:33 PM PST 24
Finished Jan 24 01:07:45 PM PST 24
Peak memory 201208 kb
Host smart-71d04800-cbdd-429b-92fc-75ead41cb9bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799272355 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2799272355
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1650025544
Short name T151
Test name
Test status
Simulation time 625180689 ps
CPU time 0.71 seconds
Started Jan 24 12:53:42 PM PST 24
Finished Jan 24 12:54:03 PM PST 24
Peak memory 183000 kb
Host smart-b6f99ff2-7c30-4e3f-a6ef-4fbe39a1b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650025544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1650025544
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2917275892
Short name T35
Test name
Test status
Simulation time 4925065825 ps
CPU time 1.95 seconds
Started Jan 24 12:53:39 PM PST 24
Finished Jan 24 12:54:00 PM PST 24
Peak memory 183052 kb
Host smart-7ba6f9a9-ca4e-42c3-ace5-dc5714e2f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917275892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2917275892
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1368934239
Short name T137
Test name
Test status
Simulation time 415949832 ps
CPU time 0.85 seconds
Started Jan 24 12:53:40 PM PST 24
Finished Jan 24 12:54:01 PM PST 24
Peak memory 182988 kb
Host smart-46eb8a00-01a2-4c0b-98d2-2a4e531265d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368934239 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1368934239
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3799479837
Short name T256
Test name
Test status
Simulation time 68312439568 ps
CPU time 39.3 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:54:47 PM PST 24
Peak memory 182868 kb
Host smart-4217e316-54ed-4313-8df7-962fa3ff2aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799479837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3799479837
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.670521227
Short name T157
Test name
Test status
Simulation time 91870731809 ps
CPU time 695.04 seconds
Started Jan 24 12:53:39 PM PST 24
Finished Jan 24 01:05:33 PM PST 24
Peak memory 198368 kb
Host smart-9a059d8d-11c5-4ba6-b29e-506bb2322368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670521227 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.670521227
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.4066398367
Short name T34
Test name
Test status
Simulation time 571825566 ps
CPU time 0.75 seconds
Started Jan 24 12:53:38 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 182956 kb
Host smart-d18cc3c7-58fa-42c8-b286-57799c0bcd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066398367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.4066398367
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1564998597
Short name T243
Test name
Test status
Simulation time 32291489713 ps
CPU time 51.99 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:55:00 PM PST 24
Peak memory 182240 kb
Host smart-e2b54796-0494-47d7-a7d4-3cbc07d31259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564998597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1564998597
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.770753257
Short name T163
Test name
Test status
Simulation time 429218755 ps
CPU time 0.63 seconds
Started Jan 24 01:36:10 PM PST 24
Finished Jan 24 01:36:44 PM PST 24
Peak memory 183016 kb
Host smart-01676e87-cb97-4a95-8b6f-33032a6df927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770753257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.770753257
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2261797238
Short name T111
Test name
Test status
Simulation time 320849834542 ps
CPU time 114.11 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:56:02 PM PST 24
Peak memory 182784 kb
Host smart-f3c5575c-6707-48ab-8f5f-08da41f54dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261797238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2261797238
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1543395169
Short name T99
Test name
Test status
Simulation time 414260276 ps
CPU time 0.7 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:54:08 PM PST 24
Peak memory 182764 kb
Host smart-e99a6cc1-88cc-4c7c-8957-153167b94fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543395169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1543395169
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3805429341
Short name T134
Test name
Test status
Simulation time 27369614421 ps
CPU time 9.55 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:54:17 PM PST 24
Peak memory 182884 kb
Host smart-5a2b0460-652d-4554-99b8-9060275ec533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805429341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3805429341
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3944801167
Short name T292
Test name
Test status
Simulation time 592525903 ps
CPU time 0.69 seconds
Started Jan 24 01:38:59 PM PST 24
Finished Jan 24 01:39:07 PM PST 24
Peak memory 183032 kb
Host smart-4496e950-b2e8-4917-9580-268f39a573d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944801167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3944801167
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1092953451
Short name T257
Test name
Test status
Simulation time 144343415933 ps
CPU time 64.35 seconds
Started Jan 24 12:53:41 PM PST 24
Finished Jan 24 12:55:06 PM PST 24
Peak memory 183124 kb
Host smart-1d60907b-9c98-4846-b222-4948c26834d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092953451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1092953451
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1078114519
Short name T148
Test name
Test status
Simulation time 27180194425 ps
CPU time 210.32 seconds
Started Jan 24 12:53:37 PM PST 24
Finished Jan 24 12:57:27 PM PST 24
Peak memory 197928 kb
Host smart-64eeb414-074d-499f-a476-c44425a22e8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078114519 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1078114519
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1154880214
Short name T196
Test name
Test status
Simulation time 423488953 ps
CPU time 1.15 seconds
Started Jan 24 12:53:38 PM PST 24
Finished Jan 24 12:53:59 PM PST 24
Peak memory 182956 kb
Host smart-241f2764-52f3-469f-a1af-ae077d94b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154880214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1154880214
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.20215292
Short name T159
Test name
Test status
Simulation time 30570617657 ps
CPU time 12.96 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:54:21 PM PST 24
Peak memory 182816 kb
Host smart-7a662a7f-b994-41fa-8d72-0039ba81350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20215292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.20215292
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2671797259
Short name T140
Test name
Test status
Simulation time 596154178 ps
CPU time 1.49 seconds
Started Jan 24 02:32:08 PM PST 24
Finished Jan 24 02:32:42 PM PST 24
Peak memory 183044 kb
Host smart-50b8a033-c3a0-477d-a828-fe848b802ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671797259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2671797259
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1558555056
Short name T36
Test name
Test status
Simulation time 260935260164 ps
CPU time 339.23 seconds
Started Jan 24 12:53:41 PM PST 24
Finished Jan 24 12:59:40 PM PST 24
Peak memory 183036 kb
Host smart-c5d23fac-942b-4000-a8a3-450f7e1afb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558555056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1558555056
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2091599429
Short name T98
Test name
Test status
Simulation time 146978775534 ps
CPU time 286.18 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:58:54 PM PST 24
Peak memory 197680 kb
Host smart-72d27546-5eaa-4de1-b16e-741339f6cbdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091599429 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2091599429
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2736724098
Short name T219
Test name
Test status
Simulation time 503502827 ps
CPU time 0.95 seconds
Started Jan 24 12:53:47 PM PST 24
Finished Jan 24 12:54:08 PM PST 24
Peak memory 182968 kb
Host smart-a6e1a810-fddd-4bcf-8557-d4659486e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736724098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2736724098
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.477713867
Short name T120
Test name
Test status
Simulation time 4846339609 ps
CPU time 7.15 seconds
Started Jan 24 12:53:35 PM PST 24
Finished Jan 24 12:54:01 PM PST 24
Peak memory 182868 kb
Host smart-ec558e06-f5f2-47bc-97d1-4993beb2f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477713867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.477713867
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.406965215
Short name T38
Test name
Test status
Simulation time 343037841 ps
CPU time 1.13 seconds
Started Jan 24 12:53:48 PM PST 24
Finished Jan 24 12:54:09 PM PST 24
Peak memory 181956 kb
Host smart-4b80f5cd-3269-411a-b091-ee0f66b60514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406965215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.406965215
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.117713876
Short name T194
Test name
Test status
Simulation time 222794647552 ps
CPU time 150.3 seconds
Started Jan 24 01:19:21 PM PST 24
Finished Jan 24 01:22:52 PM PST 24
Peak memory 183216 kb
Host smart-4a197c1d-571d-436d-acb0-be39b6952b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117713876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.117713876
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2622520958
Short name T216
Test name
Test status
Simulation time 21949149634 ps
CPU time 237.57 seconds
Started Jan 24 12:53:49 PM PST 24
Finished Jan 24 12:58:06 PM PST 24
Peak memory 197896 kb
Host smart-308b5981-8197-4ef5-b4be-74075c1a7203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622520958 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2622520958
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3693241703
Short name T162
Test name
Test status
Simulation time 546900239 ps
CPU time 1.37 seconds
Started Jan 24 12:53:52 PM PST 24
Finished Jan 24 12:54:11 PM PST 24
Peak memory 182968 kb
Host smart-25e0ef41-1cdd-4c60-8da1-286dd94f7cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693241703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3693241703
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.4285642402
Short name T126
Test name
Test status
Simulation time 44120899557 ps
CPU time 11.77 seconds
Started Jan 24 12:53:54 PM PST 24
Finished Jan 24 12:54:22 PM PST 24
Peak memory 183040 kb
Host smart-7432bd63-ca9b-4777-b797-48b5dde34021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285642402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.4285642402
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.413648276
Short name T255
Test name
Test status
Simulation time 495563714 ps
CPU time 0.72 seconds
Started Jan 24 12:53:53 PM PST 24
Finished Jan 24 12:54:11 PM PST 24
Peak memory 182924 kb
Host smart-03fdc7bf-801d-4380-8d95-e6ea098ee215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413648276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.413648276
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2424867054
Short name T112
Test name
Test status
Simulation time 259510647040 ps
CPU time 406.12 seconds
Started Jan 24 01:25:33 PM PST 24
Finished Jan 24 01:33:10 PM PST 24
Peak memory 193104 kb
Host smart-7d7b8b20-7618-4006-b47f-51d211226ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424867054 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2424867054
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2758069296
Short name T236
Test name
Test status
Simulation time 99951532584 ps
CPU time 441.1 seconds
Started Jan 24 01:15:08 PM PST 24
Finished Jan 24 01:23:00 PM PST 24
Peak memory 197944 kb
Host smart-d160e457-8896-4a90-83d6-cd7cfe81db05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758069296 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2758069296
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.660032399
Short name T109
Test name
Test status
Simulation time 447673558 ps
CPU time 0.89 seconds
Started Jan 24 02:04:16 PM PST 24
Finished Jan 24 02:05:08 PM PST 24
Peak memory 183028 kb
Host smart-f56213e3-0f2c-43ed-8c58-4b1747c4ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660032399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.660032399
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.953419089
Short name T273
Test name
Test status
Simulation time 27998469040 ps
CPU time 10.02 seconds
Started Jan 24 12:52:38 PM PST 24
Finished Jan 24 12:52:59 PM PST 24
Peak memory 182704 kb
Host smart-d4a2cada-483f-4406-8df6-5bb6fe657514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953419089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.953419089
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.2047334482
Short name T31
Test name
Test status
Simulation time 7579594545 ps
CPU time 2.86 seconds
Started Jan 24 01:33:06 PM PST 24
Finished Jan 24 01:33:35 PM PST 24
Peak memory 215252 kb
Host smart-906d9577-f940-410f-bc71-ed71711c1106
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047334482 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.2047334482
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2426400316
Short name T168
Test name
Test status
Simulation time 376558188 ps
CPU time 0.8 seconds
Started Jan 24 12:52:37 PM PST 24
Finished Jan 24 12:52:49 PM PST 24
Peak memory 182824 kb
Host smart-02a8db02-40ba-4c17-8ebb-ea3db29d83e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426400316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2426400316
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.996640814
Short name T114
Test name
Test status
Simulation time 118530217397 ps
CPU time 184.76 seconds
Started Jan 24 12:52:49 PM PST 24
Finished Jan 24 12:56:07 PM PST 24
Peak memory 194292 kb
Host smart-92c47805-4f3a-4fa3-abe3-aa9926405a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996640814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.996640814
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1463748291
Short name T260
Test name
Test status
Simulation time 677731018 ps
CPU time 0.61 seconds
Started Jan 24 12:53:53 PM PST 24
Finished Jan 24 12:54:11 PM PST 24
Peak memory 182988 kb
Host smart-3f88eda0-f101-47c0-9d84-a03901bb6be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463748291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1463748291
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.3182257124
Short name T195
Test name
Test status
Simulation time 39465169233 ps
CPU time 60.51 seconds
Started Jan 24 12:53:53 PM PST 24
Finished Jan 24 12:55:10 PM PST 24
Peak memory 182952 kb
Host smart-f8b5aadb-45f0-4c0b-8113-0a40e454dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182257124 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.3182257124
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1945774918
Short name T296
Test name
Test status
Simulation time 571472064 ps
CPU time 1.05 seconds
Started Jan 24 12:53:58 PM PST 24
Finished Jan 24 12:54:15 PM PST 24
Peak memory 182796 kb
Host smart-79146cc9-6369-4373-b8b9-348ee4d473b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945774918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1945774918
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3893064274
Short name T19
Test name
Test status
Simulation time 108719987437 ps
CPU time 112.05 seconds
Started Jan 24 12:53:53 PM PST 24
Finished Jan 24 12:56:02 PM PST 24
Peak memory 182976 kb
Host smart-38cdbf92-6f7a-475b-a2fc-316199fe1ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893064274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3893064274
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.469097714
Short name T91
Test name
Test status
Simulation time 574491755 ps
CPU time 0.96 seconds
Started Jan 24 12:53:53 PM PST 24
Finished Jan 24 12:54:12 PM PST 24
Peak memory 182856 kb
Host smart-d89a6ba2-56ee-477b-8a69-89fbba2cf839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469097714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.469097714
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3848365030
Short name T153
Test name
Test status
Simulation time 34499768063 ps
CPU time 49.53 seconds
Started Jan 24 12:53:54 PM PST 24
Finished Jan 24 12:55:00 PM PST 24
Peak memory 183044 kb
Host smart-25b8a302-ef94-4f37-8254-f459696b433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848365030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3848365030
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.872724933
Short name T189
Test name
Test status
Simulation time 609775284 ps
CPU time 1.54 seconds
Started Jan 24 12:53:55 PM PST 24
Finished Jan 24 12:54:12 PM PST 24
Peak memory 182684 kb
Host smart-ac0ae76c-5f75-454f-92bf-f1613214f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872724933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.872724933
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3575128718
Short name T88
Test name
Test status
Simulation time 323158084239 ps
CPU time 135.81 seconds
Started Jan 24 12:54:02 PM PST 24
Finished Jan 24 12:56:33 PM PST 24
Peak memory 182936 kb
Host smart-11082b1d-6753-47b3-b12c-b87ddc3cca66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575128718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3575128718
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3854758025
Short name T281
Test name
Test status
Simulation time 569455317 ps
CPU time 0.61 seconds
Started Jan 24 12:54:05 PM PST 24
Finished Jan 24 12:54:19 PM PST 24
Peak memory 183000 kb
Host smart-cb9bd267-90e7-4b51-84de-1973a9277737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854758025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3854758025
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.541077583
Short name T42
Test name
Test status
Simulation time 4253456632 ps
CPU time 1.8 seconds
Started Jan 24 12:53:58 PM PST 24
Finished Jan 24 12:54:15 PM PST 24
Peak memory 182912 kb
Host smart-5024f071-cbd9-4dd6-8a1d-fa79e74ec948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541077583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.541077583
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.222310966
Short name T230
Test name
Test status
Simulation time 468813339 ps
CPU time 1.26 seconds
Started Jan 24 12:54:05 PM PST 24
Finished Jan 24 12:54:20 PM PST 24
Peak memory 182640 kb
Host smart-d8b71616-d2d3-41fd-b3f7-797cccb06716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222310966 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.222310966
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.222190721
Short name T146
Test name
Test status
Simulation time 107585262621 ps
CPU time 74.23 seconds
Started Jan 24 12:53:59 PM PST 24
Finished Jan 24 12:55:28 PM PST 24
Peak memory 193172 kb
Host smart-04109d3f-9cff-4e54-8dcd-8fc1a8017fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222190721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.222190721
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2137544411
Short name T249
Test name
Test status
Simulation time 227425214688 ps
CPU time 356.35 seconds
Started Jan 24 12:54:02 PM PST 24
Finished Jan 24 01:00:13 PM PST 24
Peak memory 197764 kb
Host smart-a664b7a6-391a-44d1-94b8-b0c32bf8d441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137544411 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2137544411
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3095358608
Short name T297
Test name
Test status
Simulation time 567869079 ps
CPU time 0.75 seconds
Started Jan 24 12:54:28 PM PST 24
Finished Jan 24 12:54:38 PM PST 24
Peak memory 182880 kb
Host smart-65a258b0-d893-4f96-bc15-ee2dcd978189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095358608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3095358608
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1155245546
Short name T121
Test name
Test status
Simulation time 6448392948 ps
CPU time 10.71 seconds
Started Jan 24 12:54:28 PM PST 24
Finished Jan 24 12:54:47 PM PST 24
Peak memory 182900 kb
Host smart-072412d6-2b17-4f13-b3af-8344d9a28ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155245546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1155245546
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2156092603
Short name T299
Test name
Test status
Simulation time 529961686 ps
CPU time 0.66 seconds
Started Jan 24 12:54:34 PM PST 24
Finished Jan 24 12:54:43 PM PST 24
Peak memory 182788 kb
Host smart-2f38e5c2-9cb4-4027-9185-7ddd46f7ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156092603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2156092603
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.3430389423
Short name T25
Test name
Test status
Simulation time 303576433090 ps
CPU time 403.14 seconds
Started Jan 24 12:54:31 PM PST 24
Finished Jan 24 01:01:23 PM PST 24
Peak memory 206096 kb
Host smart-9febf370-52f9-4728-a658-ff8834b87326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430389423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.3430389423
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4254929494
Short name T105
Test name
Test status
Simulation time 551270669 ps
CPU time 0.72 seconds
Started Jan 24 12:54:34 PM PST 24
Finished Jan 24 12:54:43 PM PST 24
Peak memory 182912 kb
Host smart-d4ee3d94-ab82-4a65-8213-0bca22666517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254929494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4254929494
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.2751406751
Short name T235
Test name
Test status
Simulation time 4023771199 ps
CPU time 2.22 seconds
Started Jan 24 12:54:35 PM PST 24
Finished Jan 24 12:54:45 PM PST 24
Peak memory 182880 kb
Host smart-5923d743-07c6-4a6e-b9ba-a3bb7f6338e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751406751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.2751406751
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3009054714
Short name T193
Test name
Test status
Simulation time 386275113 ps
CPU time 1.16 seconds
Started Jan 24 12:54:30 PM PST 24
Finished Jan 24 12:54:39 PM PST 24
Peak memory 182832 kb
Host smart-f792f691-83da-4d1a-a1f8-711115fa8eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009054714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3009054714
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2436423879
Short name T245
Test name
Test status
Simulation time 85381926203 ps
CPU time 136.88 seconds
Started Jan 24 12:54:27 PM PST 24
Finished Jan 24 12:56:53 PM PST 24
Peak memory 194344 kb
Host smart-34748e65-4e10-4420-8bbb-b83efe43dd6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436423879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2436423879
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1637719676
Short name T97
Test name
Test status
Simulation time 28425926477 ps
CPU time 121.86 seconds
Started Jan 24 12:54:34 PM PST 24
Finished Jan 24 12:56:44 PM PST 24
Peak memory 197852 kb
Host smart-a168f342-8f03-4416-a5e3-cb2c8cea31ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637719676 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1637719676
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2623240868
Short name T53
Test name
Test status
Simulation time 477712822 ps
CPU time 0.74 seconds
Started Jan 24 12:54:34 PM PST 24
Finished Jan 24 12:54:43 PM PST 24
Peak memory 182916 kb
Host smart-25803c1e-8a13-4f3b-a3ef-d63f453cfdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623240868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2623240868
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.938851178
Short name T122
Test name
Test status
Simulation time 14411773844 ps
CPU time 19.88 seconds
Started Jan 24 12:54:29 PM PST 24
Finished Jan 24 12:54:57 PM PST 24
Peak memory 183028 kb
Host smart-039f95f4-52d1-4aca-a871-03d6e1aeae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938851178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.938851178
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.4275888378
Short name T254
Test name
Test status
Simulation time 571492678 ps
CPU time 0.79 seconds
Started Jan 24 12:54:31 PM PST 24
Finished Jan 24 12:54:41 PM PST 24
Peak memory 182872 kb
Host smart-5c0eff33-c4ba-4875-9c08-0d4a277b132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275888378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.4275888378
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1987723050
Short name T224
Test name
Test status
Simulation time 61106348294 ps
CPU time 43.23 seconds
Started Jan 24 12:54:32 PM PST 24
Finished Jan 24 12:55:24 PM PST 24
Peak memory 182976 kb
Host smart-4ea3f53a-1f87-4941-9987-4ba5435a085e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987723050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1987723050
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3816619791
Short name T238
Test name
Test status
Simulation time 256271301014 ps
CPU time 262.15 seconds
Started Jan 24 12:54:32 PM PST 24
Finished Jan 24 12:59:02 PM PST 24
Peak memory 197928 kb
Host smart-4bd37e7f-d6dd-4814-9cc6-3381ec78945f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816619791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3816619791
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.3563163609
Short name T117
Test name
Test status
Simulation time 480827127 ps
CPU time 0.56 seconds
Started Jan 24 12:54:32 PM PST 24
Finished Jan 24 12:54:41 PM PST 24
Peak memory 182856 kb
Host smart-0f6dc0eb-d8b7-4434-ab6d-d35b75c0a9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563163609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.3563163609
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4061621234
Short name T176
Test name
Test status
Simulation time 10311805942 ps
CPU time 15.92 seconds
Started Jan 24 12:54:31 PM PST 24
Finished Jan 24 12:54:56 PM PST 24
Peak memory 182924 kb
Host smart-4824f248-d6c7-47dc-bcbd-93599fdfc166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061621234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4061621234
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4233349516
Short name T41
Test name
Test status
Simulation time 469266206 ps
CPU time 1.01 seconds
Started Jan 24 12:54:35 PM PST 24
Finished Jan 24 12:54:44 PM PST 24
Peak memory 182756 kb
Host smart-6a511160-08c0-4c34-96d4-2d47b702da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233349516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4233349516
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.771356026
Short name T86
Test name
Test status
Simulation time 265523228356 ps
CPU time 199 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:58:14 PM PST 24
Peak memory 182988 kb
Host smart-1765d4c0-5792-42ae-9228-0a75cd74dae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771356026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.771356026
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.4246126032
Short name T214
Test name
Test status
Simulation time 76240286561 ps
CPU time 620.2 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 01:05:06 PM PST 24
Peak memory 198088 kb
Host smart-d4af94e4-829d-40d4-afbb-35a544664fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246126032 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.4246126032
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.399490760
Short name T152
Test name
Test status
Simulation time 443007295 ps
CPU time 1.35 seconds
Started Jan 24 12:54:40 PM PST 24
Finished Jan 24 12:54:47 PM PST 24
Peak memory 183000 kb
Host smart-ee42e47f-e235-4a42-a838-5aab29551170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399490760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.399490760
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.97490825
Short name T127
Test name
Test status
Simulation time 60177086108 ps
CPU time 22 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 12:55:07 PM PST 24
Peak memory 183044 kb
Host smart-a76b6900-b7d4-4b2f-971e-c04a1f6da223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97490825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.97490825
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1846622701
Short name T202
Test name
Test status
Simulation time 421874913 ps
CPU time 0.65 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 12:54:46 PM PST 24
Peak memory 182800 kb
Host smart-64053aec-4b2c-4eb4-8756-03bf3ffe6240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846622701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1846622701
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2440256765
Short name T248
Test name
Test status
Simulation time 201133181147 ps
CPU time 64.74 seconds
Started Jan 24 12:54:43 PM PST 24
Finished Jan 24 12:55:52 PM PST 24
Peak memory 194348 kb
Host smart-fb9818a6-7d93-45b3-a455-daa14bdacaf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440256765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2440256765
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1935919991
Short name T228
Test name
Test status
Simulation time 212577789144 ps
CPU time 890.22 seconds
Started Jan 24 12:54:35 PM PST 24
Finished Jan 24 01:09:33 PM PST 24
Peak memory 202304 kb
Host smart-e27a576b-0600-4849-83c2-2ef88f3a8780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935919991 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1935919991
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1486072064
Short name T87
Test name
Test status
Simulation time 550699966 ps
CPU time 0.75 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 12:54:46 PM PST 24
Peak memory 182948 kb
Host smart-27a9a228-6359-4e70-8316-104bc274552e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486072064 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1486072064
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3839530270
Short name T160
Test name
Test status
Simulation time 33060870018 ps
CPU time 45.81 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:55:41 PM PST 24
Peak memory 182948 kb
Host smart-b627083a-1b7a-4af1-bd72-c91bb1655a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839530270 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3839530270
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2479661079
Short name T171
Test name
Test status
Simulation time 457310029 ps
CPU time 1.21 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 12:54:47 PM PST 24
Peak memory 182840 kb
Host smart-dee9685c-ad1d-4674-ae3d-ac89f6137e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479661079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2479661079
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2260971567
Short name T103
Test name
Test status
Simulation time 247053470282 ps
CPU time 194.23 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:58:10 PM PST 24
Peak memory 192844 kb
Host smart-626cd5ab-71fe-4d3d-98e6-23266fe00e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260971567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2260971567
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1812564890
Short name T78
Test name
Test status
Simulation time 245665984882 ps
CPU time 297.46 seconds
Started Jan 24 12:54:39 PM PST 24
Finished Jan 24 12:59:43 PM PST 24
Peak memory 197928 kb
Host smart-cf6d1486-45ad-4e7a-bc69-bbeb0dc91806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812564890 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1812564890
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2644426975
Short name T271
Test name
Test status
Simulation time 589957044 ps
CPU time 0.87 seconds
Started Jan 24 12:54:47 PM PST 24
Finished Jan 24 12:54:56 PM PST 24
Peak memory 182540 kb
Host smart-e016864e-5bbf-4be8-9f41-8d00cabe9b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644426975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2644426975
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2821402733
Short name T188
Test name
Test status
Simulation time 11626902092 ps
CPU time 4.26 seconds
Started Jan 24 12:54:38 PM PST 24
Finished Jan 24 12:54:49 PM PST 24
Peak memory 182952 kb
Host smart-e12b55e1-98fd-420d-9bf4-b9941da886c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821402733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2821402733
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.4055355339
Short name T223
Test name
Test status
Simulation time 505774653 ps
CPU time 0.7 seconds
Started Jan 24 12:54:36 PM PST 24
Finished Jan 24 12:54:44 PM PST 24
Peak memory 182844 kb
Host smart-91f3f51c-6b3a-4bc8-ae75-dfbf49167329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055355339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.4055355339
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3021416565
Short name T20
Test name
Test status
Simulation time 193500442307 ps
CPU time 68.11 seconds
Started Jan 24 12:54:43 PM PST 24
Finished Jan 24 12:55:56 PM PST 24
Peak memory 183088 kb
Host smart-4d95768e-5f6d-4faa-8dea-81f37d81ff36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021416565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3021416565
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.3152844568
Short name T96
Test name
Test status
Simulation time 39145836315 ps
CPU time 199.05 seconds
Started Jan 24 12:54:43 PM PST 24
Finished Jan 24 12:58:08 PM PST 24
Peak memory 197852 kb
Host smart-3c556606-c1c8-41ea-a8a0-78f81d09bcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152844568 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.3152844568
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1171247406
Short name T108
Test name
Test status
Simulation time 459128560 ps
CPU time 1.23 seconds
Started Jan 24 12:52:47 PM PST 24
Finished Jan 24 12:52:59 PM PST 24
Peak memory 182928 kb
Host smart-31021f91-e413-48ed-bdd3-89dd6134d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171247406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1171247406
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2547801618
Short name T222
Test name
Test status
Simulation time 527601277 ps
CPU time 0.75 seconds
Started Jan 24 01:00:08 PM PST 24
Finished Jan 24 01:00:29 PM PST 24
Peak memory 182712 kb
Host smart-85e04004-c96f-4a19-b482-03206fb4610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547801618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2547801618
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2983047920
Short name T92
Test name
Test status
Simulation time 476395779664 ps
CPU time 714.32 seconds
Started Jan 24 12:55:38 PM PST 24
Finished Jan 24 01:08:03 PM PST 24
Peak memory 193096 kb
Host smart-51f3dba8-226c-4390-ab00-9433a9d14fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983047920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2983047920
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1911747944
Short name T283
Test name
Test status
Simulation time 17344146570 ps
CPU time 129.21 seconds
Started Jan 24 01:03:37 PM PST 24
Finished Jan 24 01:06:20 PM PST 24
Peak memory 197808 kb
Host smart-32ea8434-dd7e-424d-a355-f830fd212c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911747944 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1911747944
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3868078919
Short name T272
Test name
Test status
Simulation time 604039623 ps
CPU time 0.79 seconds
Started Jan 24 01:22:10 PM PST 24
Finished Jan 24 01:23:10 PM PST 24
Peak memory 183024 kb
Host smart-2e9a1365-b90a-4712-a761-0da554e15542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868078919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3868078919
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2157960130
Short name T204
Test name
Test status
Simulation time 24848301242 ps
CPU time 40.63 seconds
Started Jan 24 01:04:46 PM PST 24
Finished Jan 24 01:06:08 PM PST 24
Peak memory 183024 kb
Host smart-29f84f8a-fda3-4b5f-9fcc-846be1a6d862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157960130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2157960130
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.584624169
Short name T182
Test name
Test status
Simulation time 517308668 ps
CPU time 0.95 seconds
Started Jan 24 12:52:49 PM PST 24
Finished Jan 24 12:53:03 PM PST 24
Peak memory 182848 kb
Host smart-c429045e-0ad7-46d9-83a1-138311c7f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584624169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.584624169
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.447500738
Short name T177
Test name
Test status
Simulation time 7006733916 ps
CPU time 5.92 seconds
Started Jan 24 01:02:08 PM PST 24
Finished Jan 24 01:02:20 PM PST 24
Peak memory 183012 kb
Host smart-225e4363-e40f-4d51-9f32-d62379f7e386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447500738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.447500738
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3242233523
Short name T279
Test name
Test status
Simulation time 118852605268 ps
CPU time 511.27 seconds
Started Jan 24 12:52:49 PM PST 24
Finished Jan 24 01:01:33 PM PST 24
Peak memory 197820 kb
Host smart-d7fb2527-e8c3-42c1-be3f-d80f39d21504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242233523 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3242233523
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3725978156
Short name T265
Test name
Test status
Simulation time 445841826 ps
CPU time 1.22 seconds
Started Jan 24 01:02:52 PM PST 24
Finished Jan 24 01:03:14 PM PST 24
Peak memory 182984 kb
Host smart-c2558836-a5d9-431d-a7b7-d36824bb1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725978156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3725978156
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.1832842399
Short name T275
Test name
Test status
Simulation time 18306916278 ps
CPU time 31.05 seconds
Started Jan 24 12:57:20 PM PST 24
Finished Jan 24 12:58:16 PM PST 24
Peak memory 183036 kb
Host smart-f17e895b-527d-4347-b7bb-c316b5efeee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832842399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.1832842399
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1901209807
Short name T43
Test name
Test status
Simulation time 400430569 ps
CPU time 0.72 seconds
Started Jan 24 12:52:49 PM PST 24
Finished Jan 24 12:53:03 PM PST 24
Peak memory 182724 kb
Host smart-0e532f6f-cc93-4f51-98ae-d48bc8d3b4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901209807 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1901209807
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1248430549
Short name T187
Test name
Test status
Simulation time 163058970851 ps
CPU time 272.54 seconds
Started Jan 24 01:30:57 PM PST 24
Finished Jan 24 01:36:19 PM PST 24
Peak memory 193448 kb
Host smart-24497188-9b9f-4071-be24-2e28edac4eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248430549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1248430549
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1403246383
Short name T295
Test name
Test status
Simulation time 443748048647 ps
CPU time 775.31 seconds
Started Jan 24 01:12:21 PM PST 24
Finished Jan 24 01:26:07 PM PST 24
Peak memory 200156 kb
Host smart-a0be53c6-db5f-47c1-bcd1-4503f7122111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403246383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1403246383
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3655492899
Short name T267
Test name
Test status
Simulation time 396335982 ps
CPU time 1.22 seconds
Started Jan 24 01:22:10 PM PST 24
Finished Jan 24 01:23:10 PM PST 24
Peak memory 183024 kb
Host smart-424c8adb-a7f7-4e3e-9180-fdfa1fcd7171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655492899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3655492899
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.3713933135
Short name T240
Test name
Test status
Simulation time 18367322486 ps
CPU time 28.84 seconds
Started Jan 24 12:52:56 PM PST 24
Finished Jan 24 12:53:35 PM PST 24
Peak memory 182896 kb
Host smart-2fcc5baf-cad7-463d-a4a8-040617e9d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713933135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.3713933135
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3821226127
Short name T174
Test name
Test status
Simulation time 593493675 ps
CPU time 1.35 seconds
Started Jan 24 01:13:18 PM PST 24
Finished Jan 24 01:13:54 PM PST 24
Peak memory 182968 kb
Host smart-c9673abf-178d-408a-bc96-8f8a654f8fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821226127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3821226127
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1904466133
Short name T285
Test name
Test status
Simulation time 118021734275 ps
CPU time 88.43 seconds
Started Jan 24 12:52:56 PM PST 24
Finished Jan 24 12:54:35 PM PST 24
Peak memory 182976 kb
Host smart-e062a457-9901-4608-80c4-adb3ed3b7ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904466133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1904466133
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.107721594
Short name T266
Test name
Test status
Simulation time 356185061386 ps
CPU time 396.2 seconds
Started Jan 24 12:52:56 PM PST 24
Finished Jan 24 12:59:43 PM PST 24
Peak memory 197708 kb
Host smart-897d391a-68e6-426b-90ed-d1789d8de224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107721594 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.107721594
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.33897363
Short name T263
Test name
Test status
Simulation time 460686421 ps
CPU time 0.67 seconds
Started Jan 24 12:52:58 PM PST 24
Finished Jan 24 12:53:09 PM PST 24
Peak memory 182908 kb
Host smart-14dc59f9-1b92-4ce4-b3f1-428ad4e8ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33897363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.33897363
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3870807790
Short name T145
Test name
Test status
Simulation time 17829671952 ps
CPU time 25.14 seconds
Started Jan 24 01:59:04 PM PST 24
Finished Jan 24 01:59:32 PM PST 24
Peak memory 183112 kb
Host smart-dc66e546-a40a-4e0d-acf6-5d71bda002a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870807790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3870807790
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.87838098
Short name T183
Test name
Test status
Simulation time 492087751 ps
CPU time 0.79 seconds
Started Jan 24 01:06:21 PM PST 24
Finished Jan 24 01:07:18 PM PST 24
Peak memory 182888 kb
Host smart-63d5e0c9-8b6e-4b44-af54-63a15fed7115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87838098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.87838098
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.663471972
Short name T118
Test name
Test status
Simulation time 288728225838 ps
CPU time 486.09 seconds
Started Jan 24 01:05:44 PM PST 24
Finished Jan 24 01:14:41 PM PST 24
Peak memory 183140 kb
Host smart-72665fb4-a4d0-4384-9201-b733ff40b590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663471972 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.663471972
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.20438484
Short name T167
Test name
Test status
Simulation time 76334160552 ps
CPU time 232.35 seconds
Started Jan 24 01:31:37 PM PST 24
Finished Jan 24 01:36:21 PM PST 24
Peak memory 197960 kb
Host smart-5ed92a59-7a9b-49ba-b4ef-e6fa3b1a36c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438484 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.20438484
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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