Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 26667 1 T18 10 T19 331 T20 86
bark[1] 443 1 T49 49 T96 22 T97 21
bark[2] 325 1 T103 37 T104 16 T105 16
bark[3] 508 1 T31 16 T105 16 T93 35
bark[4] 510 1 T106 12 T107 13 T44 16
bark[5] 404 1 T29 13 T53 17 T104 22
bark[6] 908 1 T47 54 T108 52 T84 12
bark[7] 668 1 T20 33 T103 30 T109 12
bark[8] 285 1 T20 16 T31 17 T93 104
bark[9] 763 1 T19 103 T60 12 T52 410
bark[10] 890 1 T105 61 T93 21 T63 133
bark[11] 526 1 T110 21 T111 12 T112 162
bark[12] 188 1 T97 52 T113 39 T114 16
bark[13] 346 1 T61 79 T63 116 T114 17
bark[14] 560 1 T24 26 T47 16 T115 16
bark[15] 452 1 T104 16 T116 16 T46 16
bark[16] 470 1 T49 157 T52 186 T53 26
bark[17] 391 1 T31 23 T51 17 T52 17
bark[18] 184 1 T19 17 T117 72 T118 16
bark[19] 453 1 T52 44 T104 27 T105 16
bark[20] 359 1 T52 16 T40 16 T119 26
bark[21] 574 1 T120 17 T116 42 T119 22
bark[22] 542 1 T53 216 T105 207 T93 17
bark[23] 637 1 T20 73 T105 222 T97 51
bark[24] 207 1 T50 12 T121 17 T122 12
bark[25] 468 1 T31 12 T123 12 T39 12
bark[26] 423 1 T19 16 T42 13 T124 16
bark[27] 345 1 T52 134 T98 22 T125 12
bark[28] 259 1 T30 21 T47 23 T126 12
bark[29] 463 1 T52 17 T127 35 T41 12
bark[30] 67 1 T128 16 T129 22 T130 16
bark[31] 432 1 T44 22 T61 16 T131 69
bark_0 3379 1 T13 10 T14 10 T16 10


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 26186 1 T18 9 T19 54 T20 86
bite[1] 135 1 T115 16 T126 11 T98 22
bite[2] 292 1 T52 16 T122 11 T40 16
bite[3] 212 1 T31 39 T104 16 T63 16
bite[4] 351 1 T97 20 T119 22 T63 132
bite[5] 424 1 T49 156 T53 26 T116 16
bite[6] 688 1 T53 215 T47 22 T63 115
bite[7] 378 1 T60 11 T127 34 T116 41
bite[8] 693 1 T52 33 T105 44 T93 17
bite[9] 214 1 T52 16 T104 21 T44 22
bite[10] 305 1 T107 12 T108 26 T63 167
bite[11] 1020 1 T20 73 T114 199 T132 16
bite[12] 552 1 T50 11 T106 11 T61 78
bite[13] 453 1 T51 17 T53 17 T105 206
bite[14] 473 1 T30 20 T40 16 T43 11
bite[15] 481 1 T103 30 T105 16 T46 31
bite[16] 464 1 T47 16 T108 26 T133 16
bite[17] 406 1 T52 28 T103 11 T44 16
bite[18] 389 1 T52 185 T39 11 T115 39
bite[19] 637 1 T19 273 T105 60 T47 23
bite[20] 329 1 T20 32 T29 12 T108 16
bite[21] 283 1 T19 17 T41 11 T46 16
bite[22] 574 1 T123 11 T105 176 T47 25
bite[23] 525 1 T19 118 T31 17 T93 34
bite[24] 310 1 T104 16 T93 103 T40 30
bite[25] 283 1 T93 21 T44 25 T97 52
bite[26] 676 1 T31 11 T52 17 T134 16
bite[27] 426 1 T49 48 T52 138 T97 50
bite[28] 215 1 T20 16 T121 17 T47 17
bite[29] 386 1 T104 27 T93 5 T61 17
bite[30] 552 1 T47 32 T97 82 T135 11
bite[31] 911 1 T52 393 T120 17 T103 37
bite_0 3873 1 T13 10 T14 10 T16 10


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 44096 1 T13 10 T14 10 T16 10


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 797 1 T20 28 T30 31 T104 15
prescale[1] 995 1 T30 2 T127 109 T104 18
prescale[2] 524 1 T49 45 T121 15 T103 18
prescale[3] 1047 1 T19 91 T24 43 T30 2
prescale[4] 872 1 T20 49 T24 8 T57 8
prescale[5] 590 1 T51 43 T120 29 T127 2
prescale[6] 760 1 T52 76 T136 8 T121 20
prescale[7] 787 1 T30 14 T49 45 T120 31
prescale[8] 759 1 T19 15 T33 8 T52 74
prescale[9] 735 1 T19 67 T127 25 T116 37
prescale[10] 853 1 T19 15 T49 70 T52 2
prescale[11] 549 1 T24 36 T30 2 T52 91
prescale[12] 715 1 T49 8 T127 15 T116 42
prescale[13] 457 1 T19 29 T137 8 T127 2
prescale[14] 309 1 T19 15 T32 8 T52 45
prescale[15] 539 1 T30 2 T127 114 T108 34
prescale[16] 568 1 T53 15 T121 8 T95 31
prescale[17] 594 1 T52 74 T120 15 T121 24
prescale[18] 697 1 T30 57 T49 15 T51 35
prescale[19] 879 1 T21 8 T24 43 T120 25
prescale[20] 812 1 T20 28 T31 43 T53 38
prescale[21] 797 1 T19 2 T20 15 T30 31
prescale[22] 458 1 T19 2 T22 8 T30 2
prescale[23] 642 1 T52 2 T127 59 T104 15
prescale[24] 609 1 T51 15 T52 73 T127 2
prescale[25] 467 1 T20 14 T30 2 T127 112
prescale[26] 454 1 T30 2 T51 15 T52 22
prescale[27] 596 1 T19 16 T30 31 T51 15
prescale[28] 584 1 T19 2 T138 8 T52 39
prescale[29] 438 1 T23 8 T30 25 T49 31
prescale[30] 482 1 T49 15 T51 15 T52 135
prescale[31] 636 1 T19 23 T30 2 T49 16
prescale_0 23095 1 T13 10 T14 10 T16 10


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33074 1 T13 10 T14 10 T16 10
auto[1] 11022 1 T18 8 T19 60 T20 46


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 44096 1 T13 10 T14 10 T16 10


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 26140 1 T18 11 T19 291 T20 113
wkup[1] 405 1 T105 26 T93 7 T97 16
wkup[2] 438 1 T60 13 T116 26 T105 32
wkup[3] 440 1 T19 16 T52 28 T127 16
wkup[4] 640 1 T20 16 T51 26 T52 49
wkup[5] 330 1 T30 16 T51 17 T120 16
wkup[6] 701 1 T49 16 T123 13 T107 14
wkup[7] 601 1 T29 14 T31 16 T52 16
wkup[8] 518 1 T127 16 T93 21 T44 16
wkup[9] 362 1 T30 38 T52 16 T53 26
wkup[10] 528 1 T52 26 T105 42 T93 16
wkup[11] 425 1 T49 16 T105 37 T93 17
wkup[12] 584 1 T19 16 T31 23 T52 42
wkup[13] 490 1 T52 17 T105 16 T93 22
wkup[14] 535 1 T19 16 T20 16 T50 13
wkup[15] 463 1 T24 21 T53 17 T121 17
wkup[16] 237 1 T19 16 T20 16 T105 16
wkup[17] 491 1 T30 16 T31 16 T53 21
wkup[18] 512 1 T19 26 T127 32 T105 16
wkup[19] 555 1 T19 16 T20 16 T24 26
wkup[20] 406 1 T52 13 T53 17 T127 22
wkup[21] 399 1 T52 16 T103 13 T61 16
wkup[22] 554 1 T52 29 T95 27 T40 16
wkup[23] 464 1 T52 49 T105 16 T47 23
wkup[24] 411 1 T31 17 T52 16 T116 16
wkup[25] 532 1 T19 26 T20 16 T30 26
wkup[26] 434 1 T19 16 T52 16 T93 16
wkup[27] 617 1 T19 33 T30 21 T127 26
wkup[28] 490 1 T127 25 T105 16 T95 48
wkup[29] 471 1 T52 61 T106 13 T127 16
wkup[30] 519 1 T31 13 T52 16 T120 17
wkup[31] 512 1 T20 16 T103 16 T105 16
wkup_0 2892 1 T13 10 T14 10 T16 10

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