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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.31 100.00 99.35 100.00 96.90


Total test records in report: 430
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T277 /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1607555383 Feb 04 12:55:52 PM PST 24 Feb 04 12:58:11 PM PST 24 35328130126 ps
T37 /workspace/coverage/default/1.aon_timer_sec_cm.2948802047 Feb 04 12:55:20 PM PST 24 Feb 04 12:55:23 PM PST 24 4128496600 ps
T278 /workspace/coverage/default/0.aon_timer_smoke.4053857353 Feb 04 12:54:46 PM PST 24 Feb 04 12:54:49 PM PST 24 381860129 ps
T279 /workspace/coverage/default/40.aon_timer_stress_all.3745689237 Feb 04 12:55:59 PM PST 24 Feb 04 12:56:32 PM PST 24 150993579608 ps
T280 /workspace/coverage/default/10.aon_timer_prescaler.1543900561 Feb 04 12:55:34 PM PST 24 Feb 04 12:56:18 PM PST 24 47226826975 ps
T281 /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2123298366 Feb 04 12:55:22 PM PST 24 Feb 04 01:09:29 PM PST 24 454607422272 ps
T282 /workspace/coverage/default/10.aon_timer_jump.630987185 Feb 04 12:55:26 PM PST 24 Feb 04 12:55:31 PM PST 24 581766204 ps
T283 /workspace/coverage/default/38.aon_timer_stress_all.3070171837 Feb 04 12:55:54 PM PST 24 Feb 04 12:57:07 PM PST 24 157337548792 ps
T284 /workspace/coverage/default/41.aon_timer_smoke.4001154330 Feb 04 12:55:59 PM PST 24 Feb 04 12:56:03 PM PST 24 370247225 ps
T285 /workspace/coverage/default/17.aon_timer_prescaler.263399146 Feb 04 12:55:38 PM PST 24 Feb 04 12:56:16 PM PST 24 40494326343 ps
T286 /workspace/coverage/default/21.aon_timer_jump.3903703465 Feb 04 12:55:25 PM PST 24 Feb 04 12:55:29 PM PST 24 561172408 ps
T287 /workspace/coverage/default/1.aon_timer_stress_all.751560472 Feb 04 12:55:21 PM PST 24 Feb 04 12:55:45 PM PST 24 43660876065 ps
T288 /workspace/coverage/default/16.aon_timer_stress_all.2230818201 Feb 04 12:55:24 PM PST 24 Feb 04 12:56:14 PM PST 24 122482540200 ps
T289 /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1610678670 Feb 04 12:55:27 PM PST 24 Feb 04 01:16:53 PM PST 24 509337131968 ps
T290 /workspace/coverage/default/4.aon_timer_stress_all.2083997307 Feb 04 12:55:19 PM PST 24 Feb 04 12:58:27 PM PST 24 149324898840 ps
T291 /workspace/coverage/default/45.aon_timer_prescaler.4263948643 Feb 04 12:55:53 PM PST 24 Feb 04 12:56:52 PM PST 24 37834977990 ps
T292 /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3527836321 Feb 04 12:55:40 PM PST 24 Feb 04 12:58:10 PM PST 24 30371564022 ps
T293 /workspace/coverage/default/30.aon_timer_prescaler.2717467436 Feb 04 12:55:44 PM PST 24 Feb 04 12:56:01 PM PST 24 5275199188 ps
T294 /workspace/coverage/default/24.aon_timer_jump.756902709 Feb 04 12:55:29 PM PST 24 Feb 04 12:55:33 PM PST 24 582043251 ps
T295 /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1019514986 Feb 04 12:55:45 PM PST 24 Feb 04 12:57:44 PM PST 24 86600999457 ps
T296 /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3756803862 Feb 04 12:55:18 PM PST 24 Feb 04 01:00:54 PM PST 24 539468043648 ps
T297 /workspace/coverage/default/21.aon_timer_stress_all.3950469196 Feb 04 12:55:29 PM PST 24 Feb 04 12:58:19 PM PST 24 394032290615 ps
T298 /workspace/coverage/default/17.aon_timer_smoke.426553648 Feb 04 12:55:28 PM PST 24 Feb 04 12:55:33 PM PST 24 474566617 ps
T299 /workspace/coverage/default/44.aon_timer_stress_all.2946924759 Feb 04 12:55:49 PM PST 24 Feb 04 12:56:21 PM PST 24 79766301574 ps
T300 /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3653748122 Feb 04 12:55:46 PM PST 24 Feb 04 12:57:53 PM PST 24 56961324680 ps
T301 /workspace/coverage/default/40.aon_timer_prescaler.2964821515 Feb 04 12:55:59 PM PST 24 Feb 04 12:56:05 PM PST 24 18067919816 ps
T302 /workspace/coverage/default/48.aon_timer_smoke.127256565 Feb 04 12:55:50 PM PST 24 Feb 04 12:55:54 PM PST 24 468684035 ps
T38 /workspace/coverage/default/2.aon_timer_sec_cm.1187139132 Feb 04 12:55:18 PM PST 24 Feb 04 12:55:29 PM PST 24 8148436519 ps
T303 /workspace/coverage/default/1.aon_timer_prescaler.1800186648 Feb 04 12:55:24 PM PST 24 Feb 04 12:55:44 PM PST 24 22781902289 ps
T304 /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2016748372 Feb 04 12:55:21 PM PST 24 Feb 04 01:08:05 PM PST 24 91908282493 ps
T305 /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.263602419 Feb 04 12:55:53 PM PST 24 Feb 04 01:00:35 PM PST 24 67495166168 ps
T306 /workspace/coverage/default/13.aon_timer_prescaler.1351846982 Feb 04 12:55:24 PM PST 24 Feb 04 12:55:35 PM PST 24 60112159082 ps
T307 /workspace/coverage/default/30.aon_timer_stress_all.781048233 Feb 04 12:55:37 PM PST 24 Feb 04 12:57:27 PM PST 24 294075465187 ps
T308 /workspace/coverage/default/47.aon_timer_jump.1822203238 Feb 04 12:55:52 PM PST 24 Feb 04 12:55:56 PM PST 24 575168688 ps
T309 /workspace/coverage/default/27.aon_timer_smoke.3184767989 Feb 04 12:55:41 PM PST 24 Feb 04 12:55:46 PM PST 24 382204976 ps
T310 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1319466975 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:25 PM PST 24 4388434027 ps
T89 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1267357499 Feb 04 12:50:26 PM PST 24 Feb 04 12:50:31 PM PST 24 2640801137 ps
T311 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1240146941 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:41 PM PST 24 485518820 ps
T90 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1523014957 Feb 04 12:50:39 PM PST 24 Feb 04 12:50:51 PM PST 24 966447378 ps
T312 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2661476329 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:39 PM PST 24 352850576 ps
T91 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1078615852 Feb 04 12:50:24 PM PST 24 Feb 04 12:50:29 PM PST 24 2125036848 ps
T313 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2352650406 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:46 PM PST 24 419293983 ps
T314 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.259005137 Feb 04 12:50:55 PM PST 24 Feb 04 12:50:58 PM PST 24 485766254 ps
T315 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1368078247 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:24 PM PST 24 639792332 ps
T316 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2443985655 Feb 04 12:50:53 PM PST 24 Feb 04 12:50:56 PM PST 24 353295753 ps
T92 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3882797899 Feb 04 12:50:30 PM PST 24 Feb 04 12:50:36 PM PST 24 1110340695 ps
T317 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.391949124 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:32 PM PST 24 575305512 ps
T318 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.860948837 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:33 PM PST 24 474169754 ps
T319 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1654979013 Feb 04 12:50:57 PM PST 24 Feb 04 12:50:59 PM PST 24 407953134 ps
T320 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.575311257 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 354626121 ps
T321 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1393866215 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:32 PM PST 24 785965847 ps
T100 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.879550165 Feb 04 12:50:39 PM PST 24 Feb 04 12:50:52 PM PST 24 8421943645 ps
T322 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.626024177 Feb 04 12:50:42 PM PST 24 Feb 04 12:50:50 PM PST 24 526294580 ps
T323 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1124375826 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:37 PM PST 24 552976931 ps
T324 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1312278441 Feb 04 12:50:30 PM PST 24 Feb 04 12:50:35 PM PST 24 469920372 ps
T325 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.618635406 Feb 04 12:50:39 PM PST 24 Feb 04 12:50:48 PM PST 24 343852429 ps
T326 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1898861468 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:42 PM PST 24 303840059 ps
T327 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2831888535 Feb 04 12:50:38 PM PST 24 Feb 04 12:50:48 PM PST 24 327253241 ps
T328 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3407353044 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:39 PM PST 24 516496190 ps
T67 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3938664403 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:30 PM PST 24 508737436 ps
T329 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1195828564 Feb 04 12:50:20 PM PST 24 Feb 04 12:50:24 PM PST 24 579416686 ps
T330 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4052551544 Feb 04 12:50:45 PM PST 24 Feb 04 12:50:54 PM PST 24 8276229479 ps
T331 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4151670648 Feb 04 12:50:40 PM PST 24 Feb 04 12:50:51 PM PST 24 4456735736 ps
T332 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1883897910 Feb 04 12:50:27 PM PST 24 Feb 04 12:50:31 PM PST 24 381687528 ps
T101 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1557549771 Feb 04 12:50:13 PM PST 24 Feb 04 12:50:25 PM PST 24 8194664902 ps
T333 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4046410182 Feb 04 12:50:19 PM PST 24 Feb 04 12:50:22 PM PST 24 283581633 ps
T334 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.469279313 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:39 PM PST 24 433154734 ps
T335 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3613670486 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:37 PM PST 24 418779431 ps
T336 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1223764785 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:40 PM PST 24 496484386 ps
T337 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2369315200 Feb 04 12:50:58 PM PST 24 Feb 04 12:51:00 PM PST 24 588627501 ps
T68 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2279985422 Feb 04 12:50:39 PM PST 24 Feb 04 12:50:49 PM PST 24 437326668 ps
T338 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4147455627 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:32 PM PST 24 894082562 ps
T339 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.516722878 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:41 PM PST 24 403140655 ps
T340 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3912089185 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:41 PM PST 24 1057092336 ps
T341 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.470709832 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:41 PM PST 24 328655975 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3782788745 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:41 PM PST 24 11506500018 ps
T343 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3379375565 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:32 PM PST 24 2435683128 ps
T69 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3930904950 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:33 PM PST 24 580602606 ps
T70 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2453382075 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:43 PM PST 24 591179486 ps
T71 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2381641780 Feb 04 12:50:26 PM PST 24 Feb 04 12:50:33 PM PST 24 4581144320 ps
T87 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1873185413 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 928728827 ps
T344 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.329740959 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:50 PM PST 24 460653077 ps
T345 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1618853962 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:56 PM PST 24 4043233873 ps
T346 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1813015336 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:42 PM PST 24 4138918975 ps
T347 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1443299216 Feb 04 12:50:23 PM PST 24 Feb 04 12:50:27 PM PST 24 352040404 ps
T348 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.560888202 Feb 04 12:50:33 PM PST 24 Feb 04 12:50:38 PM PST 24 348363994 ps
T102 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.449125777 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:56 PM PST 24 7778498855 ps
T349 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3522616246 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:51 PM PST 24 684479219 ps
T350 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.281094192 Feb 04 12:50:52 PM PST 24 Feb 04 12:50:55 PM PST 24 325268428 ps
T351 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1992243554 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:29 PM PST 24 290663226 ps
T352 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3344521475 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:40 PM PST 24 397448974 ps
T353 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.386102508 Feb 04 12:50:39 PM PST 24 Feb 04 12:50:48 PM PST 24 532378193 ps
T354 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2116008680 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:40 PM PST 24 454652665 ps
T355 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1033577033 Feb 04 12:50:45 PM PST 24 Feb 04 12:50:50 PM PST 24 500524666 ps
T356 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3142501595 Feb 04 12:50:09 PM PST 24 Feb 04 12:50:16 PM PST 24 494776581 ps
T357 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1730825062 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:50 PM PST 24 364294811 ps
T358 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.146181503 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:50 PM PST 24 577976447 ps
T359 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2306097838 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:33 PM PST 24 726669738 ps
T360 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1844809505 Feb 04 12:50:45 PM PST 24 Feb 04 12:50:50 PM PST 24 538954130 ps
T361 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3161816132 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 340208302 ps
T362 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.946884436 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:30 PM PST 24 563839714 ps
T363 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3113734576 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:39 PM PST 24 1621336777 ps
T364 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3127658849 Feb 04 12:50:18 PM PST 24 Feb 04 12:50:20 PM PST 24 313075136 ps
T365 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.558801587 Feb 04 12:50:32 PM PST 24 Feb 04 12:50:38 PM PST 24 371556572 ps
T366 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1769124041 Feb 04 12:50:29 PM PST 24 Feb 04 12:50:33 PM PST 24 508440474 ps
T88 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2980993074 Feb 04 12:50:18 PM PST 24 Feb 04 12:50:20 PM PST 24 1390532138 ps
T72 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.57355201 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 660147886 ps
T73 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3842921466 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:30 PM PST 24 444404879 ps
T74 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1157938197 Feb 04 12:50:57 PM PST 24 Feb 04 12:50:59 PM PST 24 265722451 ps
T367 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2211803359 Feb 04 12:50:18 PM PST 24 Feb 04 12:50:21 PM PST 24 420162019 ps
T368 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2587458641 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 391898348 ps
T75 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2263834249 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:37 PM PST 24 454886941 ps
T369 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4167981722 Feb 04 12:50:42 PM PST 24 Feb 04 12:50:50 PM PST 24 278729357 ps
T370 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2308881013 Feb 04 12:50:59 PM PST 24 Feb 04 12:51:04 PM PST 24 332152131 ps
T371 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.836200240 Feb 04 12:50:32 PM PST 24 Feb 04 12:50:37 PM PST 24 322627588 ps
T372 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1043486035 Feb 04 12:50:53 PM PST 24 Feb 04 12:50:55 PM PST 24 311780189 ps
T373 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1425430658 Feb 04 12:50:50 PM PST 24 Feb 04 12:50:53 PM PST 24 406769262 ps
T374 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2892647126 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:50 PM PST 24 478554622 ps
T375 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3297315475 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:39 PM PST 24 294638735 ps
T376 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.70352480 Feb 04 12:50:17 PM PST 24 Feb 04 12:50:21 PM PST 24 4926131356 ps
T377 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3546969297 Feb 04 12:50:34 PM PST 24 Feb 04 12:50:40 PM PST 24 5002922561 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1152627878 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:41 PM PST 24 600068361 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3874665103 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:25 PM PST 24 297771799 ps
T380 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4021550727 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:37 PM PST 24 2361364663 ps
T381 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.381718978 Feb 04 12:50:40 PM PST 24 Feb 04 12:50:51 PM PST 24 718984752 ps
T86 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1336256430 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:40 PM PST 24 395708866 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2797642039 Feb 04 12:50:20 PM PST 24 Feb 04 12:50:23 PM PST 24 320776744 ps
T383 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.447078817 Feb 04 12:50:18 PM PST 24 Feb 04 12:50:23 PM PST 24 455326373 ps
T384 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2006979899 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:50 PM PST 24 392016983 ps
T385 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.262732287 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:40 PM PST 24 360076405 ps
T386 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3813034299 Feb 04 12:50:40 PM PST 24 Feb 04 12:50:49 PM PST 24 392642111 ps
T387 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4099162541 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:41 PM PST 24 421206216 ps
T388 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4175517551 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:46 PM PST 24 413014266 ps
T76 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.215809438 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:27 PM PST 24 451024817 ps
T389 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2768287320 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:33 PM PST 24 1396545803 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2699280850 Feb 04 12:50:24 PM PST 24 Feb 04 12:50:29 PM PST 24 298490820 ps
T391 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3656770859 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:25 PM PST 24 1514111120 ps
T77 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3417694653 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:41 PM PST 24 6011814579 ps
T78 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.400793879 Feb 04 12:50:26 PM PST 24 Feb 04 12:50:30 PM PST 24 603894219 ps
T392 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.802627098 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 293432733 ps
T393 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1887695967 Feb 04 12:50:17 PM PST 24 Feb 04 12:50:21 PM PST 24 444544447 ps
T394 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3934908049 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:27 PM PST 24 807619383 ps
T79 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.682267450 Feb 04 12:50:28 PM PST 24 Feb 04 12:50:32 PM PST 24 348684729 ps
T395 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.645314005 Feb 04 12:50:17 PM PST 24 Feb 04 12:50:20 PM PST 24 263888935 ps
T396 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.958319316 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:50 PM PST 24 777144302 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.289089494 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:24 PM PST 24 379032075 ps
T398 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2846552188 Feb 04 12:50:30 PM PST 24 Feb 04 12:50:36 PM PST 24 476935656 ps
T399 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1687960988 Feb 04 12:50:19 PM PST 24 Feb 04 12:50:22 PM PST 24 6455763789 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3145134615 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:26 PM PST 24 651316224 ps
T401 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1569985612 Feb 04 12:50:22 PM PST 24 Feb 04 12:50:25 PM PST 24 514236550 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3827178220 Feb 04 12:50:29 PM PST 24 Feb 04 12:50:36 PM PST 24 1349963370 ps
T403 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2628911753 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:42 PM PST 24 783379555 ps
T404 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2009508290 Feb 04 12:50:27 PM PST 24 Feb 04 12:50:32 PM PST 24 564084732 ps
T405 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.347266030 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:41 PM PST 24 1174818562 ps
T80 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2407649498 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:30 PM PST 24 6338419890 ps
T406 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3376438949 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:49 PM PST 24 1765727288 ps
T407 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.429625834 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:51 PM PST 24 639781121 ps
T408 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2869376016 Feb 04 12:50:24 PM PST 24 Feb 04 12:50:47 PM PST 24 11774317857 ps
T409 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.862015488 Feb 04 12:50:23 PM PST 24 Feb 04 12:50:27 PM PST 24 706778964 ps
T410 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1361170072 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:46 PM PST 24 456955712 ps
T411 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3323668474 Feb 04 12:50:45 PM PST 24 Feb 04 12:51:03 PM PST 24 8147079714 ps
T412 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4035002832 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:51 PM PST 24 663666256 ps
T413 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3354725271 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:36 PM PST 24 382832350 ps
T414 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2662891140 Feb 04 12:50:27 PM PST 24 Feb 04 12:50:31 PM PST 24 430185977 ps
T415 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2205311723 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:40 PM PST 24 377480916 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1722419995 Feb 04 12:50:25 PM PST 24 Feb 04 12:50:36 PM PST 24 8337933993 ps
T417 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2131806481 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:53 PM PST 24 3953626191 ps
T418 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.201281440 Feb 04 12:50:30 PM PST 24 Feb 04 12:50:35 PM PST 24 2593203044 ps
T419 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.684783055 Feb 04 12:50:21 PM PST 24 Feb 04 12:50:25 PM PST 24 404756429 ps
T420 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.826255337 Feb 04 12:50:37 PM PST 24 Feb 04 12:50:46 PM PST 24 565844493 ps
T421 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.631120191 Feb 04 12:50:26 PM PST 24 Feb 04 12:50:30 PM PST 24 389778101 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1646585847 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:41 PM PST 24 2199654596 ps
T423 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3780242395 Feb 04 12:50:36 PM PST 24 Feb 04 12:50:44 PM PST 24 4213552515 ps
T424 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1975444168 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:50 PM PST 24 416113487 ps
T425 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1541836219 Feb 04 12:50:54 PM PST 24 Feb 04 12:50:56 PM PST 24 386521087 ps
T426 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1331310553 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:40 PM PST 24 318167369 ps
T427 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.495638097 Feb 04 12:50:31 PM PST 24 Feb 04 12:50:36 PM PST 24 374162763 ps
T428 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.565297200 Feb 04 12:50:35 PM PST 24 Feb 04 12:50:40 PM PST 24 546590903 ps
T429 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.955771152 Feb 04 12:50:41 PM PST 24 Feb 04 12:50:52 PM PST 24 4230709704 ps
T430 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2433857900 Feb 04 12:50:43 PM PST 24 Feb 04 12:50:50 PM PST 24 417442903 ps

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.380360136
Short name T2
Test name
Test status
Simulation time 4273400989 ps
CPU time 6.8 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 196604 kb
Host smart-867b0b6f-24b3-4ee8-b4ec-4e139a992e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380360136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.380360136
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1513338753
Short name T19
Test name
Test status
Simulation time 72441529926 ps
CPU time 189.31 seconds
Started Feb 04 12:56:01 PM PST 24
Finished Feb 04 12:59:13 PM PST 24
Peak memory 198420 kb
Host smart-2c5c1d46-07d3-49a7-bfed-33333dff58ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513338753 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1513338753
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3226523007
Short name T93
Test name
Test status
Simulation time 43220513211 ps
CPU time 475.14 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 01:03:48 PM PST 24
Peak memory 198316 kb
Host smart-c0aa62c6-0964-41e3-8f7e-4b5a6a0fba18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226523007 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3226523007
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.4286150238
Short name T13
Test name
Test status
Simulation time 310957133 ps
CPU time 1.03 seconds
Started Feb 04 12:50:42 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182908 kb
Host smart-83a5d8cb-9141-4820-8ce0-befee0d93bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286150238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.4286150238
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1705327060
Short name T63
Test name
Test status
Simulation time 69015702672 ps
CPU time 453 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 01:03:26 PM PST 24
Peak memory 198420 kb
Host smart-08121b9d-f5ed-41a5-9ad7-981e2c850170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705327060 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1705327060
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.311592129
Short name T20
Test name
Test status
Simulation time 137225967321 ps
CPU time 200.91 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:59:07 PM PST 24
Peak memory 183500 kb
Host smart-98b6d96d-8225-4ac0-a804-a9b7f8c348ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311592129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.311592129
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3103506710
Short name T52
Test name
Test status
Simulation time 99687692001 ps
CPU time 493.94 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 01:03:57 PM PST 24
Peak memory 198540 kb
Host smart-6a290d73-0035-4630-b6a3-d0eae4159d26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103506710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3103506710
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.756663589
Short name T5
Test name
Test status
Simulation time 4600128668 ps
CPU time 1.65 seconds
Started Feb 04 12:50:23 PM PST 24
Finished Feb 04 12:50:28 PM PST 24
Peak memory 195628 kb
Host smart-e0fcb6fb-079e-4493-a37b-e51f4fd80b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756663589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.756663589
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2650100053
Short name T105
Test name
Test status
Simulation time 35398257324 ps
CPU time 367.75 seconds
Started Feb 04 12:55:15 PM PST 24
Finished Feb 04 01:01:23 PM PST 24
Peak memory 198328 kb
Host smart-daf80549-34ff-4d28-a6bd-2171ea44b089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650100053 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2650100053
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2672551421
Short name T114
Test name
Test status
Simulation time 1152466910576 ps
CPU time 619.03 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 01:05:46 PM PST 24
Peak memory 199908 kb
Host smart-7b78fe1e-4e8e-400c-a604-43b411373a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672551421 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2672551421
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.2200395574
Short name T36
Test name
Test status
Simulation time 4174167859 ps
CPU time 2.3 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:21 PM PST 24
Peak memory 215560 kb
Host smart-b46b3082-6226-4e02-9a47-6704750f8d7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200395574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.2200395574
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.891767387
Short name T120
Test name
Test status
Simulation time 213375329053 ps
CPU time 174.07 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:58:14 PM PST 24
Peak memory 194828 kb
Host smart-d67c569a-c20f-4c01-a807-6ded1c8124ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891767387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_a
ll.891767387
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2092399582
Short name T65
Test name
Test status
Simulation time 192014531842 ps
CPU time 549.75 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 01:04:32 PM PST 24
Peak memory 198784 kb
Host smart-02ca2998-9f26-4945-a626-d6fda293e356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092399582 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2092399582
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1170785713
Short name T133
Test name
Test status
Simulation time 89910066756 ps
CPU time 73.01 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:56:58 PM PST 24
Peak memory 183532 kb
Host smart-409ed73b-a945-42ad-9758-0acb0aa38584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170785713 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1170785713
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1065636044
Short name T6
Test name
Test status
Simulation time 354969481 ps
CPU time 0.7 seconds
Started Feb 04 12:50:23 PM PST 24
Finished Feb 04 12:50:27 PM PST 24
Peak memory 183032 kb
Host smart-f1c1715b-cf92-4d8a-b560-8f8143662261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065636044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1065636044
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.751560472
Short name T287
Test name
Test status
Simulation time 43660876065 ps
CPU time 22.48 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183472 kb
Host smart-82c61c24-4b25-4104-8123-e1978ed7fe57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751560472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_al
l.751560472
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1078615852
Short name T91
Test name
Test status
Simulation time 2125036848 ps
CPU time 1.53 seconds
Started Feb 04 12:50:24 PM PST 24
Finished Feb 04 12:50:29 PM PST 24
Peak memory 194464 kb
Host smart-c3772ca3-0466-4a9b-844f-887f68c1088b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078615852 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1078615852
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1557549771
Short name T101
Test name
Test status
Simulation time 8194664902 ps
CPU time 8.07 seconds
Started Feb 04 12:50:13 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 196828 kb
Host smart-9c77d6fc-03fd-4363-b049-16b3a4761b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557549771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1557549771
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1644767673
Short name T116
Test name
Test status
Simulation time 93942405630 ps
CPU time 34.43 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 183532 kb
Host smart-155426a1-6af2-45fc-be4b-b86e826ab99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644767673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1644767673
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1914732212
Short name T264
Test name
Test status
Simulation time 572008448 ps
CPU time 1.52 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 183412 kb
Host smart-1746145b-31ca-4f5d-a719-617cc158309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914732212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1914732212
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1736965343
Short name T222
Test name
Test status
Simulation time 413568339 ps
CPU time 1.12 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183404 kb
Host smart-f6d21fe2-05f8-4f79-bbe6-4166a89d6426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736965343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1736965343
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.862015488
Short name T409
Test name
Test status
Simulation time 706778964 ps
CPU time 1.19 seconds
Started Feb 04 12:50:23 PM PST 24
Finished Feb 04 12:50:27 PM PST 24
Peak memory 183072 kb
Host smart-f0bd60f2-41a6-4573-9a21-63514b9c6b61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862015488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_al
iasing.862015488
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3417694653
Short name T77
Test name
Test status
Simulation time 6011814579 ps
CPU time 16.19 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 182740 kb
Host smart-bd052cee-2962-49c1-87cc-f9bafc7cbaec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417694653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3417694653
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2980993074
Short name T88
Test name
Test status
Simulation time 1390532138 ps
CPU time 0.74 seconds
Started Feb 04 12:50:18 PM PST 24
Finished Feb 04 12:50:20 PM PST 24
Peak memory 183024 kb
Host smart-f2f508e5-5d69-403a-a6b3-3fa418a04d68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980993074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2980993074
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.3578853511
Short name T55
Test name
Test status
Simulation time 383362492 ps
CPU time 0.72 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 194292 kb
Host smart-f4258bb0-334f-4572-9413-71cd56746429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578853511 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.3578853511
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.682267450
Short name T79
Test name
Test status
Simulation time 348684729 ps
CPU time 1.11 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 183032 kb
Host smart-3387ad80-18b9-42d0-a628-041fce1d9b06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682267450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.682267450
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3127658849
Short name T364
Test name
Test status
Simulation time 313075136 ps
CPU time 0.73 seconds
Started Feb 04 12:50:18 PM PST 24
Finished Feb 04 12:50:20 PM PST 24
Peak memory 182852 kb
Host smart-0c558c25-13ba-42b1-a01b-a4a0a2ad9825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127658849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3127658849
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2797642039
Short name T382
Test name
Test status
Simulation time 320776744 ps
CPU time 0.67 seconds
Started Feb 04 12:50:20 PM PST 24
Finished Feb 04 12:50:23 PM PST 24
Peak memory 183076 kb
Host smart-7f3feecf-aa7e-4870-bf0f-ebcecc907057
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797642039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2797642039
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.802627098
Short name T392
Test name
Test status
Simulation time 293432733 ps
CPU time 0.97 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 182896 kb
Host smart-4e575832-4400-432f-a865-4e725c0d6ec6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802627098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_wa
lk.802627098
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3142501595
Short name T356
Test name
Test status
Simulation time 494776581 ps
CPU time 1.6 seconds
Started Feb 04 12:50:09 PM PST 24
Finished Feb 04 12:50:16 PM PST 24
Peak memory 197796 kb
Host smart-e2bfa9ae-53bb-4c98-a9ac-9bfe887c5334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142501595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3142501595
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3930904950
Short name T69
Test name
Test status
Simulation time 580602606 ps
CPU time 1.67 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 193152 kb
Host smart-255e0aa4-27c9-4790-a7bc-c4d4022d8160
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930904950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3930904950
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2407649498
Short name T80
Test name
Test status
Simulation time 6338419890 ps
CPU time 7.35 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 191488 kb
Host smart-345bb88c-b030-4c09-ac4c-38c23c120373
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407649498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2407649498
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.1393866215
Short name T321
Test name
Test status
Simulation time 785965847 ps
CPU time 1.17 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 183036 kb
Host smart-36e1d4f2-cd11-46bf-b4b7-0d9073e03878
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393866215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.1393866215
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.1368078247
Short name T315
Test name
Test status
Simulation time 639792332 ps
CPU time 1.02 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 197680 kb
Host smart-b5347e02-1bb9-4ed1-b3d2-80dd196c25ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368078247 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.1368078247
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.108344937
Short name T11
Test name
Test status
Simulation time 358456023 ps
CPU time 0.85 seconds
Started Feb 04 12:50:19 PM PST 24
Finished Feb 04 12:50:21 PM PST 24
Peak memory 183148 kb
Host smart-ec129a3c-ebdb-4fb8-b943-416031e0c023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108344937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.108344937
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2587458641
Short name T368
Test name
Test status
Simulation time 391898348 ps
CPU time 0.75 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 182688 kb
Host smart-adc292ec-c30f-41f1-b1f8-00151b5bbd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587458641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2587458641
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.289089494
Short name T397
Test name
Test status
Simulation time 379032075 ps
CPU time 0.76 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 182916 kb
Host smart-448e1aef-3706-42a7-aa6a-de1eff5bf7fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289089494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.289089494
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1569985612
Short name T401
Test name
Test status
Simulation time 514236550 ps
CPU time 0.74 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 182764 kb
Host smart-4c6a8cb3-34cd-49bf-b707-d40b2afbd693
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569985612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1569985612
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3379375565
Short name T343
Test name
Test status
Simulation time 2435683128 ps
CPU time 3.33 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 193724 kb
Host smart-c2a23e2d-70b8-46e1-96e9-cdf988de37f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379375565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3379375565
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.447078817
Short name T383
Test name
Test status
Simulation time 455326373 ps
CPU time 2.68 seconds
Started Feb 04 12:50:18 PM PST 24
Finished Feb 04 12:50:23 PM PST 24
Peak memory 197884 kb
Host smart-df9de870-386d-4f59-be00-82b903f04b99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447078817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.447078817
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.70352480
Short name T376
Test name
Test status
Simulation time 4926131356 ps
CPU time 1.39 seconds
Started Feb 04 12:50:17 PM PST 24
Finished Feb 04 12:50:21 PM PST 24
Peak memory 195560 kb
Host smart-fcf02dfb-1064-4a8f-be58-1905b4267f65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70352480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_i
ntg_err.70352480
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.558801587
Short name T365
Test name
Test status
Simulation time 371556572 ps
CPU time 1.22 seconds
Started Feb 04 12:50:32 PM PST 24
Finished Feb 04 12:50:38 PM PST 24
Peak memory 194036 kb
Host smart-629b91fe-29d9-4067-837c-b9d05e27f62a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558801587 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.558801587
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.2279985422
Short name T68
Test name
Test status
Simulation time 437326668 ps
CPU time 1 seconds
Started Feb 04 12:50:39 PM PST 24
Finished Feb 04 12:50:49 PM PST 24
Peak memory 182964 kb
Host smart-c6e1fd46-76ca-44bc-8fbb-502a72b07feb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279985422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.2279985422
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.860948837
Short name T318
Test name
Test status
Simulation time 474169754 ps
CPU time 1.29 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 182892 kb
Host smart-a011c1e5-b64f-41d0-84c6-b4c9b72db2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860948837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.860948837
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2768287320
Short name T389
Test name
Test status
Simulation time 1396545803 ps
CPU time 1.34 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 193128 kb
Host smart-039954e4-4300-4ce6-a593-731ae6d3ce03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768287320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2768287320
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4021550727
Short name T380
Test name
Test status
Simulation time 2361364663 ps
CPU time 2.03 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:37 PM PST 24
Peak memory 198020 kb
Host smart-8d772400-f81d-46bb-9d93-a3cdd993cae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021550727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4021550727
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3546969297
Short name T377
Test name
Test status
Simulation time 5002922561 ps
CPU time 1.25 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 195184 kb
Host smart-67a8e3cf-182c-453a-be44-deccb65430d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546969297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3546969297
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4099162541
Short name T387
Test name
Test status
Simulation time 421206216 ps
CPU time 1.29 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 194288 kb
Host smart-b5fc511c-0429-4399-8a52-4178dbc3a4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099162541 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4099162541
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1682711179
Short name T139
Test name
Test status
Simulation time 294356307 ps
CPU time 0.65 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 182936 kb
Host smart-4bfc5f8b-8948-4638-8530-c770a65a45f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682711179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1682711179
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.201281440
Short name T418
Test name
Test status
Simulation time 2593203044 ps
CPU time 1.28 seconds
Started Feb 04 12:50:30 PM PST 24
Finished Feb 04 12:50:35 PM PST 24
Peak memory 194604 kb
Host smart-195a4750-f8ab-4290-b58a-7c47362b0302
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201281440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon
_timer_same_csr_outstanding.201281440
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3613670486
Short name T335
Test name
Test status
Simulation time 418779431 ps
CPU time 1.57 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:37 PM PST 24
Peak memory 197940 kb
Host smart-bec6ebd1-6de5-40d0-a607-386e4a73aa02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613670486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3613670486
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.397734718
Short name T10
Test name
Test status
Simulation time 4277874907 ps
CPU time 7.4 seconds
Started Feb 04 12:50:30 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 196560 kb
Host smart-1998ee5f-d7f5-4cfe-93e8-df3a40441c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397734718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.397734718
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.391949124
Short name T317
Test name
Test status
Simulation time 575305512 ps
CPU time 1.07 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 195240 kb
Host smart-a92ff787-e18b-41e9-9020-36853d9087ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391949124 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.391949124
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.826255337
Short name T420
Test name
Test status
Simulation time 565844493 ps
CPU time 0.79 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:46 PM PST 24
Peak memory 183112 kb
Host smart-5aa5052d-2b99-4152-b209-0bb9d11c64ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826255337 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.826255337
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.1312278441
Short name T324
Test name
Test status
Simulation time 469920372 ps
CPU time 0.75 seconds
Started Feb 04 12:50:30 PM PST 24
Finished Feb 04 12:50:35 PM PST 24
Peak memory 182860 kb
Host smart-186efce9-4ca1-4ae1-9811-61aa765038f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312278441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.1312278441
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1969913644
Short name T3
Test name
Test status
Simulation time 1774733785 ps
CPU time 5.03 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:44 PM PST 24
Peak memory 194580 kb
Host smart-3788544f-6f41-42ac-b2c4-8eb5bab0136f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969913644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1969913644
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2453382075
Short name T70
Test name
Test status
Simulation time 591179486 ps
CPU time 3.01 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:43 PM PST 24
Peak memory 197920 kb
Host smart-c2b77764-8512-48cf-9a0a-aad141df064c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453382075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2453382075
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.449125777
Short name T102
Test name
Test status
Simulation time 7778498855 ps
CPU time 9.39 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 197004 kb
Host smart-97858f28-47be-4dc9-ac3a-92f004763b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449125777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.449125777
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3842921466
Short name T73
Test name
Test status
Simulation time 444404879 ps
CPU time 1.34 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 194988 kb
Host smart-4e4da680-df19-4a16-b976-5f3b0e3f1ea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842921466 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3842921466
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.3407353044
Short name T328
Test name
Test status
Simulation time 516496190 ps
CPU time 1.25 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 182988 kb
Host smart-dec98c17-3886-4833-9d61-838ccc1f245e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407353044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.3407353044
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3344521475
Short name T352
Test name
Test status
Simulation time 397448974 ps
CPU time 0.71 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 182816 kb
Host smart-7e5df15b-6ed8-4192-93da-c658ec55135a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344521475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3344521475
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3376438949
Short name T406
Test name
Test status
Simulation time 1765727288 ps
CPU time 4.53 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:49 PM PST 24
Peak memory 194700 kb
Host smart-62dff1a0-f4b8-4a01-8210-c3eaa1dd5895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376438949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3376438949
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1331310553
Short name T426
Test name
Test status
Simulation time 318167369 ps
CPU time 1.52 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 197752 kb
Host smart-70cfad4d-c40a-4f7b-bdbe-7820e2b36351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331310553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1331310553
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2381641780
Short name T71
Test name
Test status
Simulation time 4581144320 ps
CPU time 4.22 seconds
Started Feb 04 12:50:26 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 196520 kb
Host smart-0802b1b7-f26a-465b-8d2b-5a2d7e8deea3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381641780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2381641780
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1883897910
Short name T332
Test name
Test status
Simulation time 381687528 ps
CPU time 1.17 seconds
Started Feb 04 12:50:27 PM PST 24
Finished Feb 04 12:50:31 PM PST 24
Peak memory 194160 kb
Host smart-779bbfff-d8a1-4cc6-bf53-6a5f90f3dd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883897910 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1883897910
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2662891140
Short name T414
Test name
Test status
Simulation time 430185977 ps
CPU time 1.22 seconds
Started Feb 04 12:50:27 PM PST 24
Finished Feb 04 12:50:31 PM PST 24
Peak memory 183116 kb
Host smart-ae26dd7a-8291-4d40-b90c-02e899cd70ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662891140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2662891140
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1898861468
Short name T326
Test name
Test status
Simulation time 303840059 ps
CPU time 0.99 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 182816 kb
Host smart-cdb67fc6-b9a5-410f-a83b-18f8458a5a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898861468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1898861468
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2155435925
Short name T17
Test name
Test status
Simulation time 1189248918 ps
CPU time 0.87 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 193288 kb
Host smart-14f472f6-2d6a-4097-a241-13445568096c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155435925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2155435925
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.47879898
Short name T7
Test name
Test status
Simulation time 741597920 ps
CPU time 2 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:31 PM PST 24
Peak memory 197824 kb
Host smart-f3656efe-7799-436d-880d-6927cef763b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47879898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.47879898
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1722419995
Short name T416
Test name
Test status
Simulation time 8337933993 ps
CPU time 7.02 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 196908 kb
Host smart-f940ba93-711f-4691-975a-0fc4ad8e79e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722419995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1722419995
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1033577033
Short name T355
Test name
Test status
Simulation time 500524666 ps
CPU time 0.85 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 195464 kb
Host smart-f8879747-0cb3-459b-8b29-cd55f6d423b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033577033 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1033577033
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3938664403
Short name T67
Test name
Test status
Simulation time 508737436 ps
CPU time 1.37 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 183144 kb
Host smart-fab13fcb-55e7-411a-bbc5-006a584e2b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938664403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3938664403
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.1992243554
Short name T351
Test name
Test status
Simulation time 290663226 ps
CPU time 0.72 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:29 PM PST 24
Peak memory 182944 kb
Host smart-08072d5a-4deb-4bf7-8e54-814dc2f0af90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992243554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.1992243554
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.347266030
Short name T405
Test name
Test status
Simulation time 1174818562 ps
CPU time 1.12 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 193572 kb
Host smart-b58ca76e-076c-43cf-9f6a-7c1b923b2f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347266030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.347266030
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2628911753
Short name T403
Test name
Test status
Simulation time 783379555 ps
CPU time 1.69 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 197836 kb
Host smart-6c120f29-2f6f-4da4-9829-794a6b7fb6b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628911753 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2628911753
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.3323668474
Short name T411
Test name
Test status
Simulation time 8147079714 ps
CPU time 13.45 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:51:03 PM PST 24
Peak memory 196696 kb
Host smart-d6b68b49-427f-45a6-a63f-717752f711a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323668474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.3323668474
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.4035002832
Short name T412
Test name
Test status
Simulation time 663666256 ps
CPU time 1.14 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 197476 kb
Host smart-b159586e-d1d1-421f-ae1f-901750e193bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035002832 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.4035002832
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2263834249
Short name T75
Test name
Test status
Simulation time 454886941 ps
CPU time 1.42 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:37 PM PST 24
Peak memory 182988 kb
Host smart-84f9f27e-3b3f-4474-a6ed-60e05d18deb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263834249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2263834249
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2433857900
Short name T430
Test name
Test status
Simulation time 417442903 ps
CPU time 0.91 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182940 kb
Host smart-2f66a666-bdc6-463f-b284-a34c201a346c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433857900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2433857900
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1523014957
Short name T90
Test name
Test status
Simulation time 966447378 ps
CPU time 2.74 seconds
Started Feb 04 12:50:39 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 192000 kb
Host smart-59a7dde1-4261-42b8-84fa-245b1b783537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523014957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1523014957
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3522616246
Short name T349
Test name
Test status
Simulation time 684479219 ps
CPU time 1.89 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 197456 kb
Host smart-e077dc7b-78ae-4245-9281-77e74c7d22a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522616246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3522616246
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1618853962
Short name T345
Test name
Test status
Simulation time 4043233873 ps
CPU time 6.8 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 195036 kb
Host smart-943a2999-b530-4582-8562-e7d3ad1a7ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618853962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1618853962
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.146181503
Short name T358
Test name
Test status
Simulation time 577976447 ps
CPU time 0.85 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 195616 kb
Host smart-ada0c34a-f4c8-4c18-9cba-3c0270f97e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146181503 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.146181503
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.495638097
Short name T427
Test name
Test status
Simulation time 374162763 ps
CPU time 0.94 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 183148 kb
Host smart-429c7012-002d-4e58-8a66-2c8b086cc381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495638097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.495638097
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3882797899
Short name T92
Test name
Test status
Simulation time 1110340695 ps
CPU time 1.12 seconds
Started Feb 04 12:50:30 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 192676 kb
Host smart-3c507d43-3dd8-4af7-b738-2e5af1e96896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882797899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3882797899
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.429625834
Short name T407
Test name
Test status
Simulation time 639781121 ps
CPU time 2 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 197668 kb
Host smart-f472be31-2c95-4559-ae4e-e2f850d70f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429625834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.429625834
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2131806481
Short name T417
Test name
Test status
Simulation time 3953626191 ps
CPU time 4.13 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:53 PM PST 24
Peak memory 196524 kb
Host smart-58be2f02-909d-47e2-b417-62a52b79051e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131806481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2131806481
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.329740959
Short name T344
Test name
Test status
Simulation time 460653077 ps
CPU time 0.85 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 193656 kb
Host smart-af0f9cda-2581-4ddc-a162-14d56b59af43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329740959 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.329740959
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.2205311723
Short name T415
Test name
Test status
Simulation time 377480916 ps
CPU time 0.81 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 183024 kb
Host smart-16d8572a-c061-4764-a29f-0f350285c7cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205311723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.2205311723
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.3354725271
Short name T413
Test name
Test status
Simulation time 382832350 ps
CPU time 0.7 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 183132 kb
Host smart-c494e231-f8f6-41ac-b6f2-eb666c913b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354725271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.3354725271
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.958319316
Short name T396
Test name
Test status
Simulation time 777144302 ps
CPU time 0.92 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 191800 kb
Host smart-954715df-9f3e-4366-996d-925c906d5d2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958319316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon
_timer_same_csr_outstanding.958319316
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.1124375826
Short name T323
Test name
Test status
Simulation time 552976931 ps
CPU time 1.49 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:37 PM PST 24
Peak memory 197832 kb
Host smart-d7f9a215-c7f1-41b0-af94-4032e522b9bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124375826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.1124375826
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.879550165
Short name T100
Test name
Test status
Simulation time 8421943645 ps
CPU time 4 seconds
Started Feb 04 12:50:39 PM PST 24
Finished Feb 04 12:50:52 PM PST 24
Peak memory 196672 kb
Host smart-f07ef27d-2c20-4a49-bef0-cad22493f647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879550165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.879550165
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2352650406
Short name T313
Test name
Test status
Simulation time 419293983 ps
CPU time 1 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:46 PM PST 24
Peak memory 195624 kb
Host smart-ba9cbd23-3e23-4755-aa0f-3b8f45fcecfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352650406 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2352650406
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.626024177
Short name T322
Test name
Test status
Simulation time 526294580 ps
CPU time 0.81 seconds
Started Feb 04 12:50:42 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182568 kb
Host smart-8c21a44f-8428-4a68-9341-2f324e3b8e3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626024177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.626024177
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2622145673
Short name T140
Test name
Test status
Simulation time 363750103 ps
CPU time 0.6 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182420 kb
Host smart-d303b8fd-c048-4beb-9def-041c3cdc10ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622145673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2622145673
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3912089185
Short name T340
Test name
Test status
Simulation time 1057092336 ps
CPU time 1.12 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 192208 kb
Host smart-cfdd8401-0a43-4332-ad69-c748a74952af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912089185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3912089185
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.470709832
Short name T341
Test name
Test status
Simulation time 328655975 ps
CPU time 1.3 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 197788 kb
Host smart-5088abad-d90f-4f6c-b356-295351806ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470709832 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.470709832
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.955771152
Short name T429
Test name
Test status
Simulation time 4230709704 ps
CPU time 2.4 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:52 PM PST 24
Peak memory 196368 kb
Host smart-dcda70b1-6931-4047-a292-30efdd0651d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955771152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.955771152
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.400793879
Short name T78
Test name
Test status
Simulation time 603894219 ps
CPU time 0.69 seconds
Started Feb 04 12:50:26 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 183112 kb
Host smart-eb2ec26c-699b-4d59-9dd8-5e643a89a50f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400793879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.400793879
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1687960988
Short name T399
Test name
Test status
Simulation time 6455763789 ps
CPU time 1.75 seconds
Started Feb 04 12:50:19 PM PST 24
Finished Feb 04 12:50:22 PM PST 24
Peak memory 191384 kb
Host smart-59af13ba-4698-4a5d-a2b4-94a87b24ac9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687960988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1687960988
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3934908049
Short name T394
Test name
Test status
Simulation time 807619383 ps
CPU time 0.91 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:27 PM PST 24
Peak memory 183136 kb
Host smart-f0da6f66-1714-4b0d-bb29-9e78268d16e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934908049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3934908049
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3145134615
Short name T400
Test name
Test status
Simulation time 651316224 ps
CPU time 0.72 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 195188 kb
Host smart-7f019134-f52b-4f0e-a3df-eaf6854077c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145134615 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3145134615
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2699280850
Short name T390
Test name
Test status
Simulation time 298490820 ps
CPU time 0.89 seconds
Started Feb 04 12:50:24 PM PST 24
Finished Feb 04 12:50:29 PM PST 24
Peak memory 183064 kb
Host smart-874455fa-77e7-4d95-99cc-c56a28694113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699280850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2699280850
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2211803359
Short name T367
Test name
Test status
Simulation time 420162019 ps
CPU time 1.16 seconds
Started Feb 04 12:50:18 PM PST 24
Finished Feb 04 12:50:21 PM PST 24
Peak memory 182836 kb
Host smart-038e269a-39d6-4c96-a50e-6fe90046963c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211803359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2211803359
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.645314005
Short name T395
Test name
Test status
Simulation time 263888935 ps
CPU time 0.84 seconds
Started Feb 04 12:50:17 PM PST 24
Finished Feb 04 12:50:20 PM PST 24
Peak memory 182832 kb
Host smart-04658101-4896-4177-ae6d-8e3bcdef6c71
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645314005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.645314005
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.684783055
Short name T419
Test name
Test status
Simulation time 404756429 ps
CPU time 1.09 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 182784 kb
Host smart-4a0b999b-9202-41c8-a673-b7a9b99df68b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684783055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.684783055
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3656770859
Short name T391
Test name
Test status
Simulation time 1514111120 ps
CPU time 1.6 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 193492 kb
Host smart-9337e1ec-1e79-4997-acaa-2cf7d3ea27a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656770859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3656770859
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2846552188
Short name T398
Test name
Test status
Simulation time 476935656 ps
CPU time 2.25 seconds
Started Feb 04 12:50:30 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 197888 kb
Host smart-24622894-f83d-49a6-a92a-2ead1777905a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846552188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2846552188
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.262732287
Short name T385
Test name
Test status
Simulation time 360076405 ps
CPU time 0.66 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 183148 kb
Host smart-a953b4a0-867c-4233-aab2-c03524c4518d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262732287 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.262732287
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.4175517551
Short name T388
Test name
Test status
Simulation time 413014266 ps
CPU time 0.76 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:46 PM PST 24
Peak memory 182952 kb
Host smart-f8f41a0d-913b-4ec5-8cb1-520f563e3788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175517551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.4175517551
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.4167981722
Short name T369
Test name
Test status
Simulation time 278729357 ps
CPU time 0.87 seconds
Started Feb 04 12:50:42 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182880 kb
Host smart-c4a70273-2bc3-469f-80fc-9a8155c58891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167981722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.4167981722
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2831888535
Short name T327
Test name
Test status
Simulation time 327253241 ps
CPU time 0.79 seconds
Started Feb 04 12:50:38 PM PST 24
Finished Feb 04 12:50:48 PM PST 24
Peak memory 182972 kb
Host smart-143f1d23-f1ca-42eb-ba5b-d11907fd4509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831888535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2831888535
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.836200240
Short name T371
Test name
Test status
Simulation time 322627588 ps
CPU time 0.67 seconds
Started Feb 04 12:50:32 PM PST 24
Finished Feb 04 12:50:37 PM PST 24
Peak memory 183056 kb
Host smart-47a5b06e-741d-422b-b216-b667a6000fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836200240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.836200240
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1730825062
Short name T357
Test name
Test status
Simulation time 364294811 ps
CPU time 0.8 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 183136 kb
Host smart-54fdc7b3-b3e5-4199-a3c1-0057595a7d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730825062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1730825062
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3116273850
Short name T26
Test name
Test status
Simulation time 337506362 ps
CPU time 0.78 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:46 PM PST 24
Peak memory 182960 kb
Host smart-2bfae38c-d502-4a48-92b9-3b73ae43e38b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116273850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3116273850
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3297315475
Short name T375
Test name
Test status
Simulation time 294638735 ps
CPU time 0.74 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 182880 kb
Host smart-f112c97f-4812-429b-aa01-b93637bd5633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297315475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3297315475
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.618635406
Short name T325
Test name
Test status
Simulation time 343852429 ps
CPU time 0.72 seconds
Started Feb 04 12:50:39 PM PST 24
Finished Feb 04 12:50:48 PM PST 24
Peak memory 182672 kb
Host smart-0074a76c-d715-4465-8290-e78a6d29ddd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618635406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.618635406
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.469279313
Short name T334
Test name
Test status
Simulation time 433154734 ps
CPU time 0.69 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 182844 kb
Host smart-94264b8c-6e32-4e58-a688-af5ff3e5ff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469279313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.469279313
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.57355201
Short name T72
Test name
Test status
Simulation time 660147886 ps
CPU time 0.93 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 193244 kb
Host smart-3dddb257-48be-49d1-aeba-82e011fa3a29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57355201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_ali
asing.57355201
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2869376016
Short name T408
Test name
Test status
Simulation time 11774317857 ps
CPU time 19.19 seconds
Started Feb 04 12:50:24 PM PST 24
Finished Feb 04 12:50:47 PM PST 24
Peak memory 191436 kb
Host smart-203927d3-cb87-46f5-a5ba-edccdf875b2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869376016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2869376016
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1873185413
Short name T87
Test name
Test status
Simulation time 928728827 ps
CPU time 2.16 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 182876 kb
Host smart-be20318b-f323-496d-8e6d-c11b8db1881c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873185413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1873185413
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1887695967
Short name T393
Test name
Test status
Simulation time 444544447 ps
CPU time 1.2 seconds
Started Feb 04 12:50:17 PM PST 24
Finished Feb 04 12:50:21 PM PST 24
Peak memory 194888 kb
Host smart-5d67c0f2-d85a-4421-9c77-a3907d021a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887695967 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1887695967
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.4046410182
Short name T333
Test name
Test status
Simulation time 283581633 ps
CPU time 0.99 seconds
Started Feb 04 12:50:19 PM PST 24
Finished Feb 04 12:50:22 PM PST 24
Peak memory 183088 kb
Host smart-152f0c11-0b5f-4edd-91fc-489945a08b49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046410182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.4046410182
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.3161816132
Short name T361
Test name
Test status
Simulation time 340208302 ps
CPU time 0.9 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 182664 kb
Host smart-854cec58-cdf3-4296-b5a8-0672b79d5bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161816132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.3161816132
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1710836286
Short name T8
Test name
Test status
Simulation time 301024301 ps
CPU time 0.6 seconds
Started Feb 04 12:50:26 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 182884 kb
Host smart-e09cd506-4477-4f88-beed-635ecf2ce4cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710836286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1710836286
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.575311257
Short name T320
Test name
Test status
Simulation time 354626121 ps
CPU time 0.67 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:26 PM PST 24
Peak memory 182896 kb
Host smart-5bc9bf17-c186-46f5-a083-af44e299bda1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575311257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.575311257
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1267357499
Short name T89
Test name
Test status
Simulation time 2640801137 ps
CPU time 2.17 seconds
Started Feb 04 12:50:26 PM PST 24
Finished Feb 04 12:50:31 PM PST 24
Peak memory 194616 kb
Host smart-cbf54b92-c9f1-480d-9ca8-fa905240bbbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267357499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1267357499
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.3592962163
Short name T15
Test name
Test status
Simulation time 363157730 ps
CPU time 1.65 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 197944 kb
Host smart-433b9030-29e7-4547-9aef-7f6e4edbe31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592962163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.3592962163
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.1319466975
Short name T310
Test name
Test status
Simulation time 4388434027 ps
CPU time 2.17 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 195184 kb
Host smart-de0f7f75-e8ec-4936-b567-c33eef5e38cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319466975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.1319466975
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1975444168
Short name T424
Test name
Test status
Simulation time 416113487 ps
CPU time 0.67 seconds
Started Feb 04 12:50:41 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182748 kb
Host smart-d6da63f4-c18e-4250-a08a-37d72d14979f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975444168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1975444168
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2006979899
Short name T384
Test name
Test status
Simulation time 392016983 ps
CPU time 0.63 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182728 kb
Host smart-be1d5d11-0598-4a06-95d4-75b27be240fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006979899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2006979899
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.4282899951
Short name T27
Test name
Test status
Simulation time 335123093 ps
CPU time 0.82 seconds
Started Feb 04 12:50:42 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182928 kb
Host smart-09d888e6-f5db-45b4-ab15-639342a5a816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282899951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.4282899951
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2116008680
Short name T354
Test name
Test status
Simulation time 454652665 ps
CPU time 0.85 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 182880 kb
Host smart-51da7d11-2458-4adc-8f56-51fd7fd7402e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116008680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2116008680
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.386102508
Short name T353
Test name
Test status
Simulation time 532378193 ps
CPU time 0.75 seconds
Started Feb 04 12:50:39 PM PST 24
Finished Feb 04 12:50:48 PM PST 24
Peak memory 182864 kb
Host smart-fd598ab3-784a-4ff8-879d-8099daa4c508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386102508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.386102508
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.470552370
Short name T14
Test name
Test status
Simulation time 343783130 ps
CPU time 0.86 seconds
Started Feb 04 12:50:31 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 182804 kb
Host smart-8959eb54-851e-4d96-9336-0db9ee046121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470552370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.470552370
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2987148508
Short name T25
Test name
Test status
Simulation time 467647341 ps
CPU time 0.68 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:38 PM PST 24
Peak memory 182916 kb
Host smart-92b9585f-5a8c-47e1-a28a-f168adf4d947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987148508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2987148508
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3813034299
Short name T386
Test name
Test status
Simulation time 392642111 ps
CPU time 0.68 seconds
Started Feb 04 12:50:40 PM PST 24
Finished Feb 04 12:50:49 PM PST 24
Peak memory 182944 kb
Host smart-584a574f-fb9b-4464-8c98-7e4b100b8ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813034299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3813034299
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2892647126
Short name T374
Test name
Test status
Simulation time 478554622 ps
CPU time 0.81 seconds
Started Feb 04 12:50:43 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 182688 kb
Host smart-16c49487-e9e1-46f6-9be9-07b81bcfe789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892647126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2892647126
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.281094192
Short name T350
Test name
Test status
Simulation time 325268428 ps
CPU time 0.65 seconds
Started Feb 04 12:50:52 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 183112 kb
Host smart-b0afa435-2c97-4e86-b56b-7c334ed60c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281094192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.281094192
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1152627878
Short name T378
Test name
Test status
Simulation time 600068361 ps
CPU time 0.83 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 182524 kb
Host smart-40733e2b-cd4c-4772-bba2-c03a26d002f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152627878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1152627878
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3782788745
Short name T342
Test name
Test status
Simulation time 11506500018 ps
CPU time 17.71 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 191404 kb
Host smart-88203287-3f51-4bdf-92a1-fa48a68b6cbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782788745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3782788745
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.2306097838
Short name T359
Test name
Test status
Simulation time 726669738 ps
CPU time 1.78 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 183044 kb
Host smart-863243d4-7a76-4b5e-a504-27d85c630b62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306097838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.2306097838
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.946884436
Short name T362
Test name
Test status
Simulation time 563839714 ps
CPU time 0.98 seconds
Started Feb 04 12:50:25 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 195124 kb
Host smart-45a904fa-62a9-40ee-a2f0-b078ed18bf29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946884436 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.946884436
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.215809438
Short name T76
Test name
Test status
Simulation time 451024817 ps
CPU time 0.97 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:27 PM PST 24
Peak memory 183128 kb
Host smart-e83495ee-19d5-43c0-9381-b3024a70de69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215809438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.215809438
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3874665103
Short name T379
Test name
Test status
Simulation time 297771799 ps
CPU time 0.66 seconds
Started Feb 04 12:50:22 PM PST 24
Finished Feb 04 12:50:25 PM PST 24
Peak memory 182952 kb
Host smart-f99e4f59-a5bb-4b5c-98b4-7286ba4c9013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874665103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3874665103
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3717098312
Short name T28
Test name
Test status
Simulation time 468536222 ps
CPU time 0.6 seconds
Started Feb 04 12:50:21 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 182908 kb
Host smart-713e6fa6-b003-4f67-8e00-443ac65912c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717098312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3717098312
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1443299216
Short name T347
Test name
Test status
Simulation time 352040404 ps
CPU time 0.78 seconds
Started Feb 04 12:50:23 PM PST 24
Finished Feb 04 12:50:27 PM PST 24
Peak memory 182796 kb
Host smart-15ae4fb7-883c-4bdd-945f-b173e6a409d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443299216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1443299216
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1646585847
Short name T422
Test name
Test status
Simulation time 2199654596 ps
CPU time 2.1 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 194592 kb
Host smart-a364c2c8-8a84-4efd-92e5-deef29ace3fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646585847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1646585847
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1534512386
Short name T54
Test name
Test status
Simulation time 612696828 ps
CPU time 1.73 seconds
Started Feb 04 12:50:20 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 197864 kb
Host smart-64415657-4f2e-46ca-9050-b32b80bfe918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534512386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1534512386
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.259005137
Short name T314
Test name
Test status
Simulation time 485766254 ps
CPU time 1.25 seconds
Started Feb 04 12:50:55 PM PST 24
Finished Feb 04 12:50:58 PM PST 24
Peak memory 182916 kb
Host smart-d99705e3-2938-4983-a42f-15978699a934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259005137 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.259005137
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2443985655
Short name T316
Test name
Test status
Simulation time 353295753 ps
CPU time 1.08 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 183080 kb
Host smart-16fa2950-ff0b-47c2-9d89-e84b1c1e8bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443985655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2443985655
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1654979013
Short name T319
Test name
Test status
Simulation time 407953134 ps
CPU time 1.15 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 182948 kb
Host smart-f02abdcd-04d5-4243-b565-1ea80212d524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654979013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1654979013
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3265809199
Short name T59
Test name
Test status
Simulation time 481317237 ps
CPU time 0.79 seconds
Started Feb 04 12:50:50 PM PST 24
Finished Feb 04 12:50:53 PM PST 24
Peak memory 182868 kb
Host smart-1045b6a1-380d-4e93-a900-529364659a90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265809199 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3265809199
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2369315200
Short name T337
Test name
Test status
Simulation time 588627501 ps
CPU time 0.65 seconds
Started Feb 04 12:50:58 PM PST 24
Finished Feb 04 12:51:00 PM PST 24
Peak memory 182936 kb
Host smart-529d7f17-7a50-4c99-a040-b24f67b2accc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369315200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2369315200
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.1425430658
Short name T373
Test name
Test status
Simulation time 406769262 ps
CPU time 0.54 seconds
Started Feb 04 12:50:50 PM PST 24
Finished Feb 04 12:50:53 PM PST 24
Peak memory 182928 kb
Host smart-b834829f-a1eb-413c-9f69-7a6ad5c2a24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425430658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.1425430658
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1157938197
Short name T74
Test name
Test status
Simulation time 265722451 ps
CPU time 0.93 seconds
Started Feb 04 12:50:57 PM PST 24
Finished Feb 04 12:50:59 PM PST 24
Peak memory 183076 kb
Host smart-b895f6da-d29e-44b7-806c-618850693654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157938197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1157938197
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1541836219
Short name T425
Test name
Test status
Simulation time 386521087 ps
CPU time 0.7 seconds
Started Feb 04 12:50:54 PM PST 24
Finished Feb 04 12:50:56 PM PST 24
Peak memory 182916 kb
Host smart-9c50bacb-add3-44ca-a87a-d67d5372cd9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541836219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1541836219
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1043486035
Short name T372
Test name
Test status
Simulation time 311780189 ps
CPU time 0.64 seconds
Started Feb 04 12:50:53 PM PST 24
Finished Feb 04 12:50:55 PM PST 24
Peak memory 182820 kb
Host smart-7805d599-c329-445b-80c2-2681d09fe481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043486035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1043486035
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2308881013
Short name T370
Test name
Test status
Simulation time 332152131 ps
CPU time 0.98 seconds
Started Feb 04 12:50:59 PM PST 24
Finished Feb 04 12:51:04 PM PST 24
Peak memory 183152 kb
Host smart-b291a3e9-a1d3-48fc-bb9d-497d7492176a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308881013 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2308881013
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1240146941
Short name T311
Test name
Test status
Simulation time 485518820 ps
CPU time 1.38 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 193356 kb
Host smart-d0b9ce26-76c0-441b-8154-8bb39b167443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240146941 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1240146941
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1336256430
Short name T86
Test name
Test status
Simulation time 395708866 ps
CPU time 0.65 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 192304 kb
Host smart-0b4acbd8-5d71-4ad7-adaa-bee55ed70b7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336256430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1336256430
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4025907964
Short name T16
Test name
Test status
Simulation time 290902714 ps
CPU time 0.75 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 182816 kb
Host smart-1052888e-999c-4461-989e-eaf44b7185f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025907964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4025907964
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2630240572
Short name T4
Test name
Test status
Simulation time 2093306550 ps
CPU time 1.72 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 193636 kb
Host smart-9d4e94b0-164d-4894-81d9-47bdc983d334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630240572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2630240572
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.516722878
Short name T339
Test name
Test status
Simulation time 403140655 ps
CPU time 2.04 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:41 PM PST 24
Peak memory 197840 kb
Host smart-f2a1cccd-fb40-41f7-a952-4c2a661c2603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516722878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.516722878
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1813015336
Short name T346
Test name
Test status
Simulation time 4138918975 ps
CPU time 2.46 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 196464 kb
Host smart-5797f714-cf27-4409-95f8-42cc28213a35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813015336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1813015336
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1844809505
Short name T360
Test name
Test status
Simulation time 538954130 ps
CPU time 0.9 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 195584 kb
Host smart-18b3d2f7-37b7-4a74-b260-df8ced84601d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844809505 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1844809505
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1361170072
Short name T410
Test name
Test status
Simulation time 456955712 ps
CPU time 0.64 seconds
Started Feb 04 12:50:37 PM PST 24
Finished Feb 04 12:50:46 PM PST 24
Peak memory 183028 kb
Host smart-b81ee66c-e7c8-4bad-bb45-6c179a91ebe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361170072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1361170072
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2661476329
Short name T312
Test name
Test status
Simulation time 352850576 ps
CPU time 1.14 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 183016 kb
Host smart-3d03422b-1526-41b7-9dab-28a180a5c398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661476329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2661476329
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3113734576
Short name T363
Test name
Test status
Simulation time 1621336777 ps
CPU time 1.24 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:39 PM PST 24
Peak memory 192572 kb
Host smart-eea8e778-a27d-47cc-b183-59257813a9e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113734576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3113734576
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.2009508290
Short name T404
Test name
Test status
Simulation time 564084732 ps
CPU time 1.99 seconds
Started Feb 04 12:50:27 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 197912 kb
Host smart-52b61ba4-587e-4f36-8a28-2b9a375e2012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009508290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.2009508290
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3780242395
Short name T423
Test name
Test status
Simulation time 4213552515 ps
CPU time 3.98 seconds
Started Feb 04 12:50:36 PM PST 24
Finished Feb 04 12:50:44 PM PST 24
Peak memory 196520 kb
Host smart-923e256b-b996-468b-8a44-6e6f035f95bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780242395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3780242395
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.1235654998
Short name T99
Test name
Test status
Simulation time 367516186 ps
CPU time 0.91 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 196444 kb
Host smart-2a6665a1-f453-4c75-9d74-27ae76336453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235654998 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.1235654998
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1769124041
Short name T366
Test name
Test status
Simulation time 508440474 ps
CPU time 0.81 seconds
Started Feb 04 12:50:29 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 182964 kb
Host smart-8dd31223-4791-463d-829a-22ce62fab98e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769124041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1769124041
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.631120191
Short name T421
Test name
Test status
Simulation time 389778101 ps
CPU time 1.11 seconds
Started Feb 04 12:50:26 PM PST 24
Finished Feb 04 12:50:30 PM PST 24
Peak memory 182788 kb
Host smart-8a06e07a-5c0c-400d-be4f-e1460cbf3d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631120191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.631120191
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1759519983
Short name T12
Test name
Test status
Simulation time 1777608502 ps
CPU time 3.63 seconds
Started Feb 04 12:50:27 PM PST 24
Finished Feb 04 12:50:33 PM PST 24
Peak memory 192568 kb
Host smart-05921b34-7e45-4a8f-af01-eeb02c65baf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759519983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1759519983
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1195828564
Short name T329
Test name
Test status
Simulation time 579416686 ps
CPU time 1.38 seconds
Started Feb 04 12:50:20 PM PST 24
Finished Feb 04 12:50:24 PM PST 24
Peak memory 197680 kb
Host smart-56d07934-94a8-4f1c-a660-190c8bd0f075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195828564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1195828564
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.4052551544
Short name T330
Test name
Test status
Simulation time 8276229479 ps
CPU time 4.55 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:54 PM PST 24
Peak memory 196896 kb
Host smart-29e7fd92-d13d-4d03-a3e8-6812793f4707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052551544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.4052551544
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.65069636
Short name T94
Test name
Test status
Simulation time 596534849 ps
CPU time 1.52 seconds
Started Feb 04 12:50:27 PM PST 24
Finished Feb 04 12:50:31 PM PST 24
Peak memory 195180 kb
Host smart-30ede7dc-f0ef-4ad0-ba0d-e1c4d0ca880e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65069636 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.65069636
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1037980294
Short name T1
Test name
Test status
Simulation time 341750039 ps
CPU time 1.16 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 183132 kb
Host smart-3ae634bc-ee2c-417d-89a0-36a08954ae82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037980294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1037980294
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.888436836
Short name T58
Test name
Test status
Simulation time 478712403 ps
CPU time 0.69 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:50 PM PST 24
Peak memory 183008 kb
Host smart-d1d37b53-7bdf-4156-b1d0-ebe3f7b49965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888436836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.888436836
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3827178220
Short name T402
Test name
Test status
Simulation time 1349963370 ps
CPU time 2.22 seconds
Started Feb 04 12:50:29 PM PST 24
Finished Feb 04 12:50:36 PM PST 24
Peak memory 193604 kb
Host smart-922f742b-9bf0-4477-abf1-0a32390297af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827178220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3827178220
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3897013667
Short name T56
Test name
Test status
Simulation time 578004005 ps
CPU time 2.38 seconds
Started Feb 04 12:50:45 PM PST 24
Finished Feb 04 12:50:52 PM PST 24
Peak memory 197904 kb
Host smart-574719c0-88e2-4273-9d32-187a53a8d633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897013667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3897013667
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4151670648
Short name T331
Test name
Test status
Simulation time 4456735736 ps
CPU time 2.25 seconds
Started Feb 04 12:50:40 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 195392 kb
Host smart-cfc52f25-80f3-44b8-b327-671c8f0eab2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151670648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4151670648
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1223764785
Short name T336
Test name
Test status
Simulation time 496484386 ps
CPU time 1.28 seconds
Started Feb 04 12:50:34 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 195164 kb
Host smart-74ce49ba-c44f-4367-a8dc-badff81aff79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223764785 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1223764785
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.565297200
Short name T428
Test name
Test status
Simulation time 546590903 ps
CPU time 0.85 seconds
Started Feb 04 12:50:35 PM PST 24
Finished Feb 04 12:50:40 PM PST 24
Peak memory 183136 kb
Host smart-119a0d2e-a663-464f-be85-cdf7aa80e87d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565297200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.565297200
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.560888202
Short name T348
Test name
Test status
Simulation time 348363994 ps
CPU time 0.7 seconds
Started Feb 04 12:50:33 PM PST 24
Finished Feb 04 12:50:38 PM PST 24
Peak memory 182968 kb
Host smart-d4f790c0-4427-4e68-89cf-01354fb76792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560888202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.560888202
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.4147455627
Short name T338
Test name
Test status
Simulation time 894082562 ps
CPU time 2.45 seconds
Started Feb 04 12:50:28 PM PST 24
Finished Feb 04 12:50:32 PM PST 24
Peak memory 192588 kb
Host smart-adcfb598-b0a5-41e9-9725-d2edaff19807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147455627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.4147455627
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.381718978
Short name T381
Test name
Test status
Simulation time 718984752 ps
CPU time 2.24 seconds
Started Feb 04 12:50:40 PM PST 24
Finished Feb 04 12:50:51 PM PST 24
Peak memory 197968 kb
Host smart-0367a449-cb0c-4c74-b215-6f6db12d0636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381718978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.381718978
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2934904467
Short name T9
Test name
Test status
Simulation time 8507005965 ps
CPU time 8.47 seconds
Started Feb 04 12:50:29 PM PST 24
Finished Feb 04 12:50:42 PM PST 24
Peak memory 197020 kb
Host smart-474a306b-3ec1-406a-959e-819995ce97b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934904467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2934904467
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1929532376
Short name T107
Test name
Test status
Simulation time 349263284 ps
CPU time 0.79 seconds
Started Feb 04 12:54:55 PM PST 24
Finished Feb 04 12:54:57 PM PST 24
Peak memory 183428 kb
Host smart-e7d7fd6d-4f49-474a-b900-8ffd00f189d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929532376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1929532376
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.683989526
Short name T147
Test name
Test status
Simulation time 36058029236 ps
CPU time 3.34 seconds
Started Feb 04 12:54:55 PM PST 24
Finished Feb 04 12:55:00 PM PST 24
Peak memory 183456 kb
Host smart-a3e75585-9e7b-4287-b6bd-d8468bff8bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683989526 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.683989526
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4053857353
Short name T278
Test name
Test status
Simulation time 381860129 ps
CPU time 1.03 seconds
Started Feb 04 12:54:46 PM PST 24
Finished Feb 04 12:54:49 PM PST 24
Peak memory 183260 kb
Host smart-b6726707-d7b2-4530-a58e-409c68a54b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053857353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4053857353
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.2111576634
Short name T95
Test name
Test status
Simulation time 17875869716 ps
CPU time 130.29 seconds
Started Feb 04 12:54:47 PM PST 24
Finished Feb 04 12:57:00 PM PST 24
Peak memory 198448 kb
Host smart-2ff18605-e004-49ad-bbe9-4449611809b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111576634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.2111576634
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1800186648
Short name T303
Test name
Test status
Simulation time 22781902289 ps
CPU time 18.74 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:44 PM PST 24
Peak memory 183128 kb
Host smart-76f4ca55-428e-4e7a-abe1-0c1905b15667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800186648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1800186648
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.2948802047
Short name T37
Test name
Test status
Simulation time 4128496600 ps
CPU time 2.34 seconds
Started Feb 04 12:55:20 PM PST 24
Finished Feb 04 12:55:23 PM PST 24
Peak memory 215300 kb
Host smart-99b7de5b-7014-4756-bacd-f62bf4a8a1c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948802047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.2948802047
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.646038149
Short name T149
Test name
Test status
Simulation time 428660343 ps
CPU time 0.88 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:20 PM PST 24
Peak memory 183312 kb
Host smart-7908956a-e8b6-46e5-b054-422960c8d4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646038149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.646038149
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2123298366
Short name T281
Test name
Test status
Simulation time 454607422272 ps
CPU time 845.19 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 01:09:29 PM PST 24
Peak memory 202960 kb
Host smart-5e5d3389-c4dd-4d0a-a913-d83baedf72ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123298366 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2123298366
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.630987185
Short name T282
Test name
Test status
Simulation time 581766204 ps
CPU time 0.83 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 183372 kb
Host smart-c6a44507-de49-43e5-a6a2-25934f26e6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630987185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.630987185
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1543900561
Short name T280
Test name
Test status
Simulation time 47226826975 ps
CPU time 36.9 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 183116 kb
Host smart-6ed9a4ef-2b1c-432d-a290-7be892ce1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543900561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1543900561
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3665447225
Short name T260
Test name
Test status
Simulation time 370654789 ps
CPU time 0.68 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:55:21 PM PST 24
Peak memory 183280 kb
Host smart-1b3b9c19-746d-4f93-b6dd-d34cf6bb32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665447225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3665447225
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1797568609
Short name T178
Test name
Test status
Simulation time 143858370011 ps
CPU time 317.42 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 01:00:58 PM PST 24
Peak memory 198476 kb
Host smart-ecb78cef-7e6b-419b-91c2-a5cff59d83da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797568609 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1797568609
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.556624584
Short name T167
Test name
Test status
Simulation time 32695734792 ps
CPU time 12.64 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183456 kb
Host smart-70f4918a-8930-401f-922e-51d40bd4f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556624584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.556624584
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3497551018
Short name T206
Test name
Test status
Simulation time 566184637 ps
CPU time 0.91 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:29 PM PST 24
Peak memory 183340 kb
Host smart-409b5eb4-1281-4ab2-b062-b32d188aea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497551018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3497551018
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.4217295138
Short name T132
Test name
Test status
Simulation time 109903882038 ps
CPU time 11.77 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 12:55:53 PM PST 24
Peak memory 183260 kb
Host smart-4a9cce8b-69bb-4861-971e-7905b1af1bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217295138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.4217295138
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.436789222
Short name T176
Test name
Test status
Simulation time 155163621952 ps
CPU time 429.37 seconds
Started Feb 04 12:55:30 PM PST 24
Finished Feb 04 01:02:42 PM PST 24
Peak memory 206556 kb
Host smart-495503a7-7042-4eba-911c-7819cce4a6a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436789222 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.436789222
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2071439104
Short name T276
Test name
Test status
Simulation time 349262740 ps
CPU time 1.07 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:27 PM PST 24
Peak memory 183368 kb
Host smart-ac627962-a0a1-48dc-9256-b654f45ded9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071439104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2071439104
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.2354368865
Short name T182
Test name
Test status
Simulation time 8082557643 ps
CPU time 3.78 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183492 kb
Host smart-5d1b1b79-0067-4e5d-afe6-ed9a115c1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354368865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.2354368865
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.403218963
Short name T275
Test name
Test status
Simulation time 370907207 ps
CPU time 0.65 seconds
Started Feb 04 12:55:29 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183300 kb
Host smart-cb7bd155-a65a-4a4e-bd71-6a999b350de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403218963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.403218963
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1176416226
Short name T271
Test name
Test status
Simulation time 330577082366 ps
CPU time 476.95 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 01:03:23 PM PST 24
Peak memory 193452 kb
Host smart-c14910d2-5f87-479b-ac4b-a9d0575cb20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176416226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1176416226
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1790866189
Short name T256
Test name
Test status
Simulation time 35650300964 ps
CPU time 346.24 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 01:01:15 PM PST 24
Peak memory 198392 kb
Host smart-0e9dcefc-ff7f-4e93-a1d2-24657478018d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790866189 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1790866189
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.385793800
Short name T197
Test name
Test status
Simulation time 407235667 ps
CPU time 1.12 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:28 PM PST 24
Peak memory 183364 kb
Host smart-3139a75d-baf8-456e-a261-429f57749b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385793800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.385793800
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.1351846982
Short name T306
Test name
Test status
Simulation time 60112159082 ps
CPU time 9.23 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:35 PM PST 24
Peak memory 183508 kb
Host smart-e467be9b-f088-452b-b748-fc76e2f39128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351846982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.1351846982
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.4146174480
Short name T253
Test name
Test status
Simulation time 369381991 ps
CPU time 0.77 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:28 PM PST 24
Peak memory 183272 kb
Host smart-c88b0284-ad09-4c1b-9758-2ef7bf6491ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146174480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4146174480
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.618434194
Short name T121
Test name
Test status
Simulation time 104086697054 ps
CPU time 163.8 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:58:09 PM PST 24
Peak memory 191712 kb
Host smart-5f700ee6-1f42-4de0-b125-cc69dfc2d815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618434194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_a
ll.618434194
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.4241392088
Short name T66
Test name
Test status
Simulation time 22212447931 ps
CPU time 73.5 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:56:41 PM PST 24
Peak memory 198440 kb
Host smart-39e58667-96d9-43c7-84c0-3f849dfb6d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241392088 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.4241392088
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3631462593
Short name T198
Test name
Test status
Simulation time 381484824 ps
CPU time 1.03 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183416 kb
Host smart-cd1cd848-740a-436b-8e28-72b4d16a1f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631462593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3631462593
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3412559309
Short name T33
Test name
Test status
Simulation time 10870331290 ps
CPU time 1.38 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:55:22 PM PST 24
Peak memory 183492 kb
Host smart-7a989a0b-89ea-41a0-8149-495f631aca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412559309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3412559309
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3385377384
Short name T143
Test name
Test status
Simulation time 386384240 ps
CPU time 0.78 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:30 PM PST 24
Peak memory 183248 kb
Host smart-3d822b95-431c-4fa1-8011-de9772291567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385377384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3385377384
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2986366258
Short name T239
Test name
Test status
Simulation time 221482340128 ps
CPU time 71.02 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:56:41 PM PST 24
Peak memory 183536 kb
Host smart-fbd925ad-15b7-4b29-b22d-89e0c0a6506e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986366258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2986366258
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.79667221
Short name T165
Test name
Test status
Simulation time 24152575197 ps
CPU time 216.08 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:59:07 PM PST 24
Peak memory 198424 kb
Host smart-693c424b-d70e-42e2-a370-e14d7d93f493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79667221 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.79667221
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1375345515
Short name T261
Test name
Test status
Simulation time 549082492 ps
CPU time 0.74 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:32 PM PST 24
Peak memory 183368 kb
Host smart-58f418ad-7d35-4b7c-bd13-8e447be54ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375345515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1375345515
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1141364003
Short name T259
Test name
Test status
Simulation time 47039373644 ps
CPU time 77.39 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:56:48 PM PST 24
Peak memory 183472 kb
Host smart-08962928-741e-480e-afba-6cf4e3587def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141364003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1141364003
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2515664557
Short name T186
Test name
Test status
Simulation time 550602118 ps
CPU time 0.56 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 183408 kb
Host smart-0c0180f0-d6df-4f86-9571-779a25813b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515664557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2515664557
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1914991598
Short name T110
Test name
Test status
Simulation time 25191002958 ps
CPU time 20.52 seconds
Started Feb 04 12:55:33 PM PST 24
Finished Feb 04 12:56:01 PM PST 24
Peak memory 183488 kb
Host smart-ea0e9851-c133-412d-90e8-f112b2be8dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914991598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1914991598
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.3539360322
Short name T64
Test name
Test status
Simulation time 21787948270 ps
CPU time 178.54 seconds
Started Feb 04 12:55:33 PM PST 24
Finished Feb 04 12:58:40 PM PST 24
Peak memory 198396 kb
Host smart-7d17bb7a-2b86-438c-912e-cd64103136bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539360322 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.3539360322
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1449499461
Short name T123
Test name
Test status
Simulation time 381001773 ps
CPU time 1.06 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 183368 kb
Host smart-710c68a9-c214-4541-b785-5ba9e34b10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449499461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1449499461
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3218160505
Short name T274
Test name
Test status
Simulation time 37362156036 ps
CPU time 47.49 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 183400 kb
Host smart-19448f86-9286-4cdc-ab87-1a039bc190ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218160505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3218160505
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2827375068
Short name T175
Test name
Test status
Simulation time 593084219 ps
CPU time 0.99 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183084 kb
Host smart-f9a2b6d9-d785-4191-a130-6b4a13f5382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827375068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2827375068
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2230818201
Short name T288
Test name
Test status
Simulation time 122482540200 ps
CPU time 48.79 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:56:14 PM PST 24
Peak memory 193600 kb
Host smart-f7f3d6a8-86e3-4fed-88f1-a2619dd4b911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230818201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2230818201
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3349567864
Short name T160
Test name
Test status
Simulation time 14231917949 ps
CPU time 69.89 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:56:42 PM PST 24
Peak memory 198368 kb
Host smart-31ac464c-c781-42f2-988f-aba339c8c12e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349567864 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3349567864
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1460429442
Short name T226
Test name
Test status
Simulation time 373417430 ps
CPU time 0.68 seconds
Started Feb 04 12:55:33 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183364 kb
Host smart-cdc4c2e4-8671-4211-8acb-71eccd99a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460429442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1460429442
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.263399146
Short name T285
Test name
Test status
Simulation time 40494326343 ps
CPU time 34.28 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 12:56:16 PM PST 24
Peak memory 183440 kb
Host smart-74e041a9-720c-44ed-aa58-977b4a365150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263399146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.263399146
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.426553648
Short name T298
Test name
Test status
Simulation time 474566617 ps
CPU time 1.23 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183316 kb
Host smart-acf33c71-49bd-42e9-8eb9-de43d350c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426553648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.426553648
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.3709382264
Short name T51
Test name
Test status
Simulation time 413222232569 ps
CPU time 305.51 seconds
Started Feb 04 12:55:33 PM PST 24
Finished Feb 04 01:00:46 PM PST 24
Peak memory 183488 kb
Host smart-aa17a8d5-1000-48ac-bb32-57606517ccec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709382264 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.3709382264
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3481066892
Short name T43
Test name
Test status
Simulation time 470168109 ps
CPU time 0.7 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:55:23 PM PST 24
Peak memory 183236 kb
Host smart-44d29a9d-78f4-4062-9b4f-a2b5566922cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481066892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3481066892
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1586561315
Short name T251
Test name
Test status
Simulation time 22574703914 ps
CPU time 15.48 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:46 PM PST 24
Peak memory 183492 kb
Host smart-e119ee39-1b55-4983-be9e-8524deaee123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586561315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1586561315
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3026468580
Short name T145
Test name
Test status
Simulation time 441041290 ps
CPU time 1.26 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 12:55:43 PM PST 24
Peak memory 183204 kb
Host smart-3589b44d-e925-4e8d-9e25-03baa44913fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026468580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3026468580
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1760205659
Short name T173
Test name
Test status
Simulation time 42181215505 ps
CPU time 4.36 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:35 PM PST 24
Peak memory 191720 kb
Host smart-21128eb0-6732-4559-bb3c-f0a4e948b943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760205659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1760205659
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2016748372
Short name T304
Test name
Test status
Simulation time 91908282493 ps
CPU time 763.12 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 01:08:05 PM PST 24
Peak memory 200984 kb
Host smart-dc9e19ff-f326-4364-b541-d3a486b274f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016748372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2016748372
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2118718222
Short name T223
Test name
Test status
Simulation time 478500267 ps
CPU time 1.28 seconds
Started Feb 04 12:55:20 PM PST 24
Finished Feb 04 12:55:22 PM PST 24
Peak memory 183408 kb
Host smart-bc2e0ba0-a234-4d4f-b200-9ffec1bb35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118718222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2118718222
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.544386737
Short name T136
Test name
Test status
Simulation time 8222521827 ps
CPU time 13.64 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:41 PM PST 24
Peak memory 183440 kb
Host smart-20e1e1c9-70fe-465a-a9d7-5aca91db34f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544386737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.544386737
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2437296389
Short name T213
Test name
Test status
Simulation time 442267284 ps
CPU time 0.69 seconds
Started Feb 04 12:55:20 PM PST 24
Finished Feb 04 12:55:21 PM PST 24
Peak memory 183120 kb
Host smart-b4b47716-e159-4613-9703-3bf82b443875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437296389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2437296389
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1414350459
Short name T224
Test name
Test status
Simulation time 94664024249 ps
CPU time 127.28 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:57:29 PM PST 24
Peak memory 183360 kb
Host smart-ede08669-e1f6-4211-b8b9-c7e39a67a1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414350459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1414350459
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_jump.973378132
Short name T126
Test name
Test status
Simulation time 453001630 ps
CPU time 0.73 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:26 PM PST 24
Peak memory 183416 kb
Host smart-50ec129c-2946-47a0-8d39-31a161676a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973378132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.973378132
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2375650720
Short name T174
Test name
Test status
Simulation time 661864391 ps
CPU time 1.1 seconds
Started Feb 04 12:55:13 PM PST 24
Finished Feb 04 12:55:16 PM PST 24
Peak memory 183400 kb
Host smart-e198893c-68f9-40f0-bc93-b07153b279a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375650720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2375650720
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1187139132
Short name T38
Test name
Test status
Simulation time 8148436519 ps
CPU time 9.93 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:29 PM PST 24
Peak memory 215752 kb
Host smart-7c1841db-fabb-4807-94f6-9af3726de2ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187139132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1187139132
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1086974050
Short name T210
Test name
Test status
Simulation time 502286870 ps
CPU time 0.71 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:55:23 PM PST 24
Peak memory 183372 kb
Host smart-a5d5dd96-dd4e-4ea3-9059-999bc1f3a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086974050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1086974050
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2882238165
Short name T118
Test name
Test status
Simulation time 34374284191 ps
CPU time 49.5 seconds
Started Feb 04 12:55:15 PM PST 24
Finished Feb 04 12:56:05 PM PST 24
Peak memory 193384 kb
Host smart-49be3e9b-17d1-4b55-bae3-c2d2ae6f27eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882238165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2882238165
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3093895402
Short name T208
Test name
Test status
Simulation time 517393474 ps
CPU time 0.82 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:26 PM PST 24
Peak memory 183412 kb
Host smart-57e4a52d-722c-44c3-91d2-9383d1b98f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093895402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3093895402
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2266779374
Short name T266
Test name
Test status
Simulation time 20562752015 ps
CPU time 4.58 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:55:26 PM PST 24
Peak memory 183440 kb
Host smart-288d8974-6429-46a9-832e-f36d788edaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266779374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2266779374
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1190317718
Short name T265
Test name
Test status
Simulation time 424565663 ps
CPU time 0.68 seconds
Started Feb 04 12:55:20 PM PST 24
Finished Feb 04 12:55:21 PM PST 24
Peak memory 183296 kb
Host smart-c82de920-25f5-42ba-be79-aebd5822c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190317718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1190317718
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.2124120585
Short name T108
Test name
Test status
Simulation time 253408482708 ps
CPU time 404.78 seconds
Started Feb 04 12:55:30 PM PST 24
Finished Feb 04 01:02:17 PM PST 24
Peak memory 183428 kb
Host smart-08c5dd9c-a878-4209-931a-cd4c14e6fa4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124120585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.2124120585
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1096035407
Short name T241
Test name
Test status
Simulation time 17515417520 ps
CPU time 177.19 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:58:26 PM PST 24
Peak memory 198408 kb
Host smart-93feee24-d321-42af-8189-f60e69a54065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096035407 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1096035407
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3903703465
Short name T286
Test name
Test status
Simulation time 561172408 ps
CPU time 1.45 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:29 PM PST 24
Peak memory 183412 kb
Host smart-b1733f1c-ddcc-4163-b43f-0df8a793bdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903703465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3903703465
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3965680219
Short name T172
Test name
Test status
Simulation time 32918493454 ps
CPU time 48.92 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:56:15 PM PST 24
Peak memory 183500 kb
Host smart-28d8a1a3-9f3e-4c80-a98f-c88da0160da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965680219 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3965680219
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1746522097
Short name T203
Test name
Test status
Simulation time 561192132 ps
CPU time 1.34 seconds
Started Feb 04 12:55:34 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183324 kb
Host smart-1d258e23-3fb5-4f92-998f-ea816173026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746522097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1746522097
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3950469196
Short name T297
Test name
Test status
Simulation time 394032290615 ps
CPU time 166.71 seconds
Started Feb 04 12:55:29 PM PST 24
Finished Feb 04 12:58:19 PM PST 24
Peak memory 183428 kb
Host smart-eae3e5d6-2134-49ed-9604-ff167a2751d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950469196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3950469196
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1489493044
Short name T98
Test name
Test status
Simulation time 82745866959 ps
CPU time 598.89 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 01:05:28 PM PST 24
Peak memory 198712 kb
Host smart-faa64f30-5cda-470f-99c3-e34fd222ee3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489493044 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1489493044
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2264920419
Short name T245
Test name
Test status
Simulation time 516462504 ps
CPU time 1.3 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:28 PM PST 24
Peak memory 183392 kb
Host smart-7ea1bc57-f26b-42d9-9ba7-95a9f2429f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264920419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2264920419
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.1813785291
Short name T21
Test name
Test status
Simulation time 37432700443 ps
CPU time 28.86 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:58 PM PST 24
Peak memory 183476 kb
Host smart-0ade00cb-0bc3-4a2a-8ef2-18aa20bfd81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813785291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.1813785291
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.2455509880
Short name T228
Test name
Test status
Simulation time 523013267 ps
CPU time 0.99 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:27 PM PST 24
Peak memory 183296 kb
Host smart-45e940a1-1052-4688-9f09-ae8aa580e4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455509880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.2455509880
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2845408912
Short name T207
Test name
Test status
Simulation time 61218422167 ps
CPU time 25.15 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:52 PM PST 24
Peak memory 193668 kb
Host smart-c98231f2-7b65-450e-9792-77d4ed57549a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845408912 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2845408912
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.959637094
Short name T112
Test name
Test status
Simulation time 41157488204 ps
CPU time 413.68 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 01:02:22 PM PST 24
Peak memory 198416 kb
Host smart-b362f236-8b31-478b-9c74-783aa34a0a3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959637094 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.959637094
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3736757087
Short name T122
Test name
Test status
Simulation time 433839635 ps
CPU time 0.72 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:28 PM PST 24
Peak memory 183388 kb
Host smart-0876d0e2-eb9b-4708-952b-ebed09ed5b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736757087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3736757087
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.1562430915
Short name T201
Test name
Test status
Simulation time 39816759065 ps
CPU time 3.76 seconds
Started Feb 04 12:55:26 PM PST 24
Finished Feb 04 12:55:32 PM PST 24
Peak memory 183452 kb
Host smart-b0e4f1a6-1cef-4dcc-bce7-1ab3500dd716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562430915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.1562430915
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.54378736
Short name T141
Test name
Test status
Simulation time 478923057 ps
CPU time 1.36 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183356 kb
Host smart-b859b2e2-106a-48cb-b1c1-907ffd85cd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54378736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.54378736
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.215401680
Short name T128
Test name
Test status
Simulation time 90364126526 ps
CPU time 137.86 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:57:50 PM PST 24
Peak memory 183348 kb
Host smart-ba7606bf-80d6-4557-a8b6-aaf1d85cb5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215401680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_a
ll.215401680
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1247660250
Short name T214
Test name
Test status
Simulation time 35443456817 ps
CPU time 179.83 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:58:30 PM PST 24
Peak memory 198472 kb
Host smart-b1d0e975-9a3c-40fb-824f-8e60b1d71c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247660250 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1247660250
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.756902709
Short name T294
Test name
Test status
Simulation time 582043251 ps
CPU time 0.95 seconds
Started Feb 04 12:55:29 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183320 kb
Host smart-464cae3b-b2da-4a69-b1ac-0e3a2ebb1e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756902709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.756902709
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2005166275
Short name T81
Test name
Test status
Simulation time 2414364948 ps
CPU time 1.04 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:32 PM PST 24
Peak memory 183484 kb
Host smart-b50d1648-e7d1-4f5f-8eda-773e14ecc9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005166275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2005166275
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.3710139487
Short name T231
Test name
Test status
Simulation time 551708919 ps
CPU time 1.48 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 183200 kb
Host smart-5f5d1c5e-46ec-46b1-b5a9-ee04e4ae3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710139487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.3710139487
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2955686311
Short name T234
Test name
Test status
Simulation time 74592351052 ps
CPU time 9.42 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 12:55:40 PM PST 24
Peak memory 183488 kb
Host smart-926fc5d9-6c37-45f2-8c8c-ae2317bd57e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955686311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2955686311
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1610678670
Short name T289
Test name
Test status
Simulation time 509337131968 ps
CPU time 1282.57 seconds
Started Feb 04 12:55:27 PM PST 24
Finished Feb 04 01:16:53 PM PST 24
Peak memory 209000 kb
Host smart-469288f5-73ca-43e2-8dca-62b90cb6d1d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610678670 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1610678670
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4123390712
Short name T155
Test name
Test status
Simulation time 546029097 ps
CPU time 0.76 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183396 kb
Host smart-ddcabe5f-b949-442f-a01d-0ad427cb7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123390712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4123390712
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.2300888427
Short name T161
Test name
Test status
Simulation time 56733064298 ps
CPU time 20.72 seconds
Started Feb 04 12:55:35 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 183460 kb
Host smart-dab8fc09-a631-4d88-92b0-f702b40791d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300888427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.2300888427
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.4213540721
Short name T225
Test name
Test status
Simulation time 360582729 ps
CPU time 0.67 seconds
Started Feb 04 12:55:28 PM PST 24
Finished Feb 04 12:55:32 PM PST 24
Peak memory 183308 kb
Host smart-52ffed90-8aa4-4074-8762-bff88c86502e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213540721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.4213540721
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3114013225
Short name T236
Test name
Test status
Simulation time 168871149586 ps
CPU time 33.16 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:56:24 PM PST 24
Peak memory 193704 kb
Host smart-f35e1b9c-9dee-4023-849e-c5b413120b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114013225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3114013225
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4118645180
Short name T217
Test name
Test status
Simulation time 94878341678 ps
CPU time 243.05 seconds
Started Feb 04 12:55:43 PM PST 24
Finished Feb 04 12:59:53 PM PST 24
Peak memory 198404 kb
Host smart-83f558b8-e829-4dab-88c4-a7969db591ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118645180 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4118645180
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.4138598068
Short name T42
Test name
Test status
Simulation time 517429645 ps
CPU time 0.74 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:55:46 PM PST 24
Peak memory 183396 kb
Host smart-4670043f-1e0d-4cd3-be55-d0ebb384592f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138598068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.4138598068
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.4199482238
Short name T152
Test name
Test status
Simulation time 17055494657 ps
CPU time 24.49 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:56:10 PM PST 24
Peak memory 183480 kb
Host smart-4c167730-041f-4b16-99ba-121de1d13b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199482238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.4199482238
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3109335747
Short name T154
Test name
Test status
Simulation time 505276381 ps
CPU time 0.71 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:55:46 PM PST 24
Peak memory 183252 kb
Host smart-7b95d5a1-03d7-40bd-aca4-1a4aab1d375f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109335747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3109335747
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.4263067116
Short name T130
Test name
Test status
Simulation time 459366918152 ps
CPU time 177.68 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 12:58:41 PM PST 24
Peak memory 194632 kb
Host smart-273e3585-3763-4823-af41-f373e3aaf826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263067116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.4263067116
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3653748122
Short name T300
Test name
Test status
Simulation time 56961324680 ps
CPU time 119.97 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 12:57:53 PM PST 24
Peak memory 206624 kb
Host smart-f9e47aa1-ae01-4534-93c4-d14b32381506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653748122 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3653748122
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.1300809378
Short name T258
Test name
Test status
Simulation time 624362400 ps
CPU time 0.77 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:55:52 PM PST 24
Peak memory 183344 kb
Host smart-978086aa-26b8-4b9c-b75b-ff5c7e797dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300809378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.1300809378
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3229994285
Short name T144
Test name
Test status
Simulation time 38104743420 ps
CPU time 52.36 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:56:37 PM PST 24
Peak memory 182872 kb
Host smart-4650fa49-0528-420a-978d-5041dcef1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229994285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3229994285
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3184767989
Short name T309
Test name
Test status
Simulation time 382204976 ps
CPU time 1.11 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:55:46 PM PST 24
Peak memory 183396 kb
Host smart-0fa5c6af-f819-48e0-801a-6cb2c05dbc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184767989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3184767989
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.2887720460
Short name T97
Test name
Test status
Simulation time 27619232823 ps
CPU time 187.05 seconds
Started Feb 04 12:55:37 PM PST 24
Finished Feb 04 12:58:48 PM PST 24
Peak memory 198452 kb
Host smart-4af438ab-aa8a-4643-a29a-cb8a1e39b045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887720460 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.2887720460
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.621381278
Short name T151
Test name
Test status
Simulation time 564120704 ps
CPU time 1.37 seconds
Started Feb 04 12:55:37 PM PST 24
Finished Feb 04 12:55:43 PM PST 24
Peak memory 183384 kb
Host smart-95ccba78-eda0-474d-8684-ff6770cbb82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621381278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.621381278
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1203867979
Short name T177
Test name
Test status
Simulation time 6443129504 ps
CPU time 2.97 seconds
Started Feb 04 12:55:43 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183420 kb
Host smart-9cb049b6-b644-4a82-8336-2bc07a05908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203867979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1203867979
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2928576641
Short name T205
Test name
Test status
Simulation time 518792475 ps
CPU time 0.92 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183116 kb
Host smart-e609a19c-5416-4765-80c9-bcdbd5cbf2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928576641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2928576641
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.2524701505
Short name T124
Test name
Test status
Simulation time 185465592355 ps
CPU time 272.66 seconds
Started Feb 04 12:55:43 PM PST 24
Finished Feb 04 01:00:23 PM PST 24
Peak memory 183452 kb
Host smart-7a29b6a7-b756-4635-a10f-2da9bf1d3ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524701505 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.2524701505
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3527836321
Short name T292
Test name
Test status
Simulation time 30371564022 ps
CPU time 145.29 seconds
Started Feb 04 12:55:40 PM PST 24
Finished Feb 04 12:58:10 PM PST 24
Peak memory 198452 kb
Host smart-1dfbf7d9-832f-47e3-989d-48a87adf12e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527836321 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3527836321
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2203968083
Short name T125
Test name
Test status
Simulation time 558576146 ps
CPU time 0.88 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183316 kb
Host smart-f89ce46a-6b3c-400f-b221-ea6cdae6eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203968083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2203968083
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2413701403
Short name T216
Test name
Test status
Simulation time 12652643258 ps
CPU time 5.21 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 183444 kb
Host smart-5508fd7d-2e20-4da9-b3c6-30150e01a21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413701403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2413701403
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1173049053
Short name T246
Test name
Test status
Simulation time 532682915 ps
CPU time 1.3 seconds
Started Feb 04 12:55:37 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183248 kb
Host smart-c913f8cb-b6d7-487d-8185-911c0046ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173049053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1173049053
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1036791586
Short name T103
Test name
Test status
Simulation time 237946450472 ps
CPU time 379.51 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 01:02:13 PM PST 24
Peak memory 183476 kb
Host smart-a842684c-a175-41f2-a0d4-248c283faf7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036791586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1036791586
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.2445868383
Short name T61
Test name
Test status
Simulation time 281243107845 ps
CPU time 941.08 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 01:11:25 PM PST 24
Peak memory 202256 kb
Host smart-7d66298b-dbc0-477c-96c8-1eee59029e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445868383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.2445868383
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1825187412
Short name T184
Test name
Test status
Simulation time 501020922 ps
CPU time 0.9 seconds
Started Feb 04 12:55:12 PM PST 24
Finished Feb 04 12:55:14 PM PST 24
Peak memory 183408 kb
Host smart-309d858e-8b51-41a1-b130-35530d6b0fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825187412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1825187412
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3937110565
Short name T244
Test name
Test status
Simulation time 38705187978 ps
CPU time 53.55 seconds
Started Feb 04 12:55:23 PM PST 24
Finished Feb 04 12:56:18 PM PST 24
Peak memory 183404 kb
Host smart-f3815fc5-6838-4a0a-ae43-419acdaae436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937110565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3937110565
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1341058257
Short name T35
Test name
Test status
Simulation time 4504357062 ps
CPU time 2.22 seconds
Started Feb 04 12:55:15 PM PST 24
Finished Feb 04 12:55:18 PM PST 24
Peak memory 215632 kb
Host smart-b31bc91c-ae1e-4d6f-8dc7-227254b4d87a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341058257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1341058257
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1847125325
Short name T48
Test name
Test status
Simulation time 559663320 ps
CPU time 1.01 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:20 PM PST 24
Peak memory 183392 kb
Host smart-89c23957-b1c6-4b55-9ae6-a033bfbfdeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847125325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1847125325
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4270054825
Short name T40
Test name
Test status
Simulation time 143958775816 ps
CPU time 211.75 seconds
Started Feb 04 12:55:15 PM PST 24
Finished Feb 04 12:58:48 PM PST 24
Peak memory 193772 kb
Host smart-0b8b011c-46a3-487f-832f-79d286b8f3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270054825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4270054825
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2005312750
Short name T131
Test name
Test status
Simulation time 39247512333 ps
CPU time 171.02 seconds
Started Feb 04 12:55:13 PM PST 24
Finished Feb 04 12:58:05 PM PST 24
Peak memory 198332 kb
Host smart-f2b95c35-c44f-47cb-8f9f-47719c2675d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005312750 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2005312750
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.825293076
Short name T29
Test name
Test status
Simulation time 403173418 ps
CPU time 1.2 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:55:53 PM PST 24
Peak memory 183380 kb
Host smart-9604b3eb-a5fb-4deb-91bf-f6f6ffc9611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825293076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.825293076
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2717467436
Short name T293
Test name
Test status
Simulation time 5275199188 ps
CPU time 9.33 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:56:01 PM PST 24
Peak memory 183436 kb
Host smart-58140151-a415-4db9-91a7-3002970b3d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717467436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2717467436
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4231795602
Short name T156
Test name
Test status
Simulation time 421603286 ps
CPU time 0.75 seconds
Started Feb 04 12:55:39 PM PST 24
Finished Feb 04 12:55:44 PM PST 24
Peak memory 183284 kb
Host smart-3e8eceef-9754-4cdc-a6d9-2e9956ac6817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231795602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4231795602
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.781048233
Short name T307
Test name
Test status
Simulation time 294075465187 ps
CPU time 105.83 seconds
Started Feb 04 12:55:37 PM PST 24
Finished Feb 04 12:57:27 PM PST 24
Peak memory 183488 kb
Host smart-1ba422d0-c657-40a9-8494-d161ae207b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781048233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_a
ll.781048233
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.3167949241
Short name T219
Test name
Test status
Simulation time 111953123840 ps
CPU time 238.87 seconds
Started Feb 04 12:55:39 PM PST 24
Finished Feb 04 12:59:42 PM PST 24
Peak memory 198252 kb
Host smart-e94ffc8a-37dc-4bc9-a354-a2cc427334d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167949241 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.3167949241
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3684668867
Short name T221
Test name
Test status
Simulation time 585830385 ps
CPU time 0.58 seconds
Started Feb 04 12:55:35 PM PST 24
Finished Feb 04 12:55:42 PM PST 24
Peak memory 183388 kb
Host smart-4b6f3d76-0ff5-47e9-ae36-f67bcb23387b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684668867 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3684668867
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2091858883
Short name T83
Test name
Test status
Simulation time 10408493452 ps
CPU time 17.43 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:56:09 PM PST 24
Peak memory 183476 kb
Host smart-6552f70c-9f60-44d7-89ad-b1f933f07ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091858883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2091858883
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2452548101
Short name T200
Test name
Test status
Simulation time 539300720 ps
CPU time 0.87 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183112 kb
Host smart-62df65ef-824c-42c6-9080-0f94e2f0b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452548101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2452548101
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3508171386
Short name T270
Test name
Test status
Simulation time 118440350599 ps
CPU time 97.65 seconds
Started Feb 04 12:55:43 PM PST 24
Finished Feb 04 12:57:28 PM PST 24
Peak memory 193516 kb
Host smart-f6537850-d28d-4846-9817-f45ca059034c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508171386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3508171386
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.1019514986
Short name T295
Test name
Test status
Simulation time 86600999457 ps
CPU time 111.67 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:57:44 PM PST 24
Peak memory 198392 kb
Host smart-dcc3fc41-2b27-4f4d-a065-c7339484b669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019514986 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.1019514986
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3183971092
Short name T212
Test name
Test status
Simulation time 436140832 ps
CPU time 0.9 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183292 kb
Host smart-df454441-7068-4efa-b9a4-db41c80c1d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183971092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3183971092
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3085912576
Short name T23
Test name
Test status
Simulation time 38030768594 ps
CPU time 52.51 seconds
Started Feb 04 12:55:38 PM PST 24
Finished Feb 04 12:56:36 PM PST 24
Peak memory 183424 kb
Host smart-2b1ab554-37e8-4333-950a-ee7894f80924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085912576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3085912576
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1164605360
Short name T193
Test name
Test status
Simulation time 345281586 ps
CPU time 1.08 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183260 kb
Host smart-1e335312-823d-41a1-85d5-600641b70a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164605360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1164605360
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.283627529
Short name T252
Test name
Test status
Simulation time 170080386379 ps
CPU time 128.05 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:57:59 PM PST 24
Peak memory 193828 kb
Host smart-e4d4a870-e302-4cf0-ad4c-a3714b406672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283627529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.283627529
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.1483678712
Short name T113
Test name
Test status
Simulation time 143269853600 ps
CPU time 548.65 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 01:05:00 PM PST 24
Peak memory 198532 kb
Host smart-0d20e4fd-95ae-4523-a078-d935aa3b68d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483678712 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.1483678712
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2553542196
Short name T170
Test name
Test status
Simulation time 478420894 ps
CPU time 1.16 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:55:47 PM PST 24
Peak memory 183388 kb
Host smart-d9ef2a27-446a-4a54-a2d6-bbdf4ed83e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553542196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2553542196
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3734679752
Short name T242
Test name
Test status
Simulation time 23763358756 ps
CPU time 34.97 seconds
Started Feb 04 12:55:41 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 183352 kb
Host smart-4d7b259e-1a05-403b-8b9d-f0a7b6753c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734679752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3734679752
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.902531996
Short name T85
Test name
Test status
Simulation time 562431118 ps
CPU time 1.27 seconds
Started Feb 04 12:55:39 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183264 kb
Host smart-17d4355d-3657-4d36-a792-667fa496b425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902531996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.902531996
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.3387992708
Short name T191
Test name
Test status
Simulation time 78088850043 ps
CPU time 34.09 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:56:26 PM PST 24
Peak memory 183516 kb
Host smart-37489ab3-5679-4c4c-91d9-f1dae9ca0e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387992708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.3387992708
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1857332876
Short name T247
Test name
Test status
Simulation time 581809739 ps
CPU time 1.22 seconds
Started Feb 04 12:55:40 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183408 kb
Host smart-2eb46e8f-791c-4f28-b70a-48797c708ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857332876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1857332876
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2936802892
Short name T162
Test name
Test status
Simulation time 35258956111 ps
CPU time 6.16 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:59 PM PST 24
Peak memory 183516 kb
Host smart-f7d9c42d-81ed-4c5d-8380-b343e1e33e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936802892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2936802892
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3241855476
Short name T199
Test name
Test status
Simulation time 373203552 ps
CPU time 0.91 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183284 kb
Host smart-21242b61-c307-4d0f-aee0-97cc78690e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241855476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3241855476
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.1727981271
Short name T171
Test name
Test status
Simulation time 263708137773 ps
CPU time 111.47 seconds
Started Feb 04 12:55:40 PM PST 24
Finished Feb 04 12:57:36 PM PST 24
Peak memory 193792 kb
Host smart-1cb006e3-82a6-4a66-b675-e79e4ae3d80f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727981271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.1727981271
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.550841266
Short name T166
Test name
Test status
Simulation time 72228872747 ps
CPU time 159.11 seconds
Started Feb 04 12:55:48 PM PST 24
Finished Feb 04 12:58:32 PM PST 24
Peak memory 198428 kb
Host smart-b598c582-009e-4d77-a735-35b83df0c3ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550841266 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.550841266
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2213735469
Short name T106
Test name
Test status
Simulation time 520976240 ps
CPU time 1.35 seconds
Started Feb 04 12:55:40 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183400 kb
Host smart-b948c0f4-92d2-400b-9d82-dc92fdcc85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213735469 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2213735469
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2982422932
Short name T257
Test name
Test status
Simulation time 11309824129 ps
CPU time 5.65 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 12:55:51 PM PST 24
Peak memory 183464 kb
Host smart-735b1102-06ff-45ed-81ba-4792ee7a521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982422932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2982422932
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.1452646524
Short name T190
Test name
Test status
Simulation time 495895697 ps
CPU time 0.88 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:55:53 PM PST 24
Peak memory 183344 kb
Host smart-527d1f6d-725a-4249-9807-cd70ed45d629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452646524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.1452646524
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4077696757
Short name T39
Test name
Test status
Simulation time 463467289 ps
CPU time 0.68 seconds
Started Feb 04 12:55:48 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183316 kb
Host smart-51e3636f-69c2-45d7-b152-40cb8238515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077696757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4077696757
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1678903883
Short name T233
Test name
Test status
Simulation time 415556845 ps
CPU time 1.19 seconds
Started Feb 04 12:55:43 PM PST 24
Finished Feb 04 12:55:51 PM PST 24
Peak memory 183296 kb
Host smart-62dc0201-d4a3-4c07-b678-bdd849a9db54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678903883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1678903883
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.4042719920
Short name T181
Test name
Test status
Simulation time 364506282 ps
CPU time 0.66 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:55:52 PM PST 24
Peak memory 183212 kb
Host smart-4eecaf4c-6f39-4f2e-9c0b-a99a09014740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042719920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.4042719920
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.1447984443
Short name T115
Test name
Test status
Simulation time 171215651564 ps
CPU time 38.48 seconds
Started Feb 04 12:55:44 PM PST 24
Finished Feb 04 12:56:30 PM PST 24
Peak memory 183448 kb
Host smart-57cddad6-b900-4104-b001-4a652193d5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447984443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.1447984443
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3369143961
Short name T255
Test name
Test status
Simulation time 222647131379 ps
CPU time 588.3 seconds
Started Feb 04 12:55:51 PM PST 24
Finished Feb 04 01:05:42 PM PST 24
Peak memory 199680 kb
Host smart-00f82141-bf9e-43ec-8797-d26552857857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369143961 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3369143961
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3189648959
Short name T157
Test name
Test status
Simulation time 575927470 ps
CPU time 1.02 seconds
Started Feb 04 12:55:51 PM PST 24
Finished Feb 04 12:55:55 PM PST 24
Peak memory 183084 kb
Host smart-7c569693-2ffe-4d26-bd20-41acf737d533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189648959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3189648959
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1058954012
Short name T188
Test name
Test status
Simulation time 30477447735 ps
CPU time 46.57 seconds
Started Feb 04 12:55:47 PM PST 24
Finished Feb 04 12:56:40 PM PST 24
Peak memory 183480 kb
Host smart-e7ea0e47-fe20-4d02-aba5-65d0d5a71ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058954012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1058954012
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3340466436
Short name T248
Test name
Test status
Simulation time 566192475 ps
CPU time 1.41 seconds
Started Feb 04 12:55:39 PM PST 24
Finished Feb 04 12:55:45 PM PST 24
Peak memory 183256 kb
Host smart-7ff74d93-a5ee-41f5-8420-319f6a2a05f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340466436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3340466436
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2605869367
Short name T268
Test name
Test status
Simulation time 425000661641 ps
CPU time 317.55 seconds
Started Feb 04 12:55:42 PM PST 24
Finished Feb 04 01:01:03 PM PST 24
Peak memory 191708 kb
Host smart-0da7f2d2-b131-4eeb-b7e0-80abe869cbe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605869367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2605869367
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1902355761
Short name T254
Test name
Test status
Simulation time 1603594408087 ps
CPU time 670.88 seconds
Started Feb 04 12:55:51 PM PST 24
Finished Feb 04 01:07:05 PM PST 24
Peak memory 200484 kb
Host smart-f393d235-928f-4f6c-9c83-991a7a35d075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902355761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1902355761
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.3805757285
Short name T185
Test name
Test status
Simulation time 370885315 ps
CPU time 0.69 seconds
Started Feb 04 12:55:46 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183296 kb
Host smart-0e684a17-b058-4ce9-8cfb-9a3aee554289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805757285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.3805757285
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.4200051619
Short name T148
Test name
Test status
Simulation time 48280157844 ps
CPU time 75.95 seconds
Started Feb 04 12:55:51 PM PST 24
Finished Feb 04 12:57:10 PM PST 24
Peak memory 183436 kb
Host smart-d1bf42fb-aa88-464a-bf45-d285b49c15eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200051619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.4200051619
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2349840905
Short name T227
Test name
Test status
Simulation time 572085970 ps
CPU time 0.77 seconds
Started Feb 04 12:55:45 PM PST 24
Finished Feb 04 12:55:53 PM PST 24
Peak memory 183220 kb
Host smart-41555cc3-143b-4866-a550-6c7916db29ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349840905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2349840905
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3070171837
Short name T283
Test name
Test status
Simulation time 157337548792 ps
CPU time 70.4 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:57:07 PM PST 24
Peak memory 183496 kb
Host smart-2fd4d8b7-bbc8-45d2-ac59-8e26eb302fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070171837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3070171837
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2586768327
Short name T209
Test name
Test status
Simulation time 77340068134 ps
CPU time 557.99 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 01:05:13 PM PST 24
Peak memory 206732 kb
Host smart-c1a613f8-32d9-47d1-b0a5-aa04ebf90203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586768327 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2586768327
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.297349564
Short name T158
Test name
Test status
Simulation time 580800697 ps
CPU time 0.76 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 183376 kb
Host smart-ae586e26-057c-4b2b-bef9-a9b7765cedef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297349564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.297349564
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1665914946
Short name T137
Test name
Test status
Simulation time 18155817998 ps
CPU time 14.47 seconds
Started Feb 04 12:55:57 PM PST 24
Finished Feb 04 12:56:14 PM PST 24
Peak memory 183452 kb
Host smart-9b1f032f-122a-494d-9063-5f7e8683a780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665914946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1665914946
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.1040251543
Short name T183
Test name
Test status
Simulation time 496925027 ps
CPU time 0.86 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 183224 kb
Host smart-a7eacdae-b9be-4f33-bb17-afe1e816030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040251543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.1040251543
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.611321082
Short name T119
Test name
Test status
Simulation time 62301684664 ps
CPU time 93.89 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:57:32 PM PST 24
Peak memory 193736 kb
Host smart-363eea77-ed5c-4ea3-95f5-9904f092e6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611321082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.611321082
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.4226281360
Short name T53
Test name
Test status
Simulation time 17295561312 ps
CPU time 161.19 seconds
Started Feb 04 12:55:57 PM PST 24
Finished Feb 04 12:58:40 PM PST 24
Peak memory 198448 kb
Host smart-b710b9b1-a053-4181-aab2-42059addfac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226281360 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.4226281360
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2900071826
Short name T179
Test name
Test status
Simulation time 598186166 ps
CPU time 1.41 seconds
Started Feb 04 12:55:10 PM PST 24
Finished Feb 04 12:55:13 PM PST 24
Peak memory 183360 kb
Host smart-3424b480-b009-474e-84c4-4c0a94f1ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900071826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2900071826
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1927886901
Short name T202
Test name
Test status
Simulation time 2806725729 ps
CPU time 5.13 seconds
Started Feb 04 12:55:23 PM PST 24
Finished Feb 04 12:55:29 PM PST 24
Peak memory 183444 kb
Host smart-3c4412fe-dca1-4b99-8556-771cc2dca615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927886901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1927886901
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1656333416
Short name T34
Test name
Test status
Simulation time 7629294890 ps
CPU time 12.97 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:55:33 PM PST 24
Peak memory 215844 kb
Host smart-acdd4d53-40ae-4814-9038-5dd3e863ae56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656333416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1656333416
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2567250992
Short name T153
Test name
Test status
Simulation time 458952020 ps
CPU time 1.21 seconds
Started Feb 04 12:55:17 PM PST 24
Finished Feb 04 12:55:19 PM PST 24
Peak memory 183124 kb
Host smart-25a567bf-7553-4749-b7c3-f9cb3830f127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567250992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2567250992
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2083997307
Short name T290
Test name
Test status
Simulation time 149324898840 ps
CPU time 186.66 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:58:27 PM PST 24
Peak memory 183564 kb
Host smart-663d5298-b588-4235-9efa-73ae8678e18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083997307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2083997307
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3377384710
Short name T192
Test name
Test status
Simulation time 61324539789 ps
CPU time 248.51 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:59:29 PM PST 24
Peak memory 198420 kb
Host smart-cec25f26-d9cb-46a1-9794-bd9ec06255ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377384710 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3377384710
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2130517792
Short name T168
Test name
Test status
Simulation time 491708435 ps
CPU time 1.44 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 183360 kb
Host smart-805ef416-3407-49ab-b4a9-26780a95fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130517792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2130517792
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.2964821515
Short name T301
Test name
Test status
Simulation time 18067919816 ps
CPU time 3.91 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:05 PM PST 24
Peak memory 183460 kb
Host smart-16c8db5a-4af3-4e89-b079-459be6e5dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964821515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.2964821515
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1408875595
Short name T267
Test name
Test status
Simulation time 570477493 ps
CPU time 0.64 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 183124 kb
Host smart-033fc180-fed6-43d4-81d6-7d850b8fd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408875595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1408875595
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3745689237
Short name T279
Test name
Test status
Simulation time 150993579608 ps
CPU time 30.73 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:32 PM PST 24
Peak memory 194860 kb
Host smart-4a7aabe5-a184-4357-bfdc-4cfe74486dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745689237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3745689237
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1607555383
Short name T277
Test name
Test status
Simulation time 35328130126 ps
CPU time 135.43 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:58:11 PM PST 24
Peak memory 198456 kb
Host smart-5e840eb3-5685-423a-80bb-5e72cb59548b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607555383 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1607555383
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1562011181
Short name T111
Test name
Test status
Simulation time 377805279 ps
CPU time 0.66 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 183392 kb
Host smart-a7d0ba96-7580-486f-b57a-5ab2c77fb08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562011181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1562011181
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.56038398
Short name T138
Test name
Test status
Simulation time 54508599508 ps
CPU time 24.21 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:56:27 PM PST 24
Peak memory 183360 kb
Host smart-a7ff08fc-4b9f-43eb-b439-9aa33995cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56038398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.56038398
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.4001154330
Short name T284
Test name
Test status
Simulation time 370247225 ps
CPU time 1.15 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 183280 kb
Host smart-ee37ab5d-9fd5-466c-8b34-cc8fdb549a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001154330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.4001154330
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.225145206
Short name T134
Test name
Test status
Simulation time 97986861879 ps
CPU time 153.45 seconds
Started Feb 04 12:56:03 PM PST 24
Finished Feb 04 12:58:38 PM PST 24
Peak memory 193788 kb
Host smart-729c3c05-63ab-4eea-bc05-3261b8534860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225145206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.225145206
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.241801725
Short name T84
Test name
Test status
Simulation time 488443541 ps
CPU time 0.71 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183312 kb
Host smart-807e039e-a040-4bfe-a1b1-d9da54e141d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241801725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.241801725
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.2371119279
Short name T204
Test name
Test status
Simulation time 13565599628 ps
CPU time 6.67 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 183464 kb
Host smart-8ca461d8-9046-45a1-ac63-f5290ef59e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371119279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.2371119279
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2285410649
Short name T18
Test name
Test status
Simulation time 388664117 ps
CPU time 0.67 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183276 kb
Host smart-1219f429-26e4-4822-b99c-9e267ac81fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285410649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2285410649
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.575281949
Short name T262
Test name
Test status
Simulation time 91094454938 ps
CPU time 149.22 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:58:25 PM PST 24
Peak memory 183496 kb
Host smart-d8318041-338b-4754-97a9-678a11022433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575281949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_a
ll.575281949
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2641667227
Short name T49
Test name
Test status
Simulation time 333829623116 ps
CPU time 227.42 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:59:50 PM PST 24
Peak memory 198372 kb
Host smart-d6be712f-67e6-4858-a03c-dabdf0437d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641667227 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2641667227
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1160179817
Short name T250
Test name
Test status
Simulation time 603066760 ps
CPU time 0.7 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183384 kb
Host smart-7180d2fc-3361-45e3-8091-1190c5f6eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160179817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1160179817
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1115837926
Short name T62
Test name
Test status
Simulation time 35594808542 ps
CPU time 59.42 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:56:53 PM PST 24
Peak memory 183396 kb
Host smart-992937ac-1340-4ffd-b1d6-f52a9038303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115837926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1115837926
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.3552203389
Short name T82
Test name
Test status
Simulation time 348125628 ps
CPU time 0.67 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 183360 kb
Host smart-b39f38dc-3a09-45d3-84d6-edb66ac8e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552203389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.3552203389
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1087654222
Short name T187
Test name
Test status
Simulation time 204759813682 ps
CPU time 76.7 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:57:15 PM PST 24
Peak memory 194756 kb
Host smart-216a0341-1a8e-49fb-a6ae-684bbbb7f4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087654222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1087654222
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.4249148837
Short name T117
Test name
Test status
Simulation time 109845180686 ps
CPU time 843.73 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 01:09:59 PM PST 24
Peak memory 201424 kb
Host smart-d8bea55e-ddc2-47d8-ac03-e92064788ec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249148837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.4249148837
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3158292488
Short name T109
Test name
Test status
Simulation time 598834067 ps
CPU time 0.76 seconds
Started Feb 04 12:55:48 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183392 kb
Host smart-fd2d5add-d7f8-4233-aad5-3574674cdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158292488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3158292488
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1096993136
Short name T220
Test name
Test status
Simulation time 29934596455 ps
CPU time 41.96 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:56:39 PM PST 24
Peak memory 183456 kb
Host smart-d2198524-e6a9-46e7-8eac-0c8ab9601a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096993136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1096993136
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1063131083
Short name T164
Test name
Test status
Simulation time 509555864 ps
CPU time 1.26 seconds
Started Feb 04 12:55:59 PM PST 24
Finished Feb 04 12:56:03 PM PST 24
Peak memory 183292 kb
Host smart-18410a76-676a-4a90-9478-1f07adefdf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063131083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1063131083
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.2946924759
Short name T299
Test name
Test status
Simulation time 79766301574 ps
CPU time 27.47 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:56:21 PM PST 24
Peak memory 194628 kb
Host smart-e1e7dbda-a296-42ac-a225-aca4061602c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946924759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.2946924759
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.117261516
Short name T96
Test name
Test status
Simulation time 114795368945 ps
CPU time 228.98 seconds
Started Feb 04 12:55:54 PM PST 24
Finished Feb 04 12:59:45 PM PST 24
Peak memory 198424 kb
Host smart-39bc636b-a84d-4bfb-bf94-7a395caad9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117261516 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.117261516
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3946902081
Short name T41
Test name
Test status
Simulation time 374360690 ps
CPU time 1.07 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:55:57 PM PST 24
Peak memory 183376 kb
Host smart-2d9b1a5b-2312-431d-af55-a05067b5577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946902081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3946902081
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4263948643
Short name T291
Test name
Test status
Simulation time 37834977990 ps
CPU time 56.61 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:56:52 PM PST 24
Peak memory 183500 kb
Host smart-9c1499f8-fbc0-48d4-a038-ffffa9ea321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263948643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4263948643
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3728553466
Short name T159
Test name
Test status
Simulation time 384069138 ps
CPU time 1.17 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183264 kb
Host smart-d82e9731-929f-437e-b167-489aaaa480e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728553466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3728553466
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.688349509
Short name T46
Test name
Test status
Simulation time 195628909451 ps
CPU time 26.67 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 12:56:22 PM PST 24
Peak memory 183516 kb
Host smart-ea7bb86b-cf7e-427a-87a9-1c7a5ac4376d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688349509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.688349509
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.285296813
Short name T211
Test name
Test status
Simulation time 143575655855 ps
CPU time 161.41 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:58:39 PM PST 24
Peak memory 198400 kb
Host smart-e2c022be-150c-4177-acc5-4a567888a59e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285296813 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.285296813
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1400191397
Short name T169
Test name
Test status
Simulation time 592948710 ps
CPU time 0.57 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 183360 kb
Host smart-d289f8a1-e683-4c68-b2be-d7d600378f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400191397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1400191397
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1549976566
Short name T215
Test name
Test status
Simulation time 31560187101 ps
CPU time 22.57 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:56:19 PM PST 24
Peak memory 183456 kb
Host smart-2e2d7f31-f2b3-4fd6-9240-125d18653780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549976566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1549976566
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1836213233
Short name T263
Test name
Test status
Simulation time 574853587 ps
CPU time 0.91 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:55:59 PM PST 24
Peak memory 183300 kb
Host smart-2fcaaf9a-a943-4937-ab63-dfdd3df60fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836213233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1836213233
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.4197192027
Short name T24
Test name
Test status
Simulation time 32608897604 ps
CPU time 8.56 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 193544 kb
Host smart-eaf2073e-217c-402e-b73c-8cade1a1d9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197192027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.4197192027
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1263378615
Short name T243
Test name
Test status
Simulation time 253511512790 ps
CPU time 682.2 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 01:07:21 PM PST 24
Peak memory 199160 kb
Host smart-857930df-55cd-40d3-8efa-8a044ad08042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263378615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1263378615
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1822203238
Short name T308
Test name
Test status
Simulation time 575168688 ps
CPU time 0.95 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 183424 kb
Host smart-e8ab7ca0-88b4-4765-854a-efa755aa46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822203238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1822203238
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.980293836
Short name T272
Test name
Test status
Simulation time 25795255788 ps
CPU time 9.8 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:10 PM PST 24
Peak memory 183488 kb
Host smart-3a02cd75-fb4c-4fc3-a030-6d3d9677bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980293836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.980293836
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.4240091522
Short name T194
Test name
Test status
Simulation time 377775672 ps
CPU time 0.82 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:56:00 PM PST 24
Peak memory 183244 kb
Host smart-35fd06ae-81f3-4a74-9301-4aae2122fc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240091522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.4240091522
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1492298553
Short name T230
Test name
Test status
Simulation time 204047364358 ps
CPU time 315.54 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 01:01:09 PM PST 24
Peak memory 183540 kb
Host smart-d52ef20e-fb39-4796-b385-b9f0b5ee8224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492298553 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1492298553
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.1830009901
Short name T45
Test name
Test status
Simulation time 30986711623 ps
CPU time 123.4 seconds
Started Feb 04 12:55:58 PM PST 24
Finished Feb 04 12:58:03 PM PST 24
Peak memory 198392 kb
Host smart-1d4c75b2-05b7-4065-94a3-5e644f612338
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830009901 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.1830009901
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3523174005
Short name T232
Test name
Test status
Simulation time 594644141 ps
CPU time 0.88 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183312 kb
Host smart-b0f8fa75-4d91-4259-b81d-f57684483ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523174005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3523174005
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.2644620787
Short name T273
Test name
Test status
Simulation time 23986481232 ps
CPU time 18.69 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:56:12 PM PST 24
Peak memory 183488 kb
Host smart-b9848c1d-a6b1-493e-8700-c5ea0ebc250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644620787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.2644620787
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.127256565
Short name T302
Test name
Test status
Simulation time 468684035 ps
CPU time 0.75 seconds
Started Feb 04 12:55:50 PM PST 24
Finished Feb 04 12:55:54 PM PST 24
Peak memory 183300 kb
Host smart-afad7d91-826f-4557-adce-86082df483ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127256565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.127256565
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.822069542
Short name T104
Test name
Test status
Simulation time 114164845353 ps
CPU time 171.01 seconds
Started Feb 04 12:56:00 PM PST 24
Finished Feb 04 12:58:54 PM PST 24
Peak memory 183444 kb
Host smart-e5594e73-781b-4bbb-ab5e-3da377745d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822069542 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_a
ll.822069542
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.263602419
Short name T305
Test name
Test status
Simulation time 67495166168 ps
CPU time 279.36 seconds
Started Feb 04 12:55:53 PM PST 24
Finished Feb 04 01:00:35 PM PST 24
Peak memory 198424 kb
Host smart-3910415e-66a7-4b28-aac5-e74ab3f25b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263602419 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.263602419
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4049804845
Short name T50
Test name
Test status
Simulation time 481311681 ps
CPU time 0.93 seconds
Started Feb 04 12:55:55 PM PST 24
Finished Feb 04 12:55:59 PM PST 24
Peak memory 183376 kb
Host smart-4b3ae00f-bcb7-4169-bd08-a6f6984fae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049804845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4049804845
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2558633179
Short name T146
Test name
Test status
Simulation time 6248008411 ps
CPU time 3.43 seconds
Started Feb 04 12:55:56 PM PST 24
Finished Feb 04 12:56:02 PM PST 24
Peak memory 183512 kb
Host smart-ac666c64-df52-4a1e-ae69-0b5266e5a7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558633179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2558633179
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.716600707
Short name T163
Test name
Test status
Simulation time 415723766 ps
CPU time 0.92 seconds
Started Feb 04 12:55:52 PM PST 24
Finished Feb 04 12:55:56 PM PST 24
Peak memory 183260 kb
Host smart-beedd2fd-1b24-4990-83e5-f7cec0ed17c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716600707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.716600707
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2861453301
Short name T47
Test name
Test status
Simulation time 61347311252 ps
CPU time 18.33 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 12:56:12 PM PST 24
Peak memory 183432 kb
Host smart-f3e0f436-e0e1-4e0a-8ef9-2f9fb7cd9226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861453301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2861453301
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2849271652
Short name T30
Test name
Test status
Simulation time 95727622820 ps
CPU time 720.45 seconds
Started Feb 04 12:55:49 PM PST 24
Finished Feb 04 01:07:54 PM PST 24
Peak memory 198928 kb
Host smart-c247ad83-7da1-4496-9740-4c7bec2903e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849271652 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2849271652
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.757746535
Short name T195
Test name
Test status
Simulation time 372123483 ps
CPU time 1.09 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 12:55:22 PM PST 24
Peak memory 183420 kb
Host smart-868b6505-94ef-4332-926c-753802398c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757746535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.757746535
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.207797486
Short name T150
Test name
Test status
Simulation time 15598304817 ps
CPU time 25.16 seconds
Started Feb 04 12:55:13 PM PST 24
Finished Feb 04 12:55:39 PM PST 24
Peak memory 183500 kb
Host smart-f4835e9c-c8c5-4026-a4bd-551f917abc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207797486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.207797486
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2703580789
Short name T240
Test name
Test status
Simulation time 588466899 ps
CPU time 0.78 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:20 PM PST 24
Peak memory 183372 kb
Host smart-eb1c1e47-021d-4b55-a325-9db30ae0f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703580789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2703580789
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.425605192
Short name T44
Test name
Test status
Simulation time 5052096881 ps
CPU time 9.07 seconds
Started Feb 04 12:55:20 PM PST 24
Finished Feb 04 12:55:30 PM PST 24
Peak memory 183408 kb
Host smart-93f4ab3e-0c09-4cba-a783-f70d8ab26330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425605192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_al
l.425605192
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3756803862
Short name T296
Test name
Test status
Simulation time 539468043648 ps
CPU time 335.3 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 01:00:54 PM PST 24
Peak memory 198416 kb
Host smart-ed2a9e4b-3123-4ab7-bf5d-e34689595e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756803862 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3756803862
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.916107728
Short name T238
Test name
Test status
Simulation time 444156111 ps
CPU time 1.35 seconds
Started Feb 04 12:55:18 PM PST 24
Finished Feb 04 12:55:20 PM PST 24
Peak memory 183388 kb
Host smart-5d99695c-867d-49e4-877d-d1f4a3e3dec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916107728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.916107728
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2884854081
Short name T57
Test name
Test status
Simulation time 8923702276 ps
CPU time 14.6 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:41 PM PST 24
Peak memory 183440 kb
Host smart-b0222fa2-4658-4fec-92cc-93c82231f2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884854081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2884854081
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.1330834201
Short name T142
Test name
Test status
Simulation time 486638452 ps
CPU time 1.26 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:55:25 PM PST 24
Peak memory 183348 kb
Host smart-7151e07f-389d-44c0-84b5-0a0cfbe0f65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330834201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.1330834201
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3640003328
Short name T218
Test name
Test status
Simulation time 117304199440 ps
CPU time 95.79 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:56:59 PM PST 24
Peak memory 183452 kb
Host smart-ebd26e5b-882c-4659-aedc-b2ca896bdfef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640003328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3640003328
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.771341492
Short name T127
Test name
Test status
Simulation time 197694041362 ps
CPU time 533.21 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 01:04:20 PM PST 24
Peak memory 199124 kb
Host smart-3e345e5b-198a-4695-9db5-51b5140c88e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771341492 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.771341492
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3437749258
Short name T249
Test name
Test status
Simulation time 505398418 ps
CPU time 1.34 seconds
Started Feb 04 12:55:25 PM PST 24
Finished Feb 04 12:55:28 PM PST 24
Peak memory 183340 kb
Host smart-7f67b3e5-d921-48aa-b2f2-e2e23b58208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437749258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3437749258
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.731699362
Short name T229
Test name
Test status
Simulation time 34389414773 ps
CPU time 6.49 seconds
Started Feb 04 12:55:23 PM PST 24
Finished Feb 04 12:55:31 PM PST 24
Peak memory 183428 kb
Host smart-99db7752-35e5-495e-a846-a4e775f764e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731699362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.731699362
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3140468752
Short name T196
Test name
Test status
Simulation time 594080516 ps
CPU time 1.02 seconds
Started Feb 04 12:55:23 PM PST 24
Finished Feb 04 12:55:25 PM PST 24
Peak memory 183264 kb
Host smart-54a7ad7b-1bd5-405e-aab2-a66346df7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140468752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3140468752
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2863698462
Short name T31
Test name
Test status
Simulation time 176727303248 ps
CPU time 243.67 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:59:26 PM PST 24
Peak memory 183468 kb
Host smart-b46e559a-a067-433a-b4f0-a6b5d9093777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863698462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2863698462
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_jump.3779013259
Short name T60
Test name
Test status
Simulation time 345773463 ps
CPU time 0.94 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:55:24 PM PST 24
Peak memory 183332 kb
Host smart-755e191f-598b-46ff-8022-cb47e916db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779013259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.3779013259
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1991055598
Short name T32
Test name
Test status
Simulation time 19395137760 ps
CPU time 9.38 seconds
Started Feb 04 12:55:24 PM PST 24
Finished Feb 04 12:55:35 PM PST 24
Peak memory 183216 kb
Host smart-967eb881-b9ac-4609-87cf-90150d3dc64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991055598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1991055598
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4037298779
Short name T269
Test name
Test status
Simulation time 550109757 ps
CPU time 0.91 seconds
Started Feb 04 12:55:14 PM PST 24
Finished Feb 04 12:55:16 PM PST 24
Peak memory 183368 kb
Host smart-5583e71c-ed57-47cd-b791-188f2404da25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037298779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4037298779
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1825390783
Short name T235
Test name
Test status
Simulation time 169376136055 ps
CPU time 279.05 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 01:00:02 PM PST 24
Peak memory 194560 kb
Host smart-ea58ef15-ccdf-48c9-836a-4a4a5ad75e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825390783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1825390783
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2801311032
Short name T237
Test name
Test status
Simulation time 401204071755 ps
CPU time 749.08 seconds
Started Feb 04 12:55:19 PM PST 24
Finished Feb 04 01:07:50 PM PST 24
Peak memory 200792 kb
Host smart-7c76d187-0c00-494d-92e7-a40c1577bca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801311032 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2801311032
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4102657891
Short name T135
Test name
Test status
Simulation time 546678443 ps
CPU time 0.73 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:55:24 PM PST 24
Peak memory 183412 kb
Host smart-a4340e2e-9ec8-4ef3-b3f3-156ed11aedcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102657891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4102657891
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.4036626368
Short name T22
Test name
Test status
Simulation time 29019367890 ps
CPU time 43.94 seconds
Started Feb 04 12:55:21 PM PST 24
Finished Feb 04 12:56:06 PM PST 24
Peak memory 183432 kb
Host smart-4f2834ca-634a-41d4-a98c-c6d16df6380f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036626368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.4036626368
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3146120763
Short name T180
Test name
Test status
Simulation time 379800947 ps
CPU time 1.15 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:55:24 PM PST 24
Peak memory 183076 kb
Host smart-f4018e6d-687b-436a-ac9f-2805acee8e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146120763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3146120763
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1086507381
Short name T189
Test name
Test status
Simulation time 485329709441 ps
CPU time 737.35 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 01:07:41 PM PST 24
Peak memory 193616 kb
Host smart-5491e8e3-cdcb-49e7-8e5f-1be6d6d07002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086507381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1086507381
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.856025632
Short name T129
Test name
Test status
Simulation time 38590688792 ps
CPU time 272.94 seconds
Started Feb 04 12:55:22 PM PST 24
Finished Feb 04 12:59:56 PM PST 24
Peak memory 198224 kb
Host smart-1edc341c-d886-49a0-b8a6-37bc08c372e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856025632 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.856025632
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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