Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 25548 1 T18 11 T20 11 T21 10
bark[1] 297 1 T19 12 T57 12 T43 13
bark[2] 484 1 T22 53 T87 16 T88 60
bark[3] 546 1 T45 30 T89 22 T90 27
bark[4] 554 1 T23 16 T90 16 T77 16
bark[5] 211 1 T25 4 T32 16 T33 16
bark[6] 778 1 T90 16 T91 207 T92 31
bark[7] 214 1 T52 21 T93 19 T94 17
bark[8] 521 1 T51 17 T95 148 T96 21
bark[9] 412 1 T97 32 T98 16 T87 22
bark[10] 185 1 T99 12 T34 16 T49 21
bark[11] 302 1 T41 12 T100 1 T93 16
bark[12] 558 1 T78 66 T92 47 T101 31
bark[13] 158 1 T102 102 T103 13 T104 26
bark[14] 383 1 T23 6 T33 21 T105 17
bark[15] 215 1 T34 12 T89 46 T93 16
bark[16] 626 1 T97 17 T98 16 T106 16
bark[17] 855 1 T25 38 T50 469 T49 23
bark[18] 633 1 T47 12 T88 16 T80 16
bark[19] 430 1 T51 87 T98 16 T107 13
bark[20] 429 1 T50 17 T45 88 T108 12
bark[21] 292 1 T32 22 T34 47 T93 39
bark[22] 521 1 T22 219 T52 7 T79 16
bark[23] 300 1 T22 17 T51 28 T91 21
bark[24] 473 1 T50 17 T91 67 T102 16
bark[25] 345 1 T31 12 T34 16 T42 12
bark[26] 1037 1 T23 22 T49 16 T100 21
bark[27] 303 1 T25 26 T50 16 T90 68
bark[28] 401 1 T25 17 T48 12 T49 21
bark[29] 611 1 T50 205 T52 67 T93 161
bark[30] 527 1 T51 31 T52 41 T107 16
bark[31] 361 1 T33 12 T76 66 T109 16
bark_0 3475 1 T8 6 T13 6 T14 6


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 25412 1 T18 10 T20 10 T21 9
bite[1] 346 1 T19 11 T22 17 T25 16
bite[2] 627 1 T97 28 T81 37 T110 36
bite[3] 438 1 T89 46 T90 67 T107 12
bite[4] 232 1 T91 21 T96 16 T87 21
bite[5] 486 1 T32 22 T34 16 T47 11
bite[6] 230 1 T32 16 T111 11 T107 36
bite[7] 268 1 T77 17 T106 12 T112 12
bite[8] 216 1 T42 11 T105 16 T77 16
bite[9] 627 1 T32 22 T113 12 T100 20
bite[10] 556 1 T22 218 T52 20 T34 11
bite[11] 682 1 T23 5 T25 26 T33 11
bite[12] 232 1 T25 17 T107 82 T92 31
bite[13] 517 1 T31 11 T45 26 T97 17
bite[14] 394 1 T57 11 T114 26 T115 22
bite[15] 529 1 T49 20 T98 16 T93 35
bite[16] 263 1 T50 17 T89 32 T98 16
bite[17] 474 1 T51 86 T34 16 T49 39
bite[18] 646 1 T50 204 T95 147 T94 17
bite[19] 690 1 T50 468 T107 16 T116 11
bite[20] 177 1 T110 12 T117 16 T118 16
bite[21] 410 1 T51 48 T33 16 T45 30
bite[22] 604 1 T91 66 T119 63 T104 167
bite[23] 268 1 T50 16 T52 6 T45 88
bite[24] 563 1 T89 16 T93 16 T94 16
bite[25] 543 1 T51 27 T90 16 T94 17
bite[26] 320 1 T22 52 T23 38 T50 17
bite[27] 415 1 T76 65 T89 16 T114 22
bite[28] 529 1 T52 40 T78 17 T93 160
bite[29] 194 1 T25 3 T34 31 T43 12
bite[30] 667 1 T25 22 T52 95 T41 11
bite[31] 469 1 T95 314 T106 22 T79 16
bite_0 3961 1 T8 6 T13 6 T14 6


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 42985 1 T8 6 T13 6 T14 6


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 621 1 T25 15 T51 149 T52 31
prescale[1] 681 1 T22 21 T52 31 T49 39
prescale[2] 1061 1 T25 30 T51 422 T105 15
prescale[3] 685 1 T24 8 T51 14 T32 15
prescale[4] 1112 1 T25 52 T51 9 T49 2
prescale[5] 1069 1 T18 8 T23 2 T32 18
prescale[6] 756 1 T50 45 T49 18 T77 131
prescale[7] 1093 1 T23 31 T25 2 T50 29
prescale[8] 631 1 T49 2 T97 15 T109 131
prescale[9] 1117 1 T50 8 T52 17 T120 8
prescale[10] 540 1 T22 81 T95 16 T90 39
prescale[11] 970 1 T22 2 T32 18 T34 18
prescale[12] 610 1 T20 8 T49 16 T89 15
prescale[13] 878 1 T22 103 T50 21 T51 15
prescale[14] 387 1 T25 2 T49 59 T78 15
prescale[15] 644 1 T22 2 T23 83 T50 31
prescale[16] 682 1 T22 18 T50 2 T52 59
prescale[17] 561 1 T52 17 T49 57 T95 15
prescale[18] 456 1 T32 31 T33 18 T76 22
prescale[19] 540 1 T50 15 T33 15 T34 15
prescale[20] 363 1 T51 15 T52 61 T49 15
prescale[21] 664 1 T23 2 T50 113 T51 45
prescale[22] 666 1 T52 15 T89 40 T77 44
prescale[23] 547 1 T45 8 T49 70 T105 31
prescale[24] 366 1 T23 50 T49 15 T121 8
prescale[25] 425 1 T50 25 T52 15 T45 15
prescale[26] 766 1 T50 66 T52 31 T97 15
prescale[27] 850 1 T23 43 T50 246 T49 1
prescale[28] 398 1 T52 2 T33 35 T49 60
prescale[29] 700 1 T52 35 T122 8 T34 45
prescale[30] 553 1 T50 74 T32 58 T45 34
prescale[31] 566 1 T23 44 T25 2 T50 15
prescale_0 21027 1 T8 6 T13 6 T14 6


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31709 1 T8 6 T13 6 T14 6
auto[1] 11276 1 T18 9 T31 10 T22 72


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 42985 1 T8 6 T13 6 T14 6


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 25433 1 T18 12 T20 12 T21 11
wkup[1] 467 1 T22 16 T25 5 T50 16
wkup[2] 451 1 T50 16 T52 32 T49 16
wkup[3] 319 1 T52 36 T91 26 T93 16
wkup[4] 548 1 T98 16 T107 16 T96 37
wkup[5] 489 1 T50 13 T51 16 T33 21
wkup[6] 502 1 T50 16 T51 16 T52 16
wkup[7] 461 1 T22 17 T52 16 T99 13
wkup[8] 458 1 T22 16 T50 16 T51 64
wkup[9] 450 1 T22 16 T51 16 T32 16
wkup[10] 468 1 T22 23 T23 16 T34 16
wkup[11] 527 1 T50 26 T51 61 T52 16
wkup[12] 320 1 T50 32 T51 16 T90 22
wkup[13] 499 1 T22 26 T23 7 T51 16
wkup[14] 469 1 T22 19 T34 16 T49 16
wkup[15] 490 1 T22 16 T50 16 T32 22
wkup[16] 508 1 T50 16 T97 14 T105 16
wkup[17] 535 1 T23 16 T50 16 T52 16
wkup[18] 603 1 T19 13 T50 33 T51 32
wkup[19] 595 1 T23 16 T50 22 T52 24
wkup[20] 530 1 T50 16 T52 16 T41 13
wkup[21] 494 1 T45 16 T90 41 T77 16
wkup[22] 470 1 T57 13 T51 32 T76 7
wkup[23] 366 1 T51 26 T48 13 T113 14
wkup[24] 262 1 T50 16 T51 16 T32 16
wkup[25] 452 1 T23 16 T25 26 T50 16
wkup[26] 380 1 T31 13 T98 16 T77 16
wkup[27] 390 1 T23 22 T25 16 T52 16
wkup[28] 384 1 T25 22 T51 16 T43 14
wkup[29] 569 1 T50 37 T51 16 T52 16
wkup[30] 553 1 T23 28 T50 16 T51 32
wkup[31] 593 1 T23 16 T25 17 T32 22
wkup_0 2950 1 T8 6 T13 6 T14 6

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