Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.31 100.00 99.35 100.00 96.90


Total test records in report: 429
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T271 /workspace/coverage/default/42.aon_timer_jump.520387661 Feb 07 12:37:53 PM PST 24 Feb 07 12:37:57 PM PST 24 579837895 ps
T272 /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3128593105 Feb 07 12:37:59 PM PST 24 Feb 07 12:41:53 PM PST 24 29732117808 ps
T273 /workspace/coverage/default/27.aon_timer_smoke.3233452604 Feb 07 12:37:35 PM PST 24 Feb 07 12:37:37 PM PST 24 473575322 ps
T274 /workspace/coverage/default/17.aon_timer_stress_all.804478478 Feb 07 12:37:11 PM PST 24 Feb 07 12:37:26 PM PST 24 58963157116 ps
T275 /workspace/coverage/default/45.aon_timer_prescaler.683488045 Feb 07 12:37:57 PM PST 24 Feb 07 12:38:03 PM PST 24 9474345256 ps
T276 /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.156872694 Feb 07 12:37:29 PM PST 24 Feb 07 12:41:07 PM PST 24 90041955393 ps
T277 /workspace/coverage/default/49.aon_timer_prescaler.942255539 Feb 07 12:38:10 PM PST 24 Feb 07 12:38:20 PM PST 24 11143100366 ps
T278 /workspace/coverage/default/20.aon_timer_jump.2780442038 Feb 07 12:37:11 PM PST 24 Feb 07 12:37:13 PM PST 24 408972964 ps
T279 /workspace/coverage/default/41.aon_timer_stress_all.2250496751 Feb 07 12:37:56 PM PST 24 Feb 07 12:40:24 PM PST 24 105471343721 ps
T280 /workspace/coverage/default/14.aon_timer_prescaler.2306095998 Feb 07 12:37:06 PM PST 24 Feb 07 12:38:35 PM PST 24 61477701801 ps
T281 /workspace/coverage/default/7.aon_timer_smoke.2088490076 Feb 07 12:37:20 PM PST 24 Feb 07 12:37:22 PM PST 24 488046970 ps
T282 /workspace/coverage/default/28.aon_timer_smoke.833473092 Feb 07 12:37:35 PM PST 24 Feb 07 12:37:37 PM PST 24 489721178 ps
T283 /workspace/coverage/default/5.aon_timer_prescaler.944128178 Feb 07 12:36:58 PM PST 24 Feb 07 12:37:24 PM PST 24 13596887805 ps
T284 /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.778331688 Feb 07 12:37:43 PM PST 24 Feb 07 12:41:32 PM PST 24 85046230949 ps
T285 /workspace/coverage/default/12.aon_timer_smoke.2038186364 Feb 07 12:37:02 PM PST 24 Feb 07 12:37:04 PM PST 24 484838690 ps
T286 /workspace/coverage/default/20.aon_timer_smoke.1320487847 Feb 07 12:37:09 PM PST 24 Feb 07 12:37:10 PM PST 24 422517292 ps
T287 /workspace/coverage/default/14.aon_timer_jump.1453614844 Feb 07 12:37:13 PM PST 24 Feb 07 12:37:15 PM PST 24 382806194 ps
T288 /workspace/coverage/default/32.aon_timer_jump.574145120 Feb 07 12:37:42 PM PST 24 Feb 07 12:37:43 PM PST 24 393710681 ps
T60 /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.500395674 Feb 07 12:37:36 PM PST 24 Feb 07 12:47:23 PM PST 24 137663951541 ps
T289 /workspace/coverage/default/10.aon_timer_stress_all.1720465895 Feb 07 12:37:10 PM PST 24 Feb 07 12:37:58 PM PST 24 134860150320 ps
T290 /workspace/coverage/default/4.aon_timer_jump.1341169951 Feb 07 12:36:58 PM PST 24 Feb 07 12:37:00 PM PST 24 448332148 ps
T291 /workspace/coverage/default/9.aon_timer_prescaler.3012855690 Feb 07 12:36:56 PM PST 24 Feb 07 12:37:00 PM PST 24 23179128089 ps
T292 /workspace/coverage/default/0.aon_timer_stress_all.1660964635 Feb 07 12:36:54 PM PST 24 Feb 07 12:38:08 PM PST 24 49262850508 ps
T293 /workspace/coverage/default/16.aon_timer_jump.1861511854 Feb 07 12:37:09 PM PST 24 Feb 07 12:37:11 PM PST 24 358944285 ps
T294 /workspace/coverage/default/46.aon_timer_stress_all.2974944081 Feb 07 12:38:07 PM PST 24 Feb 07 12:39:34 PM PST 24 109111207821 ps
T295 /workspace/coverage/default/48.aon_timer_stress_all.2814418792 Feb 07 12:38:07 PM PST 24 Feb 07 12:54:39 PM PST 24 622858562801 ps
T296 /workspace/coverage/default/41.aon_timer_jump.2592135366 Feb 07 12:37:59 PM PST 24 Feb 07 12:38:01 PM PST 24 529885102 ps
T297 /workspace/coverage/default/47.aon_timer_smoke.59133677 Feb 07 12:38:13 PM PST 24 Feb 07 12:38:15 PM PST 24 362159124 ps
T298 /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3939154022 Feb 07 12:37:13 PM PST 24 Feb 07 12:43:34 PM PST 24 38872098433 ps
T299 /workspace/coverage/default/37.aon_timer_prescaler.952730448 Feb 07 12:38:00 PM PST 24 Feb 07 12:38:07 PM PST 24 16825079124 ps
T300 /workspace/coverage/default/14.aon_timer_stress_all.2815443420 Feb 07 12:37:10 PM PST 24 Feb 07 12:39:10 PM PST 24 540598483127 ps
T301 /workspace/coverage/default/34.aon_timer_prescaler.3711237153 Feb 07 12:37:40 PM PST 24 Feb 07 12:37:52 PM PST 24 7057418518 ps
T302 /workspace/coverage/default/27.aon_timer_stress_all.1394022678 Feb 07 12:37:17 PM PST 24 Feb 07 12:38:27 PM PST 24 169050580581 ps
T303 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2524622721 Feb 07 12:50:48 PM PST 24 Feb 07 12:50:49 PM PST 24 315974639 ps
T304 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1288528080 Feb 07 12:51:16 PM PST 24 Feb 07 12:51:18 PM PST 24 447467839 ps
T305 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3850984561 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:16 PM PST 24 503415604 ps
T69 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3861818023 Feb 07 12:51:03 PM PST 24 Feb 07 12:51:06 PM PST 24 1820962478 ps
T83 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2731228849 Feb 07 12:50:58 PM PST 24 Feb 07 12:51:00 PM PST 24 415963644 ps
T85 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.112525314 Feb 07 12:50:50 PM PST 24 Feb 07 12:50:53 PM PST 24 8299943945 ps
T306 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2460488499 Feb 07 12:50:48 PM PST 24 Feb 07 12:50:50 PM PST 24 465368574 ps
T307 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2211071342 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:43 PM PST 24 785856719 ps
T308 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1582187899 Feb 07 12:51:02 PM PST 24 Feb 07 12:51:06 PM PST 24 431505492 ps
T309 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2571684453 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:14 PM PST 24 351165665 ps
T82 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.886306172 Feb 07 12:51:03 PM PST 24 Feb 07 12:51:05 PM PST 24 505599270 ps
T70 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2510728959 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:15 PM PST 24 939407305 ps
T310 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3389534382 Feb 07 12:51:08 PM PST 24 Feb 07 12:51:10 PM PST 24 508033018 ps
T311 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2601603850 Feb 07 12:51:10 PM PST 24 Feb 07 12:51:11 PM PST 24 437195560 ps
T312 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2710267079 Feb 07 12:51:02 PM PST 24 Feb 07 12:51:04 PM PST 24 471835956 ps
T313 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2925333943 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:09 PM PST 24 4587716835 ps
T314 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.774694934 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:43 PM PST 24 524941039 ps
T315 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.930672352 Feb 07 12:50:58 PM PST 24 Feb 07 12:51:07 PM PST 24 4373650519 ps
T71 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3925608887 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:09 PM PST 24 996003036 ps
T316 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2026933963 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:13 PM PST 24 492234116 ps
T72 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3534223751 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:05 PM PST 24 1802072393 ps
T317 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.563263931 Feb 07 12:50:44 PM PST 24 Feb 07 12:50:46 PM PST 24 454126840 ps
T86 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2142218596 Feb 07 12:51:13 PM PST 24 Feb 07 12:51:17 PM PST 24 4401181070 ps
T318 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1817317949 Feb 07 12:51:05 PM PST 24 Feb 07 12:51:11 PM PST 24 8173929834 ps
T73 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2986800545 Feb 07 12:50:39 PM PST 24 Feb 07 12:50:41 PM PST 24 1915165214 ps
T319 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.837845043 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:15 PM PST 24 395274198 ps
T320 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1107170918 Feb 07 12:51:05 PM PST 24 Feb 07 12:51:08 PM PST 24 593399718 ps
T74 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2714065187 Feb 07 12:50:54 PM PST 24 Feb 07 12:50:55 PM PST 24 466842626 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.283942286 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:44 PM PST 24 679291890 ps
T75 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3390095925 Feb 07 12:50:43 PM PST 24 Feb 07 12:50:51 PM PST 24 2613272333 ps
T322 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3320787986 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:08 PM PST 24 298460994 ps
T323 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1718168987 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:08 PM PST 24 2173859675 ps
T61 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.336014828 Feb 07 12:51:04 PM PST 24 Feb 07 12:51:06 PM PST 24 541500829 ps
T324 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2398784631 Feb 07 12:50:37 PM PST 24 Feb 07 12:50:51 PM PST 24 8467733263 ps
T325 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1231727004 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:07 PM PST 24 413550705 ps
T326 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4262174105 Feb 07 12:51:15 PM PST 24 Feb 07 12:51:17 PM PST 24 490085387 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.905976707 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:08 PM PST 24 536782706 ps
T328 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4023685194 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:45 PM PST 24 678281997 ps
T329 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1026344141 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:18 PM PST 24 1742367557 ps
T330 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1903326238 Feb 07 12:51:07 PM PST 24 Feb 07 12:51:09 PM PST 24 391956427 ps
T331 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.549405335 Feb 07 12:50:44 PM PST 24 Feb 07 12:50:59 PM PST 24 8671684277 ps
T62 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3565221195 Feb 07 12:50:51 PM PST 24 Feb 07 12:50:53 PM PST 24 905848908 ps
T332 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1050531467 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:07 PM PST 24 563145264 ps
T63 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3612691967 Feb 07 12:50:48 PM PST 24 Feb 07 12:50:53 PM PST 24 2292899855 ps
T333 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3448663240 Feb 07 12:50:43 PM PST 24 Feb 07 12:50:57 PM PST 24 8135590208 ps
T334 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2724758804 Feb 07 12:50:56 PM PST 24 Feb 07 12:50:58 PM PST 24 328315876 ps
T335 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2276602695 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:43 PM PST 24 401721657 ps
T336 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.736294465 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:16 PM PST 24 461012463 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.952215591 Feb 07 12:50:46 PM PST 24 Feb 07 12:50:47 PM PST 24 338861192 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.984899497 Feb 07 12:50:46 PM PST 24 Feb 07 12:50:48 PM PST 24 520500913 ps
T339 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1882537518 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:15 PM PST 24 1125950013 ps
T340 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4151678331 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:16 PM PST 24 479882637 ps
T341 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3350812459 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:14 PM PST 24 484725180 ps
T342 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.538087637 Feb 07 12:50:58 PM PST 24 Feb 07 12:51:00 PM PST 24 573303015 ps
T343 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2544658684 Feb 07 12:51:16 PM PST 24 Feb 07 12:51:18 PM PST 24 322095164 ps
T344 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.719833081 Feb 07 12:51:03 PM PST 24 Feb 07 12:51:05 PM PST 24 472404094 ps
T345 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2998755027 Feb 07 12:51:05 PM PST 24 Feb 07 12:51:07 PM PST 24 506026640 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.55082703 Feb 07 12:50:48 PM PST 24 Feb 07 12:50:49 PM PST 24 468981105 ps
T347 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2469176114 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:01 PM PST 24 401327778 ps
T348 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3857834417 Feb 07 12:51:05 PM PST 24 Feb 07 12:51:06 PM PST 24 334233077 ps
T349 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3806228581 Feb 07 12:51:07 PM PST 24 Feb 07 12:51:09 PM PST 24 439285399 ps
T350 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.668104914 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:27 PM PST 24 8533430416 ps
T351 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.375913831 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:13 PM PST 24 653619912 ps
T352 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2077488710 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:02 PM PST 24 487082871 ps
T353 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1796617798 Feb 07 12:50:54 PM PST 24 Feb 07 12:50:56 PM PST 24 913363937 ps
T64 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2968877518 Feb 07 12:50:38 PM PST 24 Feb 07 12:50:40 PM PST 24 432155988 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2128084959 Feb 07 12:50:39 PM PST 24 Feb 07 12:50:42 PM PST 24 380297768 ps
T355 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3451611943 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:15 PM PST 24 373980794 ps
T356 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.425890991 Feb 07 12:50:55 PM PST 24 Feb 07 12:50:58 PM PST 24 559700489 ps
T357 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1414660549 Feb 07 12:50:47 PM PST 24 Feb 07 12:50:49 PM PST 24 284124598 ps
T358 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.757645376 Feb 07 12:50:56 PM PST 24 Feb 07 12:51:04 PM PST 24 3997619305 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1465399787 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:16 PM PST 24 446612301 ps
T360 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.18035826 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:13 PM PST 24 534662309 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3847490429 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:03 PM PST 24 471143357 ps
T362 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2467885946 Feb 07 12:51:02 PM PST 24 Feb 07 12:51:06 PM PST 24 4358413519 ps
T363 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3600772329 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:02 PM PST 24 306041492 ps
T364 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3081084277 Feb 07 12:51:13 PM PST 24 Feb 07 12:51:15 PM PST 24 279641998 ps
T365 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.114485333 Feb 07 12:51:07 PM PST 24 Feb 07 12:51:10 PM PST 24 1065682355 ps
T366 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4270529088 Feb 07 12:50:56 PM PST 24 Feb 07 12:50:59 PM PST 24 447685984 ps
T367 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3196830371 Feb 07 12:50:57 PM PST 24 Feb 07 12:50:58 PM PST 24 350310775 ps
T368 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.779318108 Feb 07 12:50:54 PM PST 24 Feb 07 12:50:56 PM PST 24 527894455 ps
T369 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1563313789 Feb 07 12:50:48 PM PST 24 Feb 07 12:50:50 PM PST 24 398530098 ps
T370 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2455003488 Feb 07 12:50:49 PM PST 24 Feb 07 12:50:55 PM PST 24 6188338373 ps
T65 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1838594946 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:43 PM PST 24 409543884 ps
T371 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3228310899 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:43 PM PST 24 418040589 ps
T372 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.875242996 Feb 07 12:50:55 PM PST 24 Feb 07 12:50:57 PM PST 24 438505869 ps
T373 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.369767444 Feb 07 12:51:15 PM PST 24 Feb 07 12:51:17 PM PST 24 434100154 ps
T66 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2663949879 Feb 07 12:51:13 PM PST 24 Feb 07 12:51:14 PM PST 24 389665614 ps
T374 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3827134573 Feb 07 12:51:14 PM PST 24 Feb 07 12:51:16 PM PST 24 508215541 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4003377395 Feb 07 12:50:39 PM PST 24 Feb 07 12:50:43 PM PST 24 6600599031 ps
T376 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2130684330 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:46 PM PST 24 4317661315 ps
T377 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3984654863 Feb 07 12:50:49 PM PST 24 Feb 07 12:50:52 PM PST 24 449941110 ps
T378 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1830938998 Feb 07 12:51:15 PM PST 24 Feb 07 12:51:17 PM PST 24 363061742 ps
T379 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3152335687 Feb 07 12:51:04 PM PST 24 Feb 07 12:51:06 PM PST 24 553275385 ps
T380 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1834089780 Feb 07 12:51:21 PM PST 24 Feb 07 12:51:24 PM PST 24 434474121 ps
T381 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2661415599 Feb 07 12:50:54 PM PST 24 Feb 07 12:50:56 PM PST 24 398955206 ps
T382 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2846025489 Feb 07 12:50:50 PM PST 24 Feb 07 12:50:52 PM PST 24 473443009 ps
T383 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1685642196 Feb 07 12:50:56 PM PST 24 Feb 07 12:50:59 PM PST 24 1500307572 ps
T384 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2657435018 Feb 07 12:50:38 PM PST 24 Feb 07 12:50:43 PM PST 24 8134644397 ps
T385 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3680800944 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:08 PM PST 24 1090746886 ps
T386 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3675356728 Feb 07 12:51:04 PM PST 24 Feb 07 12:51:06 PM PST 24 857674355 ps
T387 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3327864230 Feb 07 12:51:09 PM PST 24 Feb 07 12:51:12 PM PST 24 534236015 ps
T388 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1705604082 Feb 07 12:51:17 PM PST 24 Feb 07 12:51:18 PM PST 24 368482273 ps
T389 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1487670498 Feb 07 12:50:52 PM PST 24 Feb 07 12:50:53 PM PST 24 320167954 ps
T390 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1038267982 Feb 07 12:50:56 PM PST 24 Feb 07 12:50:59 PM PST 24 2102990309 ps
T67 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.323088732 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:44 PM PST 24 517163231 ps
T391 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.698833626 Feb 07 12:51:10 PM PST 24 Feb 07 12:51:14 PM PST 24 693443619 ps
T392 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3426977889 Feb 07 12:51:15 PM PST 24 Feb 07 12:51:20 PM PST 24 7957558792 ps
T393 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.706997664 Feb 07 12:50:50 PM PST 24 Feb 07 12:50:52 PM PST 24 348548590 ps
T394 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3366347495 Feb 07 12:51:03 PM PST 24 Feb 07 12:51:04 PM PST 24 425471889 ps
T395 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.594002085 Feb 07 12:50:56 PM PST 24 Feb 07 12:50:58 PM PST 24 562909944 ps
T396 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3544214112 Feb 07 12:50:42 PM PST 24 Feb 07 12:50:45 PM PST 24 291044216 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3437708248 Feb 07 12:50:43 PM PST 24 Feb 07 12:50:46 PM PST 24 828923779 ps
T398 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3410781901 Feb 07 12:50:42 PM PST 24 Feb 07 12:50:45 PM PST 24 1176292123 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.100884618 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:02 PM PST 24 475059420 ps
T400 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2629007536 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:52 PM PST 24 6059249511 ps
T401 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1603109175 Feb 07 12:51:04 PM PST 24 Feb 07 12:51:06 PM PST 24 1995145910 ps
T402 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2299961506 Feb 07 12:51:00 PM PST 24 Feb 07 12:51:08 PM PST 24 4456060577 ps
T403 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.743955671 Feb 07 12:50:49 PM PST 24 Feb 07 12:50:51 PM PST 24 485486208 ps
T404 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2126224202 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:12 PM PST 24 339757902 ps
T405 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1819136230 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:43 PM PST 24 435451037 ps
T406 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.234597689 Feb 07 12:50:49 PM PST 24 Feb 07 12:50:52 PM PST 24 2073682340 ps
T407 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3195825063 Feb 07 12:50:47 PM PST 24 Feb 07 12:50:50 PM PST 24 508732825 ps
T68 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2205850271 Feb 07 12:50:55 PM PST 24 Feb 07 12:50:57 PM PST 24 397925950 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.796489563 Feb 07 12:50:58 PM PST 24 Feb 07 12:51:00 PM PST 24 503215944 ps
T409 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.436451747 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:44 PM PST 24 1841787459 ps
T410 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1184735967 Feb 07 12:51:09 PM PST 24 Feb 07 12:51:11 PM PST 24 306809532 ps
T411 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1670335281 Feb 07 12:51:08 PM PST 24 Feb 07 12:51:10 PM PST 24 463665256 ps
T412 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4187114657 Feb 07 12:51:16 PM PST 24 Feb 07 12:51:18 PM PST 24 383579673 ps
T413 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1939712615 Feb 07 12:51:12 PM PST 24 Feb 07 12:51:14 PM PST 24 383916299 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2781133843 Feb 07 12:50:40 PM PST 24 Feb 07 12:50:44 PM PST 24 504311774 ps
T415 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4087996345 Feb 07 12:50:54 PM PST 24 Feb 07 12:50:55 PM PST 24 521835727 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3566157266 Feb 07 12:50:55 PM PST 24 Feb 07 12:50:57 PM PST 24 338936373 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1604914386 Feb 07 12:50:41 PM PST 24 Feb 07 12:50:44 PM PST 24 420480232 ps
T418 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3640073148 Feb 07 12:51:01 PM PST 24 Feb 07 12:51:03 PM PST 24 290377578 ps
T419 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4134195448 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:13 PM PST 24 374163389 ps
T420 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3104439736 Feb 07 12:51:01 PM PST 24 Feb 07 12:51:07 PM PST 24 4572975430 ps
T421 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.986195182 Feb 07 12:51:17 PM PST 24 Feb 07 12:51:18 PM PST 24 475141323 ps
T422 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1637810486 Feb 07 12:51:01 PM PST 24 Feb 07 12:51:03 PM PST 24 1027386130 ps
T423 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3496430693 Feb 07 12:50:42 PM PST 24 Feb 07 12:50:44 PM PST 24 438194594 ps
T424 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2049814188 Feb 07 12:51:23 PM PST 24 Feb 07 12:51:25 PM PST 24 481473738 ps
T425 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.643143318 Feb 07 12:51:11 PM PST 24 Feb 07 12:51:12 PM PST 24 515339716 ps
T426 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.280578913 Feb 07 12:51:15 PM PST 24 Feb 07 12:51:16 PM PST 24 309272151 ps
T427 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2772179288 Feb 07 12:51:06 PM PST 24 Feb 07 12:51:08 PM PST 24 447881449 ps
T428 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4261289006 Feb 07 12:51:03 PM PST 24 Feb 07 12:51:05 PM PST 24 406609130 ps
T429 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2529472838 Feb 07 12:50:53 PM PST 24 Feb 07 12:50:54 PM PST 24 1269517519 ps

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.603708205
Short name T1
Test name
Test status
Simulation time 8597858966 ps
CPU time 6.91 seconds
Started Feb 07 12:51:18 PM PST 24
Finished Feb 07 12:51:25 PM PST 24
Peak memory 197016 kb
Host smart-6cfb2887-38d6-4245-9cdc-57c060d0c6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603708205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.603708205
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.4122923086
Short name T22
Test name
Test status
Simulation time 75005813768 ps
CPU time 154.8 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:39:53 PM PST 24
Peak memory 198200 kb
Host smart-5b118768-f108-413c-b5cd-9e4f03c7e2eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122923086 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.4122923086
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.592284419
Short name T49
Test name
Test status
Simulation time 230763143591 ps
CPU time 251.48 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:41:17 PM PST 24
Peak memory 198240 kb
Host smart-a8d75f8f-6ed1-493e-a541-2364c39d8f4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592284419 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.592284419
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.76898198
Short name T2
Test name
Test status
Simulation time 448556309 ps
CPU time 0.84 seconds
Started Feb 07 12:50:39 PM PST 24
Finished Feb 07 12:50:42 PM PST 24
Peak memory 183144 kb
Host smart-69b8dd82-483e-40a6-bbfe-e2e78d340d4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76898198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.76898198
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.871373262
Short name T32
Test name
Test status
Simulation time 10912346672 ps
CPU time 8.83 seconds
Started Feb 07 12:37:55 PM PST 24
Finished Feb 07 12:38:07 PM PST 24
Peak memory 183360 kb
Host smart-de7b9e90-c15a-4d8c-8d10-be7368aa1248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871373262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.871373262
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3240881737
Short name T50
Test name
Test status
Simulation time 216521138273 ps
CPU time 604.91 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:47:04 PM PST 24
Peak memory 199708 kb
Host smart-f0eae0c5-b025-4978-ab46-53833bff333c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240881737 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3240881737
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3323967576
Short name T29
Test name
Test status
Simulation time 365790417 ps
CPU time 1.07 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 183052 kb
Host smart-42733c59-cb3b-4942-8f95-af19761e6056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323967576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3323967576
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.3052929836
Short name T79
Test name
Test status
Simulation time 354305372289 ps
CPU time 708.99 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:49:00 PM PST 24
Peak memory 200264 kb
Host smart-9110d56b-0d6f-4cac-8fae-e3088309c16f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052929836 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.3052929836
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1169242698
Short name T94
Test name
Test status
Simulation time 57227389014 ps
CPU time 46.99 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:58 PM PST 24
Peak memory 194724 kb
Host smart-7f648c57-30cd-4b75-9b6e-f5169f130f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169242698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1169242698
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3441319860
Short name T106
Test name
Test status
Simulation time 88474202630 ps
CPU time 71.99 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:38:25 PM PST 24
Peak memory 183316 kb
Host smart-c02ae404-a556-4c6d-93a5-802ed8b851a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441319860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3441319860
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.335334771
Short name T203
Test name
Test status
Simulation time 78376065196 ps
CPU time 856.26 seconds
Started Feb 07 12:38:17 PM PST 24
Finished Feb 07 12:52:34 PM PST 24
Peak memory 202532 kb
Host smart-fd6af517-f6ed-4020-a54f-d0b0e3623376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335334771 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.335334771
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.58420427
Short name T40
Test name
Test status
Simulation time 4059344222 ps
CPU time 2.28 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:37:05 PM PST 24
Peak memory 215320 kb
Host smart-ce746eb2-a9de-47a5-8d30-1a710e521efc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58420427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.58420427
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.4176946859
Short name T51
Test name
Test status
Simulation time 60263436393 ps
CPU time 232.47 seconds
Started Feb 07 12:37:44 PM PST 24
Finished Feb 07 12:41:37 PM PST 24
Peak memory 198272 kb
Host smart-226e5325-607c-4f53-8ff4-b2c768d5ed77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176946859 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.4176946859
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2231590827
Short name T10
Test name
Test status
Simulation time 7931464553 ps
CPU time 4.35 seconds
Started Feb 07 12:51:10 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 196644 kb
Host smart-23daa4bd-9b47-442a-97ee-1b6c4082060a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231590827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2231590827
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.1684321225
Short name T89
Test name
Test status
Simulation time 176812962159 ps
CPU time 64.86 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:39:06 PM PST 24
Peak memory 194484 kb
Host smart-5c1ca9c8-32c6-43b6-b066-712a997fc875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684321225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.1684321225
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3128593105
Short name T272
Test name
Test status
Simulation time 29732117808 ps
CPU time 231.66 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:41:53 PM PST 24
Peak memory 198316 kb
Host smart-78b5daed-b015-4c58-ae71-0de08a7dea66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128593105 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3128593105
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.653711398
Short name T186
Test name
Test status
Simulation time 96152311481 ps
CPU time 209.02 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:41:31 PM PST 24
Peak memory 198308 kb
Host smart-15a657a4-888d-4bfc-a3cb-61daf2c0695e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653711398 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.653711398
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.853930227
Short name T9
Test name
Test status
Simulation time 8575466529 ps
CPU time 4.47 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 196856 kb
Host smart-2ac2504a-292a-419e-87f0-066923a6d338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853930227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.853930227
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1563313789
Short name T369
Test name
Test status
Simulation time 398530098 ps
CPU time 0.91 seconds
Started Feb 07 12:50:48 PM PST 24
Finished Feb 07 12:50:50 PM PST 24
Peak memory 183132 kb
Host smart-1cc575aa-6282-4728-950f-e013d422e304
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563313789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1563313789
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3612691967
Short name T63
Test name
Test status
Simulation time 2292899855 ps
CPU time 4.32 seconds
Started Feb 07 12:50:48 PM PST 24
Finished Feb 07 12:50:53 PM PST 24
Peak memory 191364 kb
Host smart-c49f85cb-3d03-4272-ab69-4c4a01e9c982
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612691967 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3612691967
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3887010889
Short name T26
Test name
Test status
Simulation time 1375825065 ps
CPU time 1.17 seconds
Started Feb 07 12:50:46 PM PST 24
Finished Feb 07 12:50:48 PM PST 24
Peak memory 183164 kb
Host smart-5decbbd1-65f0-430b-aa2d-715be980f792
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887010889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3887010889
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2731228849
Short name T83
Test name
Test status
Simulation time 415963644 ps
CPU time 0.9 seconds
Started Feb 07 12:50:58 PM PST 24
Finished Feb 07 12:51:00 PM PST 24
Peak memory 194204 kb
Host smart-a9b3e108-971a-46eb-93a9-f4a97ca5ef67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731228849 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2731228849
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2460488499
Short name T306
Test name
Test status
Simulation time 465368574 ps
CPU time 0.57 seconds
Started Feb 07 12:50:48 PM PST 24
Finished Feb 07 12:50:50 PM PST 24
Peak memory 182904 kb
Host smart-a1bb1f4f-1896-4b72-811f-2db9060b6dee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460488499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2460488499
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1414660549
Short name T357
Test name
Test status
Simulation time 284124598 ps
CPU time 0.66 seconds
Started Feb 07 12:50:47 PM PST 24
Finished Feb 07 12:50:49 PM PST 24
Peak memory 182740 kb
Host smart-00e00f36-79d1-43ae-920b-e5eee0c025ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414660549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1414660549
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3534223751
Short name T72
Test name
Test status
Simulation time 1802072393 ps
CPU time 4.44 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:05 PM PST 24
Peak memory 192140 kb
Host smart-f49b6a5e-0738-45ef-ac83-5017cd037dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534223751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3534223751
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.1137325227
Short name T28
Test name
Test status
Simulation time 516259607 ps
CPU time 1.32 seconds
Started Feb 07 12:50:39 PM PST 24
Finished Feb 07 12:50:41 PM PST 24
Peak memory 197896 kb
Host smart-8c33900e-436a-492f-9c47-7e4e002c7b66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137325227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.1137325227
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2657435018
Short name T384
Test name
Test status
Simulation time 8134644397 ps
CPU time 4.03 seconds
Started Feb 07 12:50:38 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 196920 kb
Host smart-7f63b926-a61f-43ef-a7d4-5d164d558658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657435018 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2657435018
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2469176114
Short name T347
Test name
Test status
Simulation time 401327778 ps
CPU time 1.26 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:01 PM PST 24
Peak memory 183020 kb
Host smart-bdd08d5e-1ef1-4a28-ad79-021503b80b42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469176114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2469176114
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2629007536
Short name T400
Test name
Test status
Simulation time 6059249511 ps
CPU time 8.71 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:52 PM PST 24
Peak memory 191480 kb
Host smart-32f23dcc-7e5e-4854-b0c4-b37d8b508768
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629007536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2629007536
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.3662881434
Short name T54
Test name
Test status
Simulation time 1397304693 ps
CPU time 2.94 seconds
Started Feb 07 12:50:42 PM PST 24
Finished Feb 07 12:50:47 PM PST 24
Peak memory 183052 kb
Host smart-685d91d4-0275-4511-b059-9d8f10ef6a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662881434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.3662881434
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.796489563
Short name T408
Test name
Test status
Simulation time 503215944 ps
CPU time 1.46 seconds
Started Feb 07 12:50:58 PM PST 24
Finished Feb 07 12:51:00 PM PST 24
Peak memory 195876 kb
Host smart-bb667cb4-7372-436e-89e1-2f0d4737e56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796489563 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.796489563
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.905976707
Short name T327
Test name
Test status
Simulation time 536782706 ps
CPU time 1 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 183168 kb
Host smart-186299c1-3d38-4923-b4dd-69d1f34d6942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905976707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.905976707
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3196830371
Short name T367
Test name
Test status
Simulation time 350310775 ps
CPU time 0.65 seconds
Started Feb 07 12:50:57 PM PST 24
Finished Feb 07 12:50:58 PM PST 24
Peak memory 183140 kb
Host smart-faa04afd-2fc2-4a40-8926-108cb40888c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196830371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3196830371
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3906413597
Short name T12
Test name
Test status
Simulation time 513658128 ps
CPU time 0.74 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 183004 kb
Host smart-94abe3cb-a555-4cd0-bcf4-811a65e73c96
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906413597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3906413597
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1377335907
Short name T15
Test name
Test status
Simulation time 528007042 ps
CPU time 0.55 seconds
Started Feb 07 12:50:59 PM PST 24
Finished Feb 07 12:51:00 PM PST 24
Peak memory 182860 kb
Host smart-b7188eb4-38c3-4ba0-b472-b0b5b8b76783
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377335907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1377335907
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3390095925
Short name T75
Test name
Test status
Simulation time 2613272333 ps
CPU time 6.69 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:51 PM PST 24
Peak memory 191364 kb
Host smart-e428b278-7b10-4f25-ab94-5a32772649dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390095925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3390095925
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.4023685194
Short name T328
Test name
Test status
Simulation time 678281997 ps
CPU time 1.97 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 197828 kb
Host smart-5ecc242d-0961-498a-8459-b2c26b00c615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023685194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.4023685194
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2130684330
Short name T376
Test name
Test status
Simulation time 4317661315 ps
CPU time 3.76 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 195476 kb
Host smart-4f97d682-b4d7-464d-8cc4-aec6145c3dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130684330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2130684330
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.2077488710
Short name T352
Test name
Test status
Simulation time 487082871 ps
CPU time 0.75 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:02 PM PST 24
Peak memory 194672 kb
Host smart-36cde5f1-9107-43ba-a9fe-afd3f00f108e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077488710 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.2077488710
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.4087996345
Short name T415
Test name
Test status
Simulation time 521835727 ps
CPU time 0.8 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:55 PM PST 24
Peak memory 183056 kb
Host smart-d5201f11-4d6b-4815-86cd-6a97b4f0d97d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087996345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.4087996345
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3600772329
Short name T363
Test name
Test status
Simulation time 306041492 ps
CPU time 0.65 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:02 PM PST 24
Peak memory 183072 kb
Host smart-e707ad07-8ac3-4069-b13c-57b569be0547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600772329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3600772329
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.2529472838
Short name T429
Test name
Test status
Simulation time 1269517519 ps
CPU time 1.18 seconds
Started Feb 07 12:50:53 PM PST 24
Finished Feb 07 12:50:54 PM PST 24
Peak memory 194684 kb
Host smart-1d3ea9b1-d920-43ab-81b3-13cd349a1891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529472838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.2529472838
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.4121052452
Short name T17
Test name
Test status
Simulation time 1030872982 ps
CPU time 2.92 seconds
Started Feb 07 12:50:45 PM PST 24
Finished Feb 07 12:50:49 PM PST 24
Peak memory 197956 kb
Host smart-11c49076-a2a9-444f-8bf9-c3b64e142b39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121052452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.4121052452
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2467885946
Short name T362
Test name
Test status
Simulation time 4358413519 ps
CPU time 2.39 seconds
Started Feb 07 12:51:02 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 195456 kb
Host smart-02cf4227-1e65-4e34-9718-a76225ace375
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467885946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2467885946
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.2846025489
Short name T382
Test name
Test status
Simulation time 473443009 ps
CPU time 1.32 seconds
Started Feb 07 12:50:50 PM PST 24
Finished Feb 07 12:50:52 PM PST 24
Peak memory 194704 kb
Host smart-82368424-f56e-4a6f-b88d-e3ae1063c66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846025489 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.2846025489
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.2661415599
Short name T381
Test name
Test status
Simulation time 398955206 ps
CPU time 0.83 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:56 PM PST 24
Peak memory 183096 kb
Host smart-40a23c81-c3c5-401e-9598-425b60f24796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661415599 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.2661415599
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.1487670498
Short name T389
Test name
Test status
Simulation time 320167954 ps
CPU time 0.68 seconds
Started Feb 07 12:50:52 PM PST 24
Finished Feb 07 12:50:53 PM PST 24
Peak memory 182928 kb
Host smart-cb3e889a-c32e-4729-9675-5b28dd7fb3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487670498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.1487670498
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3675356728
Short name T386
Test name
Test status
Simulation time 857674355 ps
CPU time 1.31 seconds
Started Feb 07 12:51:04 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 193484 kb
Host smart-46f0aff4-c0eb-4266-bdbc-0e0c672f4d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675356728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3675356728
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1796617798
Short name T353
Test name
Test status
Simulation time 913363937 ps
CPU time 1.32 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:56 PM PST 24
Peak memory 197936 kb
Host smart-a4000392-e9de-4ff5-b22a-10913cff1486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796617798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1796617798
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.757645376
Short name T358
Test name
Test status
Simulation time 3997619305 ps
CPU time 7.33 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:51:04 PM PST 24
Peak memory 195136 kb
Host smart-c3e0cb90-dda6-4d26-b4e3-bacd7b2b6314
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757645376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl
_intg_err.757645376
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3566157266
Short name T416
Test name
Test status
Simulation time 338936373 ps
CPU time 1.06 seconds
Started Feb 07 12:50:55 PM PST 24
Finished Feb 07 12:50:57 PM PST 24
Peak memory 195116 kb
Host smart-cdd0e03e-e952-442e-b87a-4e2f5182b0b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566157266 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3566157266
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2772179288
Short name T427
Test name
Test status
Simulation time 447881449 ps
CPU time 1.21 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 183156 kb
Host smart-700a165d-1aff-4425-8e88-56d81aa4fef8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772179288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2772179288
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.875242996
Short name T372
Test name
Test status
Simulation time 438505869 ps
CPU time 0.71 seconds
Started Feb 07 12:50:55 PM PST 24
Finished Feb 07 12:50:57 PM PST 24
Peak memory 182944 kb
Host smart-addf6c2a-9b80-47bf-a92c-28ecdb3e3674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875242996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.875242996
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.1603109175
Short name T401
Test name
Test status
Simulation time 1995145910 ps
CPU time 1.22 seconds
Started Feb 07 12:51:04 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 194632 kb
Host smart-2d74aeac-36c3-4ddb-9376-8d59956bfab7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603109175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.1603109175
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.4270529088
Short name T366
Test name
Test status
Simulation time 447685984 ps
CPU time 1.91 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:50:59 PM PST 24
Peak memory 197808 kb
Host smart-b0f330ad-cc47-4c65-b7ee-b9eaf65523eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270529088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.4270529088
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1817317949
Short name T318
Test name
Test status
Simulation time 8173929834 ps
CPU time 4.42 seconds
Started Feb 07 12:51:05 PM PST 24
Finished Feb 07 12:51:11 PM PST 24
Peak memory 197000 kb
Host smart-29503cb5-9e93-4444-8fc2-d18532984548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817317949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1817317949
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1903326238
Short name T330
Test name
Test status
Simulation time 391956427 ps
CPU time 0.92 seconds
Started Feb 07 12:51:07 PM PST 24
Finished Feb 07 12:51:09 PM PST 24
Peak memory 197212 kb
Host smart-006c6cf8-12c5-4e60-8229-cb60f1b91d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903326238 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1903326238
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1830938998
Short name T378
Test name
Test status
Simulation time 363061742 ps
CPU time 1.08 seconds
Started Feb 07 12:51:15 PM PST 24
Finished Feb 07 12:51:17 PM PST 24
Peak memory 183068 kb
Host smart-2b4e028b-954d-44ad-b5b1-539d949f59fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830938998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1830938998
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2524622721
Short name T303
Test name
Test status
Simulation time 315974639 ps
CPU time 0.66 seconds
Started Feb 07 12:50:48 PM PST 24
Finished Feb 07 12:50:49 PM PST 24
Peak memory 182856 kb
Host smart-09665d93-d87a-40bd-a27b-9ef79c9c7ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524622721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2524622721
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3925608887
Short name T71
Test name
Test status
Simulation time 996003036 ps
CPU time 2.14 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:09 PM PST 24
Peak memory 192176 kb
Host smart-7bfa14eb-2fef-48be-bca2-86dd6f4c9ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925608887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3925608887
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.4261289006
Short name T428
Test name
Test status
Simulation time 406609130 ps
CPU time 1.18 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:05 PM PST 24
Peak memory 197592 kb
Host smart-09e56649-7732-451a-9069-76ac63828e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261289006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.4261289006
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3104439736
Short name T420
Test name
Test status
Simulation time 4572975430 ps
CPU time 4.87 seconds
Started Feb 07 12:51:01 PM PST 24
Finished Feb 07 12:51:07 PM PST 24
Peak memory 196500 kb
Host smart-db1db2c5-f2de-42ad-ad84-a38b234bc09a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104439736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3104439736
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1050531467
Short name T332
Test name
Test status
Simulation time 563145264 ps
CPU time 0.78 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:07 PM PST 24
Peak memory 195128 kb
Host smart-03d5c46e-aab6-4886-a0af-3deb78b8ae06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050531467 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1050531467
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.2205850271
Short name T68
Test name
Test status
Simulation time 397925950 ps
CPU time 0.62 seconds
Started Feb 07 12:50:55 PM PST 24
Finished Feb 07 12:50:57 PM PST 24
Peak memory 183024 kb
Host smart-cf63c048-90af-447f-80c0-4e0f6eeb13a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205850271 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.2205850271
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.100884618
Short name T399
Test name
Test status
Simulation time 475059420 ps
CPU time 1.24 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:02 PM PST 24
Peak memory 182920 kb
Host smart-febf20e8-0245-41e3-abbf-275fcc923cff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100884618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.100884618
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2510728959
Short name T70
Test name
Test status
Simulation time 939407305 ps
CPU time 1.46 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 193624 kb
Host smart-84782e3e-955e-472c-a956-23d7b4b95868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510728959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2510728959
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3195825063
Short name T407
Test name
Test status
Simulation time 508732825 ps
CPU time 1.8 seconds
Started Feb 07 12:50:47 PM PST 24
Finished Feb 07 12:50:50 PM PST 24
Peak memory 197812 kb
Host smart-8d60b5a1-f6da-4875-95a1-7ad223b3fc64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195825063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3195825063
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.930672352
Short name T315
Test name
Test status
Simulation time 4373650519 ps
CPU time 7.56 seconds
Started Feb 07 12:50:58 PM PST 24
Finished Feb 07 12:51:07 PM PST 24
Peak memory 196248 kb
Host smart-938d9eaf-2da5-4432-9cb2-bbb5056d472c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930672352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.930672352
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1184735967
Short name T410
Test name
Test status
Simulation time 306809532 ps
CPU time 1.05 seconds
Started Feb 07 12:51:09 PM PST 24
Finished Feb 07 12:51:11 PM PST 24
Peak memory 194224 kb
Host smart-cb54aaf4-8be3-4984-97d5-9754930ad79f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184735967 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1184735967
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3366347495
Short name T394
Test name
Test status
Simulation time 425471889 ps
CPU time 0.71 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:04 PM PST 24
Peak memory 183104 kb
Host smart-a9198d6a-2f5d-4d26-ab30-d716a70d64b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366347495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3366347495
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.643143318
Short name T425
Test name
Test status
Simulation time 515339716 ps
CPU time 0.67 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:12 PM PST 24
Peak memory 182904 kb
Host smart-265edd83-d3d0-40c5-839d-91d13b80ff8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643143318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.643143318
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1882537518
Short name T339
Test name
Test status
Simulation time 1125950013 ps
CPU time 1.95 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 193464 kb
Host smart-60951bf0-3d97-49a6-9ab7-cce84ef1e14d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882537518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1882537518
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.375913831
Short name T351
Test name
Test status
Simulation time 653619912 ps
CPU time 1.42 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:13 PM PST 24
Peak memory 197896 kb
Host smart-92a3d80c-30f5-4794-9ebb-327e1d6f5693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375913831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.375913831
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.668104914
Short name T350
Test name
Test status
Simulation time 8533430416 ps
CPU time 14.54 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:27 PM PST 24
Peak memory 196980 kb
Host smart-375caf21-5ccf-4d0a-8d55-3c6b7113d615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668104914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.668104914
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.886306172
Short name T82
Test name
Test status
Simulation time 505599270 ps
CPU time 1.3 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:05 PM PST 24
Peak memory 194772 kb
Host smart-1175440b-0514-46a8-bbcc-414a9059aa89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886306172 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.886306172
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.336014828
Short name T61
Test name
Test status
Simulation time 541500829 ps
CPU time 0.95 seconds
Started Feb 07 12:51:04 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 183104 kb
Host smart-9c3d7bcd-99e7-40cb-9a7d-5a80012d0c14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336014828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.336014828
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3850984561
Short name T305
Test name
Test status
Simulation time 503415604 ps
CPU time 1.27 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 182772 kb
Host smart-197d3178-1044-4434-a5e5-9a077f8a9beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850984561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3850984561
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1026344141
Short name T329
Test name
Test status
Simulation time 1742367557 ps
CPU time 2.41 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 194704 kb
Host smart-b51bb491-5862-4956-a495-f5facdfed269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026344141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1026344141
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.837845043
Short name T319
Test name
Test status
Simulation time 395274198 ps
CPU time 1.51 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 197984 kb
Host smart-988e9ab4-6c32-4465-a64c-d1dfebca61c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837845043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.837845043
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.3426977889
Short name T392
Test name
Test status
Simulation time 7957558792 ps
CPU time 4.02 seconds
Started Feb 07 12:51:15 PM PST 24
Finished Feb 07 12:51:20 PM PST 24
Peak memory 196892 kb
Host smart-fcc61ed9-c5c5-4d1c-9f26-c1147cc700d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426977889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.3426977889
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3327864230
Short name T387
Test name
Test status
Simulation time 534236015 ps
CPU time 1.45 seconds
Started Feb 07 12:51:09 PM PST 24
Finished Feb 07 12:51:12 PM PST 24
Peak memory 194908 kb
Host smart-e784ea2d-fb78-4f5f-b815-58c4b25203bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327864230 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3327864230
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.3806228581
Short name T349
Test name
Test status
Simulation time 439285399 ps
CPU time 1.24 seconds
Started Feb 07 12:51:07 PM PST 24
Finished Feb 07 12:51:09 PM PST 24
Peak memory 183136 kb
Host smart-feba946e-4f9b-4a68-9e08-6cdcf1da846b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806228581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.3806228581
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3081084277
Short name T364
Test name
Test status
Simulation time 279641998 ps
CPU time 0.77 seconds
Started Feb 07 12:51:13 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 182832 kb
Host smart-e3b23742-dab6-4bc5-b69e-fb5a2c5853e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081084277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3081084277
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.3861818023
Short name T69
Test name
Test status
Simulation time 1820962478 ps
CPU time 2.4 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 194624 kb
Host smart-0ba24154-8a13-4708-998a-d6e1d69342e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861818023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.3861818023
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1107170918
Short name T320
Test name
Test status
Simulation time 593399718 ps
CPU time 2.31 seconds
Started Feb 07 12:51:05 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 197964 kb
Host smart-6e6ee357-896e-4915-9885-37a3a220513e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107170918 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1107170918
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.2142218596
Short name T86
Test name
Test status
Simulation time 4401181070 ps
CPU time 2.83 seconds
Started Feb 07 12:51:13 PM PST 24
Finished Feb 07 12:51:17 PM PST 24
Peak memory 196560 kb
Host smart-a3876d66-c17f-4f49-9126-37fb1aa82afe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142218596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.2142218596
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.3257588978
Short name T11
Test name
Test status
Simulation time 609346322 ps
CPU time 1.19 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:05 PM PST 24
Peak memory 197792 kb
Host smart-7aadcf26-b7c2-43cc-937d-e0ee8cfdea19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257588978 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.3257588978
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.4269808334
Short name T7
Test name
Test status
Simulation time 524587789 ps
CPU time 0.82 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 183220 kb
Host smart-132237cc-f96b-4deb-87ec-588b7064fa4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269808334 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.4269808334
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1702439950
Short name T123
Test name
Test status
Simulation time 433682345 ps
CPU time 1.14 seconds
Started Feb 07 12:51:08 PM PST 24
Finished Feb 07 12:51:10 PM PST 24
Peak memory 183024 kb
Host smart-1c279367-60c7-4015-ab8c-32aff59d7532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702439950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1702439950
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3680800944
Short name T385
Test name
Test status
Simulation time 1090746886 ps
CPU time 1.6 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 193668 kb
Host smart-a09055bd-c75c-4fb9-9243-0aeb60bf2887
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680800944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3680800944
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.114485333
Short name T365
Test name
Test status
Simulation time 1065682355 ps
CPU time 1.78 seconds
Started Feb 07 12:51:07 PM PST 24
Finished Feb 07 12:51:10 PM PST 24
Peak memory 197896 kb
Host smart-cbf9a889-1113-4db2-8b2a-a38441ef958c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114485333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.114485333
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2925333943
Short name T313
Test name
Test status
Simulation time 4587716835 ps
CPU time 2.3 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:09 PM PST 24
Peak memory 195260 kb
Host smart-17f2f41c-6f87-4d4a-977e-fd75ed4e453f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925333943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2925333943
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.2710267079
Short name T312
Test name
Test status
Simulation time 471835956 ps
CPU time 1.5 seconds
Started Feb 07 12:51:02 PM PST 24
Finished Feb 07 12:51:04 PM PST 24
Peak memory 195184 kb
Host smart-e83a61a3-daa6-4563-9b64-2c29a341f4ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710267079 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.2710267079
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2663949879
Short name T66
Test name
Test status
Simulation time 389665614 ps
CPU time 0.78 seconds
Started Feb 07 12:51:13 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 182996 kb
Host smart-14f9a581-c240-41ee-aca5-6b194eb39bb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663949879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2663949879
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1670335281
Short name T411
Test name
Test status
Simulation time 463665256 ps
CPU time 0.91 seconds
Started Feb 07 12:51:08 PM PST 24
Finished Feb 07 12:51:10 PM PST 24
Peak memory 182804 kb
Host smart-69cca8c4-fe28-4022-97c5-e9c160d67a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670335281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1670335281
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1718168987
Short name T323
Test name
Test status
Simulation time 2173859675 ps
CPU time 1.95 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 194764 kb
Host smart-dbaf9a74-fe95-4c10-a49c-a2f15ede934b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718168987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1718168987
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.698833626
Short name T391
Test name
Test status
Simulation time 693443619 ps
CPU time 2.81 seconds
Started Feb 07 12:51:10 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 197984 kb
Host smart-d75f1d15-2742-46c5-8f22-10310577170e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698833626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.698833626
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1381014486
Short name T4
Test name
Test status
Simulation time 453701763 ps
CPU time 0.85 seconds
Started Feb 07 12:50:44 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 192360 kb
Host smart-496f946b-c9f0-4e1b-aa38-09e4ed35cea9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381014486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1381014486
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2939238841
Short name T55
Test name
Test status
Simulation time 4628139472 ps
CPU time 7.09 seconds
Started Feb 07 12:50:37 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 194504 kb
Host smart-f4498230-5ad9-4f35-a1d8-ad2cf80017a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939238841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2939238841
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3565221195
Short name T62
Test name
Test status
Simulation time 905848908 ps
CPU time 0.65 seconds
Started Feb 07 12:50:51 PM PST 24
Finished Feb 07 12:50:53 PM PST 24
Peak memory 182928 kb
Host smart-f2cff298-4fe5-4186-9ed8-3a4b7c53797e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565221195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3565221195
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3228310899
Short name T371
Test name
Test status
Simulation time 418040589 ps
CPU time 0.86 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 195848 kb
Host smart-c5019b0c-7b9a-4170-9285-dab2b9d44619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228310899 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3228310899
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2968877518
Short name T64
Test name
Test status
Simulation time 432155988 ps
CPU time 1.25 seconds
Started Feb 07 12:50:38 PM PST 24
Finished Feb 07 12:50:40 PM PST 24
Peak memory 183144 kb
Host smart-681a6bc2-57ec-4609-a688-949dab4d6abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968877518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2968877518
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1290433352
Short name T14
Test name
Test status
Simulation time 294716372 ps
CPU time 0.6 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:02 PM PST 24
Peak memory 182832 kb
Host smart-de07696d-7971-470d-90b6-6186944a7596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290433352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1290433352
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1827248554
Short name T53
Test name
Test status
Simulation time 415199649 ps
CPU time 0.6 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 182876 kb
Host smart-54d1662c-a8a5-4c1e-a6ac-8b1520328223
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827248554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1827248554
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2826752390
Short name T56
Test name
Test status
Simulation time 337693882 ps
CPU time 0.66 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:55 PM PST 24
Peak memory 182884 kb
Host smart-303dccf4-1534-4217-bf93-512320c877f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826752390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2826752390
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.436451747
Short name T409
Test name
Test status
Simulation time 1841787459 ps
CPU time 2.99 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 191412 kb
Host smart-0de305bd-e826-4529-a7e7-e07320a1065d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436451747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.436451747
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3847490429
Short name T361
Test name
Test status
Simulation time 471143357 ps
CPU time 2.27 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:03 PM PST 24
Peak memory 197832 kb
Host smart-c5605e49-b398-427d-b7f4-b55fe395bcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847490429 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3847490429
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.2299961506
Short name T402
Test name
Test status
Simulation time 4456060577 ps
CPU time 6.52 seconds
Started Feb 07 12:51:00 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 196564 kb
Host smart-92ca8650-47da-4ed1-9b79-6afa53f1850d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299961506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.2299961506
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2049814188
Short name T424
Test name
Test status
Simulation time 481473738 ps
CPU time 0.65 seconds
Started Feb 07 12:51:23 PM PST 24
Finished Feb 07 12:51:25 PM PST 24
Peak memory 182948 kb
Host smart-e65803e5-b517-4f1b-bfa4-911046630b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049814188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2049814188
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1939712615
Short name T413
Test name
Test status
Simulation time 383916299 ps
CPU time 1.15 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 182920 kb
Host smart-1f7d194c-3556-4c21-a81a-a8424e8034ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939712615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1939712615
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.719833081
Short name T344
Test name
Test status
Simulation time 472404094 ps
CPU time 0.73 seconds
Started Feb 07 12:51:03 PM PST 24
Finished Feb 07 12:51:05 PM PST 24
Peak memory 182868 kb
Host smart-cf660986-2d90-4c7b-9d42-2d5744b49b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719833081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.719833081
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3827134573
Short name T374
Test name
Test status
Simulation time 508215541 ps
CPU time 0.81 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 183156 kb
Host smart-f6eb9737-bca8-4c18-ac95-d6a9df25da20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827134573 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3827134573
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1834089780
Short name T380
Test name
Test status
Simulation time 434474121 ps
CPU time 1.31 seconds
Started Feb 07 12:51:21 PM PST 24
Finished Feb 07 12:51:24 PM PST 24
Peak memory 182944 kb
Host smart-71a78ab5-ebd5-490e-9a4a-589524ac71a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834089780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1834089780
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.369767444
Short name T373
Test name
Test status
Simulation time 434100154 ps
CPU time 1.35 seconds
Started Feb 07 12:51:15 PM PST 24
Finished Feb 07 12:51:17 PM PST 24
Peak memory 182900 kb
Host smart-820f5070-7ac4-40dc-bcc8-afd0b5407c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369767444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.369767444
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4262174105
Short name T326
Test name
Test status
Simulation time 490085387 ps
CPU time 0.87 seconds
Started Feb 07 12:51:15 PM PST 24
Finished Feb 07 12:51:17 PM PST 24
Peak memory 183140 kb
Host smart-50b17eb8-d400-43ac-a0e3-e6e9bdfd46b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262174105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4262174105
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.4151678331
Short name T340
Test name
Test status
Simulation time 479882637 ps
CPU time 0.67 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 182976 kb
Host smart-3c32fabe-713b-487e-a162-5b290179abb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151678331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.4151678331
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.2571684453
Short name T309
Test name
Test status
Simulation time 351165665 ps
CPU time 1.03 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 183020 kb
Host smart-26cd068f-b3f1-4877-a7d4-cb0c1bef1eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571684453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.2571684453
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2601603850
Short name T311
Test name
Test status
Simulation time 437195560 ps
CPU time 1.17 seconds
Started Feb 07 12:51:10 PM PST 24
Finished Feb 07 12:51:11 PM PST 24
Peak memory 182904 kb
Host smart-a4c4d9e8-c2ba-471f-b729-850ceb4c2335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601603850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2601603850
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.323088732
Short name T67
Test name
Test status
Simulation time 517163231 ps
CPU time 0.9 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 192272 kb
Host smart-89f82562-e4e6-4b77-a526-7edd08f2d24a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323088732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.323088732
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.4003377395
Short name T375
Test name
Test status
Simulation time 6600599031 ps
CPU time 2.53 seconds
Started Feb 07 12:50:39 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 191412 kb
Host smart-128feac6-8890-467e-bd2c-7c5cc4c8439e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003377395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.4003377395
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2211071342
Short name T307
Test name
Test status
Simulation time 785856719 ps
CPU time 1.17 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 183148 kb
Host smart-b0838629-8caf-46f6-92c6-b955cdfeefdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211071342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2211071342
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.563263931
Short name T317
Test name
Test status
Simulation time 454126840 ps
CPU time 0.75 seconds
Started Feb 07 12:50:44 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 195572 kb
Host smart-ed9bb4ed-f03b-492c-ab46-2647e1e79489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563263931 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.563263931
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.2707399668
Short name T3
Test name
Test status
Simulation time 386022091 ps
CPU time 0.68 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 183028 kb
Host smart-f58871e2-6ec8-4bb6-9731-b5ef1da4143b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707399668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.2707399668
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1819136230
Short name T405
Test name
Test status
Simulation time 435451037 ps
CPU time 1.18 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 183140 kb
Host smart-8f517b64-5d5a-4136-af22-9fa98a5b1e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819136230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1819136230
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2276602695
Short name T335
Test name
Test status
Simulation time 401721657 ps
CPU time 1.06 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 182804 kb
Host smart-e7db93a5-dad1-446d-8c9e-a3b19cb47781
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276602695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2276602695
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.774694934
Short name T314
Test name
Test status
Simulation time 524941039 ps
CPU time 0.92 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 183128 kb
Host smart-81fbf34b-f08a-4b75-b5d5-d4c30a4157f2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774694934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.774694934
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2986800545
Short name T73
Test name
Test status
Simulation time 1915165214 ps
CPU time 0.9 seconds
Started Feb 07 12:50:39 PM PST 24
Finished Feb 07 12:50:41 PM PST 24
Peak memory 194628 kb
Host smart-36146852-d6cd-45de-91e6-e99e58cb3324
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986800545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2986800545
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.2128084959
Short name T354
Test name
Test status
Simulation time 380297768 ps
CPU time 1.77 seconds
Started Feb 07 12:50:39 PM PST 24
Finished Feb 07 12:50:42 PM PST 24
Peak memory 197924 kb
Host smart-4ba824b1-2fb1-4c23-bc71-d312922110e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128084959 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.2128084959
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.2398784631
Short name T324
Test name
Test status
Simulation time 8467733263 ps
CPU time 13.45 seconds
Started Feb 07 12:50:37 PM PST 24
Finished Feb 07 12:50:51 PM PST 24
Peak memory 197052 kb
Host smart-ab72f854-7d9c-4c0e-a9d9-12a7a390e844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398784631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.2398784631
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.2126224202
Short name T404
Test name
Test status
Simulation time 339757902 ps
CPU time 1 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:12 PM PST 24
Peak memory 182908 kb
Host smart-61a9fb89-5b67-4cb8-a2cc-d9127e0f9ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126224202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.2126224202
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3350812459
Short name T341
Test name
Test status
Simulation time 484725180 ps
CPU time 0.68 seconds
Started Feb 07 12:51:12 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 182912 kb
Host smart-b3becbeb-cc18-4142-b085-caf94453f818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350812459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3350812459
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3320787986
Short name T322
Test name
Test status
Simulation time 298460994 ps
CPU time 0.77 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:08 PM PST 24
Peak memory 183076 kb
Host smart-85e01745-7978-467c-ae82-d34b71314eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320787986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3320787986
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2998755027
Short name T345
Test name
Test status
Simulation time 506026640 ps
CPU time 0.75 seconds
Started Feb 07 12:51:05 PM PST 24
Finished Feb 07 12:51:07 PM PST 24
Peak memory 182964 kb
Host smart-712ef0d1-7578-409b-aba4-06b16516da50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998755027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2998755027
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.1231727004
Short name T325
Test name
Test status
Simulation time 413550705 ps
CPU time 0.89 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:07 PM PST 24
Peak memory 182912 kb
Host smart-30274348-db11-4e84-a2a7-9c0f8889d540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231727004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.1231727004
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4187114657
Short name T412
Test name
Test status
Simulation time 383579673 ps
CPU time 1.09 seconds
Started Feb 07 12:51:16 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 182948 kb
Host smart-6bad8144-8b5f-4f58-83c4-cd7d5b9e6df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187114657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4187114657
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2026933963
Short name T316
Test name
Test status
Simulation time 492234116 ps
CPU time 1.35 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:13 PM PST 24
Peak memory 183088 kb
Host smart-0098c5c4-2dd0-4715-9f76-25d489640f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026933963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2026933963
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1288528080
Short name T304
Test name
Test status
Simulation time 447467839 ps
CPU time 1.19 seconds
Started Feb 07 12:51:16 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 182900 kb
Host smart-24b1a0a5-4f22-4f1c-b6e4-3435ced2abea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288528080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1288528080
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1904166776
Short name T8
Test name
Test status
Simulation time 416456649 ps
CPU time 1.19 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 182968 kb
Host smart-315d4017-3e97-4313-be8f-0c6d1e7c93c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904166776 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1904166776
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3132219212
Short name T16
Test name
Test status
Simulation time 394828113 ps
CPU time 0.6 seconds
Started Feb 07 12:51:16 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 183040 kb
Host smart-9e095803-86a6-4b21-9bb8-35698ff2bf45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132219212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3132219212
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2274516004
Short name T5
Test name
Test status
Simulation time 511281376 ps
CPU time 0.87 seconds
Started Feb 07 12:50:35 PM PST 24
Finished Feb 07 12:50:37 PM PST 24
Peak memory 183112 kb
Host smart-38731263-6607-41ab-b2a3-dacf573e0ba8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274516004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2274516004
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.2455003488
Short name T370
Test name
Test status
Simulation time 6188338373 ps
CPU time 5.49 seconds
Started Feb 07 12:50:49 PM PST 24
Finished Feb 07 12:50:55 PM PST 24
Peak memory 191512 kb
Host smart-5cdc641a-a5ec-41b1-9cab-aa09a349c8d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455003488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.2455003488
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3410781901
Short name T398
Test name
Test status
Simulation time 1176292123 ps
CPU time 1.25 seconds
Started Feb 07 12:50:42 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 183012 kb
Host smart-07382b3b-0980-42e9-aed2-c21a4f8ef9a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410781901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3410781901
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.538087637
Short name T342
Test name
Test status
Simulation time 573303015 ps
CPU time 1.55 seconds
Started Feb 07 12:50:58 PM PST 24
Finished Feb 07 12:51:00 PM PST 24
Peak memory 194728 kb
Host smart-f037e0ba-156d-4e4c-98e2-853c3d5d14bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538087637 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.538087637
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1838594946
Short name T65
Test name
Test status
Simulation time 409543884 ps
CPU time 0.63 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:43 PM PST 24
Peak memory 183092 kb
Host smart-83a7e26d-eef6-40d8-a5c3-87addbc86553
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838594946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1838594946
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.55082703
Short name T346
Test name
Test status
Simulation time 468981105 ps
CPU time 0.83 seconds
Started Feb 07 12:50:48 PM PST 24
Finished Feb 07 12:50:49 PM PST 24
Peak memory 182816 kb
Host smart-4eba018f-d96a-4fc0-81e1-0b02ae43a60d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55082703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.55082703
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.752083110
Short name T124
Test name
Test status
Simulation time 477756654 ps
CPU time 0.69 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:42 PM PST 24
Peak memory 182892 kb
Host smart-5e63ead9-2180-43c5-a801-7d5bbafe3bf6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752083110 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_ti
mer_mem_partial_access.752083110
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1604914386
Short name T417
Test name
Test status
Simulation time 420480232 ps
CPU time 1.16 seconds
Started Feb 07 12:50:41 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 182776 kb
Host smart-9442f0af-ce68-4387-83ba-b6d152cd872d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604914386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1604914386
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3437708248
Short name T397
Test name
Test status
Simulation time 828923779 ps
CPU time 1.74 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:46 PM PST 24
Peak memory 192192 kb
Host smart-a8deb020-9958-409a-9add-f7a221541af8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437708248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3437708248
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2781133843
Short name T414
Test name
Test status
Simulation time 504311774 ps
CPU time 1.94 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 197936 kb
Host smart-2b0bf482-f060-4840-896e-ba74942d0c62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781133843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2781133843
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3389534382
Short name T310
Test name
Test status
Simulation time 508033018 ps
CPU time 0.63 seconds
Started Feb 07 12:51:08 PM PST 24
Finished Feb 07 12:51:10 PM PST 24
Peak memory 182936 kb
Host smart-e92917ca-5a39-49cf-bd4e-50b9522320aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389534382 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3389534382
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.18035826
Short name T360
Test name
Test status
Simulation time 534662309 ps
CPU time 0.63 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:13 PM PST 24
Peak memory 182868 kb
Host smart-41ac69a4-6eec-45aa-9abe-be1d35c82191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18035826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.18035826
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3568603649
Short name T13
Test name
Test status
Simulation time 614783563 ps
CPU time 0.64 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:13 PM PST 24
Peak memory 182968 kb
Host smart-aeb86426-845a-4075-bc6e-8131cb78cd62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568603649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3568603649
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2544658684
Short name T343
Test name
Test status
Simulation time 322095164 ps
CPU time 0.92 seconds
Started Feb 07 12:51:16 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 183040 kb
Host smart-e2ba6cc9-aeec-4e92-a7a1-66e4df875f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544658684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2544658684
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.3451611943
Short name T355
Test name
Test status
Simulation time 373980794 ps
CPU time 0.83 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:15 PM PST 24
Peak memory 182944 kb
Host smart-613703bf-e1df-499a-b4b6-fe7df815318e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451611943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.3451611943
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.986195182
Short name T421
Test name
Test status
Simulation time 475141323 ps
CPU time 0.6 seconds
Started Feb 07 12:51:17 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 182868 kb
Host smart-1085e471-5ab4-46b9-a0f8-205b4ef1f89a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986195182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.986195182
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.736294465
Short name T336
Test name
Test status
Simulation time 461012463 ps
CPU time 0.86 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 182912 kb
Host smart-4ca9ffd9-be56-4754-9010-834d90832df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736294465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.736294465
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1705604082
Short name T388
Test name
Test status
Simulation time 368482273 ps
CPU time 0.6 seconds
Started Feb 07 12:51:17 PM PST 24
Finished Feb 07 12:51:18 PM PST 24
Peak memory 182884 kb
Host smart-f676d690-3276-4084-b4b4-3d4e8e0a9b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705604082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1705604082
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.280578913
Short name T426
Test name
Test status
Simulation time 309272151 ps
CPU time 0.65 seconds
Started Feb 07 12:51:15 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 183104 kb
Host smart-36ed05c9-84ac-445a-9f8d-52d48935284e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280578913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.280578913
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4030900151
Short name T84
Test name
Test status
Simulation time 461084065 ps
CPU time 1.22 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 183076 kb
Host smart-f1c3a935-0586-425f-a27a-b9984747bbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030900151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4030900151
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.594002085
Short name T395
Test name
Test status
Simulation time 562909944 ps
CPU time 1 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:50:58 PM PST 24
Peak memory 194096 kb
Host smart-ff286e14-cb85-4b7c-9bda-6092336e3d4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594002085 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.594002085
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3544214112
Short name T396
Test name
Test status
Simulation time 291044216 ps
CPU time 0.73 seconds
Started Feb 07 12:50:42 PM PST 24
Finished Feb 07 12:50:45 PM PST 24
Peak memory 183188 kb
Host smart-fbb06c2c-0ee4-426a-a2b0-e9d0405e2a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544214112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3544214112
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3496430693
Short name T423
Test name
Test status
Simulation time 438194594 ps
CPU time 0.67 seconds
Started Feb 07 12:50:42 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 182968 kb
Host smart-c1675099-35e2-4df4-bc84-afb273c90a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496430693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3496430693
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1038267982
Short name T390
Test name
Test status
Simulation time 2102990309 ps
CPU time 1.85 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:50:59 PM PST 24
Peak memory 194700 kb
Host smart-edaf5bf4-75bb-42aa-892a-84915626e34b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038267982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1038267982
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.283942286
Short name T321
Test name
Test status
Simulation time 679291890 ps
CPU time 1.84 seconds
Started Feb 07 12:50:40 PM PST 24
Finished Feb 07 12:50:44 PM PST 24
Peak memory 197924 kb
Host smart-cc566091-a277-4d9b-a437-0d2a1a4a60a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283942286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.283942286
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.549405335
Short name T331
Test name
Test status
Simulation time 8671684277 ps
CPU time 14.5 seconds
Started Feb 07 12:50:44 PM PST 24
Finished Feb 07 12:50:59 PM PST 24
Peak memory 197008 kb
Host smart-c698ee9a-56c2-4205-8556-7f7ed7155dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549405335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.549405335
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.984899497
Short name T338
Test name
Test status
Simulation time 520500913 ps
CPU time 0.73 seconds
Started Feb 07 12:50:46 PM PST 24
Finished Feb 07 12:50:48 PM PST 24
Peak memory 195148 kb
Host smart-f8d1e1ae-1892-492d-b84c-33b81cf6cb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984899497 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.984899497
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.3640073148
Short name T418
Test name
Test status
Simulation time 290377578 ps
CPU time 0.77 seconds
Started Feb 07 12:51:01 PM PST 24
Finished Feb 07 12:51:03 PM PST 24
Peak memory 183052 kb
Host smart-ea420460-e6cc-428a-8405-af14c222a701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640073148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.3640073148
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.952215591
Short name T337
Test name
Test status
Simulation time 338861192 ps
CPU time 0.64 seconds
Started Feb 07 12:50:46 PM PST 24
Finished Feb 07 12:50:47 PM PST 24
Peak memory 183112 kb
Host smart-ec91f1c0-0572-40c9-84bc-73ef0e721e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952215591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.952215591
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.1685642196
Short name T383
Test name
Test status
Simulation time 1500307572 ps
CPU time 2.09 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:50:59 PM PST 24
Peak memory 192836 kb
Host smart-d8c6efef-6e95-42c4-b9ad-b044ea159c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685642196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.1685642196
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.779318108
Short name T368
Test name
Test status
Simulation time 527894455 ps
CPU time 1.84 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:56 PM PST 24
Peak memory 197628 kb
Host smart-eda482ea-0a8f-4cee-824e-aef148ffe6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779318108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.779318108
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.112525314
Short name T85
Test name
Test status
Simulation time 8299943945 ps
CPU time 2.5 seconds
Started Feb 07 12:50:50 PM PST 24
Finished Feb 07 12:50:53 PM PST 24
Peak memory 196892 kb
Host smart-7769f559-70fc-4a2f-acea-f6657edd3b1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112525314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.112525314
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2724758804
Short name T334
Test name
Test status
Simulation time 328315876 ps
CPU time 1.11 seconds
Started Feb 07 12:50:56 PM PST 24
Finished Feb 07 12:50:58 PM PST 24
Peak memory 195776 kb
Host smart-7881a9e5-5976-4d8d-b4bf-b1aedd10fdd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724758804 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2724758804
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3857834417
Short name T348
Test name
Test status
Simulation time 334233077 ps
CPU time 0.65 seconds
Started Feb 07 12:51:05 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 182996 kb
Host smart-3155ba9a-61bb-47b9-af82-ab87bb2c7ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857834417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3857834417
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.4134195448
Short name T419
Test name
Test status
Simulation time 374163389 ps
CPU time 0.84 seconds
Started Feb 07 12:51:11 PM PST 24
Finished Feb 07 12:51:13 PM PST 24
Peak memory 182828 kb
Host smart-d1fdff6f-2242-4c0a-ae59-58096749ac1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134195448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.4134195448
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3571746758
Short name T6
Test name
Test status
Simulation time 1093926543 ps
CPU time 1.25 seconds
Started Feb 07 12:50:55 PM PST 24
Finished Feb 07 12:50:57 PM PST 24
Peak memory 192696 kb
Host smart-e1c4817c-b3ac-471c-9eeb-17acf8cbd4dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571746758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3571746758
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3984654863
Short name T377
Test name
Test status
Simulation time 449941110 ps
CPU time 1.66 seconds
Started Feb 07 12:50:49 PM PST 24
Finished Feb 07 12:50:52 PM PST 24
Peak memory 197984 kb
Host smart-3ae9f0bd-25f1-4223-8980-608ccf45e692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984654863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3984654863
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.468189159
Short name T30
Test name
Test status
Simulation time 8098425687 ps
CPU time 4.3 seconds
Started Feb 07 12:51:06 PM PST 24
Finished Feb 07 12:51:12 PM PST 24
Peak memory 196908 kb
Host smart-b3aac55f-0e59-471e-a0ef-d64c94a049ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468189159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.468189159
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3152335687
Short name T379
Test name
Test status
Simulation time 553275385 ps
CPU time 0.96 seconds
Started Feb 07 12:51:04 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 195648 kb
Host smart-3b7c2cc8-c321-497c-afc6-f78543cdca93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152335687 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3152335687
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.743955671
Short name T403
Test name
Test status
Simulation time 485486208 ps
CPU time 1.29 seconds
Started Feb 07 12:50:49 PM PST 24
Finished Feb 07 12:50:51 PM PST 24
Peak memory 183116 kb
Host smart-6e3d3c4d-b811-426a-bf3b-33e4f7d7a22c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743955671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.743955671
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.642734878
Short name T27
Test name
Test status
Simulation time 414007573 ps
CPU time 1.1 seconds
Started Feb 07 12:50:53 PM PST 24
Finished Feb 07 12:50:54 PM PST 24
Peak memory 183012 kb
Host smart-7e325a7e-4cf6-4729-8729-da8f0f01ead0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642734878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.642734878
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1637810486
Short name T422
Test name
Test status
Simulation time 1027386130 ps
CPU time 1.09 seconds
Started Feb 07 12:51:01 PM PST 24
Finished Feb 07 12:51:03 PM PST 24
Peak memory 193568 kb
Host smart-f605d6f9-415f-4d8d-87d1-0f1fd18e2cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637810486 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1637810486
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.425890991
Short name T356
Test name
Test status
Simulation time 559700489 ps
CPU time 1.43 seconds
Started Feb 07 12:50:55 PM PST 24
Finished Feb 07 12:50:58 PM PST 24
Peak memory 197872 kb
Host smart-9261f66d-e722-4852-ad11-ddb634a91693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425890991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.425890991
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.706997664
Short name T393
Test name
Test status
Simulation time 348548590 ps
CPU time 1.13 seconds
Started Feb 07 12:50:50 PM PST 24
Finished Feb 07 12:50:52 PM PST 24
Peak memory 194128 kb
Host smart-bcd64f4b-c1eb-4f51-859d-5abe8f9cb110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706997664 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.706997664
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2714065187
Short name T74
Test name
Test status
Simulation time 466842626 ps
CPU time 0.86 seconds
Started Feb 07 12:50:54 PM PST 24
Finished Feb 07 12:50:55 PM PST 24
Peak memory 183020 kb
Host smart-b5dca9f2-4c85-4cd6-9da0-152f92789953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714065187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2714065187
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1465399787
Short name T359
Test name
Test status
Simulation time 446612301 ps
CPU time 1.22 seconds
Started Feb 07 12:51:14 PM PST 24
Finished Feb 07 12:51:16 PM PST 24
Peak memory 183072 kb
Host smart-c588da11-b7a8-46e3-8121-b8ce11709a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465399787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1465399787
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.234597689
Short name T406
Test name
Test status
Simulation time 2073682340 ps
CPU time 2.04 seconds
Started Feb 07 12:50:49 PM PST 24
Finished Feb 07 12:50:52 PM PST 24
Peak memory 191368 kb
Host smart-8d384b00-ca87-4a04-989e-1668282e51f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234597689 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.234597689
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1582187899
Short name T308
Test name
Test status
Simulation time 431505492 ps
CPU time 2.49 seconds
Started Feb 07 12:51:02 PM PST 24
Finished Feb 07 12:51:06 PM PST 24
Peak memory 197984 kb
Host smart-bb02d4d9-bc04-4b3d-b745-469436da9505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582187899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1582187899
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3448663240
Short name T333
Test name
Test status
Simulation time 8135590208 ps
CPU time 12.24 seconds
Started Feb 07 12:50:43 PM PST 24
Finished Feb 07 12:50:57 PM PST 24
Peak memory 196840 kb
Host smart-af106c0d-8d0e-4a5d-8aba-705079d47a34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448663240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3448663240
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.264764983
Short name T47
Test name
Test status
Simulation time 610238308 ps
CPU time 1.01 seconds
Started Feb 07 12:36:54 PM PST 24
Finished Feb 07 12:36:56 PM PST 24
Peak memory 183276 kb
Host smart-763afb36-8bb0-48e5-95d9-b8be6c7008da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264764983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.264764983
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.306680047
Short name T208
Test name
Test status
Simulation time 32884099415 ps
CPU time 51.67 seconds
Started Feb 07 12:37:04 PM PST 24
Finished Feb 07 12:37:56 PM PST 24
Peak memory 183372 kb
Host smart-03324130-69d1-4d21-92cb-7849c6881a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306680047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.306680047
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.2023315285
Short name T131
Test name
Test status
Simulation time 350533580 ps
CPU time 0.78 seconds
Started Feb 07 12:37:21 PM PST 24
Finished Feb 07 12:37:23 PM PST 24
Peak memory 183164 kb
Host smart-1268dc08-943d-42e4-b885-8f1d9faf4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023315285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.2023315285
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1660964635
Short name T292
Test name
Test status
Simulation time 49262850508 ps
CPU time 73.34 seconds
Started Feb 07 12:36:54 PM PST 24
Finished Feb 07 12:38:08 PM PST 24
Peak memory 183548 kb
Host smart-dcf7b9e3-46a4-4fe3-8e6a-2926432d56b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660964635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1660964635
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3126126267
Short name T23
Test name
Test status
Simulation time 17173332180 ps
CPU time 160.19 seconds
Started Feb 07 12:36:48 PM PST 24
Finished Feb 07 12:39:29 PM PST 24
Peak memory 198320 kb
Host smart-2d685b49-cf5d-479e-ac66-4c1a3c6a3fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126126267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3126126267
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_jump.3181757356
Short name T237
Test name
Test status
Simulation time 571134538 ps
CPU time 0.66 seconds
Started Feb 07 12:36:57 PM PST 24
Finished Feb 07 12:36:58 PM PST 24
Peak memory 183280 kb
Host smart-272921e8-f86a-4fdc-8d22-8cfb41bb959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181757356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.3181757356
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3857153874
Short name T157
Test name
Test status
Simulation time 5024345658 ps
CPU time 2.43 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:02 PM PST 24
Peak memory 183316 kb
Host smart-54401dd1-a396-49ac-8078-706c6a29da0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857153874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3857153874
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1050803073
Short name T36
Test name
Test status
Simulation time 3949922910 ps
CPU time 6.67 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:06 PM PST 24
Peak memory 215452 kb
Host smart-a735fe45-ce9f-45e4-b4b2-ebc5b55d5df4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050803073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1050803073
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.52881397
Short name T223
Test name
Test status
Simulation time 611328201 ps
CPU time 0.67 seconds
Started Feb 07 12:36:56 PM PST 24
Finished Feb 07 12:36:58 PM PST 24
Peak memory 183168 kb
Host smart-a3f1bb10-b13c-4892-b6aa-7ed3cf010038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52881397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.52881397
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3430051377
Short name T92
Test name
Test status
Simulation time 312407272682 ps
CPU time 509.54 seconds
Started Feb 07 12:36:53 PM PST 24
Finished Feb 07 12:45:23 PM PST 24
Peak memory 191600 kb
Host smart-c2a7ee15-29c8-4b9d-9c57-ef808b893075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430051377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3430051377
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1355208410
Short name T205
Test name
Test status
Simulation time 204426906626 ps
CPU time 387.12 seconds
Started Feb 07 12:36:51 PM PST 24
Finished Feb 07 12:43:19 PM PST 24
Peak memory 198412 kb
Host smart-92cdbaa0-e7aa-418e-b861-2a043c6d03ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355208410 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1355208410
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1784857929
Short name T19
Test name
Test status
Simulation time 611945760 ps
CPU time 0.75 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:14 PM PST 24
Peak memory 183296 kb
Host smart-fa2e844a-4f98-4fc9-99b2-d291d3bad668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784857929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1784857929
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.3625889662
Short name T230
Test name
Test status
Simulation time 20847952598 ps
CPU time 16.04 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:15 PM PST 24
Peak memory 183412 kb
Host smart-835fd394-ac77-43da-ad2c-70220f5dab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625889662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.3625889662
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1137393344
Short name T46
Test name
Test status
Simulation time 451151622 ps
CPU time 0.89 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:37:09 PM PST 24
Peak memory 183136 kb
Host smart-cb274a5e-3483-4652-9b41-42a28a3113a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137393344 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1137393344
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1720465895
Short name T289
Test name
Test status
Simulation time 134860150320 ps
CPU time 47.48 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:37:58 PM PST 24
Peak memory 183312 kb
Host smart-27571a25-9a03-4045-9dcb-9f88237cd0e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720465895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1720465895
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.3660451218
Short name T202
Test name
Test status
Simulation time 373791837715 ps
CPU time 457.56 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:44:49 PM PST 24
Peak memory 198228 kb
Host smart-4d851c13-020d-4e44-a3f5-62c96f9e0f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660451218 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.3660451218
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.422195240
Short name T113
Test name
Test status
Simulation time 441031226 ps
CPU time 0.6 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:06 PM PST 24
Peak memory 183236 kb
Host smart-1b6cf600-0dba-44d9-9fcb-1323077f9cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422195240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.422195240
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1259650827
Short name T220
Test name
Test status
Simulation time 20184673018 ps
CPU time 33.55 seconds
Started Feb 07 12:37:08 PM PST 24
Finished Feb 07 12:37:42 PM PST 24
Peak memory 183092 kb
Host smart-4c8ae467-518c-4bb5-98ec-57c52194c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259650827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1259650827
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.4153011323
Short name T243
Test name
Test status
Simulation time 557793404 ps
CPU time 0.72 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:00 PM PST 24
Peak memory 183148 kb
Host smart-b2685193-ba52-4330-813e-16e488a82fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153011323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.4153011323
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3518703185
Short name T118
Test name
Test status
Simulation time 112951390942 ps
CPU time 87.3 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:38:39 PM PST 24
Peak memory 183456 kb
Host smart-3397112d-f421-47b0-8f7a-d63b2fea4adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518703185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3518703185
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.357389414
Short name T90
Test name
Test status
Simulation time 94568637850 ps
CPU time 525.21 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:46:04 PM PST 24
Peak memory 198588 kb
Host smart-7553840a-9411-4c71-a06d-781792bdf449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357389414 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.357389414
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.1056084669
Short name T241
Test name
Test status
Simulation time 485403598 ps
CPU time 0.71 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:07 PM PST 24
Peak memory 183336 kb
Host smart-90dd6d98-5d93-4883-98ae-846bee164fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056084669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.1056084669
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1216435065
Short name T24
Test name
Test status
Simulation time 6883879484 ps
CPU time 3.15 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183244 kb
Host smart-56b586fd-589f-4408-bcce-1bb8b6de406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216435065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1216435065
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2038186364
Short name T285
Test name
Test status
Simulation time 484838690 ps
CPU time 0.89 seconds
Started Feb 07 12:37:02 PM PST 24
Finished Feb 07 12:37:04 PM PST 24
Peak memory 183400 kb
Host smart-51964b6d-1047-4b7f-856e-e684bd37148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038186364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2038186364
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.354366059
Short name T262
Test name
Test status
Simulation time 139365987443 ps
CPU time 144.04 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:39:35 PM PST 24
Peak memory 194548 kb
Host smart-5fc76f69-eadf-412d-9908-78418ed19e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354366059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_a
ll.354366059
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1993768711
Short name T91
Test name
Test status
Simulation time 33860502812 ps
CPU time 262.01 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:41:32 PM PST 24
Peak memory 198320 kb
Host smart-609ec34a-b3a1-4c30-bc09-27055408a6fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993768711 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1993768711
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2782297861
Short name T138
Test name
Test status
Simulation time 462741430 ps
CPU time 1.25 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:37:20 PM PST 24
Peak memory 183256 kb
Host smart-03dbf785-c848-42da-a399-d0e43c4d7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782297861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2782297861
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2856899174
Short name T264
Test name
Test status
Simulation time 4597463450 ps
CPU time 8.2 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:18 PM PST 24
Peak memory 183372 kb
Host smart-e5e4aec1-b755-48d2-93ec-0fe759fefd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856899174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2856899174
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3136529145
Short name T259
Test name
Test status
Simulation time 372201973 ps
CPU time 1.09 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:16 PM PST 24
Peak memory 183072 kb
Host smart-6ac4639b-03b9-4aaf-a52b-67760187b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136529145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3136529145
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.2141030153
Short name T88
Test name
Test status
Simulation time 89923664087 ps
CPU time 137.27 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:39:28 PM PST 24
Peak memory 183276 kb
Host smart-44c61144-2d21-485b-84f6-dc54fb333e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141030153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.2141030153
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1453614844
Short name T287
Test name
Test status
Simulation time 382806194 ps
CPU time 0.72 seconds
Started Feb 07 12:37:13 PM PST 24
Finished Feb 07 12:37:15 PM PST 24
Peak memory 183300 kb
Host smart-21b2a162-51fe-4674-9625-d7e33014cdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453614844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1453614844
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2306095998
Short name T280
Test name
Test status
Simulation time 61477701801 ps
CPU time 88.18 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:38:35 PM PST 24
Peak memory 183320 kb
Host smart-2d950f2f-0b48-4ee1-8f77-b3f790e522c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306095998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2306095998
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.136260346
Short name T212
Test name
Test status
Simulation time 562297364 ps
CPU time 0.68 seconds
Started Feb 07 12:37:08 PM PST 24
Finished Feb 07 12:37:09 PM PST 24
Peak memory 183184 kb
Host smart-d7792b29-0c6b-47f9-a1db-ddb7a6c6490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136260346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.136260346
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.2815443420
Short name T300
Test name
Test status
Simulation time 540598483127 ps
CPU time 119.24 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:39:10 PM PST 24
Peak memory 183416 kb
Host smart-36ddba71-0632-4cab-a9e0-0078505e074d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815443420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.2815443420
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1640187136
Short name T43
Test name
Test status
Simulation time 573396461 ps
CPU time 0.71 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:12 PM PST 24
Peak memory 183292 kb
Host smart-0de517af-9486-4aad-b46e-98cbf8b9faa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640187136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1640187136
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1070144474
Short name T121
Test name
Test status
Simulation time 31833959060 ps
CPU time 4.02 seconds
Started Feb 07 12:36:55 PM PST 24
Finished Feb 07 12:37:00 PM PST 24
Peak memory 183356 kb
Host smart-86279931-0cd9-48f9-a6cc-40e7d02999dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070144474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1070144474
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3540006391
Short name T183
Test name
Test status
Simulation time 429295427 ps
CPU time 0.6 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183188 kb
Host smart-c029956d-3c1a-4826-969b-d66976876be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540006391 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3540006391
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3047603897
Short name T239
Test name
Test status
Simulation time 133306921471 ps
CPU time 56.43 seconds
Started Feb 07 12:37:07 PM PST 24
Finished Feb 07 12:38:04 PM PST 24
Peak memory 193668 kb
Host smart-bb171efe-e5aa-4783-b10d-4d23926bb395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047603897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3047603897
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2417757477
Short name T80
Test name
Test status
Simulation time 19193935644 ps
CPU time 142.61 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:39:29 PM PST 24
Peak memory 198280 kb
Host smart-f99c9316-aaa6-4a5b-93df-51fdd23e2365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417757477 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2417757477
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1861511854
Short name T293
Test name
Test status
Simulation time 358944285 ps
CPU time 1.14 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:11 PM PST 24
Peak memory 183288 kb
Host smart-557c3c7f-2665-4861-8e24-d0326abf35a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861511854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1861511854
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1003756198
Short name T185
Test name
Test status
Simulation time 39024745971 ps
CPU time 62.96 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:38:13 PM PST 24
Peak memory 183236 kb
Host smart-bb109b4e-cb51-4557-961c-d3324c958e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003756198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1003756198
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1220105479
Short name T206
Test name
Test status
Simulation time 470386567 ps
CPU time 0.66 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:06 PM PST 24
Peak memory 183136 kb
Host smart-f59e9728-81ee-4c32-ab87-04a1e1ac9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220105479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1220105479
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.1373339456
Short name T117
Test name
Test status
Simulation time 111950434136 ps
CPU time 154.43 seconds
Started Feb 07 12:37:00 PM PST 24
Finished Feb 07 12:39:36 PM PST 24
Peak memory 193604 kb
Host smart-fd175de8-b9b0-41bd-9457-50e0c7f698ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373339456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.1373339456
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.442011060
Short name T77
Test name
Test status
Simulation time 350408275192 ps
CPU time 407.96 seconds
Started Feb 07 12:37:16 PM PST 24
Finished Feb 07 12:44:04 PM PST 24
Peak memory 198440 kb
Host smart-84c86e14-651e-474a-bb52-c1149b1b14d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442011060 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.442011060
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.324325425
Short name T143
Test name
Test status
Simulation time 523593080 ps
CPU time 0.74 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:37:18 PM PST 24
Peak memory 183336 kb
Host smart-dddf2fd5-aa60-4880-9fe8-e8d8ad3aec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324325425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.324325425
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1545344083
Short name T148
Test name
Test status
Simulation time 7739892017 ps
CPU time 3.84 seconds
Started Feb 07 12:37:07 PM PST 24
Finished Feb 07 12:37:12 PM PST 24
Peak memory 183456 kb
Host smart-bab7986a-8bf5-41d7-bea4-18ee26a46f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545344083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1545344083
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3570047181
Short name T235
Test name
Test status
Simulation time 632486549 ps
CPU time 0.6 seconds
Started Feb 07 12:36:56 PM PST 24
Finished Feb 07 12:36:58 PM PST 24
Peak memory 183112 kb
Host smart-5e80bbd7-99c9-42cc-b320-bf401826467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570047181 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3570047181
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.804478478
Short name T274
Test name
Test status
Simulation time 58963157116 ps
CPU time 13.97 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:26 PM PST 24
Peak memory 183320 kb
Host smart-2f547a85-013e-4f2d-887f-19697b6ae4c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804478478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_a
ll.804478478
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.1778628031
Short name T59
Test name
Test status
Simulation time 159130827629 ps
CPU time 428.81 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:44:16 PM PST 24
Peak memory 198288 kb
Host smart-8423a37b-39d8-4095-bcdf-12716dbd07c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778628031 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.1778628031
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4262162957
Short name T201
Test name
Test status
Simulation time 436597021 ps
CPU time 1.26 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:14 PM PST 24
Peak memory 183196 kb
Host smart-ded88e74-3465-4dc7-a327-d447085a9c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262162957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4262162957
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1118918641
Short name T213
Test name
Test status
Simulation time 28745155915 ps
CPU time 19.74 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:32 PM PST 24
Peak memory 183284 kb
Host smart-d6dea90d-e2aa-49b8-8029-15aadb511fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118918641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1118918641
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3353977986
Short name T233
Test name
Test status
Simulation time 412670860 ps
CPU time 1.16 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:14 PM PST 24
Peak memory 183048 kb
Host smart-9bd50ee5-cda5-4403-88ae-f84cd5066698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353977986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3353977986
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.1969247315
Short name T33
Test name
Test status
Simulation time 121221647933 ps
CPU time 45.26 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:51 PM PST 24
Peak memory 193388 kb
Host smart-28f3c58a-cd7c-4742-83a6-d1889b2c32a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969247315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.1969247315
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3411399275
Short name T102
Test name
Test status
Simulation time 94982657945 ps
CPU time 403.69 seconds
Started Feb 07 12:37:20 PM PST 24
Finished Feb 07 12:44:04 PM PST 24
Peak memory 198304 kb
Host smart-dc7fdbfb-d4b8-4424-b850-f6554258cd14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411399275 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3411399275
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.717166837
Short name T166
Test name
Test status
Simulation time 568984126 ps
CPU time 0.65 seconds
Started Feb 07 12:37:26 PM PST 24
Finished Feb 07 12:37:27 PM PST 24
Peak memory 183260 kb
Host smart-5cf3d06a-8701-44b0-9f55-5fc880337e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717166837 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.717166837
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2335099189
Short name T260
Test name
Test status
Simulation time 26654424199 ps
CPU time 37.33 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:37:44 PM PST 24
Peak memory 183320 kb
Host smart-e11ebfb6-60bc-45ca-8f78-0139e5ef452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335099189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2335099189
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2125063804
Short name T136
Test name
Test status
Simulation time 346909137 ps
CPU time 0.96 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:07 PM PST 24
Peak memory 183116 kb
Host smart-323384cc-db9e-46d8-b33e-785dd68f6f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125063804 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2125063804
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.1036312870
Short name T169
Test name
Test status
Simulation time 179126874224 ps
CPU time 297.89 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:42:27 PM PST 24
Peak memory 193364 kb
Host smart-0ea19e6a-3d62-4d01-a3a8-74177b934f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036312870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.1036312870
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.57317768
Short name T109
Test name
Test status
Simulation time 31228210806 ps
CPU time 260.25 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:41:23 PM PST 24
Peak memory 198308 kb
Host smart-202b6e3f-6203-45c8-931b-be2e271a9738
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57317768 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.57317768
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3364935072
Short name T156
Test name
Test status
Simulation time 493785469 ps
CPU time 0.59 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183244 kb
Host smart-a3900660-dea4-4158-b1d9-fc4d23fcf64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364935072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3364935072
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3916017758
Short name T170
Test name
Test status
Simulation time 20031780025 ps
CPU time 13.64 seconds
Started Feb 07 12:36:54 PM PST 24
Finished Feb 07 12:37:09 PM PST 24
Peak memory 183476 kb
Host smart-a1755f5b-ac25-496f-8341-b6fb48750654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916017758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3916017758
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.4172613675
Short name T37
Test name
Test status
Simulation time 7882564435 ps
CPU time 4.04 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:37:06 PM PST 24
Peak memory 215624 kb
Host smart-02c24070-34f0-4623-8424-056ee744e4ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172613675 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.4172613675
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1589052280
Short name T209
Test name
Test status
Simulation time 389526552 ps
CPU time 0.6 seconds
Started Feb 07 12:36:57 PM PST 24
Finished Feb 07 12:36:58 PM PST 24
Peak memory 183280 kb
Host smart-1647a44e-7ff1-46d4-ac06-a0328170c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589052280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1589052280
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.386847206
Short name T87
Test name
Test status
Simulation time 142374094983 ps
CPU time 57.72 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:57 PM PST 24
Peak memory 193568 kb
Host smart-24d38fdc-30ba-4a41-9717-59b3d89fd467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386847206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_al
l.386847206
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2780442038
Short name T278
Test name
Test status
Simulation time 408972964 ps
CPU time 1.11 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183300 kb
Host smart-11adb339-0ebd-4b04-929f-e94ab6c2f79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780442038 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2780442038
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2905812988
Short name T188
Test name
Test status
Simulation time 5597226703 ps
CPU time 2.84 seconds
Started Feb 07 12:37:28 PM PST 24
Finished Feb 07 12:37:31 PM PST 24
Peak memory 183376 kb
Host smart-9273557e-fe5a-4bff-8631-93c13cb07392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905812988 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2905812988
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1320487847
Short name T286
Test name
Test status
Simulation time 422517292 ps
CPU time 0.58 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:10 PM PST 24
Peak memory 183140 kb
Host smart-090bb8b5-163d-49e1-9b9e-07773747546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320487847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1320487847
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.2646919838
Short name T104
Test name
Test status
Simulation time 66710846872 ps
CPU time 392.72 seconds
Started Feb 07 12:37:20 PM PST 24
Finished Feb 07 12:43:54 PM PST 24
Peak memory 198304 kb
Host smart-7dd009c9-e72f-45d8-9bcc-27d07a7f3e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646919838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.2646919838
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3827466154
Short name T231
Test name
Test status
Simulation time 429559671 ps
CPU time 1.08 seconds
Started Feb 07 12:37:25 PM PST 24
Finished Feb 07 12:37:27 PM PST 24
Peak memory 183260 kb
Host smart-71e728f5-85c6-483a-a785-aea890f32141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827466154 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3827466154
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4158268680
Short name T199
Test name
Test status
Simulation time 36189997717 ps
CPU time 25.79 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:37:55 PM PST 24
Peak memory 183340 kb
Host smart-79536fa1-601c-443e-9c2b-aedfc23747a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158268680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4158268680
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3315814253
Short name T181
Test name
Test status
Simulation time 419511194 ps
CPU time 0.6 seconds
Started Feb 07 12:37:13 PM PST 24
Finished Feb 07 12:37:15 PM PST 24
Peak memory 183180 kb
Host smart-b6cc4fac-bfbc-4356-a192-dc62c043046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315814253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3315814253
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1980456446
Short name T101
Test name
Test status
Simulation time 38689712735 ps
CPU time 17.17 seconds
Started Feb 07 12:37:27 PM PST 24
Finished Feb 07 12:37:45 PM PST 24
Peak memory 183380 kb
Host smart-744dd020-f746-459e-b121-20741a80f4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980456446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1980456446
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.1289011267
Short name T217
Test name
Test status
Simulation time 471586322527 ps
CPU time 840.78 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:51:14 PM PST 24
Peak memory 201708 kb
Host smart-7c650382-229f-4b4e-83ef-2291c7de2fe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289011267 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.1289011267
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.1132114520
Short name T160
Test name
Test status
Simulation time 549078404 ps
CPU time 1.31 seconds
Started Feb 07 12:37:07 PM PST 24
Finished Feb 07 12:37:09 PM PST 24
Peak memory 183224 kb
Host smart-e2d033ed-7570-4980-9a59-efb31cc307c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132114520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.1132114520
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2279473775
Short name T135
Test name
Test status
Simulation time 30317736862 ps
CPU time 10.46 seconds
Started Feb 07 12:38:02 PM PST 24
Finished Feb 07 12:38:14 PM PST 24
Peak memory 183056 kb
Host smart-ef5548d0-2a14-4b27-844c-e42fa6753fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279473775 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2279473775
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4239548516
Short name T128
Test name
Test status
Simulation time 629613529 ps
CPU time 0.6 seconds
Started Feb 07 12:37:24 PM PST 24
Finished Feb 07 12:37:25 PM PST 24
Peak memory 183244 kb
Host smart-372f7049-0df5-4eee-8191-321ffb28ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239548516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4239548516
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.2052149449
Short name T219
Test name
Test status
Simulation time 52206979543 ps
CPU time 6.28 seconds
Started Feb 07 12:38:02 PM PST 24
Finished Feb 07 12:38:10 PM PST 24
Peak memory 193800 kb
Host smart-39181894-5921-4d4e-8855-036031d4f74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052149449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.2052149449
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2295424389
Short name T133
Test name
Test status
Simulation time 11024134602 ps
CPU time 89.14 seconds
Started Feb 07 12:38:02 PM PST 24
Finished Feb 07 12:39:33 PM PST 24
Peak memory 197140 kb
Host smart-95118cfe-9255-45e9-834f-31eb5e451d79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295424389 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2295424389
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.2954181132
Short name T152
Test name
Test status
Simulation time 402708037 ps
CPU time 1.12 seconds
Started Feb 07 12:37:08 PM PST 24
Finished Feb 07 12:37:10 PM PST 24
Peak memory 183356 kb
Host smart-633c5a2c-6077-4be0-9c46-353dc6d26ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954181132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.2954181132
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3578282477
Short name T218
Test name
Test status
Simulation time 25275313538 ps
CPU time 10.42 seconds
Started Feb 07 12:38:02 PM PST 24
Finished Feb 07 12:38:14 PM PST 24
Peak memory 183060 kb
Host smart-317eac16-9577-4657-ab76-e5132aeaf2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578282477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3578282477
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2303115402
Short name T151
Test name
Test status
Simulation time 433877790 ps
CPU time 1.2 seconds
Started Feb 07 12:38:02 PM PST 24
Finished Feb 07 12:38:05 PM PST 24
Peak memory 182920 kb
Host smart-c40a2713-85fe-41f7-9c54-0762b7adcbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303115402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2303115402
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1588789104
Short name T107
Test name
Test status
Simulation time 111885053826 ps
CPU time 64.02 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:38:17 PM PST 24
Peak memory 183420 kb
Host smart-57fee783-1349-4198-98f8-7a58c005b0c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588789104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1588789104
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3939154022
Short name T298
Test name
Test status
Simulation time 38872098433 ps
CPU time 379.67 seconds
Started Feb 07 12:37:13 PM PST 24
Finished Feb 07 12:43:34 PM PST 24
Peak memory 198352 kb
Host smart-b721f15e-d543-42e4-a85f-432ffe3b39f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939154022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3939154022
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.2374076043
Short name T108
Test name
Test status
Simulation time 390735241 ps
CPU time 0.87 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:37:19 PM PST 24
Peak memory 183072 kb
Host smart-686ffad7-bad9-442b-b5e5-4cb690e7becd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374076043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.2374076043
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1426741993
Short name T144
Test name
Test status
Simulation time 4453965754 ps
CPU time 7.01 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:19 PM PST 24
Peak memory 183384 kb
Host smart-e1addf97-41dd-434c-a758-26dc7f1c026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426741993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1426741993
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2973638588
Short name T168
Test name
Test status
Simulation time 519054078 ps
CPU time 0.72 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:14 PM PST 24
Peak memory 183180 kb
Host smart-db40fc40-0030-4b9e-a54f-51748bf7353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973638588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2973638588
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2282728938
Short name T110
Test name
Test status
Simulation time 29726848249 ps
CPU time 24.51 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:37:42 PM PST 24
Peak memory 183288 kb
Host smart-516e5256-6fd6-4ac9-962c-5b0f03b855fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282728938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2282728938
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.1448792119
Short name T195
Test name
Test status
Simulation time 111225606732 ps
CPU time 569.89 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:46:43 PM PST 24
Peak memory 199092 kb
Host smart-6d69ae7b-53b4-4625-acd3-cc93945e0ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448792119 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.1448792119
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.1687582569
Short name T244
Test name
Test status
Simulation time 412355194 ps
CPU time 1.07 seconds
Started Feb 07 12:37:22 PM PST 24
Finished Feb 07 12:37:24 PM PST 24
Peak memory 183420 kb
Host smart-22a2c3de-ccee-45ab-8454-b76a2cabbfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687582569 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.1687582569
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.793553996
Short name T177
Test name
Test status
Simulation time 8932388572 ps
CPU time 4.38 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:37:22 PM PST 24
Peak memory 183328 kb
Host smart-3a59aec7-4d3f-43dc-aff4-e266132ef0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793553996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.793553996
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.2969323379
Short name T253
Test name
Test status
Simulation time 426457712 ps
CPU time 1.09 seconds
Started Feb 07 12:37:06 PM PST 24
Finished Feb 07 12:37:08 PM PST 24
Peak memory 183124 kb
Host smart-1ff237f3-4956-4e6e-89c7-c3564dad7211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969323379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.2969323379
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3858897253
Short name T98
Test name
Test status
Simulation time 324181542424 ps
CPU time 230.5 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:41:08 PM PST 24
Peak memory 193632 kb
Host smart-973083ff-baed-49f4-a236-4e0460b6bded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858897253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3858897253
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2275157789
Short name T211
Test name
Test status
Simulation time 572077222 ps
CPU time 0.85 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:37:20 PM PST 24
Peak memory 183276 kb
Host smart-996c1151-ea9b-4bc3-9ba5-3fdba81ece97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275157789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2275157789
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.2903108583
Short name T126
Test name
Test status
Simulation time 6597843442 ps
CPU time 11.16 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:37:29 PM PST 24
Peak memory 183160 kb
Host smart-e89b3192-0999-4c60-beca-bc7f566edd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903108583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.2903108583
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.1835667435
Short name T247
Test name
Test status
Simulation time 473567144 ps
CPU time 0.71 seconds
Started Feb 07 12:37:20 PM PST 24
Finished Feb 07 12:37:21 PM PST 24
Peak memory 183296 kb
Host smart-60848c20-367e-4c8f-8895-1833810ba56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835667435 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.1835667435
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.527035119
Short name T34
Test name
Test status
Simulation time 286889985321 ps
CPU time 210.91 seconds
Started Feb 07 12:37:19 PM PST 24
Finished Feb 07 12:40:50 PM PST 24
Peak memory 183484 kb
Host smart-8796396e-83a5-4f9e-a94d-6f9b8c565564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527035119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_a
ll.527035119
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.800905489
Short name T141
Test name
Test status
Simulation time 228834535716 ps
CPU time 266.15 seconds
Started Feb 07 12:37:30 PM PST 24
Finished Feb 07 12:41:57 PM PST 24
Peak memory 198452 kb
Host smart-e547cca8-53ec-4298-af8f-f9c87c0ac69c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800905489 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.800905489
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.538197099
Short name T189
Test name
Test status
Simulation time 445399029 ps
CPU time 1.24 seconds
Started Feb 07 12:37:35 PM PST 24
Finished Feb 07 12:37:37 PM PST 24
Peak memory 183208 kb
Host smart-7c1934e2-129c-4cb9-b5e1-60cf76096c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538197099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.538197099
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1213463742
Short name T193
Test name
Test status
Simulation time 53670235141 ps
CPU time 20.9 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:37:40 PM PST 24
Peak memory 183404 kb
Host smart-a7c8bd40-0d17-4375-88ee-26d49bf10391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213463742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1213463742
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3233452604
Short name T273
Test name
Test status
Simulation time 473575322 ps
CPU time 1.25 seconds
Started Feb 07 12:37:35 PM PST 24
Finished Feb 07 12:37:37 PM PST 24
Peak memory 183200 kb
Host smart-ee9b0eaf-ad0c-4f1f-915e-fd9418130a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233452604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3233452604
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1394022678
Short name T302
Test name
Test status
Simulation time 169050580581 ps
CPU time 69.46 seconds
Started Feb 07 12:37:17 PM PST 24
Finished Feb 07 12:38:27 PM PST 24
Peak memory 183404 kb
Host smart-053eaee9-85b3-4fa1-b8e5-8ee4138c5453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394022678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1394022678
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1111366326
Short name T257
Test name
Test status
Simulation time 102932272154 ps
CPU time 210.63 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:40:50 PM PST 24
Peak memory 198332 kb
Host smart-dd1a9e39-c30f-40e4-9588-d4061499d832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111366326 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1111366326
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3268461444
Short name T42
Test name
Test status
Simulation time 385248631 ps
CPU time 0.67 seconds
Started Feb 07 12:37:21 PM PST 24
Finished Feb 07 12:37:23 PM PST 24
Peak memory 183376 kb
Host smart-6e905144-42c2-4e93-b84c-5707b6ad0394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268461444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3268461444
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1048735225
Short name T159
Test name
Test status
Simulation time 51240297306 ps
CPU time 19.43 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:37:38 PM PST 24
Peak memory 183400 kb
Host smart-bd8bef05-1df6-4ab8-b4bd-c81e2fe864b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048735225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1048735225
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.833473092
Short name T282
Test name
Test status
Simulation time 489721178 ps
CPU time 0.71 seconds
Started Feb 07 12:37:35 PM PST 24
Finished Feb 07 12:37:37 PM PST 24
Peak memory 183204 kb
Host smart-cf2374eb-b56d-44c8-a5bb-150b40b4766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833473092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.833473092
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.778650128
Short name T45
Test name
Test status
Simulation time 139149992352 ps
CPU time 205.42 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:40:44 PM PST 24
Peak memory 193640 kb
Host smart-f92cda06-9036-4204-91ae-b17345bfe9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778650128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.778650128
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1679685394
Short name T100
Test name
Test status
Simulation time 9353997871 ps
CPU time 75.08 seconds
Started Feb 07 12:37:19 PM PST 24
Finished Feb 07 12:38:35 PM PST 24
Peak memory 198220 kb
Host smart-00781e50-07b0-4169-9c49-021b74654d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679685394 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1679685394
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.974332474
Short name T192
Test name
Test status
Simulation time 596995939 ps
CPU time 1.47 seconds
Started Feb 07 12:37:28 PM PST 24
Finished Feb 07 12:37:30 PM PST 24
Peak memory 183264 kb
Host smart-5259e68f-ae25-422c-ab8f-84bc5a8640da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974332474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.974332474
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3706393445
Short name T127
Test name
Test status
Simulation time 61020196438 ps
CPU time 8.05 seconds
Started Feb 07 12:37:36 PM PST 24
Finished Feb 07 12:37:45 PM PST 24
Peak memory 183352 kb
Host smart-55290893-8fc5-435a-b266-7796c74a228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706393445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3706393445
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2741950560
Short name T215
Test name
Test status
Simulation time 446239219 ps
CPU time 0.67 seconds
Started Feb 07 12:37:36 PM PST 24
Finished Feb 07 12:37:38 PM PST 24
Peak memory 183092 kb
Host smart-1b6f3b3b-1125-448c-9568-6bf708f71001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741950560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2741950560
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2894263600
Short name T96
Test name
Test status
Simulation time 35794064172 ps
CPU time 15.93 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:37:46 PM PST 24
Peak memory 183324 kb
Host smart-9868fa38-8fee-4d70-958e-894c39ddd14a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894263600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2894263600
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.156872694
Short name T276
Test name
Test status
Simulation time 90041955393 ps
CPU time 217.84 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:41:07 PM PST 24
Peak memory 198232 kb
Host smart-1a876441-99e9-4f73-8ab0-b5666b1298d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156872694 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.156872694
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.432369423
Short name T191
Test name
Test status
Simulation time 488242208 ps
CPU time 0.69 seconds
Started Feb 07 12:37:00 PM PST 24
Finished Feb 07 12:37:02 PM PST 24
Peak memory 183244 kb
Host smart-ac88eb58-790d-44cd-aea2-df4f39811355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432369423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.432369423
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2174412927
Short name T130
Test name
Test status
Simulation time 35126784777 ps
CPU time 47.58 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:47 PM PST 24
Peak memory 183544 kb
Host smart-0b2a99f5-710b-48fc-82e3-f38d0a0d6f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174412927 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2174412927
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3448379381
Short name T39
Test name
Test status
Simulation time 8486178814 ps
CPU time 3.97 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:37:07 PM PST 24
Peak memory 215720 kb
Host smart-a278feaf-e38e-4c03-990c-d9a1d9ef03b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448379381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3448379381
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1776408551
Short name T221
Test name
Test status
Simulation time 375316034 ps
CPU time 0.68 seconds
Started Feb 07 12:37:00 PM PST 24
Finished Feb 07 12:37:03 PM PST 24
Peak memory 183236 kb
Host smart-61e14732-476d-4886-adf8-a243b9416094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776408551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1776408551
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.931040067
Short name T187
Test name
Test status
Simulation time 20592897722 ps
CPU time 3.79 seconds
Started Feb 07 12:37:02 PM PST 24
Finished Feb 07 12:37:07 PM PST 24
Peak memory 183452 kb
Host smart-74bbd090-d70f-43d4-869a-835aa17c13f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931040067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.931040067
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.614352367
Short name T25
Test name
Test status
Simulation time 30681890110 ps
CPU time 256.35 seconds
Started Feb 07 12:37:00 PM PST 24
Finished Feb 07 12:41:18 PM PST 24
Peak memory 198264 kb
Host smart-aab4061c-5751-4d23-8ddf-33d6e4c7ab16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614352367 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.614352367
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.597614024
Short name T48
Test name
Test status
Simulation time 404034194 ps
CPU time 0.8 seconds
Started Feb 07 12:37:35 PM PST 24
Finished Feb 07 12:37:36 PM PST 24
Peak memory 183240 kb
Host smart-3c16f2a3-e997-4fe4-82c0-f8192303897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597614024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.597614024
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3772942659
Short name T120
Test name
Test status
Simulation time 12386539058 ps
CPU time 18.02 seconds
Started Feb 07 12:37:30 PM PST 24
Finished Feb 07 12:37:48 PM PST 24
Peak memory 183348 kb
Host smart-43c3a97a-e3ab-4384-a6dc-7722440e5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772942659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3772942659
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1445852795
Short name T173
Test name
Test status
Simulation time 482011434 ps
CPU time 0.69 seconds
Started Feb 07 12:37:30 PM PST 24
Finished Feb 07 12:37:31 PM PST 24
Peak memory 183140 kb
Host smart-bd00e3d5-7a54-4d35-be92-9063f401dd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445852795 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1445852795
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2224536872
Short name T245
Test name
Test status
Simulation time 126466034310 ps
CPU time 48.01 seconds
Started Feb 07 12:37:31 PM PST 24
Finished Feb 07 12:38:19 PM PST 24
Peak memory 183404 kb
Host smart-216524d3-471b-4cfa-be0a-30ef8691b6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224536872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2224536872
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.500395674
Short name T60
Test name
Test status
Simulation time 137663951541 ps
CPU time 586.07 seconds
Started Feb 07 12:37:36 PM PST 24
Finished Feb 07 12:47:23 PM PST 24
Peak memory 198636 kb
Host smart-0defc8cf-71c8-4f50-8b80-29ada7a539a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500395674 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.500395674
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1475166757
Short name T172
Test name
Test status
Simulation time 391124529 ps
CPU time 0.59 seconds
Started Feb 07 12:37:30 PM PST 24
Finished Feb 07 12:37:31 PM PST 24
Peak memory 183228 kb
Host smart-772fd723-dc21-42bb-afad-7085a688ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475166757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1475166757
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.3227579740
Short name T229
Test name
Test status
Simulation time 9120763294 ps
CPU time 4.02 seconds
Started Feb 07 12:37:34 PM PST 24
Finished Feb 07 12:37:38 PM PST 24
Peak memory 183428 kb
Host smart-51da1348-0cac-44c8-88ce-8070d505bbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227579740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.3227579740
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2890713759
Short name T214
Test name
Test status
Simulation time 489027131 ps
CPU time 0.87 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:37:30 PM PST 24
Peak memory 183168 kb
Host smart-03eb0845-b86b-43c7-b28c-d74ea873f318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890713759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2890713759
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3756955992
Short name T115
Test name
Test status
Simulation time 117140920849 ps
CPU time 165.35 seconds
Started Feb 07 12:37:30 PM PST 24
Finished Feb 07 12:40:16 PM PST 24
Peak memory 183408 kb
Host smart-6a38192d-050f-430c-8d9a-d97ad862c84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756955992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3756955992
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.600660430
Short name T93
Test name
Test status
Simulation time 65206053662 ps
CPU time 259.59 seconds
Started Feb 07 12:37:31 PM PST 24
Finished Feb 07 12:41:51 PM PST 24
Peak memory 198388 kb
Host smart-9cd4e042-c260-4658-9fcf-2581f8c3f24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600660430 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.600660430
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.574145120
Short name T288
Test name
Test status
Simulation time 393710681 ps
CPU time 0.67 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:43 PM PST 24
Peak memory 181612 kb
Host smart-beab703f-9e4f-43f7-b7cf-297941c270dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574145120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.574145120
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.2046370030
Short name T140
Test name
Test status
Simulation time 11021574651 ps
CPU time 15.8 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:58 PM PST 24
Peak memory 183320 kb
Host smart-e4f351be-9f72-4171-b41f-52d027046126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046370030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.2046370030
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1472682503
Short name T125
Test name
Test status
Simulation time 424474502 ps
CPU time 1.2 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:44 PM PST 24
Peak memory 181592 kb
Host smart-5a69a661-d0fb-4db2-92d8-0d207b74da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472682503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1472682503
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.632042424
Short name T270
Test name
Test status
Simulation time 85818910830 ps
CPU time 62.51 seconds
Started Feb 07 12:37:45 PM PST 24
Finished Feb 07 12:38:48 PM PST 24
Peak memory 193832 kb
Host smart-25f2e2b1-0aab-4d85-b324-5acf5caf045d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632042424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.632042424
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.778331688
Short name T284
Test name
Test status
Simulation time 85046230949 ps
CPU time 228.47 seconds
Started Feb 07 12:37:43 PM PST 24
Finished Feb 07 12:41:32 PM PST 24
Peak memory 206584 kb
Host smart-6ad7bd36-e4e7-4fe2-ab5f-3577a3a3f60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778331688 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.778331688
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3912799336
Short name T111
Test name
Test status
Simulation time 402544929 ps
CPU time 0.86 seconds
Started Feb 07 12:37:43 PM PST 24
Finished Feb 07 12:37:45 PM PST 24
Peak memory 183228 kb
Host smart-84fd5fc0-2634-4a6c-a112-d0a59e5cf80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912799336 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3912799336
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3565940383
Short name T129
Test name
Test status
Simulation time 9632876314 ps
CPU time 15.58 seconds
Started Feb 07 12:37:44 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183324 kb
Host smart-f953b783-d9a5-4c7c-bc63-64eca481640d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565940383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3565940383
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.1627121516
Short name T227
Test name
Test status
Simulation time 373557065 ps
CPU time 0.68 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:44 PM PST 24
Peak memory 183160 kb
Host smart-07ec4d86-07d7-4aff-895d-ab939d5115eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627121516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.1627121516
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.209758349
Short name T234
Test name
Test status
Simulation time 140696370912 ps
CPU time 108.65 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:39:32 PM PST 24
Peak memory 195044 kb
Host smart-e64036a5-287c-464e-8932-110b59488aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209758349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.209758349
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3067987786
Short name T149
Test name
Test status
Simulation time 534879267 ps
CPU time 1.23 seconds
Started Feb 07 12:37:41 PM PST 24
Finished Feb 07 12:37:43 PM PST 24
Peak memory 183252 kb
Host smart-e0b373d8-d7de-4763-858e-1eb245e0b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067987786 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3067987786
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3711237153
Short name T301
Test name
Test status
Simulation time 7057418518 ps
CPU time 10.97 seconds
Started Feb 07 12:37:40 PM PST 24
Finished Feb 07 12:37:52 PM PST 24
Peak memory 183272 kb
Host smart-06d78aab-fa8a-414a-b0f0-73108dd53ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711237153 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3711237153
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2678558631
Short name T236
Test name
Test status
Simulation time 448288888 ps
CPU time 0.56 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:43 PM PST 24
Peak memory 183112 kb
Host smart-ecba1250-25df-415c-aab8-059277c1881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678558631 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2678558631
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.995284465
Short name T258
Test name
Test status
Simulation time 415426376296 ps
CPU time 149.36 seconds
Started Feb 07 12:37:40 PM PST 24
Finished Feb 07 12:40:11 PM PST 24
Peak memory 193704 kb
Host smart-28ae5fdc-ced5-4a41-b8ff-290e05d5c236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995284465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.995284465
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.1201137768
Short name T222
Test name
Test status
Simulation time 912658964590 ps
CPU time 495.5 seconds
Started Feb 07 12:37:40 PM PST 24
Finished Feb 07 12:45:57 PM PST 24
Peak memory 198496 kb
Host smart-9abb2fac-a220-4174-bd91-3f3f3bf603fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201137768 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.1201137768
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.3587855813
Short name T263
Test name
Test status
Simulation time 640339836 ps
CPU time 0.63 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183156 kb
Host smart-920601d8-77d4-4132-9fab-0076543288dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587855813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.3587855813
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2915995504
Short name T158
Test name
Test status
Simulation time 38292563268 ps
CPU time 16.73 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:15 PM PST 24
Peak memory 183396 kb
Host smart-ef5a5eae-7fa6-4a18-97a4-4edf08ab977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915995504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2915995504
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3091295691
Short name T134
Test name
Test status
Simulation time 513554059 ps
CPU time 1.11 seconds
Started Feb 07 12:37:42 PM PST 24
Finished Feb 07 12:37:44 PM PST 24
Peak memory 183252 kb
Host smart-f3773ccd-27de-43d1-be08-fea15aa18c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091295691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3091295691
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.1249480507
Short name T190
Test name
Test status
Simulation time 54702507771 ps
CPU time 12.25 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:11 PM PST 24
Peak memory 193580 kb
Host smart-a594658c-be85-4a23-bbe1-8f761cf5f2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249480507 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.1249480507
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2825160521
Short name T105
Test name
Test status
Simulation time 77704442354 ps
CPU time 239.56 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:41:58 PM PST 24
Peak memory 198376 kb
Host smart-7950249e-dcc6-4d68-a77a-0f9d36f3a53c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825160521 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2825160521
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2292054423
Short name T174
Test name
Test status
Simulation time 591714512 ps
CPU time 0.71 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:37:59 PM PST 24
Peak memory 183200 kb
Host smart-a00a6427-b63b-4b76-a4ec-a7923719cd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292054423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2292054423
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2632096855
Short name T252
Test name
Test status
Simulation time 56164951001 ps
CPU time 21.39 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:20 PM PST 24
Peak memory 183284 kb
Host smart-4a373ad6-3ac7-4b7b-ab6a-32df1ef9c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632096855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2632096855
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.32398808
Short name T251
Test name
Test status
Simulation time 401319217 ps
CPU time 0.65 seconds
Started Feb 07 12:37:53 PM PST 24
Finished Feb 07 12:37:56 PM PST 24
Peak memory 183136 kb
Host smart-792e27bb-a3db-43f4-a80c-31e0297ac205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32398808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.32398808
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2743367262
Short name T97
Test name
Test status
Simulation time 88411992957 ps
CPU time 64.33 seconds
Started Feb 07 12:37:55 PM PST 24
Finished Feb 07 12:39:02 PM PST 24
Peak memory 193700 kb
Host smart-811d2ac1-3afc-45e3-a15a-f7c010e581d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743367262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2743367262
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3903968008
Short name T114
Test name
Test status
Simulation time 468157875708 ps
CPU time 417.91 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:44:57 PM PST 24
Peak memory 198476 kb
Host smart-ac387040-0fd0-4c34-ab18-abd6c3674bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903968008 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3903968008
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.26231567
Short name T196
Test name
Test status
Simulation time 576459730 ps
CPU time 0.97 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:38:02 PM PST 24
Peak memory 183280 kb
Host smart-c3080595-063b-4c94-86b1-69721ecd0889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26231567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.26231567
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.952730448
Short name T299
Test name
Test status
Simulation time 16825079124 ps
CPU time 5.49 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:38:07 PM PST 24
Peak memory 183368 kb
Host smart-442f8609-a867-457d-9699-eaffd28af5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952730448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.952730448
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3670372873
Short name T167
Test name
Test status
Simulation time 533980805 ps
CPU time 0.82 seconds
Started Feb 07 12:37:55 PM PST 24
Finished Feb 07 12:37:57 PM PST 24
Peak memory 183232 kb
Host smart-a373de96-a559-4ca6-8563-769f32bf07fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670372873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3670372873
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1024461227
Short name T164
Test name
Test status
Simulation time 68932716365 ps
CPU time 109.64 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:39:48 PM PST 24
Peak memory 183360 kb
Host smart-586204bd-12b2-4050-92ea-1eeef3f9920d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024461227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1024461227
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.959030039
Short name T58
Test name
Test status
Simulation time 105664953641 ps
CPU time 180.28 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:40:59 PM PST 24
Peak memory 198224 kb
Host smart-b0715659-e1a9-4d75-90e4-d427fb8f30e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959030039 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.959030039
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.978774384
Short name T224
Test name
Test status
Simulation time 568802924 ps
CPU time 0.59 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183284 kb
Host smart-752fa60b-5229-442e-988d-100e028bc219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978774384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.978774384
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.1023243718
Short name T132
Test name
Test status
Simulation time 59103422067 ps
CPU time 68.2 seconds
Started Feb 07 12:38:01 PM PST 24
Finished Feb 07 12:39:10 PM PST 24
Peak memory 183500 kb
Host smart-1ae2e787-90e0-41d9-9a79-19f3fab2d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023243718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.1023243718
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.1624200960
Short name T35
Test name
Test status
Simulation time 443409540 ps
CPU time 0.78 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:38:03 PM PST 24
Peak memory 182240 kb
Host smart-4076d9aa-594d-4415-ab53-47700280890c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624200960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.1624200960
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.1145094566
Short name T116
Test name
Test status
Simulation time 89463725735 ps
CPU time 23.95 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:23 PM PST 24
Peak memory 193528 kb
Host smart-992db9ca-957f-4a6f-9373-e3adc7e5118e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145094566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.1145094566
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.4079719300
Short name T81
Test name
Test status
Simulation time 139735590767 ps
CPU time 239.73 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:41:58 PM PST 24
Peak memory 198312 kb
Host smart-cc5f854e-5f1c-497d-891a-919b31292c5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079719300 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.4079719300
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2822575222
Short name T41
Test name
Test status
Simulation time 429637748 ps
CPU time 0.62 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183240 kb
Host smart-56a9ca56-1a65-4734-a712-737da5dde46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822575222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2822575222
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1181907036
Short name T153
Test name
Test status
Simulation time 8711944709 ps
CPU time 14.55 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:38:13 PM PST 24
Peak memory 183288 kb
Host smart-d4187451-a33b-4b45-a41a-222be013e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181907036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1181907036
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.587014021
Short name T163
Test name
Test status
Simulation time 592735102 ps
CPU time 1.35 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183124 kb
Host smart-5869b492-6c69-4d57-a088-8bbbbb0c9dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587014021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.587014021
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.632932076
Short name T256
Test name
Test status
Simulation time 76520608482 ps
CPU time 165.77 seconds
Started Feb 07 12:38:01 PM PST 24
Finished Feb 07 12:40:48 PM PST 24
Peak memory 206380 kb
Host smart-b6cbdc60-3346-41bc-9c3a-a760ebede246
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632932076 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.632932076
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1341169951
Short name T290
Test name
Test status
Simulation time 448332148 ps
CPU time 0.65 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:00 PM PST 24
Peak memory 183348 kb
Host smart-ea81fc0d-01fa-461d-b3f7-c9b369211127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341169951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1341169951
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3739740135
Short name T194
Test name
Test status
Simulation time 29215716409 ps
CPU time 45.91 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:37:48 PM PST 24
Peak memory 183364 kb
Host smart-f988074f-d528-4df5-931d-94059a5f9203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739740135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3739740135
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4033142923
Short name T38
Test name
Test status
Simulation time 4095016852 ps
CPU time 3.04 seconds
Started Feb 07 12:37:03 PM PST 24
Finished Feb 07 12:37:07 PM PST 24
Peak memory 215356 kb
Host smart-1db8a469-2772-4676-b578-e022b60e380c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033142923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4033142923
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3423859539
Short name T150
Test name
Test status
Simulation time 593619030 ps
CPU time 1.3 seconds
Started Feb 07 12:37:02 PM PST 24
Finished Feb 07 12:37:05 PM PST 24
Peak memory 183220 kb
Host smart-8b63c70b-1691-4477-a026-8e70dd253eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423859539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3423859539
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2728143421
Short name T255
Test name
Test status
Simulation time 5537736483 ps
CPU time 8.55 seconds
Started Feb 07 12:37:04 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183500 kb
Host smart-6f22ba99-d45c-48c6-ba15-9a3f11fa293f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728143421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2728143421
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.4247241753
Short name T76
Test name
Test status
Simulation time 127791184942 ps
CPU time 442.02 seconds
Started Feb 07 12:37:03 PM PST 24
Finished Feb 07 12:44:26 PM PST 24
Peak memory 206560 kb
Host smart-4d229b81-fd4d-4f18-914d-b5c0379403cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247241753 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.4247241753
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1672734906
Short name T197
Test name
Test status
Simulation time 481852952 ps
CPU time 1.25 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183112 kb
Host smart-2c22cf70-1312-414c-a2d9-a99d775b1b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672734906 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1672734906
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4247421762
Short name T137
Test name
Test status
Simulation time 11314546690 ps
CPU time 14.92 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:14 PM PST 24
Peak memory 183472 kb
Host smart-b52924ed-a10d-456e-a796-89da7f5a44a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247421762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4247421762
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.993851015
Short name T226
Test name
Test status
Simulation time 501098811 ps
CPU time 0.73 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183128 kb
Host smart-e55e65a9-ed76-436e-aeea-0da0707b08ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993851015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.993851015
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.1002545385
Short name T198
Test name
Test status
Simulation time 275039948796 ps
CPU time 1594.73 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 01:04:35 PM PST 24
Peak memory 211264 kb
Host smart-cb635ca5-743a-4ae6-95c4-86bbc046acb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002545385 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.1002545385
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2592135366
Short name T296
Test name
Test status
Simulation time 529885102 ps
CPU time 0.64 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:38:01 PM PST 24
Peak memory 183228 kb
Host smart-e0c88401-a7ed-4e50-be9c-cc4adca9b5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592135366 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2592135366
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.881739282
Short name T269
Test name
Test status
Simulation time 24686532934 ps
CPU time 36.42 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:38:38 PM PST 24
Peak memory 183468 kb
Host smart-173a9a87-8cf3-4ff2-a194-7433a7facd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881739282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.881739282
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2327438704
Short name T21
Test name
Test status
Simulation time 509860211 ps
CPU time 1.19 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183276 kb
Host smart-c549be5d-53ae-42f4-8425-9560fb43d7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327438704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2327438704
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2250496751
Short name T279
Test name
Test status
Simulation time 105471343721 ps
CPU time 145.56 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:40:24 PM PST 24
Peak memory 183472 kb
Host smart-053c0db0-7a8f-458f-987e-01cc960cf9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250496751 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2250496751
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.627760596
Short name T119
Test name
Test status
Simulation time 93396008128 ps
CPU time 97.74 seconds
Started Feb 07 12:37:55 PM PST 24
Finished Feb 07 12:39:34 PM PST 24
Peak memory 198320 kb
Host smart-69fbd8d7-c813-438a-8e6e-4c6489e31a8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627760596 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.627760596
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.520387661
Short name T271
Test name
Test status
Simulation time 579837895 ps
CPU time 1.5 seconds
Started Feb 07 12:37:53 PM PST 24
Finished Feb 07 12:37:57 PM PST 24
Peak memory 183280 kb
Host smart-cafbcf3d-b85d-44f7-b196-b547c0a98dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520387661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.520387661
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1530652228
Short name T139
Test name
Test status
Simulation time 48401955997 ps
CPU time 15.26 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:15 PM PST 24
Peak memory 183348 kb
Host smart-61a37f78-0802-418f-a898-05dcf4ea36b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530652228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1530652228
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.3401478627
Short name T249
Test name
Test status
Simulation time 476652219 ps
CPU time 0.69 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183276 kb
Host smart-ee3fcd7c-ff85-48d1-b2a7-3813986e5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401478627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.3401478627
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3199917917
Short name T162
Test name
Test status
Simulation time 590836283 ps
CPU time 1.51 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:38:03 PM PST 24
Peak memory 183280 kb
Host smart-256012dd-250c-40a1-82b8-50ea055e24c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199917917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3199917917
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3550643958
Short name T155
Test name
Test status
Simulation time 32199900323 ps
CPU time 50.37 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:38:52 PM PST 24
Peak memory 183376 kb
Host smart-8f7d200e-3d3d-4475-94d1-73c2641ee504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550643958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3550643958
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2832953132
Short name T216
Test name
Test status
Simulation time 529243951 ps
CPU time 0.75 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183236 kb
Host smart-5469a833-4180-49a4-8ad8-9ec590a49afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832953132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2832953132
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4180977985
Short name T176
Test name
Test status
Simulation time 71981437178 ps
CPU time 59.2 seconds
Started Feb 07 12:37:56 PM PST 24
Finished Feb 07 12:38:58 PM PST 24
Peak memory 183320 kb
Host smart-34aebecd-8509-4b52-a8e7-91a9d6dd95c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180977985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4180977985
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.457768118
Short name T182
Test name
Test status
Simulation time 27354514008 ps
CPU time 218.61 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:41:41 PM PST 24
Peak memory 198412 kb
Host smart-f736de13-61e5-4a06-8b0b-a946ca30e7c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457768118 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.457768118
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1058833241
Short name T31
Test name
Test status
Simulation time 526886262 ps
CPU time 1.33 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183352 kb
Host smart-a596e903-3a1b-41c9-b95e-0615ee971982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058833241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1058833241
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1740685024
Short name T18
Test name
Test status
Simulation time 7100980976 ps
CPU time 12.29 seconds
Started Feb 07 12:37:59 PM PST 24
Finished Feb 07 12:38:12 PM PST 24
Peak memory 183364 kb
Host smart-816d85c2-2fd3-42fc-a87a-fb1237b0ad61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740685024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1740685024
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.366134792
Short name T266
Test name
Test status
Simulation time 471227920 ps
CPU time 1.2 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:38:03 PM PST 24
Peak memory 183272 kb
Host smart-53535b7b-6fa9-4fe6-bca5-6afc73c97035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366134792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.366134792
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.476927654
Short name T179
Test name
Test status
Simulation time 448878374573 ps
CPU time 609.22 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:48:11 PM PST 24
Peak memory 193268 kb
Host smart-8c7cb7cf-75f4-49c6-bbbe-f9a3d9ebb6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476927654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.476927654
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.2784444090
Short name T204
Test name
Test status
Simulation time 363893333756 ps
CPU time 739.21 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:50:21 PM PST 24
Peak memory 199492 kb
Host smart-3e9367e4-6684-4149-a49b-e119ac7f689c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784444090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.2784444090
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2394351071
Short name T103
Test name
Test status
Simulation time 359375349 ps
CPU time 1.07 seconds
Started Feb 07 12:37:58 PM PST 24
Finished Feb 07 12:38:00 PM PST 24
Peak memory 183376 kb
Host smart-1e066813-afaf-4b7b-a242-98c1ac14dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394351071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2394351071
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.683488045
Short name T275
Test name
Test status
Simulation time 9474345256 ps
CPU time 4.16 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:38:03 PM PST 24
Peak memory 183272 kb
Host smart-d4d853df-0389-4e0c-8d5e-377f5ba2111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683488045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.683488045
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3789930182
Short name T210
Test name
Test status
Simulation time 333586456 ps
CPU time 1.16 seconds
Started Feb 07 12:38:00 PM PST 24
Finished Feb 07 12:38:03 PM PST 24
Peak memory 183040 kb
Host smart-63a9939a-71a1-4de1-91a5-114da91d50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789930182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3789930182
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.2309465734
Short name T267
Test name
Test status
Simulation time 116050610924 ps
CPU time 149.55 seconds
Started Feb 07 12:37:57 PM PST 24
Finished Feb 07 12:40:28 PM PST 24
Peak memory 183276 kb
Host smart-d5878a8b-4af1-4cea-9c85-d131bda8903d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309465734 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.2309465734
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2609404791
Short name T99
Test name
Test status
Simulation time 488781520 ps
CPU time 0.69 seconds
Started Feb 07 12:38:16 PM PST 24
Finished Feb 07 12:38:17 PM PST 24
Peak memory 183272 kb
Host smart-1271258c-7655-48bb-9763-0c88999a16e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609404791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2609404791
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1436009843
Short name T20
Test name
Test status
Simulation time 16272467700 ps
CPU time 13.53 seconds
Started Feb 07 12:38:07 PM PST 24
Finished Feb 07 12:38:24 PM PST 24
Peak memory 183360 kb
Host smart-f6b58a0d-8256-4225-818b-2f4bbc89b8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436009843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1436009843
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.994356543
Short name T200
Test name
Test status
Simulation time 469850500 ps
CPU time 0.74 seconds
Started Feb 07 12:38:15 PM PST 24
Finished Feb 07 12:38:17 PM PST 24
Peak memory 183204 kb
Host smart-2eaccc29-7c93-4f49-be0d-b0db7e282a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994356543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.994356543
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2974944081
Short name T294
Test name
Test status
Simulation time 109111207821 ps
CPU time 83.39 seconds
Started Feb 07 12:38:07 PM PST 24
Finished Feb 07 12:39:34 PM PST 24
Peak memory 183416 kb
Host smart-7906c1d7-9c0a-4020-808f-9faf475f6f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974944081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2974944081
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.735400384
Short name T246
Test name
Test status
Simulation time 13829978206 ps
CPU time 126.94 seconds
Started Feb 07 12:38:15 PM PST 24
Finished Feb 07 12:40:23 PM PST 24
Peak memory 198228 kb
Host smart-621a7ab8-b1ad-4a87-a0d8-dd40de20a276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735400384 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.735400384
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.720926857
Short name T238
Test name
Test status
Simulation time 459277744 ps
CPU time 0.89 seconds
Started Feb 07 12:38:15 PM PST 24
Finished Feb 07 12:38:17 PM PST 24
Peak memory 183420 kb
Host smart-b2ff5168-5c53-4365-bef9-4846464fe26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720926857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.720926857
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1951596390
Short name T248
Test name
Test status
Simulation time 18933236494 ps
CPU time 27.81 seconds
Started Feb 07 12:38:14 PM PST 24
Finished Feb 07 12:38:43 PM PST 24
Peak memory 183348 kb
Host smart-104c955e-5cc3-41e6-a6e8-4b6ab1d3b303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951596390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1951596390
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.59133677
Short name T297
Test name
Test status
Simulation time 362159124 ps
CPU time 0.68 seconds
Started Feb 07 12:38:13 PM PST 24
Finished Feb 07 12:38:15 PM PST 24
Peak memory 183284 kb
Host smart-98e62e78-8036-4c06-938f-9fc50f46e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59133677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.59133677
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2844236357
Short name T268
Test name
Test status
Simulation time 47547574854 ps
CPU time 20.11 seconds
Started Feb 07 12:38:08 PM PST 24
Finished Feb 07 12:38:31 PM PST 24
Peak memory 183376 kb
Host smart-774e9a1c-fdec-4007-a584-c76387c60ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844236357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2844236357
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2911890230
Short name T165
Test name
Test status
Simulation time 83686132803 ps
CPU time 673.31 seconds
Started Feb 07 12:38:10 PM PST 24
Finished Feb 07 12:49:24 PM PST 24
Peak memory 199616 kb
Host smart-c6848dc7-3064-44c8-934f-1dca29d4e9b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911890230 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2911890230
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2942245823
Short name T232
Test name
Test status
Simulation time 359516862 ps
CPU time 0.89 seconds
Started Feb 07 12:38:08 PM PST 24
Finished Feb 07 12:38:11 PM PST 24
Peak memory 183204 kb
Host smart-4ec95c1a-4bfc-4f99-9546-50cd33256fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942245823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2942245823
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.4119196007
Short name T265
Test name
Test status
Simulation time 17428573492 ps
CPU time 6.38 seconds
Started Feb 07 12:38:12 PM PST 24
Finished Feb 07 12:38:21 PM PST 24
Peak memory 183324 kb
Host smart-f39963b4-6eb8-4471-acb1-92777d656aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119196007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.4119196007
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2349460080
Short name T147
Test name
Test status
Simulation time 377291167 ps
CPU time 1.12 seconds
Started Feb 07 12:38:09 PM PST 24
Finished Feb 07 12:38:12 PM PST 24
Peak memory 183112 kb
Host smart-338ad930-3edd-43ff-be6b-7af0fee30380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349460080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2349460080
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2814418792
Short name T295
Test name
Test status
Simulation time 622858562801 ps
CPU time 988.78 seconds
Started Feb 07 12:38:07 PM PST 24
Finished Feb 07 12:54:39 PM PST 24
Peak memory 183308 kb
Host smart-81f0fee6-b8e2-4881-a30d-ae86369d1cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814418792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2814418792
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.555761759
Short name T112
Test name
Test status
Simulation time 460283101 ps
CPU time 0.69 seconds
Started Feb 07 12:38:17 PM PST 24
Finished Feb 07 12:38:19 PM PST 24
Peak memory 183184 kb
Host smart-52263b90-0251-4295-88d2-44f27f7f7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555761759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.555761759
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.942255539
Short name T277
Test name
Test status
Simulation time 11143100366 ps
CPU time 8.84 seconds
Started Feb 07 12:38:10 PM PST 24
Finished Feb 07 12:38:20 PM PST 24
Peak memory 183320 kb
Host smart-e85687dc-17db-4401-87a0-ff625e49a9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942255539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.942255539
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3429815613
Short name T154
Test name
Test status
Simulation time 454974776 ps
CPU time 0.72 seconds
Started Feb 07 12:38:13 PM PST 24
Finished Feb 07 12:38:15 PM PST 24
Peak memory 183176 kb
Host smart-ca1a159a-cd7f-4172-a0fb-0839ac76c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429815613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3429815613
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3890220015
Short name T145
Test name
Test status
Simulation time 276519329502 ps
CPU time 78.05 seconds
Started Feb 07 12:38:10 PM PST 24
Finished Feb 07 12:39:30 PM PST 24
Peak memory 183408 kb
Host smart-b550907d-7946-4458-a3a4-f915e4914117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890220015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3890220015
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.578889702
Short name T78
Test name
Test status
Simulation time 150973976513 ps
CPU time 203.34 seconds
Started Feb 07 12:38:17 PM PST 24
Finished Feb 07 12:41:41 PM PST 24
Peak memory 198204 kb
Host smart-73d823f3-d104-492c-9cb0-6b78c0f03c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578889702 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.578889702
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2932027440
Short name T57
Test name
Test status
Simulation time 481912403 ps
CPU time 0.93 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:11 PM PST 24
Peak memory 183288 kb
Host smart-aec46da9-9e57-45c5-a15b-8521bab12757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932027440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2932027440
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.944128178
Short name T283
Test name
Test status
Simulation time 13596887805 ps
CPU time 19.78 seconds
Started Feb 07 12:36:58 PM PST 24
Finished Feb 07 12:37:24 PM PST 24
Peak memory 183352 kb
Host smart-72015c3b-7b48-4114-abd2-e4d3c1eed377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944128178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.944128178
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3512655253
Short name T171
Test name
Test status
Simulation time 575739591 ps
CPU time 1.46 seconds
Started Feb 07 12:37:03 PM PST 24
Finished Feb 07 12:37:05 PM PST 24
Peak memory 183220 kb
Host smart-a30df1e1-049d-4f6d-96c8-459fb4d47de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512655253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3512655253
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3528520862
Short name T254
Test name
Test status
Simulation time 105973190390 ps
CPU time 44.19 seconds
Started Feb 07 12:37:09 PM PST 24
Finished Feb 07 12:37:54 PM PST 24
Peak memory 183276 kb
Host smart-c58723c8-40e2-4955-9968-b3ce48aaf8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528520862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3528520862
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.2544484975
Short name T95
Test name
Test status
Simulation time 585172000649 ps
CPU time 324.4 seconds
Started Feb 07 12:37:10 PM PST 24
Finished Feb 07 12:42:35 PM PST 24
Peak memory 198344 kb
Host smart-23aff228-fb40-4289-92c4-36905768ae79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544484975 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.2544484975
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3659378409
Short name T261
Test name
Test status
Simulation time 504888741 ps
CPU time 0.69 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:37:03 PM PST 24
Peak memory 183272 kb
Host smart-9fbc7efa-3fab-4bbb-9b92-1f5bc8328ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659378409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3659378409
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4040469091
Short name T122
Test name
Test status
Simulation time 38238283427 ps
CPU time 13.27 seconds
Started Feb 07 12:37:12 PM PST 24
Finished Feb 07 12:37:26 PM PST 24
Peak memory 183288 kb
Host smart-64d88c20-ea84-49be-aa39-3265c4a7c2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040469091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4040469091
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2738321698
Short name T44
Test name
Test status
Simulation time 376422858 ps
CPU time 0.63 seconds
Started Feb 07 12:36:57 PM PST 24
Finished Feb 07 12:36:59 PM PST 24
Peak memory 183288 kb
Host smart-1ae0413c-80a1-4cd6-9588-1e4935042429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738321698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2738321698
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2274489827
Short name T180
Test name
Test status
Simulation time 35128451662 ps
CPU time 267.07 seconds
Started Feb 07 12:37:07 PM PST 24
Finished Feb 07 12:41:35 PM PST 24
Peak memory 198388 kb
Host smart-21779ff0-5da0-492d-8b9d-b83a2c0ffc2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274489827 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2274489827
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.859392845
Short name T184
Test name
Test status
Simulation time 455347696 ps
CPU time 0.92 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183292 kb
Host smart-3a36564a-3cf1-41c1-a4fd-c88f24a33809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859392845 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.859392845
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2425734755
Short name T250
Test name
Test status
Simulation time 34502673296 ps
CPU time 11.54 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:23 PM PST 24
Peak memory 183288 kb
Host smart-685704e8-7673-49c6-afe1-4268cf8819f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425734755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2425734755
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2088490076
Short name T281
Test name
Test status
Simulation time 488046970 ps
CPU time 0.84 seconds
Started Feb 07 12:37:20 PM PST 24
Finished Feb 07 12:37:22 PM PST 24
Peak memory 183268 kb
Host smart-18fb6bd7-7442-4de3-bab7-febb8aee0cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088490076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2088490076
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.553507634
Short name T225
Test name
Test status
Simulation time 190331252428 ps
CPU time 42.04 seconds
Started Feb 07 12:37:18 PM PST 24
Finished Feb 07 12:38:01 PM PST 24
Peak memory 183380 kb
Host smart-1df6adaa-6d6a-4d1a-96e7-7be903b9c912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553507634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_al
l.553507634
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.106087698
Short name T52
Test name
Test status
Simulation time 177326634617 ps
CPU time 377.13 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:43:19 PM PST 24
Peak memory 198400 kb
Host smart-fa7d15bc-93d6-43fd-9321-e59e17cb7845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106087698 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.106087698
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1224628957
Short name T161
Test name
Test status
Simulation time 416939901 ps
CPU time 1.19 seconds
Started Feb 07 12:37:35 PM PST 24
Finished Feb 07 12:37:36 PM PST 24
Peak memory 183272 kb
Host smart-1c0a18bd-2532-4f43-b5e7-bebac8670bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224628957 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1224628957
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.4170167885
Short name T175
Test name
Test status
Simulation time 23343997521 ps
CPU time 17.95 seconds
Started Feb 07 12:37:05 PM PST 24
Finished Feb 07 12:37:24 PM PST 24
Peak memory 183324 kb
Host smart-4e7b50f5-b514-4d11-9302-6ed82c1e8444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170167885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.4170167885
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1579276541
Short name T146
Test name
Test status
Simulation time 463807455 ps
CPU time 0.7 seconds
Started Feb 07 12:37:11 PM PST 24
Finished Feb 07 12:37:13 PM PST 24
Peak memory 183088 kb
Host smart-0ac3eeca-fc3a-43c9-b24e-b7e482384197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579276541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1579276541
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1935246793
Short name T207
Test name
Test status
Simulation time 220588302550 ps
CPU time 89.17 seconds
Started Feb 07 12:37:29 PM PST 24
Finished Feb 07 12:38:58 PM PST 24
Peak memory 183380 kb
Host smart-1bfbcab0-61a4-4c82-9289-eedee489de89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935246793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1935246793
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.535753768
Short name T228
Test name
Test status
Simulation time 118778899086 ps
CPU time 242.52 seconds
Started Feb 07 12:36:52 PM PST 24
Finished Feb 07 12:40:56 PM PST 24
Peak memory 198296 kb
Host smart-e1688787-b942-457c-88be-ad306a874349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535753768 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.535753768
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1972998023
Short name T178
Test name
Test status
Simulation time 462855423 ps
CPU time 1.04 seconds
Started Feb 07 12:36:44 PM PST 24
Finished Feb 07 12:36:47 PM PST 24
Peak memory 183284 kb
Host smart-fc15a32f-7a29-435f-8795-41004c986e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972998023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1972998023
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3012855690
Short name T291
Test name
Test status
Simulation time 23179128089 ps
CPU time 3.02 seconds
Started Feb 07 12:36:56 PM PST 24
Finished Feb 07 12:37:00 PM PST 24
Peak memory 183364 kb
Host smart-c642086f-fdbb-4a9d-ba99-c88780f5218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012855690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3012855690
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.1104657984
Short name T142
Test name
Test status
Simulation time 428021542 ps
CPU time 0.68 seconds
Started Feb 07 12:36:52 PM PST 24
Finished Feb 07 12:36:53 PM PST 24
Peak memory 183228 kb
Host smart-56c49e07-8e84-4cb3-94fe-045470792cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104657984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.1104657984
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.4080805549
Short name T242
Test name
Test status
Simulation time 160637427697 ps
CPU time 15.46 seconds
Started Feb 07 12:37:21 PM PST 24
Finished Feb 07 12:37:37 PM PST 24
Peak memory 193712 kb
Host smart-42495233-1b18-45b0-bab7-593ed04c865c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080805549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.4080805549
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.1373732147
Short name T240
Test name
Test status
Simulation time 159624923170 ps
CPU time 234.76 seconds
Started Feb 07 12:37:01 PM PST 24
Finished Feb 07 12:40:57 PM PST 24
Peak memory 198308 kb
Host smart-325a817b-a4bb-4573-adfe-d4b71814e471
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373732147 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.1373732147
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%