Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 24603 1 T1 116 T2 179 T4 818
bark[1] 291 1 T32 12 T23 43 T77 59
bark[2] 398 1 T2 42 T24 56 T95 22
bark[3] 827 1 T31 84 T18 17 T76 169
bark[4] 342 1 T3 12 T11 17 T82 145
bark[5] 229 1 T96 40 T97 12 T98 12
bark[6] 230 1 T74 12 T26 90 T99 26
bark[7] 408 1 T100 12 T101 21 T78 17
bark[8] 395 1 T11 199 T27 12 T102 13
bark[9] 681 1 T26 17 T103 12 T104 31
bark[10] 330 1 T31 21 T22 12 T26 21
bark[11] 977 1 T2 16 T10 31 T76 224
bark[12] 492 1 T105 16 T106 31 T77 29
bark[13] 255 1 T24 17 T95 33 T101 31
bark[14] 155 1 T107 12 T75 37 T76 26
bark[15] 373 1 T31 17 T39 219 T108 22
bark[16] 544 1 T18 22 T24 191 T109 12
bark[17] 553 1 T18 16 T25 12 T110 13
bark[18] 393 1 T11 82 T29 12 T111 59
bark[19] 650 1 T30 12 T24 27 T112 12
bark[20] 156 1 T41 12 T75 32 T113 12
bark[21] 479 1 T10 16 T32 165 T38 26
bark[22] 513 1 T11 38 T114 30 T77 49
bark[23] 541 1 T1 66 T2 152 T10 68
bark[24] 271 1 T2 113 T32 17 T104 31
bark[25] 657 1 T31 216 T115 160 T78 12
bark[26] 330 1 T116 13 T76 16 T117 16
bark[27] 302 1 T2 58 T4 17 T81 41
bark[28] 1061 1 T31 16 T32 4 T18 16
bark[29] 405 1 T2 16 T10 60 T11 17
bark[30] 581 1 T31 17 T26 37 T82 190
bark[31] 454 1 T2 122 T11 21 T118 12
bark_0 3089 1 T1 13 T2 62 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 25474 1 T1 115 T2 139 T4 814
bite[1] 297 1 T30 11 T31 17 T102 12
bite[2] 682 1 T11 198 T32 3 T76 16
bite[3] 327 1 T32 164 T105 16 T97 11
bite[4] 375 1 T32 11 T26 16 T109 11
bite[5] 545 1 T2 16 T31 16 T18 22
bite[6] 134 1 T4 17 T107 11 T108 17
bite[7] 216 1 T38 26 T24 17 T26 38
bite[8] 393 1 T2 26 T119 11 T75 179
bite[9] 376 1 T1 50 T11 17 T31 103
bite[10] 342 1 T18 16 T75 16 T108 36
bite[11] 117 1 T103 11 T120 32 T121 16
bite[12] 518 1 T2 54 T110 12 T114 17
bite[13] 482 1 T116 12 T76 26 T122 16
bite[14] 249 1 T95 17 T98 11 T115 16
bite[15] 441 1 T2 151 T10 46 T11 20
bite[16] 419 1 T18 17 T105 16 T115 159
bite[17] 865 1 T2 57 T5 11 T41 11
bite[18] 251 1 T108 22 T120 16 T123 12
bite[19] 850 1 T2 16 T39 218 T118 11
bite[20] 484 1 T24 55 T95 34 T122 41
bite[21] 164 1 T100 11 T124 17 T125 16
bite[22] 663 1 T1 16 T31 17 T23 42
bite[23] 561 1 T2 66 T11 81 T74 11
bite[24] 534 1 T10 53 T104 22 T95 16
bite[25] 565 1 T24 190 T26 20 T114 16
bite[26] 529 1 T2 128 T11 20 T81 40
bite[27] 595 1 T2 35 T112 11 T82 144
bite[28] 80 1 T10 16 T126 16 T127 11
bite[29] 305 1 T10 60 T11 17 T22 11
bite[30] 365 1 T39 26 T78 88 T128 16
bite[31] 249 1 T3 11 T11 17 T129 11
bite_0 3518 1 T1 14 T2 72 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 41965 1 T1 195 T2 760 T3 16


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1229 1 T4 53 T11 227 T18 43
prescale[1] 1298 1 T2 39 T4 45 T31 148
prescale[2] 816 1 T11 2 T24 29 T26 8
prescale[3] 665 1 T4 46 T38 66 T24 125
prescale[4] 668 1 T10 40 T38 29 T81 21
prescale[5] 530 1 T1 14 T4 130 T11 2
prescale[6] 775 1 T31 74 T38 15 T39 15
prescale[7] 750 1 T2 2 T4 107 T8 8
prescale[8] 565 1 T7 8 T31 54 T42 8
prescale[9] 797 1 T4 15 T11 180 T17 45
prescale[10] 420 1 T10 18 T18 18 T104 24
prescale[11] 484 1 T4 15 T31 18 T32 161
prescale[12] 492 1 T32 2 T23 2 T24 79
prescale[13] 694 1 T2 2 T9 8 T11 31
prescale[14] 675 1 T4 20 T11 2 T23 2
prescale[15] 505 1 T2 2 T4 15 T32 30
prescale[16] 583 1 T10 45 T11 51 T17 15
prescale[17] 455 1 T2 18 T11 2 T39 2
prescale[18] 768 1 T1 15 T10 15 T31 10
prescale[19] 300 1 T31 2 T38 57 T24 47
prescale[20] 558 1 T11 30 T31 49 T23 66
prescale[21] 701 1 T2 33 T11 8 T31 15
prescale[22] 309 1 T1 15 T4 29 T10 15
prescale[23] 742 1 T2 2 T11 2 T31 2
prescale[24] 546 1 T2 15 T38 78 T26 45
prescale[25] 346 1 T4 55 T26 2 T81 2
prescale[26] 410 1 T4 40 T11 2 T38 87
prescale[27] 390 1 T4 15 T11 91 T31 45
prescale[28] 789 1 T2 2 T4 25 T10 15
prescale[29] 200 1 T2 2 T4 2 T18 15
prescale[30] 662 1 T1 15 T10 15 T31 15
prescale[31] 803 1 T4 160 T10 8 T26 22
prescale_0 22040 1 T1 136 T2 643 T3 16


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31676 1 T1 120 T2 593 T3 16
auto[1] 10289 1 T1 75 T2 167 T4 90


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 41965 1 T1 195 T2 760 T3 16


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 25608 1 T1 119 T2 379 T4 623
wkup[1] 343 1 T2 16 T10 22 T81 22
wkup[2] 449 1 T2 42 T11 17 T24 16
wkup[3] 566 1 T10 16 T11 16 T31 17
wkup[4] 443 1 T11 39 T32 13 T103 13
wkup[5] 555 1 T2 16 T11 48 T17 16
wkup[6] 439 1 T2 22 T11 16 T75 38
wkup[7] 475 1 T2 16 T4 16 T11 35
wkup[8] 368 1 T32 17 T23 35 T24 16
wkup[9] 454 1 T2 16 T22 13 T26 16
wkup[10] 343 1 T2 16 T31 26 T18 16
wkup[11] 441 1 T1 26 T30 13 T31 17
wkup[12] 516 1 T2 16 T10 27 T11 16
wkup[13] 545 1 T1 22 T2 16 T31 17
wkup[14] 319 1 T11 26 T31 33 T39 30
wkup[15] 480 1 T2 16 T4 16 T11 16
wkup[16] 492 1 T2 16 T4 16 T10 16
wkup[17] 367 1 T2 13 T4 23 T31 16
wkup[18] 503 1 T4 32 T31 17 T38 26
wkup[19] 465 1 T2 16 T11 16 T17 16
wkup[20] 357 1 T2 16 T11 32 T31 16
wkup[21] 492 1 T2 21 T11 29 T31 22
wkup[22] 273 1 T39 16 T116 14 T24 16
wkup[23] 535 1 T4 32 T31 32 T32 13
wkup[24] 348 1 T5 13 T32 22 T18 17
wkup[25] 665 1 T1 16 T2 16 T4 32
wkup[26] 443 1 T4 16 T11 32 T31 38
wkup[27] 398 1 T2 32 T11 23 T31 16
wkup[28] 412 1 T38 16 T39 22 T26 16
wkup[29] 465 1 T2 16 T11 16 T31 16
wkup[30] 480 1 T3 13 T4 16 T41 13
wkup[31] 383 1 T4 17 T10 32 T11 16
wkup_0 2543 1 T1 12 T2 43 T3 3

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