Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.82 95.31 100.00 99.35 100.00 96.64


Total test records in report: 422
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T130 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1332242670 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:28 PM PST 24 11614813894 ps
T282 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3398633491 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:20 PM PST 24 371391390 ps
T66 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2864322370 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:21 PM PST 24 2343988612 ps
T131 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2009236208 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:22 PM PST 24 718522356 ps
T283 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.365592580 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:26 PM PST 24 474223053 ps
T67 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2330636570 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 1482618807 ps
T132 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.242613794 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:24 PM PST 24 631775097 ps
T55 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1848244984 Feb 18 12:37:56 PM PST 24 Feb 18 12:38:05 PM PST 24 624891174 ps
T284 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3070431778 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:22 PM PST 24 415921001 ps
T56 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4187058544 Feb 18 12:37:57 PM PST 24 Feb 18 12:38:06 PM PST 24 409424494 ps
T285 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.18790796 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:10 PM PST 24 837071327 ps
T286 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2149385096 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:13 PM PST 24 507596118 ps
T287 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3963180037 Feb 18 12:38:29 PM PST 24 Feb 18 12:38:32 PM PST 24 423872768 ps
T288 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1838396799 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:19 PM PST 24 418769955 ps
T289 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3768030931 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:21 PM PST 24 397586806 ps
T290 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3362601142 Feb 18 12:38:27 PM PST 24 Feb 18 12:38:31 PM PST 24 490441578 ps
T291 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3875282572 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:19 PM PST 24 415046127 ps
T57 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4127903024 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:12 PM PST 24 11685641130 ps
T68 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.652319720 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:24 PM PST 24 2216394794 ps
T36 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4205380653 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:28 PM PST 24 4353368263 ps
T292 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.86407354 Feb 18 12:38:26 PM PST 24 Feb 18 12:38:29 PM PST 24 511727821 ps
T293 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1824125102 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 386817929 ps
T294 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3273682821 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:14 PM PST 24 438268979 ps
T295 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2628371611 Feb 18 12:38:27 PM PST 24 Feb 18 12:38:31 PM PST 24 477964600 ps
T69 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3733579858 Feb 18 12:38:00 PM PST 24 Feb 18 12:38:08 PM PST 24 853786771 ps
T296 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3726156619 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 274481746 ps
T58 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4038450960 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:13 PM PST 24 638097666 ps
T59 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.952428084 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 360399147 ps
T297 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1004116729 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:14 PM PST 24 311230405 ps
T298 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.352692168 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:17 PM PST 24 331941209 ps
T299 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1560156454 Feb 18 12:38:16 PM PST 24 Feb 18 12:38:22 PM PST 24 552559727 ps
T300 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4275300902 Feb 18 12:38:29 PM PST 24 Feb 18 12:38:32 PM PST 24 385671951 ps
T70 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4009282673 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:13 PM PST 24 1247500308 ps
T301 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2361756151 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:14 PM PST 24 359756156 ps
T302 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3366881547 Feb 18 12:38:18 PM PST 24 Feb 18 12:38:24 PM PST 24 460557515 ps
T71 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3531214869 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:19 PM PST 24 1716737988 ps
T303 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1991552982 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:12 PM PST 24 477631440 ps
T304 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2941821073 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:17 PM PST 24 435105816 ps
T305 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1307381230 Feb 18 12:38:29 PM PST 24 Feb 18 12:38:32 PM PST 24 489310175 ps
T306 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3678826933 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 590135760 ps
T72 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2792784228 Feb 18 12:38:26 PM PST 24 Feb 18 12:38:30 PM PST 24 1007660019 ps
T307 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1645911839 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:19 PM PST 24 1003880128 ps
T308 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2657981860 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:20 PM PST 24 404019227 ps
T309 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4270065478 Feb 18 12:38:03 PM PST 24 Feb 18 12:38:10 PM PST 24 532152566 ps
T310 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1207685020 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:11 PM PST 24 675246540 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3733685431 Feb 18 12:39:05 PM PST 24 Feb 18 12:39:12 PM PST 24 1649855616 ps
T311 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.337553400 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:23 PM PST 24 508064397 ps
T60 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.260884624 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 357243262 ps
T312 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.896948109 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:13 PM PST 24 1075325078 ps
T37 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1487113726 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:16 PM PST 24 4469465169 ps
T313 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.35046171 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 413733565 ps
T61 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3237696286 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:18 PM PST 24 503580608 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385851585 Feb 18 12:37:56 PM PST 24 Feb 18 12:38:05 PM PST 24 314562926 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.88602576 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:14 PM PST 24 471944837 ps
T316 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2871514455 Feb 18 12:38:26 PM PST 24 Feb 18 12:38:29 PM PST 24 313633019 ps
T317 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4248156886 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:15 PM PST 24 1261423258 ps
T318 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3527485277 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:21 PM PST 24 436606526 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3301109512 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:16 PM PST 24 443283994 ps
T320 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.369164535 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:20 PM PST 24 366831738 ps
T321 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1382733048 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 620157355 ps
T322 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2180088484 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:16 PM PST 24 411692609 ps
T323 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2638242377 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 412043715 ps
T324 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.603307410 Feb 18 12:37:57 PM PST 24 Feb 18 12:38:06 PM PST 24 1157680466 ps
T325 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1719712032 Feb 18 12:38:19 PM PST 24 Feb 18 12:38:28 PM PST 24 407613847 ps
T89 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3081279278 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:18 PM PST 24 4298799027 ps
T326 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4031269281 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:11 PM PST 24 413686811 ps
T327 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1798411619 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:12 PM PST 24 569121838 ps
T328 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2479272524 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:15 PM PST 24 531857606 ps
T88 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1200866494 Feb 18 12:37:56 PM PST 24 Feb 18 12:38:11 PM PST 24 7882644872 ps
T329 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1749305655 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:13 PM PST 24 4168081730 ps
T91 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3008853359 Feb 18 12:38:10 PM PST 24 Feb 18 12:38:18 PM PST 24 4570099855 ps
T92 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1497713840 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:17 PM PST 24 4366377677 ps
T330 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.343288881 Feb 18 12:38:24 PM PST 24 Feb 18 12:38:28 PM PST 24 385853918 ps
T331 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3953182492 Feb 18 12:37:58 PM PST 24 Feb 18 12:38:07 PM PST 24 535163861 ps
T332 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1433427632 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:25 PM PST 24 308238630 ps
T333 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.821758230 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:14 PM PST 24 503026832 ps
T334 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1290888241 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 365335744 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.61727413 Feb 18 12:38:01 PM PST 24 Feb 18 12:38:11 PM PST 24 710863447 ps
T336 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1636842451 Feb 18 12:38:24 PM PST 24 Feb 18 12:38:28 PM PST 24 445434554 ps
T337 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.664818732 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:13 PM PST 24 747869275 ps
T338 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.355525182 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 4734844111 ps
T62 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2304187449 Feb 18 12:38:00 PM PST 24 Feb 18 12:38:09 PM PST 24 443613367 ps
T339 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3829760056 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:10 PM PST 24 527550071 ps
T340 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1438794661 Feb 18 12:38:27 PM PST 24 Feb 18 12:38:31 PM PST 24 318810559 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1238315712 Feb 18 12:38:03 PM PST 24 Feb 18 12:38:10 PM PST 24 484221997 ps
T342 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1851926155 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:14 PM PST 24 571846413 ps
T343 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1231284157 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:19 PM PST 24 1141280342 ps
T344 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.321176456 Feb 18 12:38:10 PM PST 24 Feb 18 12:38:17 PM PST 24 328690248 ps
T345 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2487051487 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:34 PM PST 24 8853980242 ps
T90 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3238728980 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:13 PM PST 24 9220442100 ps
T346 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.670327878 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:12 PM PST 24 396004038 ps
T347 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1637796455 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:20 PM PST 24 814800210 ps
T348 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3163098982 Feb 18 12:38:01 PM PST 24 Feb 18 12:38:11 PM PST 24 668635502 ps
T349 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2762013913 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:14 PM PST 24 512982456 ps
T63 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2035701293 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 492449497 ps
T350 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.715648555 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:13 PM PST 24 8001520531 ps
T351 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3078855098 Feb 18 12:38:18 PM PST 24 Feb 18 12:38:25 PM PST 24 400901381 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1456035186 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:11 PM PST 24 516934198 ps
T353 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2257885545 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:10 PM PST 24 837611087 ps
T354 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.697012216 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:18 PM PST 24 435124509 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2660492704 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:14 PM PST 24 520668427 ps
T93 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.430839766 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:27 PM PST 24 8426976292 ps
T356 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1646679416 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:14 PM PST 24 489141382 ps
T357 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2527406108 Feb 18 12:37:57 PM PST 24 Feb 18 12:38:06 PM PST 24 293721365 ps
T358 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.728221445 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:13 PM PST 24 313841543 ps
T359 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2943871039 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:21 PM PST 24 313736468 ps
T360 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1971835602 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:27 PM PST 24 4538634557 ps
T361 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.648656090 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:27 PM PST 24 458942722 ps
T362 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1971853359 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:22 PM PST 24 2011638022 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1198440869 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 572667053 ps
T364 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1274867858 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:21 PM PST 24 426946551 ps
T365 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.217940157 Feb 18 12:37:56 PM PST 24 Feb 18 12:38:05 PM PST 24 1066435891 ps
T366 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3122856514 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:18 PM PST 24 469628140 ps
T367 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4079283257 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 2941984855 ps
T368 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2081445159 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:19 PM PST 24 4233830780 ps
T369 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2012929358 Feb 18 12:39:05 PM PST 24 Feb 18 12:39:14 PM PST 24 2892884302 ps
T370 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1368226412 Feb 18 12:38:10 PM PST 24 Feb 18 12:38:18 PM PST 24 401727732 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3143392072 Feb 18 12:38:03 PM PST 24 Feb 18 12:38:11 PM PST 24 459108405 ps
T372 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.258285162 Feb 18 12:38:57 PM PST 24 Feb 18 12:39:05 PM PST 24 8619273929 ps
T373 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4006387508 Feb 18 12:38:25 PM PST 24 Feb 18 12:38:29 PM PST 24 417131812 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3637117379 Feb 18 12:37:59 PM PST 24 Feb 18 12:38:07 PM PST 24 466070963 ps
T64 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1727511731 Feb 18 12:37:58 PM PST 24 Feb 18 12:38:07 PM PST 24 885810532 ps
T375 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4013822258 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:15 PM PST 24 1286278175 ps
T376 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1487865613 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:20 PM PST 24 350376384 ps
T377 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2423999477 Feb 18 12:38:00 PM PST 24 Feb 18 12:38:08 PM PST 24 380137083 ps
T378 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1971322933 Feb 18 12:38:18 PM PST 24 Feb 18 12:38:26 PM PST 24 288046727 ps
T379 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3764301718 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:27 PM PST 24 564758025 ps
T380 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.380269112 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:19 PM PST 24 4522415780 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1140229604 Feb 18 12:38:03 PM PST 24 Feb 18 12:38:16 PM PST 24 8232928355 ps
T382 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2235539929 Feb 18 12:37:58 PM PST 24 Feb 18 12:38:07 PM PST 24 431434020 ps
T383 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2921516534 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:24 PM PST 24 786120514 ps
T384 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3547120641 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 2496746166 ps
T385 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3522820052 Feb 18 12:38:24 PM PST 24 Feb 18 12:38:28 PM PST 24 348983089 ps
T386 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3483418335 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:26 PM PST 24 561220945 ps
T387 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3952959441 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:14 PM PST 24 2256420513 ps
T388 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.696697216 Feb 18 12:38:17 PM PST 24 Feb 18 12:38:25 PM PST 24 516379585 ps
T389 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.149063455 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:16 PM PST 24 1420691908 ps
T390 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.175202039 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:21 PM PST 24 425200149 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3181358020 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:29 PM PST 24 8533564840 ps
T392 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1324714215 Feb 18 12:38:09 PM PST 24 Feb 18 12:38:15 PM PST 24 340523316 ps
T393 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.360891570 Feb 18 12:38:07 PM PST 24 Feb 18 12:38:15 PM PST 24 514218041 ps
T94 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.983328155 Feb 18 12:38:13 PM PST 24 Feb 18 12:38:26 PM PST 24 4026501058 ps
T394 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.628918016 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:10 PM PST 24 2536182490 ps
T65 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4085334346 Feb 18 12:39:04 PM PST 24 Feb 18 12:39:11 PM PST 24 511692045 ps
T395 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3550662970 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:19 PM PST 24 434850278 ps
T396 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.19963537 Feb 18 12:37:56 PM PST 24 Feb 18 12:38:05 PM PST 24 454967503 ps
T397 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1886801823 Feb 18 12:38:01 PM PST 24 Feb 18 12:38:09 PM PST 24 508642435 ps
T398 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2628523567 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:10 PM PST 24 468627671 ps
T399 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2634773458 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:26 PM PST 24 462854272 ps
T400 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1050276323 Feb 18 12:38:04 PM PST 24 Feb 18 12:38:13 PM PST 24 3351438839 ps
T401 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1909304546 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:15 PM PST 24 530457725 ps
T402 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3181172630 Feb 18 12:38:10 PM PST 24 Feb 18 12:38:17 PM PST 24 367545156 ps
T403 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1032022898 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:14 PM PST 24 410424035 ps
T404 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.772193498 Feb 18 12:38:26 PM PST 24 Feb 18 12:38:30 PM PST 24 492354044 ps
T405 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.107686847 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 524127506 ps
T406 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2748566848 Feb 18 12:39:06 PM PST 24 Feb 18 12:39:16 PM PST 24 481138874 ps
T407 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.210139601 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:21 PM PST 24 509127728 ps
T408 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.645345283 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:22 PM PST 24 735486481 ps
T409 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2749172548 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:26 PM PST 24 527135128 ps
T410 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3345131900 Feb 18 12:38:14 PM PST 24 Feb 18 12:38:21 PM PST 24 551843136 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1354848553 Feb 18 12:38:12 PM PST 24 Feb 18 12:38:20 PM PST 24 603620964 ps
T412 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2983826847 Feb 18 12:38:15 PM PST 24 Feb 18 12:38:22 PM PST 24 319414219 ps
T413 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2350617389 Feb 18 12:38:08 PM PST 24 Feb 18 12:38:15 PM PST 24 409111939 ps
T414 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3602115389 Feb 18 12:38:22 PM PST 24 Feb 18 12:38:27 PM PST 24 1063942390 ps
T415 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.988111662 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 293211271 ps
T416 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3005756140 Feb 18 12:38:02 PM PST 24 Feb 18 12:38:10 PM PST 24 292749361 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1326547326 Feb 18 12:38:05 PM PST 24 Feb 18 12:38:12 PM PST 24 378288143 ps
T418 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2641739791 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:15 PM PST 24 2168299540 ps
T419 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3855745483 Feb 18 12:38:27 PM PST 24 Feb 18 12:38:31 PM PST 24 860020640 ps
T420 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3238769814 Feb 18 12:38:11 PM PST 24 Feb 18 12:38:18 PM PST 24 473144104 ps
T421 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3108108025 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:12 PM PST 24 490516572 ps
T422 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3200817822 Feb 18 12:38:06 PM PST 24 Feb 18 12:38:14 PM PST 24 600985662 ps

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2617877576
Short name T2
Test name
Test status
Simulation time 50717256054 ps
CPU time 526.14 seconds
Started Feb 18 12:40:38 PM PST 24
Finished Feb 18 12:49:27 PM PST 24
Peak memory 198308 kb
Host smart-546e7378-2107-43f7-b68c-8a4d400b55b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617877576 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2617877576
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1267232658
Short name T4
Test name
Test status
Simulation time 169982575020 ps
CPU time 359.57 seconds
Started Feb 18 12:40:09 PM PST 24
Finished Feb 18 12:46:11 PM PST 24
Peak memory 198304 kb
Host smart-4106fc5a-092a-4cc3-b1ac-416056f24b9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267232658 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1267232658
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.930527232
Short name T33
Test name
Test status
Simulation time 4930893539 ps
CPU time 2.04 seconds
Started Feb 18 12:38:01 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 196180 kb
Host smart-b27b5ec5-b56f-4b80-9ddc-f8b4e038188f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930527232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_
intg_err.930527232
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1213782629
Short name T31
Test name
Test status
Simulation time 172660885119 ps
CPU time 409.99 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 198296 kb
Host smart-ae3c9e49-6ccc-401b-a3fb-3e49733a6e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213782629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1213782629
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2257945246
Short name T76
Test name
Test status
Simulation time 112595007990 ps
CPU time 212.19 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:44:14 PM PST 24
Peak memory 198308 kb
Host smart-17a6ec46-3c22-41f4-a8c1-e83a3bbfb19a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257945246 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2257945246
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.401409684
Short name T10
Test name
Test status
Simulation time 287177644566 ps
CPU time 362.98 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:47:13 PM PST 24
Peak memory 183308 kb
Host smart-2d758137-c350-427f-8758-ab9e3317b98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401409684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.401409684
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3109322174
Short name T45
Test name
Test status
Simulation time 165534378530 ps
CPU time 859.13 seconds
Started Feb 18 12:41:09 PM PST 24
Finished Feb 18 12:55:33 PM PST 24
Peak memory 202540 kb
Host smart-89a5f57e-4733-4ea7-896a-d0eafac83700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109322174 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3109322174
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.4184453576
Short name T188
Test name
Test status
Simulation time 189008580943 ps
CPU time 303.43 seconds
Started Feb 18 12:40:26 PM PST 24
Finished Feb 18 12:45:38 PM PST 24
Peak memory 194676 kb
Host smart-e64a085e-8662-44a5-9ea9-79e97145f905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184453576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.4184453576
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1654673971
Short name T19
Test name
Test status
Simulation time 4500908089 ps
CPU time 1.89 seconds
Started Feb 18 12:40:03 PM PST 24
Finished Feb 18 12:40:06 PM PST 24
Peak memory 215180 kb
Host smart-017eb983-957b-4d9c-833c-40d665bdb80f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654673971 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1654673971
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.3652199362
Short name T257
Test name
Test status
Simulation time 187625241617 ps
CPU time 34.46 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:41:02 PM PST 24
Peak memory 194744 kb
Host smart-c9331f22-0d34-4f68-98bb-8d27c1046b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652199362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.3652199362
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2129581066
Short name T24
Test name
Test status
Simulation time 345659756312 ps
CPU time 405.67 seconds
Started Feb 18 12:40:55 PM PST 24
Finished Feb 18 12:47:42 PM PST 24
Peak memory 206476 kb
Host smart-cbde1685-6e68-40e2-a87f-258b0d8c7c77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129581066 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2129581066
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.4187058544
Short name T56
Test name
Test status
Simulation time 409424494 ps
CPU time 0.75 seconds
Started Feb 18 12:37:57 PM PST 24
Finished Feb 18 12:38:06 PM PST 24
Peak memory 183712 kb
Host smart-1b7feeea-4df4-4579-b993-6745f4ad44fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187058544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.4187058544
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1200866494
Short name T88
Test name
Test status
Simulation time 7882644872 ps
CPU time 7.91 seconds
Started Feb 18 12:37:56 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 197460 kb
Host smart-dbca063c-84eb-458b-8eea-8efeb6c5918f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200866494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1200866494
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3812728164
Short name T120
Test name
Test status
Simulation time 89750433747 ps
CPU time 149.18 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:42:57 PM PST 24
Peak memory 193688 kb
Host smart-b0308a54-2730-4aa1-890b-cab3e75c6de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812728164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3812728164
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3278135289
Short name T216
Test name
Test status
Simulation time 22066350519 ps
CPU time 34.69 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:40:55 PM PST 24
Peak memory 183432 kb
Host smart-27715383-d00f-4afc-9894-d8299baab250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278135289 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3278135289
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1848244984
Short name T55
Test name
Test status
Simulation time 624891174 ps
CPU time 1.28 seconds
Started Feb 18 12:37:56 PM PST 24
Finished Feb 18 12:38:05 PM PST 24
Peak memory 183712 kb
Host smart-7672e25a-ec49-4f44-8be5-4383856e3dde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848244984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1848244984
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1487113726
Short name T37
Test name
Test status
Simulation time 4469465169 ps
CPU time 4.32 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 196184 kb
Host smart-7a35710f-a0c9-4866-a1cc-b51cc266e413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487113726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1487113726
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.aon_timer_jump.4266279302
Short name T212
Test name
Test status
Simulation time 588474081 ps
CPU time 0.67 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:40:06 PM PST 24
Peak memory 183288 kb
Host smart-6d272d04-83a5-4700-bea9-1bd6ba478357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266279302 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.4266279302
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1616872561
Short name T42
Test name
Test status
Simulation time 10772034611 ps
CPU time 12.03 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183312 kb
Host smart-811a9fbc-d464-409d-a311-f8d77140499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616872561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1616872561
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.1219194797
Short name T223
Test name
Test status
Simulation time 34138045743 ps
CPU time 176.84 seconds
Started Feb 18 12:40:19 PM PST 24
Finished Feb 18 12:43:25 PM PST 24
Peak memory 198256 kb
Host smart-8f7c0ef3-33f7-44ce-8a88-c4fa71c53224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219194797 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.1219194797
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1050276323
Short name T400
Test name
Test status
Simulation time 3351438839 ps
CPU time 3.58 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 192152 kb
Host smart-afc231bd-6aa2-4e16-ac9e-3fe0ccc0b0ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050276323 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1050276323
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.217940157
Short name T365
Test name
Test status
Simulation time 1066435891 ps
CPU time 1 seconds
Started Feb 18 12:37:56 PM PST 24
Finished Feb 18 12:38:05 PM PST 24
Peak memory 183756 kb
Host smart-66151b82-1435-4d87-9008-d299fd851a8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217940157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.217940157
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1991552982
Short name T303
Test name
Test status
Simulation time 477631440 ps
CPU time 2.31 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 198608 kb
Host smart-5d5b01db-4515-439d-b053-b3e912a224aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991552982 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1991552982
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3637117379
Short name T374
Test name
Test status
Simulation time 466070963 ps
CPU time 0.72 seconds
Started Feb 18 12:37:59 PM PST 24
Finished Feb 18 12:38:07 PM PST 24
Peak memory 183452 kb
Host smart-b5dac4d7-0dfd-40cd-8333-cb4171d74dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637117379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3637117379
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.19963537
Short name T396
Test name
Test status
Simulation time 454967503 ps
CPU time 1.19 seconds
Started Feb 18 12:37:56 PM PST 24
Finished Feb 18 12:38:05 PM PST 24
Peak memory 183528 kb
Host smart-d0e0c940-da77-496c-b35c-8a1ccaba39ec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963537 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_tim
er_mem_partial_access.19963537
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2385851585
Short name T314
Test name
Test status
Simulation time 314562926 ps
CPU time 0.74 seconds
Started Feb 18 12:37:56 PM PST 24
Finished Feb 18 12:38:05 PM PST 24
Peak memory 183476 kb
Host smart-d5dec169-cae6-4a67-a729-0cedf5067991
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385851585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2385851585
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.3733579858
Short name T69
Test name
Test status
Simulation time 853786771 ps
CPU time 0.9 seconds
Started Feb 18 12:38:00 PM PST 24
Finished Feb 18 12:38:08 PM PST 24
Peak memory 194168 kb
Host smart-fa3a19e3-deed-43d7-a0ce-130de8400daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733579858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.3733579858
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2235539929
Short name T382
Test name
Test status
Simulation time 431434020 ps
CPU time 2.01 seconds
Started Feb 18 12:37:58 PM PST 24
Finished Feb 18 12:38:07 PM PST 24
Peak memory 198484 kb
Host smart-842367e2-c7ae-41b7-ab4c-7b45ec5dfbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235539929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2235539929
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.242613794
Short name T132
Test name
Test status
Simulation time 631775097 ps
CPU time 0.93 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:24 PM PST 24
Peak memory 183800 kb
Host smart-2b7705c1-7239-40f4-baff-0ac2824eba6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242613794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_al
iasing.242613794
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.4127903024
Short name T57
Test name
Test status
Simulation time 11685641130 ps
CPU time 3.72 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 192140 kb
Host smart-47c3ef34-95c5-43bf-9471-c399d362ac44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127903024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.4127903024
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.603307410
Short name T324
Test name
Test status
Simulation time 1157680466 ps
CPU time 0.96 seconds
Started Feb 18 12:37:57 PM PST 24
Finished Feb 18 12:38:06 PM PST 24
Peak memory 183764 kb
Host smart-f9a8e214-42b5-4ecb-a514-ed8d2daedc28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603307410 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.603307410
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.645345283
Short name T408
Test name
Test status
Simulation time 735486481 ps
CPU time 2.31 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 198480 kb
Host smart-86e5c91a-565f-44cb-910a-f8c63db61637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645345283 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.645345283
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2527406108
Short name T357
Test name
Test status
Simulation time 293721365 ps
CPU time 1.02 seconds
Started Feb 18 12:37:57 PM PST 24
Finished Feb 18 12:38:06 PM PST 24
Peak memory 183688 kb
Host smart-74f39c46-4489-47cf-98ab-049c8d942113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527406108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2527406108
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2361756151
Short name T301
Test name
Test status
Simulation time 359756156 ps
CPU time 0.7 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183456 kb
Host smart-38a7b986-2142-4a21-94ca-bfb54199534d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361756151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2361756151
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3005756140
Short name T416
Test name
Test status
Simulation time 292749361 ps
CPU time 0.98 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183284 kb
Host smart-cf958f2d-32cd-43cb-bfd9-308876b55b10
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005756140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3005756140
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1456035186
Short name T352
Test name
Test status
Simulation time 516934198 ps
CPU time 1.22 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 183412 kb
Host smart-56f18c87-59ce-43e0-bfbd-52233fd3f41f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456035186 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1456035186
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3531214869
Short name T71
Test name
Test status
Simulation time 1716737988 ps
CPU time 1.45 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 194164 kb
Host smart-e787738e-0186-4e2d-905d-5fe5fc9a5cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531214869 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3531214869
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1207685020
Short name T310
Test name
Test status
Simulation time 675246540 ps
CPU time 2.31 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 198592 kb
Host smart-509f44e1-9326-457a-9ba3-b9b2e601bde8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207685020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1207685020
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.1140229604
Short name T381
Test name
Test status
Simulation time 8232928355 ps
CPU time 7.15 seconds
Started Feb 18 12:38:03 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 197424 kb
Host smart-754ee84a-0650-48a3-ae70-4d8cb7a7d139
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140229604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.1140229604
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1645911839
Short name T307
Test name
Test status
Simulation time 1003880128 ps
CPU time 2.47 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 198584 kb
Host smart-bc521e5e-fc45-44d3-9edb-a442247731c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645911839 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1645911839
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1004116729
Short name T297
Test name
Test status
Simulation time 311230405 ps
CPU time 1.01 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183692 kb
Host smart-99a85e45-ac4c-4879-a539-67b64e59f96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004116729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1004116729
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.352692168
Short name T298
Test name
Test status
Simulation time 331941209 ps
CPU time 0.97 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:17 PM PST 24
Peak memory 183628 kb
Host smart-b1544a6c-64bc-4309-a7d3-efa4c2a7d2a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352692168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.352692168
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.4009282673
Short name T70
Test name
Test status
Simulation time 1247500308 ps
CPU time 2.34 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 194156 kb
Host smart-2943840a-8b8b-44a4-9a3b-8f48d26ffd3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009282673 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.4009282673
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1032022898
Short name T403
Test name
Test status
Simulation time 410424035 ps
CPU time 3.01 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 198708 kb
Host smart-3f785072-5b44-4a45-986d-891018db4a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032022898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1032022898
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3550662970
Short name T395
Test name
Test status
Simulation time 434850278 ps
CPU time 1.7 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 198528 kb
Host smart-73e177f7-8597-4b87-aba5-23822a92bd09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550662970 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3550662970
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1636842451
Short name T336
Test name
Test status
Simulation time 445434554 ps
CPU time 0.74 seconds
Started Feb 18 12:38:24 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 183560 kb
Host smart-72e6baf1-dfab-4dca-b9dd-7bcafff936a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636842451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1636842451
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.697012216
Short name T354
Test name
Test status
Simulation time 435124509 ps
CPU time 0.7 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183324 kb
Host smart-88e3fa96-de47-4594-9057-2037c014ce73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697012216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.697012216
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2330636570
Short name T67
Test name
Test status
Simulation time 1482618807 ps
CPU time 1.58 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 194204 kb
Host smart-10747534-0b18-4dc2-81ea-a6a0f7630e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330636570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2330636570
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.1637796455
Short name T347
Test name
Test status
Simulation time 814800210 ps
CPU time 1.91 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 198536 kb
Host smart-038ff412-f7cf-46c3-bba9-ed17b32d1972
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637796455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.1637796455
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2487051487
Short name T345
Test name
Test status
Simulation time 8853980242 ps
CPU time 13.6 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:34 PM PST 24
Peak memory 197460 kb
Host smart-7abcfd89-ef16-4a85-8af4-cb48a2957214
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487051487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2487051487
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.2180088484
Short name T322
Test name
Test status
Simulation time 411692609 ps
CPU time 2.06 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 198628 kb
Host smart-4e4aacb1-dbe4-4ed4-8c92-46f26cbf54b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180088484 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.2180088484
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.952428084
Short name T59
Test name
Test status
Simulation time 360399147 ps
CPU time 0.67 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183596 kb
Host smart-f8ed5cc1-2119-4aa5-bb88-644a17609d39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952428084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.952428084
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3875282572
Short name T291
Test name
Test status
Simulation time 415046127 ps
CPU time 1.18 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 183520 kb
Host smart-53485d21-66a1-40ce-9955-f40d4b0b9e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875282572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3875282572
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.896948109
Short name T312
Test name
Test status
Simulation time 1075325078 ps
CPU time 1.37 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 193492 kb
Host smart-465d7ced-4831-497a-868d-c1eadbb99ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896948109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon
_timer_same_csr_outstanding.896948109
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.3108108025
Short name T421
Test name
Test status
Simulation time 490516572 ps
CPU time 1.38 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 198648 kb
Host smart-94732f9e-798a-4a48-b0ff-92a03ad17a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108108025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.3108108025
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.355525182
Short name T338
Test name
Test status
Simulation time 4734844111 ps
CPU time 1.47 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 196060 kb
Host smart-69919998-2c16-4417-a36f-a0c1e38f3e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355525182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.355525182
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1354848553
Short name T411
Test name
Test status
Simulation time 603620964 ps
CPU time 2.13 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 198508 kb
Host smart-e095b76e-b974-4999-9689-c08758367f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354848553 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1354848553
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.321176456
Short name T344
Test name
Test status
Simulation time 328690248 ps
CPU time 1.07 seconds
Started Feb 18 12:38:10 PM PST 24
Finished Feb 18 12:38:17 PM PST 24
Peak memory 183692 kb
Host smart-deeae5d5-a3f3-4556-a87c-234225f087ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321176456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.321176456
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2149385096
Short name T286
Test name
Test status
Simulation time 507596118 ps
CPU time 1.28 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 183664 kb
Host smart-82cde8b5-f124-44e7-aaf7-1b877df6e9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149385096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2149385096
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2792784228
Short name T72
Test name
Test status
Simulation time 1007660019 ps
CPU time 0.93 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 12:38:30 PM PST 24
Peak memory 193104 kb
Host smart-38244025-27a3-4b00-b1d7-568a8a50470d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792784228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2792784228
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1368226412
Short name T370
Test name
Test status
Simulation time 401727732 ps
CPU time 2.04 seconds
Started Feb 18 12:38:10 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 198564 kb
Host smart-af552b15-a302-457a-bd93-172f2e0607b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368226412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1368226412
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2081445159
Short name T368
Test name
Test status
Simulation time 4233830780 ps
CPU time 7.11 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 196108 kb
Host smart-43a730f1-9f5f-4a75-b8cb-9cf356e10364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081445159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2081445159
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1231284157
Short name T343
Test name
Test status
Simulation time 1141280342 ps
CPU time 1.69 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 198468 kb
Host smart-3cf9c0eb-a6e1-4916-996a-c45d98cd04c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231284157 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1231284157
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.369164535
Short name T320
Test name
Test status
Simulation time 366831738 ps
CPU time 1.11 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 183704 kb
Host smart-2b3ca8ea-0596-4200-a5cc-9e56e9726f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369164535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.369164535
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.988111662
Short name T415
Test name
Test status
Simulation time 293211271 ps
CPU time 0.99 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183436 kb
Host smart-bad34999-dfb8-4211-a127-b4afdc9b8255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988111662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.988111662
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.2864322370
Short name T66
Test name
Test status
Simulation time 2343988612 ps
CPU time 2.5 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 195000 kb
Host smart-98c0e1e4-bdf0-4096-9ab8-4f1026c384cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864322370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.2864322370
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2660492704
Short name T355
Test name
Test status
Simulation time 520668427 ps
CPU time 1.74 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 198548 kb
Host smart-0896ebe5-554d-42a4-8747-13dc68c474f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660492704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2660492704
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.380269112
Short name T380
Test name
Test status
Simulation time 4522415780 ps
CPU time 2.63 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 197124 kb
Host smart-0a9cfabd-b145-41f2-922b-a8044fca1f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380269112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl
_intg_err.380269112
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1198440869
Short name T363
Test name
Test status
Simulation time 572667053 ps
CPU time 1.37 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 198580 kb
Host smart-5b7acbe3-d19e-49f3-ac6b-924fdf981012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198440869 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1198440869
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3483418335
Short name T386
Test name
Test status
Simulation time 561220945 ps
CPU time 0.77 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 183700 kb
Host smart-7ff88d5f-9298-4098-b2b7-221ab0154daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483418335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3483418335
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.4275300902
Short name T300
Test name
Test status
Simulation time 385671951 ps
CPU time 0.78 seconds
Started Feb 18 12:38:29 PM PST 24
Finished Feb 18 12:38:32 PM PST 24
Peak memory 183316 kb
Host smart-009ae3fa-1df8-4eb2-a58f-637b92429268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275300902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.4275300902
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.1689890398
Short name T35
Test name
Test status
Simulation time 1236830069 ps
CPU time 0.86 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 194060 kb
Host smart-8388041a-cf4c-4c32-b336-0e53d2322659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689890398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.1689890398
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.337553400
Short name T311
Test name
Test status
Simulation time 508064397 ps
CPU time 2.08 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:23 PM PST 24
Peak memory 198504 kb
Host smart-2d81128f-b8a4-4f1c-9057-1f0e5a9b6434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337553400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.337553400
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1971835602
Short name T360
Test name
Test status
Simulation time 4538634557 ps
CPU time 6.95 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:27 PM PST 24
Peak memory 197108 kb
Host smart-f7732a93-55be-44b2-8714-35dcff46d32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971835602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1971835602
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.2748566848
Short name T406
Test name
Test status
Simulation time 481138874 ps
CPU time 1.7 seconds
Started Feb 18 12:39:06 PM PST 24
Finished Feb 18 12:39:16 PM PST 24
Peak memory 198492 kb
Host smart-c850e237-ac00-496a-b5a7-0df090d6e795
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748566848 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.2748566848
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1909304546
Short name T401
Test name
Test status
Simulation time 530457725 ps
CPU time 1.42 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 183608 kb
Host smart-7e0a429d-2e5a-48ab-a77b-a2c6f504b0bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909304546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1909304546
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2657981860
Short name T308
Test name
Test status
Simulation time 404019227 ps
CPU time 0.65 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 183464 kb
Host smart-e39973f6-35e0-44ed-823e-6d49459334ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657981860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2657981860
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3602115389
Short name T414
Test name
Test status
Simulation time 1063942390 ps
CPU time 1.7 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:27 PM PST 24
Peak memory 194156 kb
Host smart-f6030fcf-6b73-45ea-8f72-177299f3f4c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602115389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3602115389
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.648656090
Short name T361
Test name
Test status
Simulation time 458942722 ps
CPU time 1.3 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:27 PM PST 24
Peak memory 198420 kb
Host smart-a01050e6-6823-4162-b387-d77e4060df45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648656090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.648656090
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.983328155
Short name T94
Test name
Test status
Simulation time 4026501058 ps
CPU time 6.82 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 197332 kb
Host smart-93843906-4c80-47a9-baf5-ca019601c03e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983328155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl
_intg_err.983328155
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3855745483
Short name T419
Test name
Test status
Simulation time 860020640 ps
CPU time 1.81 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:38:31 PM PST 24
Peak memory 198448 kb
Host smart-efeaec11-4f61-4bd4-abeb-1dfa91b6bc1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855745483 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3855745483
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.4085334346
Short name T65
Test name
Test status
Simulation time 511692045 ps
CPU time 0.72 seconds
Started Feb 18 12:39:04 PM PST 24
Finished Feb 18 12:39:11 PM PST 24
Peak memory 183664 kb
Host smart-e39af9ed-c624-4d69-8076-6f6f43f7e471
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085334346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.4085334346
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3181172630
Short name T402
Test name
Test status
Simulation time 367545156 ps
CPU time 1.16 seconds
Started Feb 18 12:38:10 PM PST 24
Finished Feb 18 12:38:17 PM PST 24
Peak memory 183436 kb
Host smart-771b27bb-5e70-4a97-9818-4609e188ae35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181172630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3181172630
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.149063455
Short name T389
Test name
Test status
Simulation time 1420691908 ps
CPU time 0.83 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 194176 kb
Host smart-0440bf7d-d44e-49ea-901b-4c60b4535c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149063455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.149063455
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1438794661
Short name T340
Test name
Test status
Simulation time 318810559 ps
CPU time 1.52 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:38:31 PM PST 24
Peak memory 198336 kb
Host smart-585847cb-9661-45a2-a1fc-716608a1ad7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438794661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1438794661
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3181358020
Short name T391
Test name
Test status
Simulation time 8533564840 ps
CPU time 10.5 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:29 PM PST 24
Peak memory 197392 kb
Host smart-8b8a8a7b-837f-4b01-8418-12d1c92ef0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181358020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3181358020
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.107686847
Short name T405
Test name
Test status
Simulation time 524127506 ps
CPU time 2.56 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 198512 kb
Host smart-7934eb77-6f37-4d50-a405-a51ba769fe7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107686847 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.107686847
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3237696286
Short name T61
Test name
Test status
Simulation time 503580608 ps
CPU time 0.78 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183588 kb
Host smart-7c478771-1aa8-46b7-826a-a1bc382038f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237696286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3237696286
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.210139601
Short name T407
Test name
Test status
Simulation time 509127728 ps
CPU time 0.74 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183224 kb
Host smart-82e9b4fe-61a2-4054-81ea-4acfd2011c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210139601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.210139601
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2012929358
Short name T369
Test name
Test status
Simulation time 2892884302 ps
CPU time 1.68 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:14 PM PST 24
Peak memory 195252 kb
Host smart-a5e9c685-6f50-4f22-a713-13e13d8f8ce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012929358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2012929358
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.772193498
Short name T404
Test name
Test status
Simulation time 492354044 ps
CPU time 1.37 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 12:38:30 PM PST 24
Peak memory 198360 kb
Host smart-43a180c4-92c0-418e-9f7a-baba4a5775da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772193498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.772193498
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.430839766
Short name T93
Test name
Test status
Simulation time 8426976292 ps
CPU time 13.6 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:27 PM PST 24
Peak memory 197400 kb
Host smart-a8dc120c-f2c3-4bbc-a47b-111b70c11ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430839766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.430839766
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3764301718
Short name T379
Test name
Test status
Simulation time 564758025 ps
CPU time 1.4 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:27 PM PST 24
Peak memory 198528 kb
Host smart-61fc861a-5947-48be-82ad-b508718e3327
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764301718 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3764301718
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2350617389
Short name T413
Test name
Test status
Simulation time 409111939 ps
CPU time 1.39 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 183708 kb
Host smart-15a87805-9d91-4d60-b3b9-0d42424415b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350617389 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2350617389
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2479272524
Short name T328
Test name
Test status
Simulation time 531857606 ps
CPU time 0.7 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 183448 kb
Host smart-697a0693-25e6-4671-b9a5-37bc6226dfdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479272524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2479272524
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3733685431
Short name T73
Test name
Test status
Simulation time 1649855616 ps
CPU time 1.57 seconds
Started Feb 18 12:39:05 PM PST 24
Finished Feb 18 12:39:12 PM PST 24
Peak memory 194740 kb
Host smart-17e87901-0a56-4468-88ba-2358b450b522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733685431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3733685431
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3678826933
Short name T306
Test name
Test status
Simulation time 590135760 ps
CPU time 1.85 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 198564 kb
Host smart-c1371b86-d399-4518-9873-46f6b77da3b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678826933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3678826933
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.258285162
Short name T372
Test name
Test status
Simulation time 8619273929 ps
CPU time 4.41 seconds
Started Feb 18 12:38:57 PM PST 24
Finished Feb 18 12:39:05 PM PST 24
Peak memory 197552 kb
Host smart-918f0ae8-0f2a-4571-9259-9d26cff07da4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258285162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.258285162
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2035701293
Short name T63
Test name
Test status
Simulation time 492449497 ps
CPU time 0.96 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 183716 kb
Host smart-56a8997e-ec3e-426f-8c78-0c96337817bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035701293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2035701293
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1332242670
Short name T130
Test name
Test status
Simulation time 11614813894 ps
CPU time 13.8 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 192188 kb
Host smart-64f785f8-abb5-46ca-93bb-6d51243ca728
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332242670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1332242670
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4248156886
Short name T317
Test name
Test status
Simulation time 1261423258 ps
CPU time 1.49 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 183700 kb
Host smart-3930f2d4-0517-413a-a88e-35ef561b43ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248156886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4248156886
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3200817822
Short name T422
Test name
Test status
Simulation time 600985662 ps
CPU time 3.02 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 198512 kb
Host smart-a709156f-eb6e-4ccc-a908-c3db0dd245a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200817822 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3200817822
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.3953182492
Short name T331
Test name
Test status
Simulation time 535163861 ps
CPU time 0.94 seconds
Started Feb 18 12:37:58 PM PST 24
Finished Feb 18 12:38:07 PM PST 24
Peak memory 183700 kb
Host smart-c828961d-b03e-415e-9e57-a95c18211478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953182492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.3953182492
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2941821073
Short name T304
Test name
Test status
Simulation time 435105816 ps
CPU time 1.22 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:17 PM PST 24
Peak memory 183480 kb
Host smart-d58c7518-325a-463f-a8e2-a292733a7511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941821073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2941821073
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2628523567
Short name T398
Test name
Test status
Simulation time 468627671 ps
CPU time 0.88 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183408 kb
Host smart-9b7ccf69-859a-4906-9481-ee15e7d6ab47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628523567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2628523567
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2638242377
Short name T323
Test name
Test status
Simulation time 412043715 ps
CPU time 1.2 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 183232 kb
Host smart-78d80eda-0b2d-498a-bd89-4befd8595d9a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638242377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2638242377
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.4013822258
Short name T375
Test name
Test status
Simulation time 1286278175 ps
CPU time 1.15 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 193180 kb
Host smart-bebd505f-5f83-44ed-b0be-21dce55b9a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013822258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.4013822258
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.3163098982
Short name T348
Test name
Test status
Simulation time 668635502 ps
CPU time 2.94 seconds
Started Feb 18 12:38:01 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 198484 kb
Host smart-47f94f86-8d1f-447e-80b3-586fcdf4b357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163098982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.3163098982
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3081279278
Short name T89
Test name
Test status
Simulation time 4298799027 ps
CPU time 7.4 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 197092 kb
Host smart-9c18a6ab-014a-46a2-b604-9bf1d39fb80a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081279278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3081279278
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2749172548
Short name T409
Test name
Test status
Simulation time 527135128 ps
CPU time 0.71 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 183456 kb
Host smart-c574d55e-9e65-4fed-ab89-e9aac498166a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749172548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2749172548
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1307381230
Short name T305
Test name
Test status
Simulation time 489310175 ps
CPU time 0.6 seconds
Started Feb 18 12:38:29 PM PST 24
Finished Feb 18 12:38:32 PM PST 24
Peak memory 183384 kb
Host smart-7ba40c66-7d43-4444-87ca-c7cc42a055cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307381230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1307381230
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3238769814
Short name T420
Test name
Test status
Simulation time 473144104 ps
CPU time 1.24 seconds
Started Feb 18 12:38:11 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183452 kb
Host smart-3a5bcf16-1457-4807-937e-0c5b98b86969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238769814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3238769814
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.2634773458
Short name T399
Test name
Test status
Simulation time 462854272 ps
CPU time 0.62 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 183456 kb
Host smart-c1993054-dea9-4a98-8ad3-ccf88cad2cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634773458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.2634773458
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.3522820052
Short name T385
Test name
Test status
Simulation time 348983089 ps
CPU time 1.06 seconds
Started Feb 18 12:38:24 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 183316 kb
Host smart-a26932ca-3c14-4c46-8e8e-7a82a254eaf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522820052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.3522820052
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.343288881
Short name T330
Test name
Test status
Simulation time 385853918 ps
CPU time 1.08 seconds
Started Feb 18 12:38:24 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 183300 kb
Host smart-a4af1d2c-bc35-4cb3-bb0d-b2698a46a28e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343288881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.343288881
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1274867858
Short name T364
Test name
Test status
Simulation time 426946551 ps
CPU time 0.79 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183644 kb
Host smart-0cda790f-9dd9-4487-bd07-ae9b49c6930c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274867858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1274867858
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.175202039
Short name T390
Test name
Test status
Simulation time 425200149 ps
CPU time 0.66 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183640 kb
Host smart-f053e39a-aece-4fb2-afec-7e3d8ab5b6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175202039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.175202039
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.696697216
Short name T388
Test name
Test status
Simulation time 516379585 ps
CPU time 1.21 seconds
Started Feb 18 12:38:17 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 183440 kb
Host smart-f14310b4-4707-4be3-9bf9-f27b37540987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696697216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.696697216
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.1824125102
Short name T293
Test name
Test status
Simulation time 386817929 ps
CPU time 1.1 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 183652 kb
Host smart-374f88ca-cbb8-4433-bf1d-0336eb18bbc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824125102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.1824125102
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.2304187449
Short name T62
Test name
Test status
Simulation time 443613367 ps
CPU time 1.48 seconds
Started Feb 18 12:38:00 PM PST 24
Finished Feb 18 12:38:09 PM PST 24
Peak memory 183724 kb
Host smart-4966df56-609b-4e7d-906c-b982a6c3911d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304187449 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.2304187449
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.1727511731
Short name T64
Test name
Test status
Simulation time 885810532 ps
CPU time 1.61 seconds
Started Feb 18 12:37:58 PM PST 24
Finished Feb 18 12:38:07 PM PST 24
Peak memory 192112 kb
Host smart-c12a9d56-2f74-4fb4-9f0a-942b99632fbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727511731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.1727511731
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.2257885545
Short name T353
Test name
Test status
Simulation time 837611087 ps
CPU time 0.62 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183672 kb
Host smart-e21c371e-e585-4a70-80cc-959dca5b7106
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257885545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.2257885545
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1798411619
Short name T327
Test name
Test status
Simulation time 569121838 ps
CPU time 2.76 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 198584 kb
Host smart-e171fdd8-51f3-4eef-b92f-7b9cb42e03c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798411619 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1798411619
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.260884624
Short name T60
Test name
Test status
Simulation time 357243262 ps
CPU time 0.9 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 183724 kb
Host smart-a6ebcb50-d36b-4e1b-9a9a-2f73f8e418ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260884624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.260884624
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1238315712
Short name T341
Test name
Test status
Simulation time 484221997 ps
CPU time 0.72 seconds
Started Feb 18 12:38:03 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183660 kb
Host smart-76ee64d8-9c4a-47c9-9941-7463774df19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238315712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1238315712
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2762013913
Short name T349
Test name
Test status
Simulation time 512982456 ps
CPU time 0.67 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183400 kb
Host smart-50e35e22-3365-4212-9f21-5782ad3bd0fd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762013913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2762013913
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3143392072
Short name T371
Test name
Test status
Simulation time 459108405 ps
CPU time 1.24 seconds
Started Feb 18 12:38:03 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 183788 kb
Host smart-80b39aea-3288-4ab1-949d-9272d100145d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143392072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3143392072
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2641739791
Short name T418
Test name
Test status
Simulation time 2168299540 ps
CPU time 3.86 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 193272 kb
Host smart-3aa19dbb-ac18-4d29-8517-64f33286d9fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641739791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2641739791
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.728221445
Short name T358
Test name
Test status
Simulation time 313841543 ps
CPU time 1.51 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 198352 kb
Host smart-04168354-e723-4b78-932f-ef00faeb9adc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728221445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.728221445
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3238728980
Short name T90
Test name
Test status
Simulation time 9220442100 ps
CPU time 1.66 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 197464 kb
Host smart-5f9dc613-14fa-4a6e-9fd4-1ecc68e05176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238728980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3238728980
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1971322933
Short name T378
Test name
Test status
Simulation time 288046727 ps
CPU time 0.91 seconds
Started Feb 18 12:38:18 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 183464 kb
Host smart-8b2306fe-427f-40e3-873f-8b0701c60b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971322933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1971322933
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1560156454
Short name T299
Test name
Test status
Simulation time 552559727 ps
CPU time 0.68 seconds
Started Feb 18 12:38:16 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 183448 kb
Host smart-05fec86e-b482-4960-9bcb-a20942386d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560156454 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1560156454
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3122856514
Short name T366
Test name
Test status
Simulation time 469628140 ps
CPU time 0.89 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 183640 kb
Host smart-0048a90b-08de-4635-839c-c288e0a41bb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122856514 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3122856514
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3398633491
Short name T282
Test name
Test status
Simulation time 371391390 ps
CPU time 1.06 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 183456 kb
Host smart-9f98e9a9-7a48-4aab-ae77-ff646da15f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398633491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3398633491
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3963180037
Short name T287
Test name
Test status
Simulation time 423872768 ps
CPU time 0.71 seconds
Started Feb 18 12:38:29 PM PST 24
Finished Feb 18 12:38:32 PM PST 24
Peak memory 183464 kb
Host smart-4c373c45-204f-4228-b762-dc24db75910e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963180037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3963180037
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2943871039
Short name T359
Test name
Test status
Simulation time 313736468 ps
CPU time 1.01 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183416 kb
Host smart-9c99492d-ed92-4aba-9f86-cc648068cc22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943871039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2943871039
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3362601142
Short name T290
Test name
Test status
Simulation time 490441578 ps
CPU time 1.11 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:38:31 PM PST 24
Peak memory 183672 kb
Host smart-1339d930-953f-4d89-ba8e-1c9db8733b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362601142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3362601142
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.2983826847
Short name T412
Test name
Test status
Simulation time 319414219 ps
CPU time 0.65 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 183460 kb
Host smart-a2096d45-985c-4815-8a83-edb257790052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983826847 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.2983826847
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.86407354
Short name T292
Test name
Test status
Simulation time 511727821 ps
CPU time 0.72 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 12:38:29 PM PST 24
Peak memory 183516 kb
Host smart-50faa84d-9280-47f5-8122-abc36b7346e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86407354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.86407354
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3366881547
Short name T302
Test name
Test status
Simulation time 460557515 ps
CPU time 0.56 seconds
Started Feb 18 12:38:18 PM PST 24
Finished Feb 18 12:38:24 PM PST 24
Peak memory 183644 kb
Host smart-4bf665b1-f6e8-44e5-bdd8-edd82f79d50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366881547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3366881547
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.4270065478
Short name T309
Test name
Test status
Simulation time 532152566 ps
CPU time 0.96 seconds
Started Feb 18 12:38:03 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183680 kb
Host smart-0dd8744e-a8b6-43ee-82fb-6e90d56f3a80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270065478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.4270065478
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.4038450960
Short name T58
Test name
Test status
Simulation time 638097666 ps
CPU time 1.77 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 183892 kb
Host smart-3f94acf4-fc71-4291-8790-6012b13e4b86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038450960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.4038450960
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.18790796
Short name T285
Test name
Test status
Simulation time 837071327 ps
CPU time 0.96 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183708 kb
Host smart-ba5b1b77-27c0-449f-9cc6-208f64f05df1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18790796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw_
reset.18790796
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1326547326
Short name T417
Test name
Test status
Simulation time 378288143 ps
CPU time 1.5 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 198572 kb
Host smart-8e22d0d2-f66c-471e-819c-74e140307a85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326547326 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1326547326
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.670327878
Short name T346
Test name
Test status
Simulation time 396004038 ps
CPU time 0.67 seconds
Started Feb 18 12:38:06 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 192828 kb
Host smart-a2f4deb1-7ab1-437b-9dae-e2ff1711eb0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670327878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.670327878
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.4031269281
Short name T326
Test name
Test status
Simulation time 413686811 ps
CPU time 0.69 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 183444 kb
Host smart-ab11ac0b-3b00-4f86-8fee-74b9e1746950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031269281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.4031269281
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.88602576
Short name T315
Test name
Test status
Simulation time 471944837 ps
CPU time 0.68 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183412 kb
Host smart-52490440-1b2e-4ac2-b86f-0aec679d1c64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88602576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_tim
er_mem_partial_access.88602576
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1886801823
Short name T397
Test name
Test status
Simulation time 508642435 ps
CPU time 1.34 seconds
Started Feb 18 12:38:01 PM PST 24
Finished Feb 18 12:38:09 PM PST 24
Peak memory 183396 kb
Host smart-0d96e9e4-ed4d-4264-a9d5-7cf9b7ada58b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886801823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1886801823
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.4079283257
Short name T367
Test name
Test status
Simulation time 2941984855 ps
CPU time 1.14 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 193552 kb
Host smart-1550f7b9-a792-4fac-87ea-b733878b18f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079283257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.4079283257
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.61727413
Short name T335
Test name
Test status
Simulation time 710863447 ps
CPU time 2.42 seconds
Started Feb 18 12:38:01 PM PST 24
Finished Feb 18 12:38:11 PM PST 24
Peak memory 198588 kb
Host smart-425ad9ae-0f61-4d1b-a05c-e5c06f1088b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61727413 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.61727413
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1749305655
Short name T329
Test name
Test status
Simulation time 4168081730 ps
CPU time 2.46 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 196116 kb
Host smart-34949359-108e-4211-8845-878b1ec1f13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749305655 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1749305655
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1719712032
Short name T325
Test name
Test status
Simulation time 407613847 ps
CPU time 0.88 seconds
Started Feb 18 12:38:19 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 183464 kb
Host smart-75a676e0-d78a-4dd3-aa12-bdd20c0e6dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719712032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1719712032
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.4006387508
Short name T373
Test name
Test status
Simulation time 417131812 ps
CPU time 1.12 seconds
Started Feb 18 12:38:25 PM PST 24
Finished Feb 18 12:38:29 PM PST 24
Peak memory 183672 kb
Host smart-9cb0092d-a91b-4848-9a45-60bd0d4a9ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006387508 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.4006387508
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2628371611
Short name T295
Test name
Test status
Simulation time 477964600 ps
CPU time 1.3 seconds
Started Feb 18 12:38:27 PM PST 24
Finished Feb 18 12:38:31 PM PST 24
Peak memory 183372 kb
Host smart-a88067a1-6994-4260-a108-41ec7dc40bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628371611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2628371611
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3768030931
Short name T289
Test name
Test status
Simulation time 397586806 ps
CPU time 0.84 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183628 kb
Host smart-b6084752-a0c9-4cec-a704-6de000418283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768030931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3768030931
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.35046171
Short name T313
Test name
Test status
Simulation time 413733565 ps
CPU time 0.71 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 183628 kb
Host smart-6b6efe79-30f3-4e91-afff-e72b1419f489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35046171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.35046171
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2871514455
Short name T316
Test name
Test status
Simulation time 313633019 ps
CPU time 0.8 seconds
Started Feb 18 12:38:26 PM PST 24
Finished Feb 18 12:38:29 PM PST 24
Peak memory 183324 kb
Host smart-5b29f277-7e87-4315-b216-24f585c4c436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871514455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2871514455
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.3078855098
Short name T351
Test name
Test status
Simulation time 400901381 ps
CPU time 1.09 seconds
Started Feb 18 12:38:18 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 183464 kb
Host smart-8b149eff-f48d-4e67-bae1-40d5c8f5b5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078855098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.3078855098
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1838396799
Short name T288
Test name
Test status
Simulation time 418769955 ps
CPU time 0.68 seconds
Started Feb 18 12:38:12 PM PST 24
Finished Feb 18 12:38:19 PM PST 24
Peak memory 183624 kb
Host smart-55a18b58-f274-47b2-b3d9-c885edd89198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838396799 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1838396799
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.365592580
Short name T283
Test name
Test status
Simulation time 474223053 ps
CPU time 0.66 seconds
Started Feb 18 12:38:22 PM PST 24
Finished Feb 18 12:38:26 PM PST 24
Peak memory 183308 kb
Host smart-c14a4e27-1ff0-4414-bb8e-3c4ae8f11590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365592580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.365592580
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.1433427632
Short name T332
Test name
Test status
Simulation time 308238630 ps
CPU time 0.66 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 183636 kb
Host smart-246d3b2d-11e2-4108-9d1d-64700b985bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433427632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.1433427632
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2921516534
Short name T383
Test name
Test status
Simulation time 786120514 ps
CPU time 2.48 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:24 PM PST 24
Peak memory 198236 kb
Host smart-7076f959-0f78-453a-af07-57d926d96e54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921516534 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2921516534
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1324714215
Short name T392
Test name
Test status
Simulation time 340523316 ps
CPU time 0.77 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 183720 kb
Host smart-3244ebe2-98f8-4279-a223-d4a6263715cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324714215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1324714215
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2423999477
Short name T377
Test name
Test status
Simulation time 380137083 ps
CPU time 0.63 seconds
Started Feb 18 12:38:00 PM PST 24
Finished Feb 18 12:38:08 PM PST 24
Peak memory 183660 kb
Host smart-4ff9034e-043d-4ed6-b929-eb462eca568c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423999477 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2423999477
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.3547120641
Short name T384
Test name
Test status
Simulation time 2496746166 ps
CPU time 1.59 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 193348 kb
Host smart-e43f9107-daf2-4cce-ac2b-3943f4346390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547120641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.3547120641
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3070431778
Short name T284
Test name
Test status
Simulation time 415921001 ps
CPU time 2.62 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 198564 kb
Host smart-0d1e8fd3-d8fb-48b7-a03a-827c0bd3e8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070431778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3070431778
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.715648555
Short name T350
Test name
Test status
Simulation time 8001520531 ps
CPU time 3.79 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 197460 kb
Host smart-30553f0d-3574-4de9-aa46-90d5aabd2c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715648555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_
intg_err.715648555
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3301109512
Short name T319
Test name
Test status
Simulation time 443283994 ps
CPU time 2.07 seconds
Started Feb 18 12:38:09 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 198464 kb
Host smart-5d072c2c-dd04-484b-aedc-a431d8494c13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301109512 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3301109512
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2446223634
Short name T34
Test name
Test status
Simulation time 507018008 ps
CPU time 0.74 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 183800 kb
Host smart-e222f2e9-1b38-44d5-b648-011e622d471c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446223634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2446223634
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3726156619
Short name T296
Test name
Test status
Simulation time 274481746 ps
CPU time 0.92 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 183660 kb
Host smart-89d4d6e8-d679-46a0-b9ec-969ae0d44fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726156619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3726156619
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.628918016
Short name T394
Test name
Test status
Simulation time 2536182490 ps
CPU time 1.14 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 192952 kb
Host smart-f2d3b2c6-7dcd-473f-8737-90fb8cb4fc52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628918016 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.628918016
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.664818732
Short name T337
Test name
Test status
Simulation time 747869275 ps
CPU time 1.85 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:13 PM PST 24
Peak memory 198540 kb
Host smart-ed5654ad-aa30-4923-b276-5b191d61a654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664818732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.664818732
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.821758230
Short name T333
Test name
Test status
Simulation time 503026832 ps
CPU time 1.56 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 198432 kb
Host smart-d2a5c3f0-fbda-499f-a864-b73d809655eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821758230 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.821758230
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1290888241
Short name T334
Test name
Test status
Simulation time 365335744 ps
CPU time 1.1 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 183720 kb
Host smart-adcf5dcd-9e7d-4907-91bd-d82d2c09d797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290888241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1290888241
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1646679416
Short name T356
Test name
Test status
Simulation time 489141382 ps
CPU time 1.22 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183456 kb
Host smart-2b7b3ff4-8643-423f-b764-d4603dce59a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646679416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1646679416
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.3952959441
Short name T387
Test name
Test status
Simulation time 2256420513 ps
CPU time 3.81 seconds
Started Feb 18 12:38:05 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 195252 kb
Host smart-e056260f-015f-4cdf-9b07-529b4dc93ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952959441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.3952959441
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.3273682821
Short name T294
Test name
Test status
Simulation time 438268979 ps
CPU time 2.1 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 198444 kb
Host smart-c152532e-d966-48e4-8914-2706b55826b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273682821 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.3273682821
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1497713840
Short name T92
Test name
Test status
Simulation time 4366377677 ps
CPU time 7.7 seconds
Started Feb 18 12:38:02 PM PST 24
Finished Feb 18 12:38:17 PM PST 24
Peak memory 197264 kb
Host smart-0f3d2019-0798-40fe-ac5d-048d89bad39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497713840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1497713840
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1382733048
Short name T321
Test name
Test status
Simulation time 620157355 ps
CPU time 1.42 seconds
Started Feb 18 12:38:15 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 198436 kb
Host smart-28f71c29-1db0-4d39-916a-2df0df7a0118
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382733048 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1382733048
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3345131900
Short name T410
Test name
Test status
Simulation time 551843136 ps
CPU time 0.76 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 183520 kb
Host smart-4fffe845-fece-4790-8210-5ed63a21a9f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345131900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3345131900
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3829760056
Short name T339
Test name
Test status
Simulation time 527550071 ps
CPU time 0.72 seconds
Started Feb 18 12:38:04 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 183456 kb
Host smart-50272789-ff7e-437e-8161-c95ff4b3344c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829760056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3829760056
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1971853359
Short name T362
Test name
Test status
Simulation time 2011638022 ps
CPU time 3.45 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 195164 kb
Host smart-000f0f0b-f1af-4a74-ade8-a3733d8b6b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971853359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1971853359
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3527485277
Short name T318
Test name
Test status
Simulation time 436606526 ps
CPU time 2.4 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:21 PM PST 24
Peak memory 198464 kb
Host smart-6e84ccb4-9240-4b0d-b216-c723e0cda2ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527485277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3527485277
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.4205380653
Short name T36
Test name
Test status
Simulation time 4353368263 ps
CPU time 7.34 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:28 PM PST 24
Peak memory 197248 kb
Host smart-25ee45c6-69bc-4a8f-9681-99bb70f4bc80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205380653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.4205380653
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.2009236208
Short name T131
Test name
Test status
Simulation time 718522356 ps
CPU time 3.22 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 198568 kb
Host smart-d89343b5-cf8d-47d0-bf5a-8676c0acc9dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009236208 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.2009236208
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1851926155
Short name T342
Test name
Test status
Simulation time 571846413 ps
CPU time 0.71 seconds
Started Feb 18 12:38:08 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 183808 kb
Host smart-685bac0a-19de-45db-9733-b616221b42a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851926155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1851926155
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1487865613
Short name T376
Test name
Test status
Simulation time 350376384 ps
CPU time 0.98 seconds
Started Feb 18 12:38:13 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 183444 kb
Host smart-46ae425e-1a75-499f-88ae-9dc1b245e2ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487865613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1487865613
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.652319720
Short name T68
Test name
Test status
Simulation time 2216394794 ps
CPU time 3.84 seconds
Started Feb 18 12:38:14 PM PST 24
Finished Feb 18 12:38:24 PM PST 24
Peak memory 195360 kb
Host smart-a198e3da-f72a-459d-a59b-f66c4b97f70a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652319720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.652319720
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.360891570
Short name T393
Test name
Test status
Simulation time 514218041 ps
CPU time 2.55 seconds
Started Feb 18 12:38:07 PM PST 24
Finished Feb 18 12:38:15 PM PST 24
Peak memory 198584 kb
Host smart-51792d74-d0ee-46b2-8ee1-921efc7e4d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360891570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.360891570
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.3008853359
Short name T91
Test name
Test status
Simulation time 4570099855 ps
CPU time 2.01 seconds
Started Feb 18 12:38:10 PM PST 24
Finished Feb 18 12:38:18 PM PST 24
Peak memory 195692 kb
Host smart-f32d143f-f18e-43ca-91d9-c0a12045af59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008853359 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.3008853359
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4158988929
Short name T231
Test name
Test status
Simulation time 589410848 ps
CPU time 1.01 seconds
Started Feb 18 12:40:02 PM PST 24
Finished Feb 18 12:40:04 PM PST 24
Peak memory 183308 kb
Host smart-9c5fe9f8-08cb-432e-9f33-f6357ed9e2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158988929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4158988929
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.1790690230
Short name T262
Test name
Test status
Simulation time 40070559401 ps
CPU time 48.95 seconds
Started Feb 18 12:40:03 PM PST 24
Finished Feb 18 12:40:54 PM PST 24
Peak memory 183452 kb
Host smart-bf3ebad4-10a7-465a-8a36-c4c3b2d9ea2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790690230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.1790690230
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.294645747
Short name T177
Test name
Test status
Simulation time 499161194 ps
CPU time 0.9 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:40:07 PM PST 24
Peak memory 183268 kb
Host smart-681a4917-8b09-4460-8dc1-c7f587df318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294645747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.294645747
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.1869425634
Short name T126
Test name
Test status
Simulation time 165912925757 ps
CPU time 228.76 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:43:54 PM PST 24
Peak memory 183424 kb
Host smart-372e8e02-b4ce-449b-958f-ccdbef17a697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869425634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.1869425634
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.1033638787
Short name T218
Test name
Test status
Simulation time 15774339799 ps
CPU time 25.22 seconds
Started Feb 18 12:40:02 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 183320 kb
Host smart-f94b0423-78e4-4250-864b-d50183f49621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033638787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.1033638787
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3302301824
Short name T20
Test name
Test status
Simulation time 3800068179 ps
CPU time 3.69 seconds
Started Feb 18 12:40:07 PM PST 24
Finished Feb 18 12:40:13 PM PST 24
Peak memory 215100 kb
Host smart-e1ae3b81-50d7-4beb-8165-4fb2e1151844
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302301824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3302301824
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.485298008
Short name T235
Test name
Test status
Simulation time 398160673 ps
CPU time 1.15 seconds
Started Feb 18 12:40:15 PM PST 24
Finished Feb 18 12:40:25 PM PST 24
Peak memory 183264 kb
Host smart-41ab7696-70ca-41fa-b57b-61ec170318ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485298008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.485298008
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.3374895569
Short name T219
Test name
Test status
Simulation time 114149448261 ps
CPU time 300.06 seconds
Started Feb 18 12:39:59 PM PST 24
Finished Feb 18 12:45:01 PM PST 24
Peak memory 198324 kb
Host smart-3c425242-c226-40ab-aa45-fccf56d1e170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374895569 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.3374895569
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.1098331791
Short name T47
Test name
Test status
Simulation time 465733431 ps
CPU time 0.72 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:40:28 PM PST 24
Peak memory 183280 kb
Host smart-5466fc3b-4eb7-49ca-aac3-4a0f918d901d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098331791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.1098331791
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2681222232
Short name T145
Test name
Test status
Simulation time 29674309810 ps
CPU time 39.45 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:41:08 PM PST 24
Peak memory 183352 kb
Host smart-ac7cb68e-ac69-4509-b408-c7b57e162de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681222232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2681222232
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.1400667061
Short name T136
Test name
Test status
Simulation time 617796449 ps
CPU time 0.69 seconds
Started Feb 18 12:40:13 PM PST 24
Finished Feb 18 12:40:22 PM PST 24
Peak memory 183300 kb
Host smart-81d87eb7-7993-4c12-b3de-77c6f0e5d63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400667061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.1400667061
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.3944863282
Short name T225
Test name
Test status
Simulation time 584732551651 ps
CPU time 465.34 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:48:16 PM PST 24
Peak memory 183404 kb
Host smart-18f6fb4b-d415-479e-9a54-4a386acfad78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944863282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.3944863282
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.558843
Short name T108
Test name
Test status
Simulation time 99132356893 ps
CPU time 432.21 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:47:43 PM PST 24
Peak memory 198300 kb
Host smart-329b3d76-ddf0-46e8-9873-20af4b4d1724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558843 -assert nopost
proc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.558843
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.1836785119
Short name T102
Test name
Test status
Simulation time 442530097 ps
CPU time 0.91 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 183308 kb
Host smart-f7754cbf-ac15-401b-9d8e-d82b02a80633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836785119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.1836785119
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1165793378
Short name T12
Test name
Test status
Simulation time 636665855 ps
CPU time 0.65 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:40:30 PM PST 24
Peak memory 183296 kb
Host smart-6fd99a02-a65b-45cf-aaab-660fe87e90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165793378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1165793378
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3445791197
Short name T155
Test name
Test status
Simulation time 128211008517 ps
CPU time 99.26 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:42:09 PM PST 24
Peak memory 194732 kb
Host smart-a1918fe2-2437-48e4-afb5-e6a315a0652a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445791197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3445791197
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3036887266
Short name T163
Test name
Test status
Simulation time 563338656 ps
CPU time 1.35 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 183304 kb
Host smart-24cf227e-9b31-466e-b25d-a6178c0cd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036887266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3036887266
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.827304516
Short name T195
Test name
Test status
Simulation time 37987588158 ps
CPU time 54.66 seconds
Started Feb 18 12:40:22 PM PST 24
Finished Feb 18 12:41:26 PM PST 24
Peak memory 183332 kb
Host smart-73293b23-63f2-4ea9-831c-6064bbd2b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827304516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.827304516
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2123237335
Short name T260
Test name
Test status
Simulation time 470351491 ps
CPU time 1.25 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 183284 kb
Host smart-c5fe687a-0663-481f-89ab-91e17972bc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123237335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2123237335
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1823296706
Short name T82
Test name
Test status
Simulation time 203665134661 ps
CPU time 387.72 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:46:55 PM PST 24
Peak memory 198276 kb
Host smart-156aa772-0f94-4e1c-8d9f-9547a9e72eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823296706 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1823296706
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1269678681
Short name T109
Test name
Test status
Simulation time 692479297 ps
CPU time 0.63 seconds
Started Feb 18 12:40:22 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 183308 kb
Host smart-f7065f03-b796-478d-bf78-5e1a1a088ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269678681 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1269678681
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.956927314
Short name T139
Test name
Test status
Simulation time 46397492778 ps
CPU time 70.82 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:41:37 PM PST 24
Peak memory 183480 kb
Host smart-bfa223e6-2474-4403-92e8-89b79a319d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956927314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.956927314
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3980094463
Short name T153
Test name
Test status
Simulation time 370994546 ps
CPU time 0.73 seconds
Started Feb 18 12:40:19 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 183200 kb
Host smart-3a668120-5813-48b9-bb27-1bd6b7a06f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980094463 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3980094463
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.3487249977
Short name T121
Test name
Test status
Simulation time 50577549724 ps
CPU time 50.51 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:41:20 PM PST 24
Peak memory 183364 kb
Host smart-004a9c37-90e5-41b3-bd4b-f095d5f6f094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487249977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.3487249977
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2373364185
Short name T252
Test name
Test status
Simulation time 54092308923 ps
CPU time 450.43 seconds
Started Feb 18 12:40:19 PM PST 24
Finished Feb 18 12:47:59 PM PST 24
Peak memory 198192 kb
Host smart-e69a3bc6-f72c-4007-bfcd-0f51f94ea539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373364185 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2373364185
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.959800479
Short name T30
Test name
Test status
Simulation time 484033409 ps
CPU time 0.96 seconds
Started Feb 18 12:40:19 PM PST 24
Finished Feb 18 12:40:30 PM PST 24
Peak memory 183264 kb
Host smart-5f25564f-36a5-4191-8995-64986998884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959800479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.959800479
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1577972657
Short name T274
Test name
Test status
Simulation time 4097343813 ps
CPU time 5.81 seconds
Started Feb 18 12:40:21 PM PST 24
Finished Feb 18 12:40:36 PM PST 24
Peak memory 183360 kb
Host smart-05522d13-beeb-4e3e-9b14-b039b8f79e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577972657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1577972657
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2639411266
Short name T205
Test name
Test status
Simulation time 407111240 ps
CPU time 0.58 seconds
Started Feb 18 12:40:21 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 183200 kb
Host smart-c1d5c8d5-45b9-445a-8417-d245e3069938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639411266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2639411266
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.167563903
Short name T101
Test name
Test status
Simulation time 311938909330 ps
CPU time 238.68 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:44:29 PM PST 24
Peak memory 183324 kb
Host smart-4b52e9f5-ea62-4dd5-a17f-db862b59c795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167563903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.167563903
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.3076723560
Short name T214
Test name
Test status
Simulation time 46009335040 ps
CPU time 522.53 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:49:09 PM PST 24
Peak memory 198260 kb
Host smart-6e3ee244-6e4a-430e-9880-fa0d70ab4fbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076723560 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.3076723560
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.340157974
Short name T192
Test name
Test status
Simulation time 521012786 ps
CPU time 0.8 seconds
Started Feb 18 12:40:18 PM PST 24
Finished Feb 18 12:40:28 PM PST 24
Peak memory 183308 kb
Host smart-b23a53e0-3733-4c1e-b519-d189fac9e3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340157974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.340157974
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.382292483
Short name T9
Test name
Test status
Simulation time 17279140088 ps
CPU time 27.05 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:40:54 PM PST 24
Peak memory 183280 kb
Host smart-b9b4d00f-f60e-45bc-adbf-c356619930e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382292483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.382292483
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.538997746
Short name T249
Test name
Test status
Simulation time 400485053 ps
CPU time 0.74 seconds
Started Feb 18 12:40:20 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 183220 kb
Host smart-e75e51e8-4161-4c88-8863-0ee7184246df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538997746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.538997746
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1550606880
Short name T52
Test name
Test status
Simulation time 60034058926 ps
CPU time 16.83 seconds
Started Feb 18 12:40:23 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 191568 kb
Host smart-763c20c2-74a0-4b9d-ada2-3be9e9fe2b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550606880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1550606880
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.4063796324
Short name T275
Test name
Test status
Simulation time 199015738252 ps
CPU time 537.99 seconds
Started Feb 18 12:40:28 PM PST 24
Finished Feb 18 12:49:33 PM PST 24
Peak memory 198932 kb
Host smart-aff2bcf7-3cf1-4760-860b-1308d06d0ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063796324 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.4063796324
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.375752325
Short name T123
Test name
Test status
Simulation time 517657027 ps
CPU time 1.34 seconds
Started Feb 18 12:40:26 PM PST 24
Finished Feb 18 12:40:35 PM PST 24
Peak memory 183308 kb
Host smart-f2081de4-3cd7-4fb3-97b4-ccb50b5b83e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375752325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.375752325
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3973318409
Short name T232
Test name
Test status
Simulation time 28106696770 ps
CPU time 40.25 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 183404 kb
Host smart-1dfb6e33-bfc0-4464-8878-c00b1c0ab074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973318409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3973318409
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2611555161
Short name T198
Test name
Test status
Simulation time 353253435 ps
CPU time 1.05 seconds
Started Feb 18 12:40:28 PM PST 24
Finished Feb 18 12:40:36 PM PST 24
Peak memory 183200 kb
Host smart-4d66939d-fefc-4165-9afd-68f6af9ae0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611555161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2611555161
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.948180796
Short name T255
Test name
Test status
Simulation time 358636323519 ps
CPU time 484.85 seconds
Started Feb 18 12:40:24 PM PST 24
Finished Feb 18 12:48:38 PM PST 24
Peak memory 191464 kb
Host smart-2c00407f-681f-480d-97c4-9a4ed3e00cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948180796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_a
ll.948180796
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.520968657
Short name T99
Test name
Test status
Simulation time 120458284318 ps
CPU time 344.64 seconds
Started Feb 18 12:40:24 PM PST 24
Finished Feb 18 12:46:18 PM PST 24
Peak memory 198284 kb
Host smart-cdce8c7a-4bf4-4d4e-8de0-f565e42026fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520968657 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.520968657
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1212898249
Short name T112
Test name
Test status
Simulation time 504046136 ps
CPU time 1.1 seconds
Started Feb 18 12:40:23 PM PST 24
Finished Feb 18 12:40:34 PM PST 24
Peak memory 183276 kb
Host smart-9d638f21-24bc-429b-bc8b-ad51f2bb741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212898249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1212898249
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1239730444
Short name T54
Test name
Test status
Simulation time 24234933337 ps
CPU time 19.96 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:40:53 PM PST 24
Peak memory 183332 kb
Host smart-549784d0-758a-4d94-9020-b4e22b7bb323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239730444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1239730444
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.275733861
Short name T240
Test name
Test status
Simulation time 400044057 ps
CPU time 1.11 seconds
Started Feb 18 12:40:24 PM PST 24
Finished Feb 18 12:40:34 PM PST 24
Peak memory 183180 kb
Host smart-a430f726-5f13-4580-9ddf-8a0badd5aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275733861 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.275733861
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.2969304660
Short name T81
Test name
Test status
Simulation time 22906133552 ps
CPU time 165.78 seconds
Started Feb 18 12:40:26 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 198240 kb
Host smart-2ee3a0ec-e328-4b33-b32f-9eb32b47f191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969304660 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.2969304660
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.1437473067
Short name T41
Test name
Test status
Simulation time 486156844 ps
CPU time 1.24 seconds
Started Feb 18 12:40:34 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183368 kb
Host smart-2d2a3537-e6c1-4cb9-a747-9734ad039566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437473067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.1437473067
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1748020157
Short name T168
Test name
Test status
Simulation time 44808097949 ps
CPU time 16.76 seconds
Started Feb 18 12:40:23 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 183332 kb
Host smart-8f8fe137-cdc4-4619-9278-60630cfdda01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748020157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1748020157
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1322793453
Short name T134
Test name
Test status
Simulation time 523150284 ps
CPU time 0.84 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:40:34 PM PST 24
Peak memory 183320 kb
Host smart-53788968-3b48-492d-84d4-1a0b99b2d268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322793453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1322793453
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2127161031
Short name T277
Test name
Test status
Simulation time 179905003035 ps
CPU time 52.19 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:41:26 PM PST 24
Peak memory 193552 kb
Host smart-1b798ce3-ba33-475f-a11f-898bbb77e994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127161031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2127161031
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.646935523
Short name T103
Test name
Test status
Simulation time 581684974 ps
CPU time 1.34 seconds
Started Feb 18 12:40:24 PM PST 24
Finished Feb 18 12:40:34 PM PST 24
Peak memory 183320 kb
Host smart-340ae2e4-3cf5-4b60-bdfe-e2719f5130f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646935523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.646935523
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1272216372
Short name T248
Test name
Test status
Simulation time 5768550225 ps
CPU time 8.84 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:40:47 PM PST 24
Peak memory 183396 kb
Host smart-3d44b5be-e3fb-46e5-8f1d-06d163f03cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272216372 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1272216372
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2435613355
Short name T160
Test name
Test status
Simulation time 475992210 ps
CPU time 0.71 seconds
Started Feb 18 12:40:26 PM PST 24
Finished Feb 18 12:40:35 PM PST 24
Peak memory 183200 kb
Host smart-4590e532-9c4b-41c8-8b6b-90c7fab676d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435613355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2435613355
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3813664696
Short name T237
Test name
Test status
Simulation time 176786774421 ps
CPU time 183.85 seconds
Started Feb 18 12:40:23 PM PST 24
Finished Feb 18 12:43:37 PM PST 24
Peak memory 193344 kb
Host smart-a24e8e84-6a2c-4cd9-a3b0-6788037655d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813664696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3813664696
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1334862721
Short name T75
Test name
Test status
Simulation time 224655369477 ps
CPU time 787.16 seconds
Started Feb 18 12:40:28 PM PST 24
Finished Feb 18 12:53:43 PM PST 24
Peak memory 201436 kb
Host smart-7c29f0ee-e1ba-4c5d-acfd-5324ab95345b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334862721 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1334862721
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3255112233
Short name T119
Test name
Test status
Simulation time 558416216 ps
CPU time 1.36 seconds
Started Feb 18 12:40:06 PM PST 24
Finished Feb 18 12:40:10 PM PST 24
Peak memory 183344 kb
Host smart-17873b47-38bb-46f2-904e-97fdee2371bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255112233 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3255112233
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2732870294
Short name T53
Test name
Test status
Simulation time 26973564638 ps
CPU time 20.58 seconds
Started Feb 18 12:40:05 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 183356 kb
Host smart-03649cd1-b7fb-4f3d-8d0f-3274439cef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732870294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2732870294
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2067480293
Short name T14
Test name
Test status
Simulation time 8366601194 ps
CPU time 4.38 seconds
Started Feb 18 12:40:06 PM PST 24
Finished Feb 18 12:40:13 PM PST 24
Peak memory 215220 kb
Host smart-0535a0bb-1a10-453d-ade9-1709494435a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067480293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2067480293
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3610205871
Short name T268
Test name
Test status
Simulation time 556302687 ps
CPU time 1.41 seconds
Started Feb 18 12:40:05 PM PST 24
Finished Feb 18 12:40:09 PM PST 24
Peak memory 183056 kb
Host smart-df56ace7-9d71-4f40-96c7-1fceb26795b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610205871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3610205871
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2198711144
Short name T171
Test name
Test status
Simulation time 263643684631 ps
CPU time 379.39 seconds
Started Feb 18 12:40:07 PM PST 24
Finished Feb 18 12:46:29 PM PST 24
Peak memory 193484 kb
Host smart-fcbe95f5-d2d9-41b2-9ad6-1ec1caa7fef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198711144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2198711144
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.558920254
Short name T115
Test name
Test status
Simulation time 26925376538 ps
CPU time 271.49 seconds
Started Feb 18 12:40:06 PM PST 24
Finished Feb 18 12:44:40 PM PST 24
Peak memory 198352 kb
Host smart-377b7ce5-817d-4c0d-bd50-f7d24f1054ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558920254 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.558920254
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.1136823299
Short name T46
Test name
Test status
Simulation time 568513566 ps
CPU time 0.74 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:40:34 PM PST 24
Peak memory 183304 kb
Host smart-cb815984-2850-4759-8388-2fbcdd660884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136823299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.1136823299
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.2254549536
Short name T28
Test name
Test status
Simulation time 20391113806 ps
CPU time 33.99 seconds
Started Feb 18 12:40:25 PM PST 24
Finished Feb 18 12:41:07 PM PST 24
Peak memory 183316 kb
Host smart-8f6c8078-ab48-4d4f-a156-d505aa7ec2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254549536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.2254549536
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.1866584052
Short name T6
Test name
Test status
Simulation time 511417106 ps
CPU time 0.92 seconds
Started Feb 18 12:40:22 PM PST 24
Finished Feb 18 12:40:32 PM PST 24
Peak memory 183296 kb
Host smart-0b36947d-9c81-4fe7-92c2-42b58cd3e73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866584052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.1866584052
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1490917919
Short name T247
Test name
Test status
Simulation time 117457073109 ps
CPU time 33.6 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183380 kb
Host smart-b8be1d9a-2938-44ad-b0fe-dc7d53518bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490917919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1490917919
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1638152458
Short name T279
Test name
Test status
Simulation time 21493203323 ps
CPU time 170.79 seconds
Started Feb 18 12:40:23 PM PST 24
Finished Feb 18 12:43:23 PM PST 24
Peak memory 198256 kb
Host smart-3acce4ef-787a-40f5-b8db-55aa8c724cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638152458 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1638152458
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3948379802
Short name T129
Test name
Test status
Simulation time 520531795 ps
CPU time 0.59 seconds
Started Feb 18 12:40:33 PM PST 24
Finished Feb 18 12:40:38 PM PST 24
Peak memory 183396 kb
Host smart-42a4dc1e-c652-4cd5-810a-16d2d69b1460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948379802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3948379802
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1414817691
Short name T254
Test name
Test status
Simulation time 55557048259 ps
CPU time 72.32 seconds
Started Feb 18 12:40:33 PM PST 24
Finished Feb 18 12:41:50 PM PST 24
Peak memory 183316 kb
Host smart-30860e88-26aa-4d0e-aae5-487c18990078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414817691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1414817691
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.3768732177
Short name T200
Test name
Test status
Simulation time 431277575 ps
CPU time 0.71 seconds
Started Feb 18 12:40:31 PM PST 24
Finished Feb 18 12:40:37 PM PST 24
Peak memory 183140 kb
Host smart-7470ed02-ff31-460f-bcf8-08414a05c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768732177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.3768732177
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.3567228291
Short name T111
Test name
Test status
Simulation time 67751641535 ps
CPU time 94.55 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 183352 kb
Host smart-f9029227-ed85-4258-8a88-c4f8fb6d4418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567228291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.3567228291
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3428710533
Short name T187
Test name
Test status
Simulation time 58579830940 ps
CPU time 470.8 seconds
Started Feb 18 12:40:31 PM PST 24
Finished Feb 18 12:48:28 PM PST 24
Peak memory 198312 kb
Host smart-24be3255-3b41-49fc-8b7e-699c95b49bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428710533 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3428710533
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2423205658
Short name T148
Test name
Test status
Simulation time 596861121 ps
CPU time 1.48 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183292 kb
Host smart-877cf7c6-f43b-4722-9e59-9ef8a71aaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423205658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2423205658
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2793270949
Short name T142
Test name
Test status
Simulation time 3905418376 ps
CPU time 3.02 seconds
Started Feb 18 12:40:31 PM PST 24
Finished Feb 18 12:40:40 PM PST 24
Peak memory 183360 kb
Host smart-d24b4e08-02e3-4998-8690-f9d7fb71c203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793270949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2793270949
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3345947911
Short name T149
Test name
Test status
Simulation time 590059593 ps
CPU time 0.63 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:40:37 PM PST 24
Peak memory 183316 kb
Host smart-3f28926c-6b82-4f84-94ac-81dd2027d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345947911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3345947911
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.490069520
Short name T281
Test name
Test status
Simulation time 88807540415 ps
CPU time 130.88 seconds
Started Feb 18 12:40:33 PM PST 24
Finished Feb 18 12:42:49 PM PST 24
Peak memory 193356 kb
Host smart-5fc99c6c-0bcf-4f74-9106-2b33bc9883bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490069520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.490069520
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.4083340524
Short name T209
Test name
Test status
Simulation time 85707210872 ps
CPU time 179.91 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:43:39 PM PST 24
Peak memory 198304 kb
Host smart-b6e372e2-3f86-48f9-8fde-4cf22f9aa6e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083340524 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.4083340524
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.1052611465
Short name T74
Test name
Test status
Simulation time 395670432 ps
CPU time 0.67 seconds
Started Feb 18 12:40:33 PM PST 24
Finished Feb 18 12:40:38 PM PST 24
Peak memory 183296 kb
Host smart-03bd0c73-6d7a-43ba-a547-2682bca9ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052611465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.1052611465
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.163812468
Short name T8
Test name
Test status
Simulation time 15636516634 ps
CPU time 25.08 seconds
Started Feb 18 12:40:30 PM PST 24
Finished Feb 18 12:41:01 PM PST 24
Peak memory 183424 kb
Host smart-9bfeca02-637e-4886-88b6-a5723afe3899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163812468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.163812468
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.2306020896
Short name T144
Test name
Test status
Simulation time 560330655 ps
CPU time 1.18 seconds
Started Feb 18 12:40:33 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183192 kb
Host smart-e99d8341-b40a-412e-b6df-fe22f3896f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306020896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.2306020896
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2906002427
Short name T117
Test name
Test status
Simulation time 122846094696 ps
CPU time 44.09 seconds
Started Feb 18 12:40:31 PM PST 24
Finished Feb 18 12:41:21 PM PST 24
Peak memory 183376 kb
Host smart-fea82eda-ace2-46f2-9ecf-b229b84d3947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906002427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2906002427
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1113751368
Short name T98
Test name
Test status
Simulation time 414376707 ps
CPU time 0.64 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:40:38 PM PST 24
Peak memory 183376 kb
Host smart-7caaacf9-aa20-4943-974a-13b4cb839ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113751368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1113751368
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1426567166
Short name T167
Test name
Test status
Simulation time 2978120093 ps
CPU time 2.92 seconds
Started Feb 18 12:40:32 PM PST 24
Finished Feb 18 12:40:40 PM PST 24
Peak memory 183300 kb
Host smart-e6813025-45fd-41ff-9300-71e9dde1d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426567166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1426567166
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1471603756
Short name T251
Test name
Test status
Simulation time 389835773 ps
CPU time 1.13 seconds
Started Feb 18 12:40:31 PM PST 24
Finished Feb 18 12:40:38 PM PST 24
Peak memory 183268 kb
Host smart-4d36f6c8-e82d-4caa-8cc5-a9b0f013e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471603756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1471603756
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1363369897
Short name T273
Test name
Test status
Simulation time 277816418408 ps
CPU time 90.48 seconds
Started Feb 18 12:40:40 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 193516 kb
Host smart-1aeaf678-3903-4514-b4fa-3e7ab14aca0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363369897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1363369897
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.503888235
Short name T178
Test name
Test status
Simulation time 360478345 ps
CPU time 1.01 seconds
Started Feb 18 12:40:40 PM PST 24
Finished Feb 18 12:40:43 PM PST 24
Peak memory 183328 kb
Host smart-3329bb35-0408-4191-9e71-2ecec2b19f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503888235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.503888235
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.4268650747
Short name T40
Test name
Test status
Simulation time 30404940520 ps
CPU time 45.34 seconds
Started Feb 18 12:40:43 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 183408 kb
Host smart-8098df37-1cd5-479a-8836-2684ba6c8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268650747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.4268650747
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.353835515
Short name T159
Test name
Test status
Simulation time 528562480 ps
CPU time 0.74 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:40:43 PM PST 24
Peak memory 183260 kb
Host smart-1c64543d-f2dc-4411-84af-7d658f7ca74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353835515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.353835515
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1570719195
Short name T230
Test name
Test status
Simulation time 295015188233 ps
CPU time 412.36 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:47:35 PM PST 24
Peak memory 183320 kb
Host smart-811577db-a35f-4ba0-9f6d-ab8ca02d040f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570719195 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1570719195
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.3720178188
Short name T78
Test name
Test status
Simulation time 41785502966 ps
CPU time 308.8 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:45:48 PM PST 24
Peak memory 198172 kb
Host smart-f355be3b-35a9-483a-a8ac-fe027d9f9270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720178188 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.3720178188
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.427847394
Short name T22
Test name
Test status
Simulation time 502569801 ps
CPU time 0.78 seconds
Started Feb 18 12:40:43 PM PST 24
Finished Feb 18 12:40:45 PM PST 24
Peak memory 183376 kb
Host smart-eb030cb2-9117-447a-9508-e9dda6f43a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427847394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.427847394
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.3437677582
Short name T220
Test name
Test status
Simulation time 6219666352 ps
CPU time 2.44 seconds
Started Feb 18 12:40:34 PM PST 24
Finished Feb 18 12:40:41 PM PST 24
Peak memory 183408 kb
Host smart-392c4088-3cad-4386-8d33-99bc6d7e6ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437677582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.3437677582
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2954129728
Short name T197
Test name
Test status
Simulation time 568093332 ps
CPU time 1.33 seconds
Started Feb 18 12:40:41 PM PST 24
Finished Feb 18 12:40:43 PM PST 24
Peak memory 183212 kb
Host smart-b2f4dec9-3ae1-4a2a-af8a-68a66ff0b171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954129728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2954129728
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1596487926
Short name T114
Test name
Test status
Simulation time 35581637321 ps
CPU time 8.77 seconds
Started Feb 18 12:40:39 PM PST 24
Finished Feb 18 12:40:50 PM PST 24
Peak memory 193732 kb
Host smart-0850e01a-12c8-4bdf-bc1e-4758aa092800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596487926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1596487926
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.987458241
Short name T39
Test name
Test status
Simulation time 58004591760 ps
CPU time 288.84 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:45:37 PM PST 24
Peak memory 198256 kb
Host smart-2dc39e67-3614-436c-ba7d-0a157c87c2d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987458241 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.987458241
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.2084502332
Short name T180
Test name
Test status
Simulation time 453739155 ps
CPU time 0.95 seconds
Started Feb 18 12:40:39 PM PST 24
Finished Feb 18 12:40:42 PM PST 24
Peak memory 183312 kb
Host smart-a3c3458f-ef37-44ae-92d2-249468c3c371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084502332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.2084502332
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1438772198
Short name T259
Test name
Test status
Simulation time 1181189272 ps
CPU time 0.69 seconds
Started Feb 18 12:40:43 PM PST 24
Finished Feb 18 12:40:45 PM PST 24
Peak memory 183272 kb
Host smart-e4236549-6bf0-4357-95f1-4210c44d875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438772198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1438772198
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.417901440
Short name T226
Test name
Test status
Simulation time 358757892 ps
CPU time 0.82 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183220 kb
Host smart-56097bb0-58bc-4318-ba88-045c57716286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417901440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.417901440
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1772194286
Short name T95
Test name
Test status
Simulation time 3330618595 ps
CPU time 4.41 seconds
Started Feb 18 12:40:36 PM PST 24
Finished Feb 18 12:40:44 PM PST 24
Peak memory 183348 kb
Host smart-b83d5ef2-cdce-453f-85fb-cebe6b2a433e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772194286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1772194286
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_jump.767634866
Short name T239
Test name
Test status
Simulation time 478287354 ps
CPU time 1.37 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:40:40 PM PST 24
Peak memory 183312 kb
Host smart-467732fd-96e7-430e-bab5-9553e3a2b891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767634866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.767634866
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2076979237
Short name T140
Test name
Test status
Simulation time 5098201732 ps
CPU time 2.39 seconds
Started Feb 18 12:40:35 PM PST 24
Finished Feb 18 12:40:42 PM PST 24
Peak memory 183340 kb
Host smart-23b2ec5a-c7e7-4657-90f6-d52c0c95d000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076979237 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2076979237
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.3476549672
Short name T48
Test name
Test status
Simulation time 514281298 ps
CPU time 0.97 seconds
Started Feb 18 12:40:39 PM PST 24
Finished Feb 18 12:40:42 PM PST 24
Peak memory 183192 kb
Host smart-a4ed1b13-ca4d-4cb8-af05-0e47ce091f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476549672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.3476549672
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.4086080030
Short name T105
Test name
Test status
Simulation time 93870480699 ps
CPU time 149.01 seconds
Started Feb 18 12:40:45 PM PST 24
Finished Feb 18 12:43:15 PM PST 24
Peak memory 183368 kb
Host smart-8d6502cd-7466-40ef-b869-ce881804dc8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086080030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.4086080030
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.3959934763
Short name T86
Test name
Test status
Simulation time 94210431522 ps
CPU time 691.12 seconds
Started Feb 18 12:40:40 PM PST 24
Finished Feb 18 12:52:13 PM PST 24
Peak memory 199824 kb
Host smart-368051bd-a408-429b-87b3-ee28bf9308c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959934763 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.3959934763
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2767723664
Short name T116
Test name
Test status
Simulation time 589622657 ps
CPU time 1.42 seconds
Started Feb 18 12:40:44 PM PST 24
Finished Feb 18 12:40:47 PM PST 24
Peak memory 183312 kb
Host smart-3a0067b1-18a9-43c0-bded-b121284c679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767723664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2767723664
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2404676517
Short name T267
Test name
Test status
Simulation time 18987687276 ps
CPU time 27.09 seconds
Started Feb 18 12:40:42 PM PST 24
Finished Feb 18 12:41:11 PM PST 24
Peak memory 183424 kb
Host smart-7881a35d-ce6b-471f-b2ca-6eff8d30a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404676517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2404676517
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2902368956
Short name T162
Test name
Test status
Simulation time 509189639 ps
CPU time 0.75 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 183264 kb
Host smart-4e399e35-fd40-45e2-9002-7687a4f3789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902368956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2902368956
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.1353288850
Short name T206
Test name
Test status
Simulation time 38474350964 ps
CPU time 29.01 seconds
Started Feb 18 12:40:43 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 193708 kb
Host smart-b1b758f3-b2a7-427e-83ee-a86d212f811d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353288850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.1353288850
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1251000355
Short name T27
Test name
Test status
Simulation time 372847515 ps
CPU time 0.68 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:40:07 PM PST 24
Peak memory 183308 kb
Host smart-e9dada0d-e775-424b-a1b9-e2c3f2563ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251000355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1251000355
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3661320823
Short name T146
Test name
Test status
Simulation time 10017686396 ps
CPU time 5.01 seconds
Started Feb 18 12:40:10 PM PST 24
Finished Feb 18 12:40:22 PM PST 24
Peak memory 183340 kb
Host smart-dc14d54d-16eb-405b-939d-2520f79abde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661320823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3661320823
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.3126685200
Short name T16
Test name
Test status
Simulation time 4416326178 ps
CPU time 2.22 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 215280 kb
Host smart-fadc2a5d-3a8b-4edd-a1be-8f50bb34dced
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126685200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.3126685200
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2085215177
Short name T229
Test name
Test status
Simulation time 495488453 ps
CPU time 0.66 seconds
Started Feb 18 12:40:08 PM PST 24
Finished Feb 18 12:40:11 PM PST 24
Peak memory 183384 kb
Host smart-793ae607-f36e-420f-b089-ba6c154c64fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085215177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2085215177
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1229511557
Short name T243
Test name
Test status
Simulation time 165679198415 ps
CPU time 58.89 seconds
Started Feb 18 12:40:04 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 194480 kb
Host smart-3f6eb12e-92d6-4c67-9983-03417c5a16d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229511557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1229511557
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4034406387
Short name T183
Test name
Test status
Simulation time 379502626 ps
CPU time 0.63 seconds
Started Feb 18 12:40:44 PM PST 24
Finished Feb 18 12:40:46 PM PST 24
Peak memory 183296 kb
Host smart-07ebca44-deed-43a7-92b7-bbc7a456d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034406387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4034406387
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.826465381
Short name T7
Test name
Test status
Simulation time 15831991935 ps
CPU time 26.21 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:41:15 PM PST 24
Peak memory 183240 kb
Host smart-9f6087f0-44b9-4f7d-8874-736dad12fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826465381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.826465381
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.245785059
Short name T196
Test name
Test status
Simulation time 468568081 ps
CPU time 1.18 seconds
Started Feb 18 12:40:44 PM PST 24
Finished Feb 18 12:40:46 PM PST 24
Peak memory 183188 kb
Host smart-4b63088c-7a9f-463f-9c92-89d9b0efb5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245785059 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.245785059
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1725626086
Short name T96
Test name
Test status
Simulation time 44218234299 ps
CPU time 65.07 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:41:53 PM PST 24
Peak memory 193476 kb
Host smart-e91e57b9-1b2f-426a-a642-afa7c1079361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725626086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1725626086
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.1930299510
Short name T165
Test name
Test status
Simulation time 435370668 ps
CPU time 1.27 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 183284 kb
Host smart-55a4d00f-4385-4eef-8746-b2f68a17f0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930299510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.1930299510
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.299502827
Short name T150
Test name
Test status
Simulation time 20912658647 ps
CPU time 6.85 seconds
Started Feb 18 12:40:45 PM PST 24
Finished Feb 18 12:40:53 PM PST 24
Peak memory 183336 kb
Host smart-c7c801c2-3691-4bca-b90f-512cc13f46bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299502827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.299502827
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3490695555
Short name T152
Test name
Test status
Simulation time 480537700 ps
CPU time 1.3 seconds
Started Feb 18 12:40:44 PM PST 24
Finished Feb 18 12:40:47 PM PST 24
Peak memory 183216 kb
Host smart-65c7590c-669e-46cb-b6b9-6901eb6813fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490695555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3490695555
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.1519103549
Short name T191
Test name
Test status
Simulation time 446980863886 ps
CPU time 61.68 seconds
Started Feb 18 12:40:42 PM PST 24
Finished Feb 18 12:41:46 PM PST 24
Peak memory 183452 kb
Host smart-fe89bd3b-9c32-415d-9ff0-7e24a1a53520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519103549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.1519103549
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.939626155
Short name T50
Test name
Test status
Simulation time 50005975746 ps
CPU time 543.52 seconds
Started Feb 18 12:40:45 PM PST 24
Finished Feb 18 12:49:50 PM PST 24
Peak memory 198300 kb
Host smart-e374e36a-f94d-495e-a26a-6e17df7de82e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939626155 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.939626155
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3674422695
Short name T3
Test name
Test status
Simulation time 425145464 ps
CPU time 0.71 seconds
Started Feb 18 12:40:45 PM PST 24
Finished Feb 18 12:40:48 PM PST 24
Peak memory 183276 kb
Host smart-f0383053-ec9b-484b-952b-ff201fe3e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674422695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3674422695
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1713900607
Short name T172
Test name
Test status
Simulation time 30662184439 ps
CPU time 5.88 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:40:56 PM PST 24
Peak memory 183408 kb
Host smart-557b1e57-b943-46d3-9fdf-55bb26155de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713900607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1713900607
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2308525420
Short name T184
Test name
Test status
Simulation time 573942999 ps
CPU time 0.74 seconds
Started Feb 18 12:40:42 PM PST 24
Finished Feb 18 12:40:45 PM PST 24
Peak memory 183300 kb
Host smart-8eb58640-5326-4496-9c0b-7b0cbd941b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308525420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2308525420
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.830762104
Short name T104
Test name
Test status
Simulation time 140953255065 ps
CPU time 54.68 seconds
Started Feb 18 12:40:51 PM PST 24
Finished Feb 18 12:41:48 PM PST 24
Peak memory 193520 kb
Host smart-a3eb5ead-38ad-44c8-8d01-8844756f598f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830762104 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.830762104
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.850891963
Short name T77
Test name
Test status
Simulation time 34361228510 ps
CPU time 258.53 seconds
Started Feb 18 12:40:51 PM PST 24
Finished Feb 18 12:45:12 PM PST 24
Peak memory 198236 kb
Host smart-d76d6b04-3ec5-47ee-877a-287b01d2f683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850891963 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.850891963
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.1498358303
Short name T107
Test name
Test status
Simulation time 511437955 ps
CPU time 0.71 seconds
Started Feb 18 12:40:48 PM PST 24
Finished Feb 18 12:40:51 PM PST 24
Peak memory 183308 kb
Host smart-76139d9a-b9fa-4377-b161-5c1b46951f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498358303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.1498358303
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3947529746
Short name T181
Test name
Test status
Simulation time 22066864366 ps
CPU time 34.11 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:41:22 PM PST 24
Peak memory 183420 kb
Host smart-67bd1683-8516-4080-965e-d9f33b3dcdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947529746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3947529746
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2473364021
Short name T158
Test name
Test status
Simulation time 536912252 ps
CPU time 0.9 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 183176 kb
Host smart-b88ca2b0-ef79-4cbd-9f31-0a27baba7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473364021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2473364021
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1594083171
Short name T125
Test name
Test status
Simulation time 67132807473 ps
CPU time 14.87 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:41:04 PM PST 24
Peak memory 183436 kb
Host smart-e74f13fe-f4e4-40f9-8c08-537b33420f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594083171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1594083171
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2544609465
Short name T23
Test name
Test status
Simulation time 30642425782 ps
CPU time 253.8 seconds
Started Feb 18 12:40:48 PM PST 24
Finished Feb 18 12:45:04 PM PST 24
Peak memory 198276 kb
Host smart-9baebcfc-3406-4b8a-8604-fbdc3cf186ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544609465 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2544609465
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1501950897
Short name T215
Test name
Test status
Simulation time 458900047 ps
CPU time 1.18 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:40:50 PM PST 24
Peak memory 183304 kb
Host smart-4a86d764-cfa2-4350-be9d-96494a162b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501950897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1501950897
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1869326706
Short name T263
Test name
Test status
Simulation time 20086069916 ps
CPU time 19.52 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:41:09 PM PST 24
Peak memory 183476 kb
Host smart-9dfcb9c1-c2d1-4e6c-bebb-a51991bf5634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869326706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1869326706
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.573194273
Short name T157
Test name
Test status
Simulation time 473193014 ps
CPU time 0.84 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:40:51 PM PST 24
Peak memory 183380 kb
Host smart-0c35fc46-caf1-47af-8422-877b60ce9543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573194273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.573194273
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2627797177
Short name T207
Test name
Test status
Simulation time 141570394105 ps
CPU time 40.69 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:41:31 PM PST 24
Peak memory 183432 kb
Host smart-91c61e39-1a91-4d31-9b37-5738c4847a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627797177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2627797177
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2791525187
Short name T199
Test name
Test status
Simulation time 76652115272 ps
CPU time 281.84 seconds
Started Feb 18 12:40:47 PM PST 24
Finished Feb 18 12:45:32 PM PST 24
Peak memory 198140 kb
Host smart-952efe1e-9a0b-4cac-8d96-651bb508ce3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791525187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2791525187
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1524054204
Short name T127
Test name
Test status
Simulation time 398139168 ps
CPU time 0.69 seconds
Started Feb 18 12:40:48 PM PST 24
Finished Feb 18 12:40:51 PM PST 24
Peak memory 183284 kb
Host smart-0671580b-9197-4dc3-9a4e-73b15f6789c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524054204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1524054204
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.2617966276
Short name T236
Test name
Test status
Simulation time 9053708126 ps
CPU time 12.43 seconds
Started Feb 18 12:40:51 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 183272 kb
Host smart-d50ee63d-2ca8-4296-bbdf-1273080d2850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617966276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.2617966276
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2505797155
Short name T203
Test name
Test status
Simulation time 507424901 ps
CPU time 0.65 seconds
Started Feb 18 12:40:46 PM PST 24
Finished Feb 18 12:40:49 PM PST 24
Peak memory 183176 kb
Host smart-5774ce83-25b5-43e6-8182-f048bf7ce949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505797155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2505797155
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.2013205397
Short name T276
Test name
Test status
Simulation time 4510545495 ps
CPU time 4.43 seconds
Started Feb 18 12:40:56 PM PST 24
Finished Feb 18 12:41:01 PM PST 24
Peak memory 183432 kb
Host smart-8d85d1e8-ea19-4453-8a17-f9003b0e7c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013205397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.2013205397
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.1640124909
Short name T38
Test name
Test status
Simulation time 158631883771 ps
CPU time 87.28 seconds
Started Feb 18 12:40:50 PM PST 24
Finished Feb 18 12:42:19 PM PST 24
Peak memory 198280 kb
Host smart-5a11462b-eeb1-4f7e-86e1-874f88769faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640124909 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.1640124909
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.2541459493
Short name T256
Test name
Test status
Simulation time 507999023 ps
CPU time 1.24 seconds
Started Feb 18 12:40:57 PM PST 24
Finished Feb 18 12:40:59 PM PST 24
Peak memory 183348 kb
Host smart-3ea73199-1d87-4006-bfee-04b3e2959ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541459493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.2541459493
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.1801631395
Short name T133
Test name
Test status
Simulation time 40952061633 ps
CPU time 18.67 seconds
Started Feb 18 12:40:54 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 183356 kb
Host smart-e0c5b24a-7064-4d8a-82a6-d1812cba8b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801631395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.1801631395
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1446811926
Short name T49
Test name
Test status
Simulation time 566655835 ps
CPU time 1.28 seconds
Started Feb 18 12:40:59 PM PST 24
Finished Feb 18 12:41:01 PM PST 24
Peak memory 183132 kb
Host smart-986712c3-93c4-4399-985d-97697ae91d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446811926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1446811926
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.802853618
Short name T265
Test name
Test status
Simulation time 78371675224 ps
CPU time 120.01 seconds
Started Feb 18 12:40:55 PM PST 24
Finished Feb 18 12:42:56 PM PST 24
Peak memory 183328 kb
Host smart-8364cc3f-fe97-4cfe-9c0e-660a92252de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802853618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.802853618
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1313103988
Short name T11
Test name
Test status
Simulation time 82512719878 ps
CPU time 612.64 seconds
Started Feb 18 12:40:57 PM PST 24
Finished Feb 18 12:51:11 PM PST 24
Peak memory 198832 kb
Host smart-025eb36c-fab1-4705-b8a4-e621c6474238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313103988 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1313103988
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1132714695
Short name T258
Test name
Test status
Simulation time 421002118 ps
CPU time 1.27 seconds
Started Feb 18 12:40:57 PM PST 24
Finished Feb 18 12:41:00 PM PST 24
Peak memory 183324 kb
Host smart-0dbfebb5-11b6-45ba-a5c8-f6bf5835b4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132714695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1132714695
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.721143796
Short name T234
Test name
Test status
Simulation time 61421755893 ps
CPU time 90.38 seconds
Started Feb 18 12:40:57 PM PST 24
Finished Feb 18 12:42:29 PM PST 24
Peak memory 183408 kb
Host smart-b49f4ffe-7e44-45fc-b8fa-6cb31b6554c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721143796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.721143796
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4017813176
Short name T143
Test name
Test status
Simulation time 570307134 ps
CPU time 0.75 seconds
Started Feb 18 12:40:54 PM PST 24
Finished Feb 18 12:40:56 PM PST 24
Peak memory 183300 kb
Host smart-b1dcd25a-43a9-4f78-873a-433c31a8afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017813176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4017813176
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2192087057
Short name T122
Test name
Test status
Simulation time 167679258203 ps
CPU time 58.4 seconds
Started Feb 18 12:40:55 PM PST 24
Finished Feb 18 12:41:55 PM PST 24
Peak memory 194736 kb
Host smart-68275965-ced5-4ae3-9076-011d6aa3c2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192087057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2192087057
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_jump.766768259
Short name T110
Test name
Test status
Simulation time 535553538 ps
CPU time 0.96 seconds
Started Feb 18 12:40:57 PM PST 24
Finished Feb 18 12:41:00 PM PST 24
Peak memory 183308 kb
Host smart-78af3602-6618-4787-b294-a97c8c08800a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766768259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.766768259
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2139913543
Short name T228
Test name
Test status
Simulation time 61645281482 ps
CPU time 45.26 seconds
Started Feb 18 12:40:59 PM PST 24
Finished Feb 18 12:41:45 PM PST 24
Peak memory 183288 kb
Host smart-907f1659-538b-4562-b985-3074642e810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139913543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2139913543
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3082293836
Short name T204
Test name
Test status
Simulation time 394660294 ps
CPU time 0.66 seconds
Started Feb 18 12:40:54 PM PST 24
Finished Feb 18 12:40:56 PM PST 24
Peak memory 183344 kb
Host smart-4443b581-a2d9-44c6-a8de-de3f0c693acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082293836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3082293836
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.150332112
Short name T190
Test name
Test status
Simulation time 108212222774 ps
CPU time 61.43 seconds
Started Feb 18 12:40:56 PM PST 24
Finished Feb 18 12:41:59 PM PST 24
Peak memory 193452 kb
Host smart-b1b2fa80-8635-4ff7-adb8-366938db85ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150332112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.150332112
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.360563971
Short name T83
Test name
Test status
Simulation time 147449251981 ps
CPU time 278.78 seconds
Started Feb 18 12:40:55 PM PST 24
Finished Feb 18 12:45:35 PM PST 24
Peak memory 198244 kb
Host smart-db0766cd-8c25-4626-84e1-9013661abdfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360563971 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.360563971
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1795125439
Short name T176
Test name
Test status
Simulation time 527977283 ps
CPU time 1.2 seconds
Started Feb 18 12:40:56 PM PST 24
Finished Feb 18 12:40:59 PM PST 24
Peak memory 183284 kb
Host smart-86d59375-5e56-437b-b20b-ca9bf9348973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795125439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1795125439
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1211354985
Short name T213
Test name
Test status
Simulation time 5184045200 ps
CPU time 7.45 seconds
Started Feb 18 12:40:56 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 183476 kb
Host smart-f6fa7868-cbd9-4dc1-b907-8ad26089accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211354985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1211354985
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.2603636328
Short name T151
Test name
Test status
Simulation time 610185553 ps
CPU time 0.71 seconds
Started Feb 18 12:40:55 PM PST 24
Finished Feb 18 12:40:57 PM PST 24
Peak memory 183184 kb
Host smart-ef409d39-6961-4483-a27c-b6d90615678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603636328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.2603636328
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1330343791
Short name T26
Test name
Test status
Simulation time 87364404379 ps
CPU time 490.58 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:49:28 PM PST 24
Peak memory 198204 kb
Host smart-37e31da2-b8f2-41e1-9912-c24c3cd823b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330343791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1330343791
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.768224928
Short name T161
Test name
Test status
Simulation time 511092242 ps
CPU time 1.02 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:40:22 PM PST 24
Peak memory 183328 kb
Host smart-c398e580-63a4-4e36-af45-4b54bc109b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768224928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.768224928
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.1434453175
Short name T174
Test name
Test status
Simulation time 23385685877 ps
CPU time 36.17 seconds
Started Feb 18 12:40:07 PM PST 24
Finished Feb 18 12:40:46 PM PST 24
Peak memory 183444 kb
Host smart-ce948bec-e52c-4556-81c0-9abcc151dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434453175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.1434453175
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.684188078
Short name T15
Test name
Test status
Simulation time 8518173436 ps
CPU time 13.97 seconds
Started Feb 18 12:40:10 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 215296 kb
Host smart-b24a8991-d80a-4706-a688-d28be15bd948
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684188078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.684188078
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2414111989
Short name T221
Test name
Test status
Simulation time 459292607 ps
CPU time 0.73 seconds
Started Feb 18 12:40:05 PM PST 24
Finished Feb 18 12:40:09 PM PST 24
Peak memory 183200 kb
Host smart-2bd5134a-75e8-46b0-8e08-98a9dc90ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414111989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2414111989
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.966086728
Short name T244
Test name
Test status
Simulation time 183229465484 ps
CPU time 120.2 seconds
Started Feb 18 12:40:15 PM PST 24
Finished Feb 18 12:42:24 PM PST 24
Peak memory 193620 kb
Host smart-7729d406-b005-4942-b372-243bb4034cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966086728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_al
l.966086728
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1378164932
Short name T266
Test name
Test status
Simulation time 65522281215 ps
CPU time 244.66 seconds
Started Feb 18 12:40:05 PM PST 24
Finished Feb 18 12:44:13 PM PST 24
Peak memory 198288 kb
Host smart-6aec036d-4b19-492e-a87a-401e4868a19c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378164932 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1378164932
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3769422726
Short name T233
Test name
Test status
Simulation time 474150101 ps
CPU time 1.31 seconds
Started Feb 18 12:41:03 PM PST 24
Finished Feb 18 12:41:07 PM PST 24
Peak memory 183368 kb
Host smart-23bb65f8-e4e7-4cdb-9112-c4548321b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769422726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3769422726
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1654491849
Short name T194
Test name
Test status
Simulation time 29820750909 ps
CPU time 46.55 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:42:03 PM PST 24
Peak memory 183312 kb
Host smart-a518a0d4-8dd8-4f24-9234-e3cc98ffb910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654491849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1654491849
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3381625936
Short name T210
Test name
Test status
Simulation time 464297404 ps
CPU time 1.12 seconds
Started Feb 18 12:41:11 PM PST 24
Finished Feb 18 12:41:17 PM PST 24
Peak memory 183368 kb
Host smart-c95878e6-d04a-404e-9d0d-d1b697ec23ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381625936 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3381625936
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2530601570
Short name T270
Test name
Test status
Simulation time 170841897036 ps
CPU time 119.02 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:43:09 PM PST 24
Peak memory 193448 kb
Host smart-d5d6f161-0938-4c2b-b554-d6e89c6275a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530601570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2530601570
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.579825559
Short name T211
Test name
Test status
Simulation time 189207158385 ps
CPU time 421.75 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:48:14 PM PST 24
Peak memory 198276 kb
Host smart-3901aa00-f1c1-4ba7-9242-7c5a7154bb6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579825559 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.579825559
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3979744796
Short name T100
Test name
Test status
Simulation time 491926405 ps
CPU time 1 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183364 kb
Host smart-f2fd6b6d-6fb7-41d8-9a09-7a91844c426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979744796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3979744796
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2894329999
Short name T208
Test name
Test status
Simulation time 736371688 ps
CPU time 0.61 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183248 kb
Host smart-9b79067c-6b90-44d3-a2e3-42bacee05ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894329999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2894329999
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.977528279
Short name T21
Test name
Test status
Simulation time 377815578 ps
CPU time 1.11 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183204 kb
Host smart-a5094d0c-6ae1-4e9e-8b2f-a61516a85cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977528279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.977528279
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.4144325339
Short name T238
Test name
Test status
Simulation time 44422390476 ps
CPU time 11.02 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:20 PM PST 24
Peak memory 183364 kb
Host smart-32ab1520-9e73-4c3d-8e3b-0381750dcaff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144325339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.4144325339
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1168063314
Short name T84
Test name
Test status
Simulation time 114204149945 ps
CPU time 123.82 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:43:13 PM PST 24
Peak memory 198392 kb
Host smart-806f2a48-39a4-46c9-8a14-fb8f3974e1a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168063314 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1168063314
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.573480300
Short name T25
Test name
Test status
Simulation time 451037286 ps
CPU time 0.72 seconds
Started Feb 18 12:41:03 PM PST 24
Finished Feb 18 12:41:06 PM PST 24
Peak memory 183316 kb
Host smart-bb3e219a-49f2-45e0-b8b1-5a98d3fa0031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573480300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.573480300
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3761982415
Short name T250
Test name
Test status
Simulation time 23619454741 ps
CPU time 17.33 seconds
Started Feb 18 12:41:04 PM PST 24
Finished Feb 18 12:41:24 PM PST 24
Peak memory 183320 kb
Host smart-89f2e34f-497d-4787-930d-7f30e00185ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761982415 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3761982415
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1735425954
Short name T135
Test name
Test status
Simulation time 597217326 ps
CPU time 0.76 seconds
Started Feb 18 12:41:04 PM PST 24
Finished Feb 18 12:41:08 PM PST 24
Peak memory 183432 kb
Host smart-052c0146-8828-4162-8802-05c0c0fb2b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735425954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1735425954
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.1280261561
Short name T186
Test name
Test status
Simulation time 5744746286 ps
CPU time 2.96 seconds
Started Feb 18 12:41:04 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183216 kb
Host smart-f4c69311-204d-4fef-82c6-2ed84cf1e9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280261561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.1280261561
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.3885874840
Short name T227
Test name
Test status
Simulation time 100401849042 ps
CPU time 323.15 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:46:33 PM PST 24
Peak memory 198260 kb
Host smart-f9bb6d84-ec16-4a83-9f92-1bdd762cf9ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885874840 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.3885874840
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.129585722
Short name T5
Test name
Test status
Simulation time 398417087 ps
CPU time 0.7 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:41:11 PM PST 24
Peak memory 183348 kb
Host smart-784b510a-6764-4dd5-ac0a-37ddc86cea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129585722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.129585722
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.1858710036
Short name T43
Test name
Test status
Simulation time 18085533097 ps
CPU time 26.17 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:41:36 PM PST 24
Peak memory 183300 kb
Host smart-96f41ff9-de16-4611-929b-72bf0d4a4067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858710036 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.1858710036
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.2179275882
Short name T156
Test name
Test status
Simulation time 411833452 ps
CPU time 0.76 seconds
Started Feb 18 12:41:04 PM PST 24
Finished Feb 18 12:41:08 PM PST 24
Peak memory 183160 kb
Host smart-782f14db-1dd0-4bb7-9f6a-b4f1778d0644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179275882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.2179275882
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2785930969
Short name T264
Test name
Test status
Simulation time 104971215955 ps
CPU time 26.45 seconds
Started Feb 18 12:41:03 PM PST 24
Finished Feb 18 12:41:33 PM PST 24
Peak memory 193256 kb
Host smart-febf7ccb-c803-42e6-96fe-c2b2818b23b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785930969 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2785930969
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1196967032
Short name T170
Test name
Test status
Simulation time 494843514 ps
CPU time 1.27 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183308 kb
Host smart-8b094b10-5427-4e8d-81f7-fe0cf11064e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196967032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1196967032
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3924231503
Short name T173
Test name
Test status
Simulation time 3158752057 ps
CPU time 1.81 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:10 PM PST 24
Peak memory 183380 kb
Host smart-3f5dd73b-f8a7-4fea-839b-c0a52bb71720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924231503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3924231503
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1000573082
Short name T51
Test name
Test status
Simulation time 459182473 ps
CPU time 1.17 seconds
Started Feb 18 12:41:02 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 183164 kb
Host smart-09a4b542-2f35-4867-b73d-b3ca8b994fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000573082 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1000573082
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1619965871
Short name T222
Test name
Test status
Simulation time 17456969053 ps
CPU time 24.52 seconds
Started Feb 18 12:41:05 PM PST 24
Finished Feb 18 12:41:34 PM PST 24
Peak memory 183456 kb
Host smart-ccdb8282-871b-424d-a0bb-86f6d0e2eca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619965871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1619965871
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1172759425
Short name T141
Test name
Test status
Simulation time 535656045 ps
CPU time 0.65 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:41:17 PM PST 24
Peak memory 183236 kb
Host smart-a498d008-ee09-4a2b-b00d-5b0602069225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172759425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1172759425
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.142770916
Short name T271
Test name
Test status
Simulation time 21735858583 ps
CPU time 16.48 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:41:28 PM PST 24
Peak memory 183452 kb
Host smart-f903e9bb-6232-4ab4-ae7c-03e7ca8b4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142770916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.142770916
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2371637109
Short name T185
Test name
Test status
Simulation time 608455244 ps
CPU time 0.82 seconds
Started Feb 18 12:41:06 PM PST 24
Finished Feb 18 12:41:12 PM PST 24
Peak memory 183084 kb
Host smart-f93a4d19-5611-443c-b728-b2ed425dd354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371637109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2371637109
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.125768739
Short name T18
Test name
Test status
Simulation time 270393691471 ps
CPU time 390.13 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:47:42 PM PST 24
Peak memory 183284 kb
Host smart-194ff294-4ca6-48a7-b2fe-b00b0f3620df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125768739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.125768739
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3985858793
Short name T32
Test name
Test status
Simulation time 40129228984 ps
CPU time 127.46 seconds
Started Feb 18 12:41:11 PM PST 24
Finished Feb 18 12:43:23 PM PST 24
Peak memory 198316 kb
Host smart-70ab797f-d21f-4105-9efb-8fd48afcaeab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985858793 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3985858793
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1087435873
Short name T29
Test name
Test status
Simulation time 400010700 ps
CPU time 0.86 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:41:13 PM PST 24
Peak memory 183396 kb
Host smart-1a99a155-7399-4645-8f1d-3bfcbc809c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087435873 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1087435873
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.4039287902
Short name T138
Test name
Test status
Simulation time 1433946908 ps
CPU time 1.62 seconds
Started Feb 18 12:41:09 PM PST 24
Finished Feb 18 12:41:17 PM PST 24
Peak memory 183336 kb
Host smart-c3da11c9-dcc0-4832-a0c7-417dfb8a4999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039287902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.4039287902
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.904555294
Short name T13
Test name
Test status
Simulation time 524616239 ps
CPU time 0.69 seconds
Started Feb 18 12:41:08 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 183200 kb
Host smart-67d0e6ce-c5ef-48e1-84c9-47f69f5e1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904555294 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.904555294
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.462441880
Short name T272
Test name
Test status
Simulation time 136312347775 ps
CPU time 97.47 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:42:55 PM PST 24
Peak memory 183428 kb
Host smart-d017ff45-96dc-4447-9608-32725b28d8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462441880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.462441880
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1958709968
Short name T79
Test name
Test status
Simulation time 62540877171 ps
CPU time 666.76 seconds
Started Feb 18 12:41:09 PM PST 24
Finished Feb 18 12:52:22 PM PST 24
Peak memory 198700 kb
Host smart-4677131d-bbc0-4ed6-9e63-51558c1d3e4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958709968 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1958709968
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1021451812
Short name T269
Test name
Test status
Simulation time 452355278 ps
CPU time 0.74 seconds
Started Feb 18 12:41:08 PM PST 24
Finished Feb 18 12:41:14 PM PST 24
Peak memory 183284 kb
Host smart-c080d094-18a0-4ec5-a210-171f5bd249d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021451812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1021451812
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3725314504
Short name T164
Test name
Test status
Simulation time 34076501190 ps
CPU time 52.84 seconds
Started Feb 18 12:41:10 PM PST 24
Finished Feb 18 12:42:08 PM PST 24
Peak memory 183328 kb
Host smart-7ba8d781-657e-4d0e-baf0-4ef3a9392bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725314504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3725314504
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.1646667380
Short name T280
Test name
Test status
Simulation time 367068612 ps
CPU time 0.78 seconds
Started Feb 18 12:41:10 PM PST 24
Finished Feb 18 12:41:16 PM PST 24
Peak memory 183256 kb
Host smart-add078f0-7b96-4be7-a422-73e90767749f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646667380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.1646667380
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2580011915
Short name T278
Test name
Test status
Simulation time 321633449724 ps
CPU time 205.19 seconds
Started Feb 18 12:41:08 PM PST 24
Finished Feb 18 12:44:39 PM PST 24
Peak memory 183304 kb
Host smart-525a02ba-106f-4908-bb25-7c0cbadc13fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580011915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2580011915
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.854382630
Short name T189
Test name
Test status
Simulation time 509810233 ps
CPU time 0.85 seconds
Started Feb 18 12:41:09 PM PST 24
Finished Feb 18 12:41:15 PM PST 24
Peak memory 183312 kb
Host smart-2c77f57a-69bf-4d7f-b8a4-d99180d7fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854382630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.854382630
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1439346308
Short name T175
Test name
Test status
Simulation time 19373712371 ps
CPU time 15.9 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:41:28 PM PST 24
Peak memory 183356 kb
Host smart-78bf2ef1-bbed-4d0c-9e29-8b9dba641591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439346308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1439346308
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.503930130
Short name T246
Test name
Test status
Simulation time 491019466 ps
CPU time 0.63 seconds
Started Feb 18 12:41:07 PM PST 24
Finished Feb 18 12:41:13 PM PST 24
Peak memory 183392 kb
Host smart-0eb5f350-4104-4ead-b97b-d8e90e9f6444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503930130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.503930130
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.2982444260
Short name T1
Test name
Test status
Simulation time 104260917847 ps
CPU time 15.23 seconds
Started Feb 18 12:41:10 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 183380 kb
Host smart-274f2543-49bd-4b16-a064-1054e2b75baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982444260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.2982444260
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1052285316
Short name T193
Test name
Test status
Simulation time 177298385079 ps
CPU time 753.29 seconds
Started Feb 18 12:41:08 PM PST 24
Finished Feb 18 12:53:47 PM PST 24
Peak memory 201140 kb
Host smart-b000ef9a-ed23-4384-9da7-bf23bedb574f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052285316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1052285316
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2718496196
Short name T241
Test name
Test status
Simulation time 578286877 ps
CPU time 1.36 seconds
Started Feb 18 12:41:09 PM PST 24
Finished Feb 18 12:41:16 PM PST 24
Peak memory 183380 kb
Host smart-abb6477e-c54a-4da7-812f-78e11ec40f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718496196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2718496196
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3479004636
Short name T169
Test name
Test status
Simulation time 24234963510 ps
CPU time 34.66 seconds
Started Feb 18 12:41:10 PM PST 24
Finished Feb 18 12:41:50 PM PST 24
Peak memory 183356 kb
Host smart-db935ddc-cfa1-41a8-b966-b0655656998c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479004636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3479004636
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.3441784796
Short name T147
Test name
Test status
Simulation time 539793216 ps
CPU time 0.58 seconds
Started Feb 18 12:41:13 PM PST 24
Finished Feb 18 12:41:18 PM PST 24
Peak memory 183188 kb
Host smart-b95af68b-4d33-4740-939d-c3e0a2add6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441784796 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.3441784796
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.156433444
Short name T124
Test name
Test status
Simulation time 80388694961 ps
CPU time 122.61 seconds
Started Feb 18 12:41:08 PM PST 24
Finished Feb 18 12:43:16 PM PST 24
Peak memory 183324 kb
Host smart-ed7615bc-b334-4f48-8f9d-62e549879907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156433444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.156433444
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2070492799
Short name T85
Test name
Test status
Simulation time 126876915753 ps
CPU time 233.43 seconds
Started Feb 18 12:41:12 PM PST 24
Finished Feb 18 12:45:11 PM PST 24
Peak memory 198276 kb
Host smart-27d5fed6-8d6d-4042-9d36-fb7f9720eb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070492799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2070492799
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.3964859797
Short name T154
Test name
Test status
Simulation time 511676326 ps
CPU time 0.75 seconds
Started Feb 18 12:40:07 PM PST 24
Finished Feb 18 12:40:10 PM PST 24
Peak memory 183296 kb
Host smart-ec3109fc-7bcf-4fe3-8c6f-76541666600b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964859797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.3964859797
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2173337014
Short name T202
Test name
Test status
Simulation time 13008210380 ps
CPU time 11.24 seconds
Started Feb 18 12:40:06 PM PST 24
Finished Feb 18 12:40:20 PM PST 24
Peak memory 183268 kb
Host smart-01cd56bf-a0a2-42b7-aeb3-7b272f04746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173337014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2173337014
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3471293768
Short name T166
Test name
Test status
Simulation time 355648440 ps
CPU time 1.08 seconds
Started Feb 18 12:40:09 PM PST 24
Finished Feb 18 12:40:13 PM PST 24
Peak memory 183312 kb
Host smart-3495c1d5-b8f8-4320-84d8-2d454fff296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471293768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3471293768
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1233365882
Short name T17
Test name
Test status
Simulation time 227818565514 ps
CPU time 99.65 seconds
Started Feb 18 12:40:11 PM PST 24
Finished Feb 18 12:41:57 PM PST 24
Peak memory 193644 kb
Host smart-a19fc4d7-edce-440c-b527-26fff1c902a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233365882 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1233365882
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1430343822
Short name T87
Test name
Test status
Simulation time 174111773523 ps
CPU time 1140.85 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:59:21 PM PST 24
Peak memory 203272 kb
Host smart-6fac24c6-266b-446a-9b3e-d6d1886adc0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430343822 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1430343822
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.4066807200
Short name T97
Test name
Test status
Simulation time 598487089 ps
CPU time 0.7 seconds
Started Feb 18 12:40:21 PM PST 24
Finished Feb 18 12:40:31 PM PST 24
Peak memory 183348 kb
Host smart-13ceabfd-e339-415f-b3dc-a3a0b6ced4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066807200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.4066807200
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.2114756850
Short name T44
Test name
Test status
Simulation time 11563893867 ps
CPU time 16.34 seconds
Started Feb 18 12:40:21 PM PST 24
Finished Feb 18 12:40:47 PM PST 24
Peak memory 183380 kb
Host smart-0daa57da-8737-4923-9f0a-8a704fdf221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114756850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.2114756850
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.461295068
Short name T242
Test name
Test status
Simulation time 482804252 ps
CPU time 1.28 seconds
Started Feb 18 12:40:10 PM PST 24
Finished Feb 18 12:40:19 PM PST 24
Peak memory 183208 kb
Host smart-2dc64a3c-094c-4b9d-bfa1-07e75572616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461295068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.461295068
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1961440378
Short name T128
Test name
Test status
Simulation time 115942682670 ps
CPU time 166.15 seconds
Started Feb 18 12:40:13 PM PST 24
Finished Feb 18 12:43:07 PM PST 24
Peak memory 183364 kb
Host smart-0bd6a090-2437-49c2-b07f-4cba2ab2796d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961440378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1961440378
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3218863575
Short name T118
Test name
Test status
Simulation time 408058377 ps
CPU time 0.69 seconds
Started Feb 18 12:40:11 PM PST 24
Finished Feb 18 12:40:19 PM PST 24
Peak memory 183332 kb
Host smart-994e6e8c-5d70-41c5-880d-222cb917ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218863575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3218863575
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2377362003
Short name T137
Test name
Test status
Simulation time 45062507406 ps
CPU time 69.76 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:41:29 PM PST 24
Peak memory 183340 kb
Host smart-63ce22bb-d320-4908-b9d7-ca80b18cdc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377362003 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2377362003
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3208944061
Short name T179
Test name
Test status
Simulation time 433598343 ps
CPU time 1.17 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:40:21 PM PST 24
Peak memory 183324 kb
Host smart-6d21b35b-07ba-40b1-be13-ff5340634475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208944061 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3208944061
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1521879397
Short name T224
Test name
Test status
Simulation time 390820259564 ps
CPU time 303.45 seconds
Started Feb 18 12:40:13 PM PST 24
Finished Feb 18 12:45:24 PM PST 24
Peak memory 183328 kb
Host smart-69a300b2-a3ae-4457-8a21-9165aea66ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521879397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1521879397
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.683486697
Short name T182
Test name
Test status
Simulation time 58231199190 ps
CPU time 79.75 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:41:39 PM PST 24
Peak memory 198356 kb
Host smart-3a0221fb-c908-4a58-9d24-b4f2f03636c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683486697 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.683486697
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.1418338207
Short name T113
Test name
Test status
Simulation time 534559838 ps
CPU time 1.31 seconds
Started Feb 18 12:40:14 PM PST 24
Finished Feb 18 12:40:23 PM PST 24
Peak memory 183268 kb
Host smart-b24b0c2f-7343-472e-ae93-430ad3617301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418338207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.1418338207
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1046275419
Short name T217
Test name
Test status
Simulation time 59029292827 ps
CPU time 43.06 seconds
Started Feb 18 12:40:13 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 183344 kb
Host smart-00a165a8-3c11-4547-9512-d48342cb0b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046275419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1046275419
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3505761426
Short name T253
Test name
Test status
Simulation time 400023851 ps
CPU time 0.67 seconds
Started Feb 18 12:40:14 PM PST 24
Finished Feb 18 12:40:22 PM PST 24
Peak memory 183188 kb
Host smart-0108afdd-e283-4f72-a904-ba122e273d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505761426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3505761426
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.787700927
Short name T80
Test name
Test status
Simulation time 113448507643 ps
CPU time 336.52 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:45:57 PM PST 24
Peak memory 198232 kb
Host smart-96cf60ae-7881-42de-a440-77e6e53d18ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787700927 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.787700927
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.4016258142
Short name T261
Test name
Test status
Simulation time 572542162 ps
CPU time 0.9 seconds
Started Feb 18 12:40:11 PM PST 24
Finished Feb 18 12:40:18 PM PST 24
Peak memory 183308 kb
Host smart-cb398738-bf21-42ce-9250-1c6e32599ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016258142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.4016258142
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.3050667412
Short name T201
Test name
Test status
Simulation time 36737981659 ps
CPU time 13.02 seconds
Started Feb 18 12:40:17 PM PST 24
Finished Feb 18 12:40:39 PM PST 24
Peak memory 183340 kb
Host smart-2ca1c2cd-8b73-43b2-8673-3fa670174807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050667412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.3050667412
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2917063049
Short name T245
Test name
Test status
Simulation time 447318591 ps
CPU time 0.68 seconds
Started Feb 18 12:40:13 PM PST 24
Finished Feb 18 12:40:22 PM PST 24
Peak memory 183164 kb
Host smart-2107e7d4-ab30-4ced-b3a4-9e8bfb6754de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917063049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2917063049
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.2033118026
Short name T106
Test name
Test status
Simulation time 85805066116 ps
CPU time 119.43 seconds
Started Feb 18 12:40:12 PM PST 24
Finished Feb 18 12:42:19 PM PST 24
Peak memory 193528 kb
Host smart-75e6216e-2573-41c1-8a8f-81cab4c1eed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033118026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.2033118026
Directory /workspace/9.aon_timer_stress_all/latest
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