Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 27988 1 T1 11 T3 164 T5 752
bark[1] 304 1 T15 6 T33 22 T86 12
bark[2] 241 1 T87 26 T88 16 T68 140
bark[3] 236 1 T22 22 T89 13 T87 16
bark[4] 268 1 T90 17 T91 41 T92 16
bark[5] 659 1 T14 12 T38 22 T78 16
bark[6] 149 1 T21 21 T74 70 T93 17
bark[7] 367 1 T5 16 T32 17 T35 184
bark[8] 866 1 T7 26 T32 242 T94 21
bark[9] 478 1 T9 31 T22 69 T95 26
bark[10] 323 1 T21 97 T94 21 T96 32
bark[11] 463 1 T32 17 T33 139 T97 16
bark[12] 356 1 T10 16 T90 50 T94 12
bark[13] 338 1 T3 17 T7 16 T32 16
bark[14] 496 1 T91 16 T75 45 T98 166
bark[15] 250 1 T2 12 T9 22 T38 26
bark[16] 566 1 T10 17 T36 17 T74 22
bark[17] 152 1 T9 13 T21 4 T93 16
bark[18] 649 1 T32 263 T34 84 T94 16
bark[19] 614 1 T91 16 T99 71 T100 17
bark[20] 179 1 T10 17 T101 12 T102 21
bark[21] 789 1 T32 170 T103 17 T34 226
bark[22] 679 1 T5 127 T38 16 T39 12
bark[23] 283 1 T12 12 T21 16 T23 12
bark[24] 650 1 T10 27 T38 30 T32 16
bark[25] 486 1 T9 53 T32 26 T104 17
bark[26] 720 1 T3 40 T21 6 T33 272
bark[27] 638 1 T33 39 T105 154 T88 81
bark[28] 523 1 T102 22 T106 17 T105 17
bark[29] 399 1 T10 16 T107 13 T91 27
bark[30] 424 1 T3 16 T9 53 T75 16
bark[31] 753 1 T10 219 T97 26 T108 16
bark_0 3591 1 T1 4 T2 4 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 27385 1 T1 10 T3 163 T5 708
bite[1] 459 1 T105 17 T109 11 T110 16
bite[2] 737 1 T10 44 T32 169 T75 44
bite[3] 589 1 T38 16 T101 11 T23 11
bite[4] 454 1 T21 3 T94 11 T87 17
bite[5] 539 1 T9 31 T10 201 T89 12
bite[6] 501 1 T32 16 T90 17 T102 21
bite[7] 263 1 T3 17 T12 11 T38 22
bite[8] 722 1 T32 26 T97 16 T106 22
bite[9] 772 1 T9 53 T105 11 T108 32
bite[10] 223 1 T111 20 T100 17 T112 17
bite[11] 409 1 T9 34 T33 22 T36 16
bite[12] 426 1 T2 11 T5 40 T106 16
bite[13] 802 1 T32 503 T103 17 T105 23
bite[14] 352 1 T10 16 T15 5 T94 21
bite[15] 687 1 T86 11 T87 26 T106 33
bite[16] 124 1 T21 5 T75 5 T100 17
bite[17] 236 1 T3 16 T22 21 T113 11
bite[18] 234 1 T9 53 T38 26 T88 80
bite[19] 360 1 T94 21 T106 32 T74 53
bite[20] 284 1 T107 12 T74 32 T75 16
bite[21] 546 1 T10 17 T39 11 T95 31
bite[22] 207 1 T22 68 T33 22 T106 12
bite[23] 692 1 T3 40 T7 26 T32 17
bite[24] 904 1 T5 131 T33 271 T34 225
bite[25] 148 1 T32 16 T93 16 T67 5
bite[26] 456 1 T21 112 T114 11 T90 49
bite[27] 379 1 T10 33 T14 11 T95 26
bite[28] 191 1 T5 16 T87 16 T108 16
bite[29] 618 1 T38 30 T91 27 T68 20
bite[30] 670 1 T61 11 T32 17 T115 11
bite[31] 413 1 T21 20 T32 17 T102 22
bite_0 4095 1 T1 5 T2 5 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 45877 1 T1 15 T2 16 T3 241


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 694 1 T15 2 T35 157 T87 30
prescale[1] 828 1 T9 25 T10 77 T15 61
prescale[2] 798 1 T15 2 T21 89 T95 15
prescale[3] 701 1 T5 46 T21 61 T32 70
prescale[4] 588 1 T7 45 T15 15 T21 2
prescale[5] 667 1 T7 25 T21 39 T62 8
prescale[6] 625 1 T3 31 T7 14 T35 2
prescale[7] 431 1 T10 2 T32 55 T116 8
prescale[8] 1040 1 T10 2 T11 8 T33 22
prescale[9] 716 1 T10 57 T21 93 T22 73
prescale[10] 1292 1 T21 4 T22 100 T32 53
prescale[11] 606 1 T10 16 T38 15 T32 85
prescale[12] 561 1 T5 2 T22 2 T32 98
prescale[13] 574 1 T3 15 T21 2 T22 4
prescale[14] 610 1 T95 76 T32 47 T33 4
prescale[15] 647 1 T22 34 T32 15 T33 30
prescale[16] 709 1 T5 2 T32 70 T87 26
prescale[17] 601 1 T5 2 T10 73 T117 8
prescale[18] 879 1 T9 15 T21 8 T22 8
prescale[19] 1163 1 T5 2 T7 21 T15 2
prescale[20] 705 1 T38 30 T32 39 T33 15
prescale[21] 750 1 T38 41 T32 8 T90 56
prescale[22] 537 1 T5 66 T21 44 T33 15
prescale[23] 849 1 T5 71 T9 24 T34 2
prescale[24] 512 1 T1 8 T5 2 T87 2
prescale[25] 624 1 T5 55 T10 88 T33 15
prescale[26] 694 1 T5 15 T21 27 T32 69
prescale[27] 678 1 T3 15 T5 8 T9 18
prescale[28] 347 1 T37 8 T32 31 T90 18
prescale[29] 591 1 T6 8 T9 15 T10 15
prescale[30] 687 1 T3 15 T5 144 T34 15
prescale[31] 735 1 T10 71 T32 12 T90 26
prescale_0 23438 1 T1 7 T2 16 T3 165


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33387 1 T1 6 T2 16 T3 141
auto[1] 12490 1 T1 9 T3 100 T5 131


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 45877 1 T1 15 T2 16 T3 241


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 27046 1 T1 12 T3 165 T5 557
wkup[1] 595 1 T5 48 T10 77 T32 71
wkup[2] 492 1 T10 27 T14 13 T21 22
wkup[3] 479 1 T5 32 T9 14 T38 22
wkup[4] 374 1 T32 48 T94 13 T75 16
wkup[5] 442 1 T3 23 T5 38 T21 16
wkup[6] 691 1 T21 24 T33 16 T34 16
wkup[7] 652 1 T3 16 T9 37 T10 13
wkup[8] 330 1 T9 16 T34 16 T106 14
wkup[9] 473 1 T21 32 T39 13 T32 32
wkup[10] 561 1 T10 16 T32 71 T34 16
wkup[11] 350 1 T15 16 T33 16 T87 42
wkup[12] 557 1 T5 53 T10 16 T32 30
wkup[13] 473 1 T9 16 T32 32 T36 29
wkup[14] 551 1 T95 16 T32 17 T33 22
wkup[15] 509 1 T32 26 T86 13 T36 17
wkup[16] 515 1 T3 17 T5 16 T10 33
wkup[17] 454 1 T7 16 T32 13 T33 22
wkup[18] 522 1 T5 16 T21 16 T38 26
wkup[19] 420 1 T5 26 T107 14 T32 32
wkup[20] 544 1 T2 13 T22 21 T32 29
wkup[21] 533 1 T5 42 T10 16 T12 13
wkup[22] 619 1 T5 13 T7 26 T22 16
wkup[23] 576 1 T21 16 T32 27 T33 16
wkup[24] 551 1 T7 16 T61 13 T95 36
wkup[25] 416 1 T5 16 T22 7 T95 26
wkup[26] 356 1 T9 16 T32 16 T34 16
wkup[27] 633 1 T5 16 T21 42 T22 26
wkup[28] 407 1 T15 16 T21 32 T22 32
wkup[29] 641 1 T3 17 T5 16 T9 16
wkup[30] 486 1 T5 16 T10 42 T21 27
wkup[31] 590 1 T21 23 T32 17 T33 22
wkup_0 3039 1 T1 3 T2 3 T3 3

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