Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.82 95.31 100.00 99.35 100.00 96.64


Total test records in report: 428
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T286 /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1252026615 Feb 21 12:31:58 PM PST 24 Feb 21 12:36:27 PM PST 24 100159647431 ps
T287 /workspace/coverage/default/42.aon_timer_stress_all.3825925556 Feb 21 12:32:20 PM PST 24 Feb 21 12:33:58 PM PST 24 125198425311 ps
T288 /workspace/coverage/default/7.aon_timer_prescaler.2723476523 Feb 21 12:32:01 PM PST 24 Feb 21 12:32:16 PM PST 24 15251770128 ps
T289 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2000593855 Feb 21 12:42:20 PM PST 24 Feb 21 12:42:22 PM PST 24 343762268 ps
T30 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1876406643 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:10 PM PST 24 1272081689 ps
T24 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2159601831 Feb 21 12:42:37 PM PST 24 Feb 21 12:42:39 PM PST 24 940197281 ps
T31 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3818079025 Feb 21 12:42:18 PM PST 24 Feb 21 12:42:19 PM PST 24 362532623 ps
T290 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.200924830 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:12 PM PST 24 419269474 ps
T291 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.290200560 Feb 21 12:41:56 PM PST 24 Feb 21 12:42:00 PM PST 24 481507620 ps
T25 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.956244754 Feb 21 12:42:19 PM PST 24 Feb 21 12:42:20 PM PST 24 557935104 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1094543973 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 364718316 ps
T293 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3861674140 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:16 PM PST 24 555920564 ps
T294 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1869726546 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:11 PM PST 24 363163457 ps
T26 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2648189320 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:20 PM PST 24 2307115710 ps
T295 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4103116408 Feb 21 12:42:15 PM PST 24 Feb 21 12:42:16 PM PST 24 489111799 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.828728875 Feb 21 12:42:01 PM PST 24 Feb 21 12:42:04 PM PST 24 733932642 ps
T297 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3424890109 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 483797707 ps
T298 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.203332194 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:15 PM PST 24 377855654 ps
T299 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1145139418 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 352362034 ps
T300 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3059621307 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 309898447 ps
T301 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3801155561 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 437393601 ps
T27 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.536323008 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:14 PM PST 24 4363168950 ps
T302 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.203919035 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:54 PM PST 24 328545183 ps
T55 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2854904225 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:12 PM PST 24 1975004374 ps
T40 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1682520490 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 342003672 ps
T28 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3940056320 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:13 PM PST 24 4244152654 ps
T303 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.408540598 Feb 21 12:42:15 PM PST 24 Feb 21 12:42:17 PM PST 24 337697336 ps
T304 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2540268144 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 476434020 ps
T56 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.376145619 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:13 PM PST 24 2114124353 ps
T305 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2838467438 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:08 PM PST 24 412231829 ps
T29 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2034331519 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:16 PM PST 24 7732248515 ps
T80 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2155488658 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:18 PM PST 24 4180131964 ps
T306 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1281333184 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:15 PM PST 24 551733321 ps
T307 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1172676257 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 454776070 ps
T308 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3928234001 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:10 PM PST 24 570989931 ps
T309 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3891995738 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:21 PM PST 24 6018482227 ps
T310 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2600070717 Feb 21 12:42:01 PM PST 24 Feb 21 12:42:05 PM PST 24 334147254 ps
T311 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.396075907 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:58 PM PST 24 729613878 ps
T312 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2341693116 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 310370603 ps
T313 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3820162500 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 482708417 ps
T314 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1080701411 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 406607353 ps
T315 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1242167479 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 400293483 ps
T316 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.679306596 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 533968586 ps
T317 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.384667577 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 291092760 ps
T318 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4140232917 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:11 PM PST 24 452929383 ps
T319 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1345976408 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 504509725 ps
T41 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1896661924 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:15 PM PST 24 683670580 ps
T320 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2951062604 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:10 PM PST 24 525950804 ps
T42 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1913085914 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 316839247 ps
T321 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4202097980 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:13 PM PST 24 445227846 ps
T322 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1225529940 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:12 PM PST 24 763110613 ps
T81 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.654862980 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:18 PM PST 24 7925661012 ps
T84 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.359633200 Feb 21 12:41:58 PM PST 24 Feb 21 12:42:06 PM PST 24 7569570162 ps
T323 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1149541403 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 372113390 ps
T57 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1601818106 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 1039794192 ps
T58 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2340585479 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:11 PM PST 24 2343180961 ps
T59 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.988555612 Feb 21 12:42:01 PM PST 24 Feb 21 12:42:05 PM PST 24 1085791451 ps
T324 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2147405163 Feb 21 12:42:01 PM PST 24 Feb 21 12:42:04 PM PST 24 580019586 ps
T60 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4065487445 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:52 PM PST 24 1343234211 ps
T325 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3056633234 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:13 PM PST 24 928958531 ps
T326 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.848174777 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:17 PM PST 24 423972154 ps
T327 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1868563140 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:11 PM PST 24 394961293 ps
T328 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2013658072 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 446829755 ps
T329 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1495026682 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 632055491 ps
T330 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2111816128 Feb 21 12:41:53 PM PST 24 Feb 21 12:42:00 PM PST 24 378333953 ps
T331 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1059011982 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 501575796 ps
T332 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2348136871 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 622651743 ps
T333 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2152665069 Feb 21 12:41:56 PM PST 24 Feb 21 12:42:10 PM PST 24 8168949359 ps
T334 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3195069709 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:32 PM PST 24 11702656710 ps
T43 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.40502079 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 542459829 ps
T335 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3729096520 Feb 21 12:41:58 PM PST 24 Feb 21 12:42:00 PM PST 24 508200012 ps
T336 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3213364067 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 443866404 ps
T337 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2266436051 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 484944315 ps
T44 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1325838886 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 358997424 ps
T338 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1713505010 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:12 PM PST 24 410456026 ps
T339 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1944146166 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 1683211535 ps
T340 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3960030493 Feb 21 12:41:57 PM PST 24 Feb 21 12:42:02 PM PST 24 1860988300 ps
T341 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.453418047 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:57 PM PST 24 3878098898 ps
T45 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1826656523 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:08 PM PST 24 407868182 ps
T85 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4219436660 Feb 21 12:41:49 PM PST 24 Feb 21 12:41:54 PM PST 24 8612099473 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1144611815 Feb 21 12:41:57 PM PST 24 Feb 21 12:41:59 PM PST 24 389721068 ps
T343 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.91519992 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:15 PM PST 24 413192014 ps
T46 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4185517905 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:18 PM PST 24 11325992508 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2820734083 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 758429109 ps
T345 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2141616066 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 486201531 ps
T346 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3739514577 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 362464682 ps
T347 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.564643647 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:07 PM PST 24 456574090 ps
T47 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1857761863 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:52 PM PST 24 459723054 ps
T348 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2448440411 Feb 21 12:42:14 PM PST 24 Feb 21 12:42:16 PM PST 24 411135100 ps
T349 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3200905925 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:22 PM PST 24 8697567756 ps
T350 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3215217824 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 359546498 ps
T351 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4246090624 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:13 PM PST 24 4657150715 ps
T53 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2093418517 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 337059509 ps
T352 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3673227459 Feb 21 12:41:59 PM PST 24 Feb 21 12:42:03 PM PST 24 502778102 ps
T353 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.454515208 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 327751936 ps
T354 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.537711349 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 340863900 ps
T355 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1358948549 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:24 PM PST 24 515603238 ps
T356 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2386767286 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:14 PM PST 24 600539256 ps
T357 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1708328596 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:22 PM PST 24 632689844 ps
T358 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3856089974 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:10 PM PST 24 643354537 ps
T359 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1285936422 Feb 21 12:42:40 PM PST 24 Feb 21 12:42:41 PM PST 24 363811169 ps
T48 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3181294074 Feb 21 12:42:16 PM PST 24 Feb 21 12:42:18 PM PST 24 293140623 ps
T360 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.677167432 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 517509193 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3019290190 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 405296903 ps
T362 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3115008201 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 380005992 ps
T363 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.704454699 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 389582667 ps
T82 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.203484381 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:55 PM PST 24 8269407169 ps
T54 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.136413558 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:06 PM PST 24 316904233 ps
T364 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3925066407 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 327033436 ps
T365 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1889237690 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:10 PM PST 24 1803460902 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2384696583 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 2410222415 ps
T367 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2650990930 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:12 PM PST 24 597064174 ps
T368 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3856883019 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:07 PM PST 24 324426815 ps
T369 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2965856023 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:09 PM PST 24 486499834 ps
T370 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1291315985 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:12 PM PST 24 421641068 ps
T371 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2228795740 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:57 PM PST 24 478426268 ps
T372 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1980847472 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:11 PM PST 24 300947353 ps
T83 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.36967709 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:15 PM PST 24 4412961246 ps
T373 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3431405386 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:14 PM PST 24 2098114406 ps
T374 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.388444006 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 340456947 ps
T375 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2899167880 Feb 21 12:42:04 PM PST 24 Feb 21 12:42:07 PM PST 24 447601862 ps
T49 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3063586107 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:11 PM PST 24 6558893253 ps
T50 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3126542639 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 474377379 ps
T376 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3150530933 Feb 21 12:42:18 PM PST 24 Feb 21 12:42:19 PM PST 24 459243187 ps
T377 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2535705106 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:19 PM PST 24 637572062 ps
T378 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4026566189 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:11 PM PST 24 290585416 ps
T379 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2041790063 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 502642749 ps
T380 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4041958085 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:19 PM PST 24 572976812 ps
T381 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3924209931 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 484901058 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3810396311 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:55 PM PST 24 344812004 ps
T383 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.797097506 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 1109462940 ps
T51 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2103652002 Feb 21 12:41:48 PM PST 24 Feb 21 12:41:50 PM PST 24 608407321 ps
T384 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2275535309 Feb 21 12:42:13 PM PST 24 Feb 21 12:42:19 PM PST 24 8427746327 ps
T385 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3658197865 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:19 PM PST 24 476974950 ps
T386 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3483394855 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:19 PM PST 24 464482116 ps
T387 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3239209836 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:10 PM PST 24 540930679 ps
T388 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4110306978 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:09 PM PST 24 9066867748 ps
T389 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.247167103 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:54 PM PST 24 341674333 ps
T390 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.714211984 Feb 21 12:41:54 PM PST 24 Feb 21 12:41:56 PM PST 24 1389740729 ps
T391 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.279272727 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 421580200 ps
T392 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.692726158 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:10 PM PST 24 288940466 ps
T393 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3199010843 Feb 21 12:42:14 PM PST 24 Feb 21 12:42:16 PM PST 24 484951382 ps
T394 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2257005044 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 503365261 ps
T395 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3250125272 Feb 21 12:42:15 PM PST 24 Feb 21 12:42:16 PM PST 24 355557019 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1520053543 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 2655970838 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3151517166 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:21 PM PST 24 5790799130 ps
T397 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.374170126 Feb 21 12:42:16 PM PST 24 Feb 21 12:42:19 PM PST 24 506705410 ps
T398 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3287927490 Feb 21 12:41:52 PM PST 24 Feb 21 12:41:53 PM PST 24 301085273 ps
T399 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1640793461 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:12 PM PST 24 2129576545 ps
T400 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3476750022 Feb 21 12:41:55 PM PST 24 Feb 21 12:41:58 PM PST 24 413527447 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4077417924 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 361544187 ps
T402 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1985646057 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:12 PM PST 24 389673309 ps
T403 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1943646844 Feb 21 12:41:50 PM PST 24 Feb 21 12:41:51 PM PST 24 329224889 ps
T404 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1776716279 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:15 PM PST 24 483262046 ps
T405 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2641859986 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 410037421 ps
T406 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2050943626 Feb 21 12:42:07 PM PST 24 Feb 21 12:42:09 PM PST 24 407428013 ps
T407 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2475637524 Feb 21 12:42:15 PM PST 24 Feb 21 12:42:17 PM PST 24 461620367 ps
T408 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1094751735 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 398231169 ps
T409 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3155147643 Feb 21 12:42:05 PM PST 24 Feb 21 12:42:08 PM PST 24 371774032 ps
T410 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1057458644 Feb 21 12:41:54 PM PST 24 Feb 21 12:42:01 PM PST 24 4118634460 ps
T411 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2071663407 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:23 PM PST 24 8568831263 ps
T412 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.54877251 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 897154257 ps
T413 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3432155178 Feb 21 12:42:17 PM PST 24 Feb 21 12:42:18 PM PST 24 683748659 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3960617315 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 400951609 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3760083868 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:13 PM PST 24 450319528 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2412418106 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:20 PM PST 24 4214261881 ps
T417 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1596090260 Feb 21 12:42:02 PM PST 24 Feb 21 12:42:05 PM PST 24 1258587983 ps
T418 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1810148926 Feb 21 12:42:11 PM PST 24 Feb 21 12:42:14 PM PST 24 437170118 ps
T419 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3904071584 Feb 21 12:42:27 PM PST 24 Feb 21 12:42:29 PM PST 24 294452584 ps
T420 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.402539911 Feb 21 12:42:09 PM PST 24 Feb 21 12:42:17 PM PST 24 4429067132 ps
T421 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.321511863 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:08 PM PST 24 331298916 ps
T422 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2513104043 Feb 21 12:42:08 PM PST 24 Feb 21 12:42:12 PM PST 24 2270204263 ps
T423 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3328741782 Feb 21 12:42:03 PM PST 24 Feb 21 12:42:07 PM PST 24 390871462 ps
T424 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3616037476 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:25 PM PST 24 311021057 ps
T425 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.953234885 Feb 21 12:42:12 PM PST 24 Feb 21 12:42:17 PM PST 24 1064606417 ps
T426 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4259364800 Feb 21 12:42:10 PM PST 24 Feb 21 12:42:15 PM PST 24 270697925 ps
T427 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3935775010 Feb 21 12:41:55 PM PST 24 Feb 21 12:42:00 PM PST 24 4076289701 ps
T428 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2909397854 Feb 21 12:42:06 PM PST 24 Feb 21 12:42:09 PM PST 24 559108295 ps

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.192709463
Short name T5
Test name
Test status
Simulation time 142572233638 ps
CPU time 531.83 seconds
Started Feb 21 12:32:04 PM PST 24
Finished Feb 21 12:40:57 PM PST 24
Peak memory 198620 kb
Host smart-8226c052-ccd8-4ca2-95e6-5360a47119c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192709463 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.192709463
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2412988015
Short name T21
Test name
Test status
Simulation time 36486547393 ps
CPU time 383.63 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:38:20 PM PST 24
Peak memory 198260 kb
Host smart-964f82dd-4484-4c7b-829f-2ea060e5a011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412988015 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2412988015
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.4070842622
Short name T32
Test name
Test status
Simulation time 640130894725 ps
CPU time 1121.58 seconds
Started Feb 21 12:33:03 PM PST 24
Finished Feb 21 12:51:46 PM PST 24
Peak memory 206664 kb
Host smart-b288d223-9205-4f7d-9822-7e08dde1c32b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070842622 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.4070842622
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2034331519
Short name T29
Test name
Test status
Simulation time 7732248515 ps
CPU time 11.44 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 197344 kb
Host smart-32316192-3b8d-4132-86dc-c460901b5c38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034331519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2034331519
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.3153808440
Short name T9
Test name
Test status
Simulation time 183320837802 ps
CPU time 135.36 seconds
Started Feb 21 12:32:23 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194636 kb
Host smart-2857f31d-ee22-4c1d-84cc-692ea9746774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153808440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.3153808440
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3240039805
Short name T16
Test name
Test status
Simulation time 4401946973 ps
CPU time 3.78 seconds
Started Feb 21 12:31:58 PM PST 24
Finished Feb 21 12:32:02 PM PST 24
Peak memory 215152 kb
Host smart-0ce6cf52-9edb-4c60-acba-7752a5fc0000
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240039805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3240039805
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.406843599
Short name T10
Test name
Test status
Simulation time 70509542852 ps
CPU time 372.34 seconds
Started Feb 21 12:32:34 PM PST 24
Finished Feb 21 12:38:48 PM PST 24
Peak memory 198296 kb
Host smart-45a71fbd-4362-4b10-a343-995b1fed0175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406843599 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.406843599
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3646787604
Short name T224
Test name
Test status
Simulation time 43094152390 ps
CPU time 409.96 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:39:01 PM PST 24
Peak memory 198412 kb
Host smart-a04febd0-56c4-471d-9134-fa68d2f2dd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646787604 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3646787604
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.1291771715
Short name T33
Test name
Test status
Simulation time 150600347790 ps
CPU time 425.74 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:39:03 PM PST 24
Peak memory 206532 kb
Host smart-6faf16cb-0ca0-446d-92ad-f268093c9581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291771715 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.1291771715
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2159601831
Short name T24
Test name
Test status
Simulation time 940197281 ps
CPU time 1.14 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:42:39 PM PST 24
Peak memory 193820 kb
Host smart-e573122e-8e0a-4b88-a648-905253c9d526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159601831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2159601831
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3112459310
Short name T243
Test name
Test status
Simulation time 350529340965 ps
CPU time 685.1 seconds
Started Feb 21 12:32:06 PM PST 24
Finished Feb 21 12:43:32 PM PST 24
Peak memory 200076 kb
Host smart-b5f90daf-3678-4d35-b216-8a258d7ef1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112459310 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3112459310
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.558923254
Short name T159
Test name
Test status
Simulation time 193622645264 ps
CPU time 47.65 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:58 PM PST 24
Peak memory 193788 kb
Host smart-f543545b-aba6-424c-aaa8-6a0961418b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558923254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.558923254
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.4285240035
Short name T111
Test name
Test status
Simulation time 367833115863 ps
CPU time 700.75 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:43:41 PM PST 24
Peak memory 200500 kb
Host smart-1e7298cf-4f5e-4fcf-989c-a656eaff0d10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285240035 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.4285240035
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.3126542639
Short name T50
Test name
Test status
Simulation time 474377379 ps
CPU time 1.16 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 193404 kb
Host smart-f38ce6de-b2f7-4ab9-be96-bb038187fbe3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126542639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.3126542639
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.856884330
Short name T105
Test name
Test status
Simulation time 305636254526 ps
CPU time 511.16 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:40:44 PM PST 24
Peak memory 198224 kb
Host smart-7abb78f4-f3c0-4d5c-a633-2d444f39f487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856884330 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.856884330
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.2275535309
Short name T384
Test name
Test status
Simulation time 8427746327 ps
CPU time 4.53 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 196928 kb
Host smart-6250785e-ee07-42a9-86b9-511ea009132a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275535309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.2275535309
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4185517905
Short name T46
Test name
Test status
Simulation time 11325992508 ps
CPU time 4.85 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 191668 kb
Host smart-b1f5f448-9396-4609-ba96-f3c7da56c326
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185517905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4185517905
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.1225529940
Short name T322
Test name
Test status
Simulation time 763110613 ps
CPU time 1.66 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183224 kb
Host smart-e61a8a5f-1fd7-458f-95bd-cc72c808781b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225529940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.1225529940
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2535705106
Short name T377
Test name
Test status
Simulation time 637572062 ps
CPU time 1.14 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 198248 kb
Host smart-5788a5ba-9d7f-4538-8028-865b5dec3997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535705106 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2535705106
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.3818079025
Short name T31
Test name
Test status
Simulation time 362532623 ps
CPU time 0.69 seconds
Started Feb 21 12:42:18 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 183588 kb
Host smart-a1c14fd9-2e43-4641-a92f-56b202853e83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818079025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.3818079025
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.203332194
Short name T298
Test name
Test status
Simulation time 377855654 ps
CPU time 0.65 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183092 kb
Host smart-480903d5-bf23-4653-9294-9455603f4198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203332194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.203332194
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1810148926
Short name T418
Test name
Test status
Simulation time 437170118 ps
CPU time 1.22 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:14 PM PST 24
Peak memory 183020 kb
Host smart-adf7798c-9f12-46a7-95c9-e9ba1de0a009
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810148926 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1810148926
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.1291315985
Short name T370
Test name
Test status
Simulation time 421641068 ps
CPU time 0.85 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183144 kb
Host smart-a22b50e1-ea80-40a9-a2bf-5c25eb77618e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291315985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.1291315985
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.797097506
Short name T383
Test name
Test status
Simulation time 1109462940 ps
CPU time 1.07 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 192864 kb
Host smart-1e2d2da0-df2a-479e-a238-39ba471f957c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797097506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.797097506
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.290200560
Short name T291
Test name
Test status
Simulation time 481507620 ps
CPU time 2.65 seconds
Started Feb 21 12:41:56 PM PST 24
Finished Feb 21 12:42:00 PM PST 24
Peak memory 198156 kb
Host smart-6f9fa645-3a3b-4b44-8917-0b6afa7576e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290200560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.290200560
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.3658197865
Short name T385
Test name
Test status
Simulation time 476974950 ps
CPU time 1.39 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 192548 kb
Host smart-0a5a36a7-732c-4940-9fac-b92b87410e1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658197865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.3658197865
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3891995738
Short name T309
Test name
Test status
Simulation time 6018482227 ps
CPU time 14.48 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:21 PM PST 24
Peak memory 183388 kb
Host smart-a9a41d71-cc3c-41fd-934b-5e77fe7de7fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891995738 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3891995738
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2820734083
Short name T344
Test name
Test status
Simulation time 758429109 ps
CPU time 0.85 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183240 kb
Host smart-ea30302e-fef1-4d76-a23e-e5b83905b9c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820734083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2820734083
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3673227459
Short name T352
Test name
Test status
Simulation time 502778102 ps
CPU time 0.82 seconds
Started Feb 21 12:41:59 PM PST 24
Finished Feb 21 12:42:03 PM PST 24
Peak memory 194852 kb
Host smart-10cb787a-d39a-40a9-8c91-050282f6428a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673227459 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3673227459
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.388444006
Short name T374
Test name
Test status
Simulation time 340456947 ps
CPU time 1.01 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183336 kb
Host smart-8641c773-f1b5-4425-b429-9e9a5ad178bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388444006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.388444006
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2000593855
Short name T289
Test name
Test status
Simulation time 343762268 ps
CPU time 0.95 seconds
Started Feb 21 12:42:20 PM PST 24
Finished Feb 21 12:42:22 PM PST 24
Peak memory 183092 kb
Host smart-b12e902b-58da-4b92-a634-7b0c140d158e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000593855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2000593855
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1144611815
Short name T342
Test name
Test status
Simulation time 389721068 ps
CPU time 0.62 seconds
Started Feb 21 12:41:57 PM PST 24
Finished Feb 21 12:41:59 PM PST 24
Peak memory 182764 kb
Host smart-66be0a9a-77fc-4839-890f-61778d1b22e4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144611815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1144611815
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.408540598
Short name T303
Test name
Test status
Simulation time 337697336 ps
CPU time 0.95 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 183096 kb
Host smart-d586bf3e-11e9-41f6-8025-fc590238991c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408540598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.408540598
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1520053543
Short name T396
Test name
Test status
Simulation time 2655970838 ps
CPU time 1.75 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 194972 kb
Host smart-8764bef1-aafc-4188-befd-fc7d0a123be5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520053543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1520053543
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2838467438
Short name T305
Test name
Test status
Simulation time 412231829 ps
CPU time 2.33 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 198148 kb
Host smart-b6b85702-b792-43c1-b199-e159a7e1dcb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838467438 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2838467438
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.203484381
Short name T82
Test name
Test status
Simulation time 8269407169 ps
CPU time 2.13 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 197164 kb
Host smart-fc1ac66c-c25d-435e-833f-7a10b266f71f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203484381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_
intg_err.203484381
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3213364067
Short name T336
Test name
Test status
Simulation time 443866404 ps
CPU time 1.35 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 195168 kb
Host smart-7377e43f-373b-47d0-b652-4c4825b75dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213364067 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3213364067
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.454515208
Short name T353
Test name
Test status
Simulation time 327751936 ps
CPU time 1.21 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 183376 kb
Host smart-79ec8452-f493-4dbf-8172-64a108da14e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454515208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.454515208
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2475637524
Short name T407
Test name
Test status
Simulation time 461620367 ps
CPU time 1.2 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 182968 kb
Host smart-ec6c9ad8-095e-4cfa-8390-90d98749cdc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475637524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2475637524
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1944146166
Short name T339
Test name
Test status
Simulation time 1683211535 ps
CPU time 1.11 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 193876 kb
Host smart-fd9ffcef-c2b6-404a-82e8-5b1f525cd1b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944146166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1944146166
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.564643647
Short name T347
Test name
Test status
Simulation time 456574090 ps
CPU time 1.86 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 198204 kb
Host smart-60b897b7-8a51-4b00-b9ea-a434df252812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564643647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.564643647
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.2152665069
Short name T333
Test name
Test status
Simulation time 8168949359 ps
CPU time 13.63 seconds
Started Feb 21 12:41:56 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 196976 kb
Host smart-76365407-06f4-42be-bb72-919db087412d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152665069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.2152665069
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.4077417924
Short name T401
Test name
Test status
Simulation time 361544187 ps
CPU time 1.03 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 194460 kb
Host smart-857eae52-af6b-4ffb-90ca-60b5a1a556f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077417924 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.4077417924
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.40502079
Short name T43
Test name
Test status
Simulation time 542459829 ps
CPU time 0.57 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183416 kb
Host smart-3d8f7759-8422-4d8d-b868-7881acf460d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40502079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.40502079
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.692726158
Short name T392
Test name
Test status
Simulation time 288940466 ps
CPU time 0.83 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 183160 kb
Host smart-d77d3308-a48a-4622-becc-435fc54a3ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692726158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.692726158
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3056633234
Short name T325
Test name
Test status
Simulation time 928958531 ps
CPU time 2.36 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 198168 kb
Host smart-e0467d64-fefc-4bf1-8191-ec57ad26f522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056633234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3056633234
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1057458644
Short name T410
Test name
Test status
Simulation time 4118634460 ps
CPU time 6.7 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:42:01 PM PST 24
Peak memory 196648 kb
Host smart-1510e180-19ab-40b6-b24d-6bdaf022aaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057458644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1057458644
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.1094751735
Short name T408
Test name
Test status
Simulation time 398231169 ps
CPU time 0.78 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 196096 kb
Host smart-c25580e6-1d1f-4d38-9922-f11e0c21402c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094751735 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.1094751735
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.1943646844
Short name T403
Test name
Test status
Simulation time 329224889 ps
CPU time 0.65 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 183372 kb
Host smart-d22353e3-494c-4619-8777-f61c80214782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943646844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.1943646844
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2341693116
Short name T312
Test name
Test status
Simulation time 310370603 ps
CPU time 0.66 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 183032 kb
Host smart-046be8cd-5995-4395-a345-f857e9b0733c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341693116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2341693116
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2340585479
Short name T58
Test name
Test status
Simulation time 2343180961 ps
CPU time 2.99 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 193068 kb
Host smart-f3b5367f-7ecf-4bd4-b85a-b690c4e84c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340585479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2340585479
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.953234885
Short name T425
Test name
Test status
Simulation time 1064606417 ps
CPU time 2.74 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 198372 kb
Host smart-ab930a5b-ce7e-40a7-9e63-a8ef91bb70f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953234885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.953234885
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.654862980
Short name T81
Test name
Test status
Simulation time 7925661012 ps
CPU time 4.26 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 197160 kb
Host smart-2dd466b5-78fa-4295-887d-f32e48bb86f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654862980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl
_intg_err.654862980
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3924209931
Short name T381
Test name
Test status
Simulation time 484901058 ps
CPU time 1.44 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 194528 kb
Host smart-8f20d579-1e2a-4a02-9ce3-b4ade4fffc30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924209931 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3924209931
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1913085914
Short name T42
Test name
Test status
Simulation time 316839247 ps
CPU time 0.76 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183372 kb
Host smart-957c6678-7e77-4d6b-8990-f11a6428761c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913085914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1913085914
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2266436051
Short name T337
Test name
Test status
Simulation time 484944315 ps
CPU time 1.23 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183072 kb
Host smart-718429ef-ff36-46ec-9680-b13c4655beab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266436051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2266436051
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1889237690
Short name T365
Test name
Test status
Simulation time 1803460902 ps
CPU time 2.1 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 191552 kb
Host smart-3159001e-8238-4708-a492-e700c4681950
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889237690 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1889237690
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.3861674140
Short name T293
Test name
Test status
Simulation time 555920564 ps
CPU time 1.43 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 198060 kb
Host smart-27e7d248-9b2e-40ba-88e8-4bc9e32e25cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861674140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.3861674140
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.3200905925
Short name T349
Test name
Test status
Simulation time 8697567756 ps
CPU time 12.41 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:22 PM PST 24
Peak memory 197144 kb
Host smart-4d139e75-3e3a-4384-ba8a-3f364b30dcd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200905925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.3200905925
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2147405163
Short name T324
Test name
Test status
Simulation time 580019586 ps
CPU time 0.79 seconds
Started Feb 21 12:42:01 PM PST 24
Finished Feb 21 12:42:04 PM PST 24
Peak memory 195072 kb
Host smart-b825e77a-2c31-4049-8473-55b01f927c02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147405163 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2147405163
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.1325838886
Short name T44
Test name
Test status
Simulation time 358997424 ps
CPU time 0.76 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183340 kb
Host smart-007c4500-7e80-4083-8098-4359cfd396ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325838886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.1325838886
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1985646057
Short name T402
Test name
Test status
Simulation time 389673309 ps
CPU time 0.68 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183072 kb
Host smart-778008f6-a75c-4ac6-96d2-eeb0b667110a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985646057 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1985646057
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1640793461
Short name T399
Test name
Test status
Simulation time 2129576545 ps
CPU time 1.52 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 193828 kb
Host smart-efdbf140-bd04-4e93-8ef8-c2fa35c80f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640793461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1640793461
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.679306596
Short name T316
Test name
Test status
Simulation time 533968586 ps
CPU time 1.31 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 198184 kb
Host smart-34bdfc3f-f115-4eff-9e3f-f5e33b590a82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679306596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.679306596
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2412418106
Short name T416
Test name
Test status
Simulation time 4214261881 ps
CPU time 7.92 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:20 PM PST 24
Peak memory 196836 kb
Host smart-ba7fd07e-9fe0-4ff7-83e8-f4a22da2d265
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412418106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2412418106
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1495026682
Short name T329
Test name
Test status
Simulation time 632055491 ps
CPU time 1.41 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 195876 kb
Host smart-6b50a7a9-beac-420a-a9e9-f64fc5e1f316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495026682 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1495026682
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2899167880
Short name T375
Test name
Test status
Simulation time 447601862 ps
CPU time 0.88 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183252 kb
Host smart-46002e9e-6ae3-41d8-98fa-dc7352cf09ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899167880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2899167880
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2228795740
Short name T371
Test name
Test status
Simulation time 478426268 ps
CPU time 0.68 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 183072 kb
Host smart-c6cf5df5-675c-4e79-911f-e5b57c095f96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228795740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2228795740
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.714211984
Short name T390
Test name
Test status
Simulation time 1389740729 ps
CPU time 1.51 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:56 PM PST 24
Peak memory 193528 kb
Host smart-85b7d464-8371-4563-9f4f-b87807d92021
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714211984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.714211984
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.704454699
Short name T363
Test name
Test status
Simulation time 389582667 ps
CPU time 1.68 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 198196 kb
Host smart-67fcf231-1f54-4a7e-8dee-77823cc78b00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704454699 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.704454699
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.4246090624
Short name T351
Test name
Test status
Simulation time 4657150715 ps
CPU time 2.54 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 195536 kb
Host smart-bd3203e9-edee-47ab-b819-96d6cb9ba7db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246090624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.4246090624
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3928234001
Short name T308
Test name
Test status
Simulation time 570989931 ps
CPU time 1.6 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 195000 kb
Host smart-693ba24e-dc88-489f-a35c-ecd8d5042bdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928234001 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3928234001
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1285936422
Short name T359
Test name
Test status
Simulation time 363811169 ps
CPU time 0.76 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 12:42:41 PM PST 24
Peak memory 183248 kb
Host smart-f973c126-45ca-4f48-aff2-b1b100126275
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285936422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1285936422
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2540268144
Short name T304
Test name
Test status
Simulation time 476434020 ps
CPU time 0.7 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183144 kb
Host smart-5f29abfe-012d-4db9-9a0c-cff818c49396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540268144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2540268144
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.4065487445
Short name T60
Test name
Test status
Simulation time 1343234211 ps
CPU time 1.43 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:52 PM PST 24
Peak memory 192720 kb
Host smart-2b2c76e4-313a-450a-96a0-594323c9c33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065487445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.4065487445
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.1345976408
Short name T319
Test name
Test status
Simulation time 504509725 ps
CPU time 1.36 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 198152 kb
Host smart-710b7547-62f8-4991-b5bc-9cb0c6e1a90c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345976408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.1345976408
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.4110306978
Short name T388
Test name
Test status
Simulation time 9066867748 ps
CPU time 3.98 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 197124 kb
Host smart-99d35e2b-d299-49b2-bf7c-3918ce2b78c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110306978 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.4110306978
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3199010843
Short name T393
Test name
Test status
Simulation time 484951382 ps
CPU time 0.97 seconds
Started Feb 21 12:42:14 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 197732 kb
Host smart-008247f0-7621-4b2b-b2c2-46681a51ca70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199010843 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3199010843
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2141616066
Short name T345
Test name
Test status
Simulation time 486201531 ps
CPU time 0.64 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:51 PM PST 24
Peak memory 183244 kb
Host smart-c5b2bb53-5806-4d04-a757-0b21f30a6bbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141616066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2141616066
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.321511863
Short name T421
Test name
Test status
Simulation time 331298916 ps
CPU time 1.08 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 183096 kb
Host smart-f6eb9a28-cb0a-47c9-84c7-00773acd2c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321511863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.321511863
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.1876406643
Short name T30
Test name
Test status
Simulation time 1272081689 ps
CPU time 3.33 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 192764 kb
Host smart-275e577f-b6d8-46a7-a7e1-6887a2bdd17d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876406643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.1876406643
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.2641859986
Short name T405
Test name
Test status
Simulation time 410037421 ps
CPU time 1.52 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 198004 kb
Host smart-3d90954e-f846-4a28-b6df-ffb0fff06016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641859986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.2641859986
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3940056320
Short name T28
Test name
Test status
Simulation time 4244152654 ps
CPU time 7.02 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 195696 kb
Host smart-249bb609-1440-4bcf-9d17-67423799885f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940056320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3940056320
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.2348136871
Short name T332
Test name
Test status
Simulation time 622651743 ps
CPU time 0.98 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 197180 kb
Host smart-06ea973e-e295-495f-bf0e-68d215077031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348136871 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.2348136871
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.136413558
Short name T54
Test name
Test status
Simulation time 316904233 ps
CPU time 0.98 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 183372 kb
Host smart-ad073197-52b3-4125-b8a6-d53500294d54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136413558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.136413558
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2013658072
Short name T328
Test name
Test status
Simulation time 446829755 ps
CPU time 0.78 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183276 kb
Host smart-93cb6609-33dd-45f9-a8f6-1e2f41ab95df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013658072 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2013658072
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2854904225
Short name T55
Test name
Test status
Simulation time 1975004374 ps
CPU time 2.11 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 192336 kb
Host smart-1b7ff38b-5099-473e-a3d7-e8c6fc9881ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854904225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2854904225
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3856089974
Short name T358
Test name
Test status
Simulation time 643354537 ps
CPU time 1.7 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 198284 kb
Host smart-6f13e915-a9c7-4366-90ca-c5beb5b7d020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856089974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3856089974
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.2071663407
Short name T411
Test name
Test status
Simulation time 8568831263 ps
CPU time 12.6 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:23 PM PST 24
Peak memory 197304 kb
Host smart-9c884a49-325c-4077-96fc-1a0a4a82f7da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071663407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.2071663407
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.3820162500
Short name T313
Test name
Test status
Simulation time 482708417 ps
CPU time 0.95 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 194664 kb
Host smart-f4e5f68a-2320-402a-9a3f-b40b9ab6a58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820162500 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.3820162500
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.384667577
Short name T317
Test name
Test status
Simulation time 291092760 ps
CPU time 1.05 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 183332 kb
Host smart-d24a8575-ac23-4c64-bfcf-bc563d63dfeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384667577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.384667577
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1145139418
Short name T299
Test name
Test status
Simulation time 352362034 ps
CPU time 0.68 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183520 kb
Host smart-26691bf6-de07-48ae-921e-df62f990ca3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145139418 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1145139418
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3431405386
Short name T373
Test name
Test status
Simulation time 2098114406 ps
CPU time 1.9 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:14 PM PST 24
Peak memory 191560 kb
Host smart-1eaf5bb6-6ac3-4daa-9063-25a0a114439a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431405386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3431405386
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2257005044
Short name T394
Test name
Test status
Simulation time 503365261 ps
CPU time 1.53 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 198020 kb
Host smart-79ba0a7f-e4bd-4f28-8dae-ce8721ccf1a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257005044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2257005044
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.536323008
Short name T27
Test name
Test status
Simulation time 4363168950 ps
CPU time 2.13 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:14 PM PST 24
Peak memory 196824 kb
Host smart-f537ae0c-92ee-4d17-94b0-b2c075a7c4f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536323008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.536323008
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.2103652002
Short name T51
Test name
Test status
Simulation time 608407321 ps
CPU time 1.54 seconds
Started Feb 21 12:41:48 PM PST 24
Finished Feb 21 12:41:50 PM PST 24
Peak memory 192668 kb
Host smart-113036c1-90b2-4198-8791-c11bf43327db
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103652002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.2103652002
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3151517166
Short name T52
Test name
Test status
Simulation time 5790799130 ps
CPU time 8.7 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:21 PM PST 24
Peak memory 183648 kb
Host smart-431dd667-edc5-482c-ac7c-a2ed680ba1bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151517166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3151517166
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.3432155178
Short name T413
Test name
Test status
Simulation time 683748659 ps
CPU time 0.73 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 183372 kb
Host smart-e6105187-7bfa-4002-97be-7752f0edab07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432155178 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.3432155178
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3810396311
Short name T382
Test name
Test status
Simulation time 344812004 ps
CPU time 1.16 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:55 PM PST 24
Peak memory 195092 kb
Host smart-2be74ce3-fcb2-47a9-9cb9-722df564627c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810396311 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3810396311
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1682520490
Short name T40
Test name
Test status
Simulation time 342003672 ps
CPU time 0.81 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 183356 kb
Host smart-556806f9-171b-4e4f-9399-cc3f1ef00d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682520490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1682520490
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.1869726546
Short name T294
Test name
Test status
Simulation time 363163457 ps
CPU time 1.12 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183096 kb
Host smart-a7290430-ba04-4460-8012-faf3b25421b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869726546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.1869726546
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3287927490
Short name T398
Test name
Test status
Simulation time 301085273 ps
CPU time 0.62 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:53 PM PST 24
Peak memory 182992 kb
Host smart-6f277c8d-9b93-4c82-b9e4-80dce25c83d4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287927490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3287927490
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.203919035
Short name T302
Test name
Test status
Simulation time 328545183 ps
CPU time 0.99 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 183096 kb
Host smart-f0978ef3-3f68-4583-859e-64a875fdc57c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203919035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_wa
lk.203919035
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2384696583
Short name T366
Test name
Test status
Simulation time 2410222415 ps
CPU time 1.54 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 194888 kb
Host smart-1f96e490-8040-4c4a-beca-4bc6c6e40f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384696583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2384696583
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.396075907
Short name T311
Test name
Test status
Simulation time 729613878 ps
CPU time 1.48 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:58 PM PST 24
Peak memory 198000 kb
Host smart-5a357d4c-129f-40b7-b8de-f11bdba635bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396075907 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.396075907
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.3935775010
Short name T427
Test name
Test status
Simulation time 4076289701 ps
CPU time 3.44 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:42:00 PM PST 24
Peak memory 197000 kb
Host smart-3b453da2-f049-494d-85cc-d1ab885a2045
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935775010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.3935775010
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.3925066407
Short name T364
Test name
Test status
Simulation time 327033436 ps
CPU time 0.98 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183144 kb
Host smart-6d899d9b-e96e-4c7c-87dc-a793a5fc20ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925066407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.3925066407
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.848174777
Short name T326
Test name
Test status
Simulation time 423972154 ps
CPU time 0.59 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 183028 kb
Host smart-657560cb-4383-4cd0-9ee1-baba8d229103
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848174777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.848174777
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3616037476
Short name T424
Test name
Test status
Simulation time 311021057 ps
CPU time 0.69 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:25 PM PST 24
Peak memory 183208 kb
Host smart-27347ce4-3d59-4e1e-8c40-5c7cff6d7b58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616037476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3616037476
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1980847472
Short name T372
Test name
Test status
Simulation time 300947353 ps
CPU time 0.63 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183092 kb
Host smart-f6e34a1a-ffcd-456a-9f76-17d3ad5c2502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980847472 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1980847472
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1172676257
Short name T307
Test name
Test status
Simulation time 454776070 ps
CPU time 0.65 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183092 kb
Host smart-cf1c2624-05a6-4b71-a51c-1aa3603196ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172676257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1172676257
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1776716279
Short name T404
Test name
Test status
Simulation time 483262046 ps
CPU time 1.05 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183520 kb
Host smart-853e423a-b417-4215-b85d-bf1ac57b006c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776716279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1776716279
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3059621307
Short name T300
Test name
Test status
Simulation time 309898447 ps
CPU time 0.78 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183076 kb
Host smart-c14f273b-6bd1-4d10-9f48-f0cc874dddd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059621307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3059621307
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3239209836
Short name T387
Test name
Test status
Simulation time 540930679 ps
CPU time 0.7 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 183092 kb
Host smart-9d41ee49-1c11-4651-a057-70f14b6f0636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239209836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3239209836
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1713505010
Short name T338
Test name
Test status
Simulation time 410456026 ps
CPU time 1.08 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183292 kb
Host smart-e24052fe-ca8c-4088-8e18-117eace4b215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713505010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1713505010
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.4140232917
Short name T318
Test name
Test status
Simulation time 452929383 ps
CPU time 0.69 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183076 kb
Host smart-c36c5dfc-2fc7-49f4-907d-f234c7701679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140232917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.4140232917
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1857761863
Short name T47
Test name
Test status
Simulation time 459723054 ps
CPU time 1.32 seconds
Started Feb 21 12:41:50 PM PST 24
Finished Feb 21 12:41:52 PM PST 24
Peak memory 183372 kb
Host smart-7462f36e-7f2c-4849-a481-2859316441c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857761863 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1857761863
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3063586107
Short name T49
Test name
Test status
Simulation time 6558893253 ps
CPU time 2.98 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 191776 kb
Host smart-873752d1-8a67-483c-a0c8-a9f4e1029263
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063586107 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3063586107
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.1896661924
Short name T41
Test name
Test status
Simulation time 683670580 ps
CPU time 0.69 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183408 kb
Host smart-484517f8-d25e-4075-bc84-627fe53438eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896661924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.1896661924
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.54877251
Short name T412
Test name
Test status
Simulation time 897154257 ps
CPU time 0.96 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 197956 kb
Host smart-cdff3719-4020-4339-98df-1f6a14df876c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54877251 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.54877251
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.537711349
Short name T354
Test name
Test status
Simulation time 340863900 ps
CPU time 1.04 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183260 kb
Host smart-80d74963-864d-455c-9150-3d3832b593e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537711349 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.537711349
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4259364800
Short name T426
Test name
Test status
Simulation time 270697925 ps
CPU time 0.91 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183280 kb
Host smart-e120789f-956c-4e42-8e12-d61fff15c2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259364800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4259364800
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.3115008201
Short name T362
Test name
Test status
Simulation time 380005992 ps
CPU time 0.65 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183028 kb
Host smart-db8aec00-fce0-46ca-ae7a-3d9170bdba15
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115008201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.3115008201
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3155147643
Short name T409
Test name
Test status
Simulation time 371774032 ps
CPU time 0.63 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 183212 kb
Host smart-51ac78d9-0407-4020-aec0-b8c707e3022f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155147643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3155147643
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1596090260
Short name T417
Test name
Test status
Simulation time 1258587983 ps
CPU time 0.97 seconds
Started Feb 21 12:42:02 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 193096 kb
Host smart-fbcc9759-b878-4ba9-b73c-dc2d95590514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596090260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1596090260
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1358948549
Short name T355
Test name
Test status
Simulation time 515603238 ps
CPU time 2.87 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:24 PM PST 24
Peak memory 198196 kb
Host smart-2dbc29c9-40b0-499f-ab76-6b9dad3097b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358948549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1358948549
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.453418047
Short name T341
Test name
Test status
Simulation time 3878098898 ps
CPU time 2.86 seconds
Started Feb 21 12:41:54 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 195596 kb
Host smart-4286117e-6d75-46c4-9958-820b53059063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453418047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.453418047
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3739514577
Short name T346
Test name
Test status
Simulation time 362464682 ps
CPU time 1.06 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 183060 kb
Host smart-d0ac920b-637c-4b31-ac46-e305a1bcc21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739514577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3739514577
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1868563140
Short name T327
Test name
Test status
Simulation time 394961293 ps
CPU time 0.69 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183076 kb
Host smart-b34bf146-e4d7-41cd-9464-405f954af873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868563140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1868563140
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.91519992
Short name T343
Test name
Test status
Simulation time 413192014 ps
CPU time 0.84 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 183120 kb
Host smart-e393ae51-736b-4d60-8916-9e208832bb6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91519992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.91519992
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.374170126
Short name T397
Test name
Test status
Simulation time 506705410 ps
CPU time 1.36 seconds
Started Feb 21 12:42:16 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 183296 kb
Host smart-51e9939b-7bd2-471a-a306-899118057483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374170126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.374170126
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3801155561
Short name T301
Test name
Test status
Simulation time 437393601 ps
CPU time 0.59 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183068 kb
Host smart-80753e7c-9ced-4f06-893a-4d240843c697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801155561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3801155561
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.4026566189
Short name T378
Test name
Test status
Simulation time 290585416 ps
CPU time 0.94 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183160 kb
Host smart-89bf0f9e-75ff-420e-add9-916c83c96fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026566189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.4026566189
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3424890109
Short name T297
Test name
Test status
Simulation time 483797707 ps
CPU time 1.03 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 182836 kb
Host smart-9b5d3ca3-3908-4d02-b26b-8d74bb379928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424890109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3424890109
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.4103116408
Short name T295
Test name
Test status
Simulation time 489111799 ps
CPU time 0.57 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 183304 kb
Host smart-83a1b75b-221f-49a8-893d-a17e9affdf18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103116408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.4103116408
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.279272727
Short name T391
Test name
Test status
Simulation time 421580200 ps
CPU time 1.19 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 182916 kb
Host smart-b05b82c5-92b0-41b7-bbba-edebda3bd3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279272727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.279272727
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3250125272
Short name T395
Test name
Test status
Simulation time 355557019 ps
CPU time 0.63 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 183092 kb
Host smart-0d6e77b7-e1ef-4f7f-9a14-dd38116316b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250125272 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3250125272
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2111816128
Short name T330
Test name
Test status
Simulation time 378333953 ps
CPU time 1.37 seconds
Started Feb 21 12:41:53 PM PST 24
Finished Feb 21 12:42:00 PM PST 24
Peak memory 192544 kb
Host smart-5562c682-f28b-4579-ad6e-37bc093e9751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111816128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2111816128
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3195069709
Short name T334
Test name
Test status
Simulation time 11702656710 ps
CPU time 22.87 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:32 PM PST 24
Peak memory 191760 kb
Host smart-45059ff3-6a19-4497-94b1-edf94dcf8873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195069709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3195069709
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.828728875
Short name T296
Test name
Test status
Simulation time 733932642 ps
CPU time 0.69 seconds
Started Feb 21 12:42:01 PM PST 24
Finished Feb 21 12:42:04 PM PST 24
Peak memory 183372 kb
Host smart-3002d10c-6383-44da-9450-eba2356cce1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828728875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_hw
_reset.828728875
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3215217824
Short name T350
Test name
Test status
Simulation time 359546498 ps
CPU time 1.05 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 196836 kb
Host smart-4edbe527-fb62-49f8-b9be-893b6dbba5ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215217824 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3215217824
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.3760083868
Short name T415
Test name
Test status
Simulation time 450319528 ps
CPU time 1.19 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 183376 kb
Host smart-b7fddf5d-9866-4d57-8179-37705e2234f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760083868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.3760083868
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1094543973
Short name T292
Test name
Test status
Simulation time 364718316 ps
CPU time 0.59 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183236 kb
Host smart-7ed93799-a7a7-477b-ad5c-3cccc1e4f4d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094543973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1094543973
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2951062604
Short name T320
Test name
Test status
Simulation time 525950804 ps
CPU time 0.72 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:10 PM PST 24
Peak memory 183264 kb
Host smart-fe1e62c3-29f6-459b-8669-457df714d252
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951062604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2951062604
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.3729096520
Short name T335
Test name
Test status
Simulation time 508200012 ps
CPU time 0.87 seconds
Started Feb 21 12:41:58 PM PST 24
Finished Feb 21 12:42:00 PM PST 24
Peak memory 183056 kb
Host smart-e308b058-4ccb-4017-b4d9-d90dbcbbe787
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729096520 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.3729096520
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.1601818106
Short name T57
Test name
Test status
Simulation time 1039794192 ps
CPU time 0.86 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 192832 kb
Host smart-4425b421-e383-43ba-9b55-34a198da9b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601818106 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.1601818106
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3019290190
Short name T361
Test name
Test status
Simulation time 405296903 ps
CPU time 1.88 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:57 PM PST 24
Peak memory 198104 kb
Host smart-1b07549b-28a0-491e-a318-0f04a71faa59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019290190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3019290190
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.36967709
Short name T83
Test name
Test status
Simulation time 4412961246 ps
CPU time 4.37 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 196904 kb
Host smart-886ab4fb-09ae-4fb8-956e-2dcb31dbaf1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36967709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_i
ntg_err.36967709
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3150530933
Short name T376
Test name
Test status
Simulation time 459243187 ps
CPU time 0.67 seconds
Started Feb 21 12:42:18 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 183296 kb
Host smart-c193c360-99dd-42a9-9ab2-665bb4f46a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150530933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3150530933
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1080701411
Short name T314
Test name
Test status
Simulation time 406607353 ps
CPU time 0.81 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 183180 kb
Host smart-4e268bb8-d22d-46ff-8831-2e97208462e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080701411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1080701411
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1149541403
Short name T323
Test name
Test status
Simulation time 372113390 ps
CPU time 1.11 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 182916 kb
Host smart-9239074e-de82-406d-98cd-36c8c9e971ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149541403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1149541403
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.3483394855
Short name T386
Test name
Test status
Simulation time 464482116 ps
CPU time 0.89 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 183512 kb
Host smart-42a0f0b1-3770-4dd4-b600-fbfbd59abec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483394855 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.3483394855
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.2600070717
Short name T310
Test name
Test status
Simulation time 334147254 ps
CPU time 1.05 seconds
Started Feb 21 12:42:01 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 183120 kb
Host smart-66d88b28-2326-40d8-b1a6-84702a8ebb1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600070717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.2600070717
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2050943626
Short name T406
Test name
Test status
Simulation time 407428013 ps
CPU time 1.11 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183100 kb
Host smart-f790a0c3-6341-4ce6-bcfe-a79304b99e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050943626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2050943626
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1242167479
Short name T315
Test name
Test status
Simulation time 400293483 ps
CPU time 1.05 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:11 PM PST 24
Peak memory 182984 kb
Host smart-00bd76ad-5ff8-410a-ac81-ec03dc369998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242167479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1242167479
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3904071584
Short name T419
Test name
Test status
Simulation time 294452584 ps
CPU time 1.01 seconds
Started Feb 21 12:42:27 PM PST 24
Finished Feb 21 12:42:29 PM PST 24
Peak memory 183048 kb
Host smart-d946672b-e30d-435d-8cc6-88426f08eb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904071584 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3904071584
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2041790063
Short name T379
Test name
Test status
Simulation time 502642749 ps
CPU time 0.69 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183048 kb
Host smart-e8eb0c78-e9ae-4d88-a9b1-0742ab31aab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041790063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2041790063
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2965856023
Short name T369
Test name
Test status
Simulation time 486499834 ps
CPU time 0.69 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183308 kb
Host smart-6ec53bfc-3340-4017-92fd-c0c82662cdbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965856023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2965856023
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.956244754
Short name T25
Test name
Test status
Simulation time 557935104 ps
CPU time 1.01 seconds
Started Feb 21 12:42:19 PM PST 24
Finished Feb 21 12:42:20 PM PST 24
Peak memory 195868 kb
Host smart-b5abf451-26d1-470d-a2c9-107d94fae04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956244754 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.956244754
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.2650990930
Short name T367
Test name
Test status
Simulation time 597064174 ps
CPU time 0.62 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183356 kb
Host smart-8842d0db-4beb-4627-a782-372ca3ffe7e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650990930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.2650990930
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.3960617315
Short name T414
Test name
Test status
Simulation time 400951609 ps
CPU time 0.66 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 183092 kb
Host smart-2d23ecf6-7ebf-4544-877d-6b5aeb3b7e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960617315 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.3960617315
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.988555612
Short name T59
Test name
Test status
Simulation time 1085791451 ps
CPU time 1.45 seconds
Started Feb 21 12:42:01 PM PST 24
Finished Feb 21 12:42:05 PM PST 24
Peak memory 193680 kb
Host smart-ef519876-b834-4ca3-829c-57bfc3d6e9fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988555612 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.988555612
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2386767286
Short name T356
Test name
Test status
Simulation time 600539256 ps
CPU time 2.87 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:14 PM PST 24
Peak memory 198128 kb
Host smart-f43e66e6-d1a7-4af8-a57b-b152ca7c018c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386767286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2386767286
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.4041958085
Short name T380
Test name
Test status
Simulation time 572976812 ps
CPU time 1.44 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:42:19 PM PST 24
Peak memory 194424 kb
Host smart-250a23ef-2c0a-4f0b-b6fc-264e31fd2d01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041958085 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.4041958085
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2448440411
Short name T348
Test name
Test status
Simulation time 411135100 ps
CPU time 0.68 seconds
Started Feb 21 12:42:14 PM PST 24
Finished Feb 21 12:42:16 PM PST 24
Peak memory 183376 kb
Host smart-87fd575d-a74b-4357-b739-0d3811f11324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448440411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2448440411
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.3328741782
Short name T423
Test name
Test status
Simulation time 390871462 ps
CPU time 0.61 seconds
Started Feb 21 12:42:03 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183108 kb
Host smart-2dc0d954-6831-4124-8d26-6a4282993064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328741782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.3328741782
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.3960030493
Short name T340
Test name
Test status
Simulation time 1860988300 ps
CPU time 3.33 seconds
Started Feb 21 12:41:57 PM PST 24
Finished Feb 21 12:42:02 PM PST 24
Peak memory 193704 kb
Host smart-0301ea66-6ded-4553-ac74-c3b6f0722664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960030493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.3960030493
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.4202097980
Short name T321
Test name
Test status
Simulation time 445227846 ps
CPU time 2.5 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 198216 kb
Host smart-21138645-dc9a-40a1-a0c5-890b1bf71d9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202097980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.4202097980
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2155488658
Short name T80
Test name
Test status
Simulation time 4180131964 ps
CPU time 6.68 seconds
Started Feb 21 12:42:11 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 196728 kb
Host smart-d4366011-a3c5-48a5-a0ee-bb4d7f93a4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155488658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2155488658
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2909397854
Short name T428
Test name
Test status
Simulation time 559108295 ps
CPU time 1.53 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 194752 kb
Host smart-a246a9dd-4029-42dd-b551-56082c85ec75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909397854 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2909397854
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.2093418517
Short name T53
Test name
Test status
Simulation time 337059509 ps
CPU time 0.69 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 183372 kb
Host smart-b333ffd0-fe94-44df-b46f-14988cf70f13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093418517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.2093418517
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.3856883019
Short name T368
Test name
Test status
Simulation time 324426815 ps
CPU time 0.96 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:07 PM PST 24
Peak memory 183160 kb
Host smart-cbdc68f3-91d5-4332-a128-378e78cd611e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856883019 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.3856883019
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2513104043
Short name T422
Test name
Test status
Simulation time 2270204263 ps
CPU time 2.83 seconds
Started Feb 21 12:42:08 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 192788 kb
Host smart-54a3a3da-d1da-4694-b146-0b0c9ba3bca0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513104043 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2513104043
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1708328596
Short name T357
Test name
Test status
Simulation time 632689844 ps
CPU time 1.6 seconds
Started Feb 21 12:42:10 PM PST 24
Finished Feb 21 12:42:22 PM PST 24
Peak memory 198144 kb
Host smart-f8710ed5-0845-4e82-b9e8-b024fbc57dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708328596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1708328596
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.402539911
Short name T420
Test name
Test status
Simulation time 4429067132 ps
CPU time 6.69 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:17 PM PST 24
Peak memory 196832 kb
Host smart-d91da437-fb7d-4f2f-b5b6-f0c1a03e4239
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402539911 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.402539911
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.677167432
Short name T360
Test name
Test status
Simulation time 517509193 ps
CPU time 1.43 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 194048 kb
Host smart-b5f38b2a-138d-493b-b499-7c0f20b56468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677167432 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.677167432
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.3181294074
Short name T48
Test name
Test status
Simulation time 293140623 ps
CPU time 0.99 seconds
Started Feb 21 12:42:16 PM PST 24
Finished Feb 21 12:42:18 PM PST 24
Peak memory 183384 kb
Host smart-18b8051b-d805-4434-bfa9-9b8001102641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181294074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.3181294074
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3476750022
Short name T400
Test name
Test status
Simulation time 413527447 ps
CPU time 1.07 seconds
Started Feb 21 12:41:55 PM PST 24
Finished Feb 21 12:41:58 PM PST 24
Peak memory 183192 kb
Host smart-f1c1e235-bcbd-41f6-87bb-61056435463d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476750022 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3476750022
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.376145619
Short name T56
Test name
Test status
Simulation time 2114124353 ps
CPU time 2.06 seconds
Started Feb 21 12:42:05 PM PST 24
Finished Feb 21 12:42:13 PM PST 24
Peak memory 192848 kb
Host smart-524e5115-d517-47e0-93c9-4105c0ac14b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376145619 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_
timer_same_csr_outstanding.376145619
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.247167103
Short name T389
Test name
Test status
Simulation time 341674333 ps
CPU time 1.71 seconds
Started Feb 21 12:41:52 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 198108 kb
Host smart-a9453402-ac73-46c8-98ba-e6b2957baf9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247167103 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.247167103
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.359633200
Short name T84
Test name
Test status
Simulation time 7569570162 ps
CPU time 6.59 seconds
Started Feb 21 12:41:58 PM PST 24
Finished Feb 21 12:42:06 PM PST 24
Peak memory 197052 kb
Host smart-88d38696-346b-465d-b90b-68e2990e200a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359633200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_
intg_err.359633200
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1281333184
Short name T306
Test name
Test status
Simulation time 551733321 ps
CPU time 1.01 seconds
Started Feb 21 12:42:13 PM PST 24
Finished Feb 21 12:42:15 PM PST 24
Peak memory 196232 kb
Host smart-78c4d009-c054-4773-a718-a359a03f6ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281333184 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1281333184
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1826656523
Short name T45
Test name
Test status
Simulation time 407868182 ps
CPU time 1.23 seconds
Started Feb 21 12:42:04 PM PST 24
Finished Feb 21 12:42:08 PM PST 24
Peak memory 183260 kb
Host smart-f18f5123-1a21-4960-b379-afe3fbb4c0bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826656523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1826656523
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.1059011982
Short name T331
Test name
Test status
Simulation time 501575796 ps
CPU time 0.89 seconds
Started Feb 21 12:42:06 PM PST 24
Finished Feb 21 12:42:09 PM PST 24
Peak memory 183072 kb
Host smart-a5855c25-d0bc-45b8-ae91-dfdc76bda81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059011982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.1059011982
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2648189320
Short name T26
Test name
Test status
Simulation time 2307115710 ps
CPU time 6.26 seconds
Started Feb 21 12:42:07 PM PST 24
Finished Feb 21 12:42:20 PM PST 24
Peak memory 193140 kb
Host smart-d6949b65-a850-47e8-9873-e014cd16302c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648189320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2648189320
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.200924830
Short name T290
Test name
Test status
Simulation time 419269474 ps
CPU time 1.71 seconds
Started Feb 21 12:42:09 PM PST 24
Finished Feb 21 12:42:12 PM PST 24
Peak memory 198144 kb
Host smart-ace75d20-3507-4509-9e0d-4f9ac37c43d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200924830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.200924830
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.4219436660
Short name T85
Test name
Test status
Simulation time 8612099473 ps
CPU time 4.26 seconds
Started Feb 21 12:41:49 PM PST 24
Finished Feb 21 12:41:54 PM PST 24
Peak memory 197248 kb
Host smart-1b95873c-e8b1-41c8-8791-6e131faf59df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219436660 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.4219436660
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1881715754
Short name T137
Test name
Test status
Simulation time 407492518 ps
CPU time 1.17 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:31:58 PM PST 24
Peak memory 183288 kb
Host smart-d5620cbc-4910-46d3-a1b3-a50a1912388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881715754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1881715754
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.771674173
Short name T222
Test name
Test status
Simulation time 40362973331 ps
CPU time 14.46 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183172 kb
Host smart-13b5e62e-31f3-4512-bd00-51af8381e0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771674173 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.771674173
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.778780908
Short name T168
Test name
Test status
Simulation time 658680217 ps
CPU time 0.62 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 182624 kb
Host smart-1438592b-0d5f-42f5-bdb5-979bffe504f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778780908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.778780908
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3246584473
Short name T165
Test name
Test status
Simulation time 103162833994 ps
CPU time 47.69 seconds
Started Feb 21 12:31:52 PM PST 24
Finished Feb 21 12:32:40 PM PST 24
Peak memory 183284 kb
Host smart-42cbd1f2-9e4a-4f19-b22c-a11256227183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246584473 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3246584473
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.297966864
Short name T261
Test name
Test status
Simulation time 419348637 ps
CPU time 1.19 seconds
Started Feb 21 12:31:58 PM PST 24
Finished Feb 21 12:32:00 PM PST 24
Peak memory 183636 kb
Host smart-a9c8ff84-2e17-4c0e-80b9-cbc7b2833f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297966864 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.297966864
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.588858383
Short name T174
Test name
Test status
Simulation time 26725311140 ps
CPU time 4.29 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:06 PM PST 24
Peak memory 183400 kb
Host smart-e57e0eb9-9641-43ce-a48c-c11fcb6dd095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588858383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.588858383
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1719954116
Short name T17
Test name
Test status
Simulation time 4707899995 ps
CPU time 1.08 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:32:04 PM PST 24
Peak memory 215192 kb
Host smart-81c49781-670d-4a1d-9fcb-693caa846a29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719954116 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1719954116
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.883939730
Short name T272
Test name
Test status
Simulation time 442083325 ps
CPU time 1.24 seconds
Started Feb 21 12:31:58 PM PST 24
Finished Feb 21 12:32:00 PM PST 24
Peak memory 183632 kb
Host smart-508eeef4-5c60-4149-b95e-f39c4c84c317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883939730 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.883939730
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1266463341
Short name T187
Test name
Test status
Simulation time 153736398975 ps
CPU time 120.19 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:34:04 PM PST 24
Peak memory 194664 kb
Host smart-5095b652-1d27-4282-b95b-a1cf8a500a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266463341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1266463341
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2502957329
Short name T131
Test name
Test status
Simulation time 575683905 ps
CPU time 0.81 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183256 kb
Host smart-c33c2313-6f28-4d8e-8d04-d5b13d4214e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502957329 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2502957329
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.4273410842
Short name T265
Test name
Test status
Simulation time 52817962419 ps
CPU time 80.13 seconds
Started Feb 21 12:31:58 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 183288 kb
Host smart-1e2fa594-854f-483c-b7d0-a2a82876105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273410842 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.4273410842
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3354626692
Short name T157
Test name
Test status
Simulation time 504052192 ps
CPU time 0.72 seconds
Started Feb 21 12:31:55 PM PST 24
Finished Feb 21 12:31:56 PM PST 24
Peak memory 183152 kb
Host smart-628d76f3-404a-4d1d-ba48-9891682b1962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354626692 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3354626692
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2516457081
Short name T103
Test name
Test status
Simulation time 88098077596 ps
CPU time 145.58 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:34:46 PM PST 24
Peak memory 182652 kb
Host smart-92d68b7b-132d-4309-adfd-dddba659c57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516457081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2516457081
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1584236903
Short name T267
Test name
Test status
Simulation time 21249266249 ps
CPU time 169.54 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 198232 kb
Host smart-c4476b76-544c-4c6e-bd64-2084c28ab601
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584236903 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1584236903
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.534380326
Short name T133
Test name
Test status
Simulation time 493747037 ps
CPU time 0.74 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:01 PM PST 24
Peak memory 183272 kb
Host smart-1e085a0a-061a-4b19-9f59-480149f41ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534380326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.534380326
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.41624227
Short name T182
Test name
Test status
Simulation time 30433530535 ps
CPU time 12.39 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:32:16 PM PST 24
Peak memory 183312 kb
Host smart-0b785cc4-c37c-48f3-9161-649f2581cd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41624227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.41624227
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3286825860
Short name T162
Test name
Test status
Simulation time 402610216 ps
CPU time 1.08 seconds
Started Feb 21 12:31:59 PM PST 24
Finished Feb 21 12:32:00 PM PST 24
Peak memory 183144 kb
Host smart-59405ac4-3fbb-429d-938d-bceb0b8a9385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286825860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3286825860
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.3458465687
Short name T189
Test name
Test status
Simulation time 477822121967 ps
CPU time 293.31 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:36:50 PM PST 24
Peak memory 191532 kb
Host smart-f313a329-d504-411c-a3e9-e5f213e312bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458465687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.3458465687
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.450300962
Short name T129
Test name
Test status
Simulation time 521857571 ps
CPU time 1.32 seconds
Started Feb 21 12:32:04 PM PST 24
Finished Feb 21 12:32:06 PM PST 24
Peak memory 183272 kb
Host smart-5b9633ba-56f1-4997-be46-291e52cf7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450300962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.450300962
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3228809772
Short name T117
Test name
Test status
Simulation time 33180821624 ps
CPU time 50.31 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:51 PM PST 24
Peak memory 183712 kb
Host smart-057a62e5-46d6-4a3e-81b7-8900678bd076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228809772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3228809772
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.378857616
Short name T127
Test name
Test status
Simulation time 525024429 ps
CPU time 0.75 seconds
Started Feb 21 12:31:55 PM PST 24
Finished Feb 21 12:31:56 PM PST 24
Peak memory 183160 kb
Host smart-aa518805-42c4-467f-9275-774b6ad1d278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378857616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.378857616
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.4139608698
Short name T180
Test name
Test status
Simulation time 66053643224 ps
CPU time 13.32 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183376 kb
Host smart-56f71886-6074-4118-809f-baadb0b087e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139608698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.4139608698
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3412446159
Short name T254
Test name
Test status
Simulation time 49380168981 ps
CPU time 373.91 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:38:11 PM PST 24
Peak memory 198168 kb
Host smart-6286fa95-7eb5-46e0-8c29-cc6bf625d65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412446159 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3412446159
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1283525783
Short name T280
Test name
Test status
Simulation time 448626973 ps
CPU time 1.2 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:32:04 PM PST 24
Peak memory 183244 kb
Host smart-55ed9691-013e-441d-8b9d-1256fe20d521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283525783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1283525783
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.4137907056
Short name T6
Test name
Test status
Simulation time 37412576337 ps
CPU time 13.64 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:32:17 PM PST 24
Peak memory 183324 kb
Host smart-318191a3-a455-4787-9d74-b28204dad781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137907056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.4137907056
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2917997781
Short name T134
Test name
Test status
Simulation time 562947359 ps
CPU time 0.66 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183188 kb
Host smart-a9c360b9-908f-4d00-8994-39514a918132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917997781 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2917997781
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.4056517445
Short name T200
Test name
Test status
Simulation time 100432908584 ps
CPU time 59.98 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:33:03 PM PST 24
Peak memory 183304 kb
Host smart-e20cd81e-e7a2-4150-8c71-725322a632fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056517445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.4056517445
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2786122146
Short name T74
Test name
Test status
Simulation time 86249082866 ps
CPU time 622.38 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:42:25 PM PST 24
Peak memory 199340 kb
Host smart-e8e3509e-8c2c-4566-8bd2-bb3cb5439e14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786122146 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2786122146
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.1291572587
Short name T166
Test name
Test status
Simulation time 372317060 ps
CPU time 0.71 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183296 kb
Host smart-56fd1532-62c9-4079-a9db-52fe9af92bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291572587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.1291572587
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.4186872575
Short name T116
Test name
Test status
Simulation time 9871467386 ps
CPU time 4.03 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183280 kb
Host smart-255c13c3-7b0b-482a-8025-e3afbca69f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186872575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.4186872575
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.4087226310
Short name T244
Test name
Test status
Simulation time 335565707 ps
CPU time 0.81 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183188 kb
Host smart-fd283874-445f-448c-b3ff-00d485c2ad64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087226310 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4087226310
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1754423980
Short name T108
Test name
Test status
Simulation time 110454785685 ps
CPU time 41.91 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:42 PM PST 24
Peak memory 193416 kb
Host smart-915c06ae-81bc-43a9-b3b7-2dcf14830c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754423980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1754423980
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.697650956
Short name T15
Test name
Test status
Simulation time 42624822309 ps
CPU time 87.02 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:33:24 PM PST 24
Peak memory 198264 kb
Host smart-8352e43c-03ba-43ef-a1ab-765d0f1bdf68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697650956 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.697650956
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.4075630678
Short name T89
Test name
Test status
Simulation time 433762662 ps
CPU time 0.72 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183264 kb
Host smart-107db5e8-6a57-4b55-a115-5ef8c7dffc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075630678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.4075630678
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.726083979
Short name T276
Test name
Test status
Simulation time 24667699809 ps
CPU time 9.63 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:32:12 PM PST 24
Peak memory 183272 kb
Host smart-6becab6d-1148-4fd9-90ce-c8c72e95d205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726083979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.726083979
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.3417022453
Short name T141
Test name
Test status
Simulation time 565772266 ps
CPU time 0.8 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:32:04 PM PST 24
Peak memory 183192 kb
Host smart-8d8f7c65-ada4-472c-a322-7850f32ae152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417022453 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.3417022453
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.4055858639
Short name T225
Test name
Test status
Simulation time 75403681098 ps
CPU time 118.95 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:34:01 PM PST 24
Peak memory 183396 kb
Host smart-4c29b335-d215-4990-8782-03f9643822af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055858639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.4055858639
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2111632061
Short name T110
Test name
Test status
Simulation time 150084034895 ps
CPU time 69.05 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 198212 kb
Host smart-9b78f4d6-5669-4b74-8f7c-81da16dffab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111632061 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2111632061
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.379646308
Short name T86
Test name
Test status
Simulation time 388056949 ps
CPU time 1.17 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183180 kb
Host smart-6d2fb9b6-b88a-4e68-a49e-3d59063cc9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379646308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.379646308
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3395360515
Short name T273
Test name
Test status
Simulation time 23290807566 ps
CPU time 9.46 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:32:12 PM PST 24
Peak memory 183224 kb
Host smart-789693b1-c5fa-42fc-a001-2261cc160c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395360515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3395360515
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.762848459
Short name T167
Test name
Test status
Simulation time 453944745 ps
CPU time 0.94 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:32:04 PM PST 24
Peak memory 183080 kb
Host smart-397ad990-432f-4509-8b2b-11954a506630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762848459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.762848459
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2793137422
Short name T146
Test name
Test status
Simulation time 11665656727 ps
CPU time 3.22 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183424 kb
Host smart-675716e7-48c0-460f-bdb2-6a8839a8f3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793137422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2793137422
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1951858954
Short name T107
Test name
Test status
Simulation time 352459130 ps
CPU time 1.1 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:31:58 PM PST 24
Peak memory 183264 kb
Host smart-a2d05d0b-fd38-4a7f-ab90-61d99f7f136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951858954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1951858954
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2852698073
Short name T236
Test name
Test status
Simulation time 38258964452 ps
CPU time 5.95 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183300 kb
Host smart-0b49870f-1201-4f7d-9e00-6b29fafcec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852698073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2852698073
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.1892453930
Short name T241
Test name
Test status
Simulation time 468944977 ps
CPU time 0.69 seconds
Started Feb 21 12:32:04 PM PST 24
Finished Feb 21 12:32:05 PM PST 24
Peak memory 183288 kb
Host smart-cc4e5735-2f57-4114-8f58-99d3a909ce88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892453930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.1892453930
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.95530500
Short name T100
Test name
Test status
Simulation time 55120125565 ps
CPU time 92.36 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:33:43 PM PST 24
Peak memory 183340 kb
Host smart-cec57def-548d-466d-a2c4-ae0ad79e2360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95530500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_al
l.95530500
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3435286005
Short name T76
Test name
Test status
Simulation time 18113424843 ps
CPU time 132.52 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:34:29 PM PST 24
Peak memory 198324 kb
Host smart-690c8371-c749-4985-8f5b-c668b138ef5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435286005 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3435286005
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4273487954
Short name T216
Test name
Test status
Simulation time 425792210 ps
CPU time 0.88 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183288 kb
Host smart-a87f82a8-c577-4d0b-b8c2-450c5eab235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273487954 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4273487954
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1983215566
Short name T232
Test name
Test status
Simulation time 58158324125 ps
CPU time 46.33 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:57 PM PST 24
Peak memory 183308 kb
Host smart-5049e780-16bb-440d-81c5-6d7ebf42f1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983215566 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1983215566
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3805779517
Short name T196
Test name
Test status
Simulation time 368454920 ps
CPU time 0.78 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183188 kb
Host smart-5ee6da6a-c62c-42b1-8f07-39e5acb200ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805779517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3805779517
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.418503626
Short name T263
Test name
Test status
Simulation time 167571735179 ps
CPU time 67.36 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:33:17 PM PST 24
Peak memory 183424 kb
Host smart-703a4743-7ded-499a-a25c-059aa226f5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418503626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.418503626
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1075306465
Short name T164
Test name
Test status
Simulation time 20833191739 ps
CPU time 170.86 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:35:03 PM PST 24
Peak memory 198240 kb
Host smart-ee19a355-dfb3-4383-ac24-81fde158f1bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075306465 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1075306465
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1790613209
Short name T253
Test name
Test status
Simulation time 489813548 ps
CPU time 0.64 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183260 kb
Host smart-bcdf52a3-852f-46b5-98c1-b99461d2d0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790613209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1790613209
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3635850894
Short name T143
Test name
Test status
Simulation time 43493468389 ps
CPU time 63.02 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 183416 kb
Host smart-a620e955-7382-4833-89db-07e0eb3da8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635850894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3635850894
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1576131443
Short name T63
Test name
Test status
Simulation time 388205252 ps
CPU time 1.18 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183196 kb
Host smart-61ce0f84-7638-4dc9-90bd-04d6ee3a2118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576131443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1576131443
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.3676901874
Short name T90
Test name
Test status
Simulation time 126642051786 ps
CPU time 30.23 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:32:40 PM PST 24
Peak memory 193748 kb
Host smart-3478671f-794a-4c85-9390-fe41d64b0325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676901874 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.3676901874
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.2398051758
Short name T67
Test name
Test status
Simulation time 59435512219 ps
CPU time 678.21 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:43:27 PM PST 24
Peak memory 198336 kb
Host smart-367b8c66-68f0-4d6f-b176-7ecb6145c9d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398051758 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.2398051758
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1926538503
Short name T195
Test name
Test status
Simulation time 534823718 ps
CPU time 0.96 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:31:58 PM PST 24
Peak memory 183288 kb
Host smart-dc83585c-3ba7-424a-9457-0afab00c0a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926538503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1926538503
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1688711392
Short name T170
Test name
Test status
Simulation time 18901523559 ps
CPU time 8.17 seconds
Started Feb 21 12:31:59 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183256 kb
Host smart-07c049e7-9b93-4954-9503-0703a9afdd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688711392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1688711392
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2875903145
Short name T4
Test name
Test status
Simulation time 8498263649 ps
CPU time 3.76 seconds
Started Feb 21 12:31:55 PM PST 24
Finished Feb 21 12:32:00 PM PST 24
Peak memory 215344 kb
Host smart-8fd36010-71d9-43cf-80a1-5d3b7a28c553
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875903145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2875903145
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1390560963
Short name T65
Test name
Test status
Simulation time 378630565 ps
CPU time 1.09 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:31:56 PM PST 24
Peak memory 183308 kb
Host smart-a37a3425-5fe2-44a6-843c-c7d55e837595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390560963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1390560963
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1744950351
Short name T99
Test name
Test status
Simulation time 226607520165 ps
CPU time 80.47 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:33:15 PM PST 24
Peak memory 193648 kb
Host smart-fffa1e55-3863-424a-9172-ab0f9d162019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744950351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1744950351
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2151725075
Short name T73
Test name
Test status
Simulation time 96008706328 ps
CPU time 453.69 seconds
Started Feb 21 12:32:03 PM PST 24
Finished Feb 21 12:39:37 PM PST 24
Peak memory 198232 kb
Host smart-a2929911-6582-41d6-82ee-e3ce7a58739c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151725075 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2151725075
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.64282087
Short name T192
Test name
Test status
Simulation time 437472954 ps
CPU time 0.58 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183248 kb
Host smart-2cd5df60-5e91-4571-9dcc-47248889b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64282087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.64282087
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3060157040
Short name T197
Test name
Test status
Simulation time 45073407674 ps
CPU time 66.33 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:33:14 PM PST 24
Peak memory 183224 kb
Host smart-bb269f6b-31d9-46e2-883b-45ffb73f8b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060157040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3060157040
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3564209031
Short name T242
Test name
Test status
Simulation time 575000041 ps
CPU time 1.36 seconds
Started Feb 21 12:32:05 PM PST 24
Finished Feb 21 12:32:07 PM PST 24
Peak memory 183180 kb
Host smart-b59723a2-672a-4f51-9d0f-f939a2f407f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564209031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3564209031
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3200627903
Short name T173
Test name
Test status
Simulation time 86405284645 ps
CPU time 32.89 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:45 PM PST 24
Peak memory 194656 kb
Host smart-63280263-46a4-4320-8d76-59b281677967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200627903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3200627903
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.483861165
Short name T69
Test name
Test status
Simulation time 33085194929 ps
CPU time 307.9 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:37:16 PM PST 24
Peak memory 198216 kb
Host smart-84024b58-473b-4c13-b571-8f4376e983d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483861165 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.483861165
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.425321048
Short name T284
Test name
Test status
Simulation time 443095432 ps
CPU time 1.03 seconds
Started Feb 21 12:32:05 PM PST 24
Finished Feb 21 12:32:07 PM PST 24
Peak memory 183416 kb
Host smart-bb3cad9a-92e7-4958-8b6d-998de83560d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425321048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.425321048
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1162244992
Short name T37
Test name
Test status
Simulation time 54047314594 ps
CPU time 41.74 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:53 PM PST 24
Peak memory 183448 kb
Host smart-d7203ed8-400f-49fe-b48f-ef5d0e45d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162244992 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1162244992
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1609109227
Short name T132
Test name
Test status
Simulation time 489433165 ps
CPU time 0.74 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183156 kb
Host smart-8dc079ae-c89f-48e1-ac14-d7fcd046a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609109227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1609109227
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2109385183
Short name T266
Test name
Test status
Simulation time 4707951241 ps
CPU time 4.12 seconds
Started Feb 21 12:32:44 PM PST 24
Finished Feb 21 12:32:48 PM PST 24
Peak memory 193320 kb
Host smart-f4d92634-3502-4c81-ad02-ae1132dfc7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109385183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2109385183
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.2742263022
Short name T283
Test name
Test status
Simulation time 69828537205 ps
CPU time 72.24 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:33:23 PM PST 24
Peak memory 198348 kb
Host smart-9d64b945-14e9-437e-86b9-533581955e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742263022 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.2742263022
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2512540031
Short name T23
Test name
Test status
Simulation time 372565224 ps
CPU time 0.73 seconds
Started Feb 21 12:32:06 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183260 kb
Host smart-e489e54f-9ee4-4146-a2b5-4eea6e70ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512540031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2512540031
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.3057448447
Short name T145
Test name
Test status
Simulation time 30819871870 ps
CPU time 50.6 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:33:02 PM PST 24
Peak memory 183292 kb
Host smart-68ac5d7b-1b2c-43f4-9828-a28bf37c21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057448447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.3057448447
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3357158654
Short name T66
Test name
Test status
Simulation time 347907094 ps
CPU time 1.09 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:32:17 PM PST 24
Peak memory 183192 kb
Host smart-bf6414f8-de5f-4add-b995-dbe06287690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357158654 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3357158654
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.4245858613
Short name T185
Test name
Test status
Simulation time 351365253248 ps
CPU time 41.17 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:32:51 PM PST 24
Peak memory 183316 kb
Host smart-cb7f93d3-deab-4501-96fc-3281a2da16e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245858613 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.4245858613
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3076676221
Short name T34
Test name
Test status
Simulation time 185059022153 ps
CPU time 204.02 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:35:35 PM PST 24
Peak memory 198352 kb
Host smart-6a82f776-28af-4a48-9fa5-be6b99571fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076676221 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3076676221
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3716653529
Short name T251
Test name
Test status
Simulation time 490910501 ps
CPU time 0.75 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183364 kb
Host smart-eebd1370-c27f-483d-bc03-f8ec7b58260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716653529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3716653529
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2453123411
Short name T213
Test name
Test status
Simulation time 16644291372 ps
CPU time 2.24 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:14 PM PST 24
Peak memory 183288 kb
Host smart-2cc99534-4e83-412f-809a-a6644efea9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453123411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2453123411
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.4077038081
Short name T124
Test name
Test status
Simulation time 439370868 ps
CPU time 0.72 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183256 kb
Host smart-e0c8c87d-0ff8-4f53-b93a-6bf18d71f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077038081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.4077038081
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.3891930215
Short name T102
Test name
Test status
Simulation time 115923358543 ps
CPU time 153.01 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 193636 kb
Host smart-24473f44-b46a-401a-b4e4-aeeb132bd9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891930215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.3891930215
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3121012943
Short name T246
Test name
Test status
Simulation time 348240411 ps
CPU time 1.1 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183180 kb
Host smart-e70cfada-2737-4210-b711-2d80d575c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121012943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3121012943
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1902793745
Short name T205
Test name
Test status
Simulation time 20293511563 ps
CPU time 15.57 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:28 PM PST 24
Peak memory 183296 kb
Host smart-cb1c0a76-26d6-45a9-b0b7-114d8c75a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902793745 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1902793745
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2036378311
Short name T123
Test name
Test status
Simulation time 438271857 ps
CPU time 1.13 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:32:17 PM PST 24
Peak memory 183252 kb
Host smart-662bae9d-5c8b-4a42-b62b-4efde59a301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036378311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2036378311
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.2670744075
Short name T112
Test name
Test status
Simulation time 91729535634 ps
CPU time 132.63 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 183320 kb
Host smart-51323e5f-8454-41be-986f-ebfae6b8d808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670744075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.2670744075
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3736247687
Short name T218
Test name
Test status
Simulation time 634844830 ps
CPU time 1.48 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183436 kb
Host smart-b0868a01-e7fd-4e99-a307-98da9bbded9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736247687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3736247687
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1712080308
Short name T158
Test name
Test status
Simulation time 36615476862 ps
CPU time 28.72 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:32:38 PM PST 24
Peak memory 183228 kb
Host smart-0ed097a4-1d42-4ccc-aadc-9ebc3ef2a491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712080308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1712080308
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.856646011
Short name T191
Test name
Test status
Simulation time 565023078 ps
CPU time 0.73 seconds
Started Feb 21 12:32:14 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183128 kb
Host smart-7bc870d7-d45d-49a2-8ae7-8e2b8385bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856646011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.856646011
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.860901538
Short name T75
Test name
Test status
Simulation time 312529771768 ps
CPU time 1184.06 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:51:56 PM PST 24
Peak memory 206268 kb
Host smart-33a8b6f5-d6cc-45ab-803f-b6378d358f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860901538 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.860901538
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.2161612769
Short name T178
Test name
Test status
Simulation time 347240518 ps
CPU time 1.1 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:11 PM PST 24
Peak memory 183280 kb
Host smart-86876978-5f4b-4bc7-89f5-bfb7c9f6c9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161612769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.2161612769
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1603902175
Short name T256
Test name
Test status
Simulation time 24897696274 ps
CPU time 40.4 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:53 PM PST 24
Peak memory 183284 kb
Host smart-ea0d9cd5-9dea-4b4e-acde-bc15c6888a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603902175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1603902175
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2950077111
Short name T171
Test name
Test status
Simulation time 551062850 ps
CPU time 1.33 seconds
Started Feb 21 12:32:12 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183352 kb
Host smart-59c6d4bc-b4ad-4529-a2d5-2a92e48434d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950077111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2950077111
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.3129772703
Short name T245
Test name
Test status
Simulation time 264526062670 ps
CPU time 410.38 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:39:01 PM PST 24
Peak memory 183264 kb
Host smart-4bfb74a9-baed-42ff-98e5-6fea796f1352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129772703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.3129772703
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2019351115
Short name T248
Test name
Test status
Simulation time 156513989154 ps
CPU time 472.1 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:40:14 PM PST 24
Peak memory 198372 kb
Host smart-8bb48e85-a287-437d-8f23-dd8224f86d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019351115 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2019351115
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3791296535
Short name T201
Test name
Test status
Simulation time 615694623 ps
CPU time 0.87 seconds
Started Feb 21 12:32:33 PM PST 24
Finished Feb 21 12:32:36 PM PST 24
Peak memory 183308 kb
Host smart-0aea5858-dd5e-4e9f-a8a5-cc864584e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791296535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3791296535
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.3154072172
Short name T62
Test name
Test status
Simulation time 10065373925 ps
CPU time 15.95 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:29 PM PST 24
Peak memory 183416 kb
Host smart-d64ab453-271e-40d1-b6a0-cf800d2ca104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154072172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.3154072172
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3106322066
Short name T150
Test name
Test status
Simulation time 483218497 ps
CPU time 0.99 seconds
Started Feb 21 12:33:44 PM PST 24
Finished Feb 21 12:33:47 PM PST 24
Peak memory 182404 kb
Host smart-36986955-2d4d-41f2-86af-54e582c07a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106322066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3106322066
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3262575550
Short name T91
Test name
Test status
Simulation time 145764506046 ps
CPU time 105.04 seconds
Started Feb 21 12:35:36 PM PST 24
Finished Feb 21 12:37:22 PM PST 24
Peak memory 182568 kb
Host smart-ac95ec01-8ac8-4bc0-860e-83ff4ff59ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262575550 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3262575550
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.416861627
Short name T186
Test name
Test status
Simulation time 63937428157 ps
CPU time 353.17 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:38:05 PM PST 24
Peak memory 198216 kb
Host smart-0239b13f-d37b-4615-a4eb-4110dbea7da3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416861627 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.416861627
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1682260931
Short name T39
Test name
Test status
Simulation time 618795826 ps
CPU time 0.72 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:18 PM PST 24
Peak memory 183248 kb
Host smart-be55f4aa-9b0b-4a28-80af-02523e824ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682260931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1682260931
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1133513450
Short name T257
Test name
Test status
Simulation time 1375762632 ps
CPU time 2.68 seconds
Started Feb 21 12:32:12 PM PST 24
Finished Feb 21 12:32:16 PM PST 24
Peak memory 183196 kb
Host smart-fc84653d-f7f9-45b8-9b14-5820a675aac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133513450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1133513450
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.2899230387
Short name T163
Test name
Test status
Simulation time 362762147 ps
CPU time 0.72 seconds
Started Feb 21 12:33:27 PM PST 24
Finished Feb 21 12:33:28 PM PST 24
Peak memory 182304 kb
Host smart-833a5fca-4e0b-41b2-8f46-ab779983a812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899230387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.2899230387
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1800361165
Short name T115
Test name
Test status
Simulation time 172364002202 ps
CPU time 255.7 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:36:34 PM PST 24
Peak memory 183032 kb
Host smart-00a9cd22-6dac-4fe6-91ab-67738765f5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800361165 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1800361165
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4275744990
Short name T77
Test name
Test status
Simulation time 43932643468 ps
CPU time 130.92 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:34:28 PM PST 24
Peak memory 198236 kb
Host smart-8e99c57d-2f1e-4062-ab2b-c1934d71c167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275744990 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4275744990
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1217935853
Short name T260
Test name
Test status
Simulation time 607469078 ps
CPU time 0.76 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:12 PM PST 24
Peak memory 183204 kb
Host smart-bf66f196-5614-4b63-9f2f-fb4a57607ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217935853 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1217935853
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.4133940682
Short name T208
Test name
Test status
Simulation time 3714010433 ps
CPU time 2.03 seconds
Started Feb 21 12:32:23 PM PST 24
Finished Feb 21 12:32:26 PM PST 24
Peak memory 183312 kb
Host smart-9c161931-66ec-493a-838a-695db8c241e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133940682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.4133940682
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.837380783
Short name T172
Test name
Test status
Simulation time 502406443 ps
CPU time 0.6 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:18 PM PST 24
Peak memory 183244 kb
Host smart-4b51abea-2c5d-4b51-88cc-11c5909f2bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837380783 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.837380783
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2700986998
Short name T106
Test name
Test status
Simulation time 160515982332 ps
CPU time 40.26 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:33:07 PM PST 24
Peak memory 183292 kb
Host smart-2e2671d9-d6c0-4094-8312-86b9f42dc189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700986998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2700986998
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1139325340
Short name T92
Test name
Test status
Simulation time 141030278325 ps
CPU time 205.53 seconds
Started Feb 21 12:32:09 PM PST 24
Finished Feb 21 12:35:35 PM PST 24
Peak memory 198200 kb
Host smart-86cded5e-3ded-4ddc-b610-048f2796358d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139325340 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1139325340
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1823814158
Short name T114
Test name
Test status
Simulation time 453892353 ps
CPU time 0.66 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:01 PM PST 24
Peak memory 183224 kb
Host smart-622b2449-5016-4999-bef6-42fbda3018b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823814158 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1823814158
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.172293905
Short name T227
Test name
Test status
Simulation time 26448376302 ps
CPU time 37.69 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:39 PM PST 24
Peak memory 183296 kb
Host smart-f1d623e9-cea7-4ef0-8464-d31cb9c2c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172293905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.172293905
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.2520165844
Short name T18
Test name
Test status
Simulation time 4288054755 ps
CPU time 4.23 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:04 PM PST 24
Peak memory 214984 kb
Host smart-205162a6-08ba-4fc6-bf0d-ad5631ce427a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520165844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.2520165844
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.1550597419
Short name T233
Test name
Test status
Simulation time 575173813 ps
CPU time 0.99 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:02 PM PST 24
Peak memory 183168 kb
Host smart-5d3a35ec-7ccd-4006-94b5-bcf6654e9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550597419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.1550597419
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1335936711
Short name T247
Test name
Test status
Simulation time 77968385756 ps
CPU time 116.16 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:33:58 PM PST 24
Peak memory 193448 kb
Host smart-374b764d-87e8-4c15-a7ad-aab72a5e1e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335936711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1335936711
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_jump.1085354822
Short name T194
Test name
Test status
Simulation time 558717878 ps
CPU time 0.91 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:11 PM PST 24
Peak memory 183232 kb
Host smart-27a76e7d-3772-402f-b04e-62e84f73e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085354822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.1085354822
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2801880133
Short name T204
Test name
Test status
Simulation time 1166808355 ps
CPU time 1.07 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183264 kb
Host smart-7fdf353f-0b64-4827-a6ee-0621d290dcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801880133 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2801880133
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1747619079
Short name T279
Test name
Test status
Simulation time 487167141 ps
CPU time 0.74 seconds
Started Feb 21 12:32:17 PM PST 24
Finished Feb 21 12:32:20 PM PST 24
Peak memory 183140 kb
Host smart-f5c3a112-e99c-4fc4-a734-d980adf4a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747619079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1747619079
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2978364010
Short name T169
Test name
Test status
Simulation time 98719750866 ps
CPU time 77.27 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:33:47 PM PST 24
Peak memory 183356 kb
Host smart-30a7edc1-e5fd-4ab2-a14f-0ed992a2490a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978364010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2978364010
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.820204225
Short name T277
Test name
Test status
Simulation time 35944296353 ps
CPU time 117.34 seconds
Started Feb 21 12:32:23 PM PST 24
Finished Feb 21 12:34:21 PM PST 24
Peak memory 198280 kb
Host smart-f6921dc1-c37c-4149-90f5-bf28d8b8ebe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820204225 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.820204225
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2205090149
Short name T144
Test name
Test status
Simulation time 487025576 ps
CPU time 1.26 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:31 PM PST 24
Peak memory 183276 kb
Host smart-c8d72516-17ce-4ab4-9a26-1dac1e93b214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205090149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2205090149
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4270516670
Short name T177
Test name
Test status
Simulation time 3343309087 ps
CPU time 2.11 seconds
Started Feb 21 12:32:06 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183268 kb
Host smart-9d9bfb31-306d-4554-91a8-5c3c0e24583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270516670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4270516670
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.2092589819
Short name T13
Test name
Test status
Simulation time 398423791 ps
CPU time 0.68 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183200 kb
Host smart-e6e98b03-b7be-4a08-91d2-bc0e5799de61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092589819 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.2092589819
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2561532928
Short name T219
Test name
Test status
Simulation time 33701294315 ps
CPU time 50.4 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:33:11 PM PST 24
Peak memory 193480 kb
Host smart-d3b5c555-17ce-47b5-8b66-36fa8e21377a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561532928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2561532928
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4127376481
Short name T138
Test name
Test status
Simulation time 469656064 ps
CPU time 0.7 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:37 PM PST 24
Peak memory 183296 kb
Host smart-6996f1f3-75d6-44e0-9d27-75821f77d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127376481 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4127376481
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.495374027
Short name T274
Test name
Test status
Simulation time 44350774917 ps
CPU time 5.67 seconds
Started Feb 21 12:32:17 PM PST 24
Finished Feb 21 12:32:24 PM PST 24
Peak memory 183324 kb
Host smart-58e3ed62-bf4b-4335-9780-daaa8b1ae6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495374027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.495374027
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3965311466
Short name T207
Test name
Test status
Simulation time 521854510 ps
CPU time 1.29 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:19 PM PST 24
Peak memory 183276 kb
Host smart-a30f13e8-fb61-4d9a-8c02-7074683c1aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965311466 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3965311466
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.122433980
Short name T94
Test name
Test status
Simulation time 110517660784 ps
CPU time 73.33 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:33:43 PM PST 24
Peak memory 183356 kb
Host smart-f86bf168-8918-432b-bd50-336d1ee3ce5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122433980 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.122433980
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.436558578
Short name T98
Test name
Test status
Simulation time 168736942179 ps
CPU time 283.67 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:37:13 PM PST 24
Peak memory 198284 kb
Host smart-88e4d592-3a2a-4247-95cf-3ecc03b54460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436558578 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.436558578
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3949078213
Short name T223
Test name
Test status
Simulation time 347477979 ps
CPU time 0.79 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:29 PM PST 24
Peak memory 183244 kb
Host smart-4050ab4d-4bf9-4389-99d8-ad12564bacd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949078213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3949078213
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1894272982
Short name T188
Test name
Test status
Simulation time 5004160276 ps
CPU time 7.9 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:04 PM PST 24
Peak memory 183296 kb
Host smart-6e30b27f-15fb-4697-9eae-8af22079a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894272982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1894272982
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.613639406
Short name T183
Test name
Test status
Simulation time 522023409 ps
CPU time 0.64 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:28 PM PST 24
Peak memory 183136 kb
Host smart-04301474-b0d5-447b-bce1-5b80abc56891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613639406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.613639406
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.55937577
Short name T152
Test name
Test status
Simulation time 300585462226 ps
CPU time 60.83 seconds
Started Feb 21 12:32:21 PM PST 24
Finished Feb 21 12:33:22 PM PST 24
Peak memory 183256 kb
Host smart-9ca5327c-d985-4484-ac60-c2916eeec6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55937577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_al
l.55937577
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.1203276175
Short name T258
Test name
Test status
Simulation time 36719868112 ps
CPU time 295.47 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:37:08 PM PST 24
Peak memory 198212 kb
Host smart-5e6632c7-cc53-4999-bad2-8e464a3d660a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203276175 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.1203276175
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.3467688700
Short name T140
Test name
Test status
Simulation time 391312851 ps
CPU time 0.83 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:33 PM PST 24
Peak memory 183252 kb
Host smart-7d5ea55a-d6a7-4e5b-8277-0d8db820d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467688700 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.3467688700
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3708992923
Short name T221
Test name
Test status
Simulation time 36042027374 ps
CPU time 15.92 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:48 PM PST 24
Peak memory 183276 kb
Host smart-cbed21cf-1d07-4d4b-9ce2-f79fbd9dd373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708992923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3708992923
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.1054506171
Short name T142
Test name
Test status
Simulation time 453230890 ps
CPU time 0.72 seconds
Started Feb 21 12:32:12 PM PST 24
Finished Feb 21 12:32:14 PM PST 24
Peak memory 183184 kb
Host smart-be02427c-2646-42b6-a62d-0acf6998c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054506171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.1054506171
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.984091394
Short name T264
Test name
Test status
Simulation time 53716857034 ps
CPU time 87.62 seconds
Started Feb 21 12:32:14 PM PST 24
Finished Feb 21 12:33:48 PM PST 24
Peak memory 193888 kb
Host smart-f79c3783-35a9-4fca-b7ca-32529018dd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984091394 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.984091394
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2761739505
Short name T79
Test name
Test status
Simulation time 88071604615 ps
CPU time 164.16 seconds
Started Feb 21 12:32:31 PM PST 24
Finished Feb 21 12:35:16 PM PST 24
Peak memory 198216 kb
Host smart-38030b11-b4d8-4d76-a8b5-83e411641941
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761739505 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2761739505
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1433929092
Short name T61
Test name
Test status
Simulation time 435367164 ps
CPU time 0.89 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183320 kb
Host smart-faa40e45-68a1-4414-84f0-5aa70dd9a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433929092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1433929092
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.724290217
Short name T118
Test name
Test status
Simulation time 2483785364 ps
CPU time 3.94 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183412 kb
Host smart-4c4eccb4-fc5d-4ac3-ac03-4f2803a35425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724290217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.724290217
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.101513458
Short name T282
Test name
Test status
Simulation time 510215789 ps
CPU time 1.3 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:34 PM PST 24
Peak memory 183244 kb
Host smart-08fa08d5-c3ba-439b-861a-8154375d58d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101513458 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.101513458
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.134016360
Short name T249
Test name
Test status
Simulation time 173703831898 ps
CPU time 56.67 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:33:19 PM PST 24
Peak memory 193952 kb
Host smart-b4622a1e-a383-4983-b8bf-b5e911f19cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134016360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.134016360
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3834079951
Short name T88
Test name
Test status
Simulation time 92500442870 ps
CPU time 201.95 seconds
Started Feb 21 12:32:14 PM PST 24
Finished Feb 21 12:35:36 PM PST 24
Peak memory 198336 kb
Host smart-1bd07ac5-01a1-420f-9895-6adaaa075bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834079951 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3834079951
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.3654631369
Short name T238
Test name
Test status
Simulation time 604375504 ps
CPU time 0.76 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:32:22 PM PST 24
Peak memory 183292 kb
Host smart-b85c9c10-5fa7-4fd7-90b5-6fc0463a0f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654631369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.3654631369
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2275523000
Short name T11
Test name
Test status
Simulation time 15960675237 ps
CPU time 2.89 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183660 kb
Host smart-6447d9fd-c323-4870-9add-9a4dd47d299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275523000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2275523000
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1097267156
Short name T199
Test name
Test status
Simulation time 584967119 ps
CPU time 0.77 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:32:16 PM PST 24
Peak memory 183260 kb
Host smart-bcd8b944-10f1-46e7-8b9f-0a757c7613bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097267156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1097267156
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.682055647
Short name T7
Test name
Test status
Simulation time 47635493390 ps
CPU time 18.46 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:32:38 PM PST 24
Peak memory 193504 kb
Host smart-e65bbdb8-3b5f-4bf4-890d-95e9611bb015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682055647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_a
ll.682055647
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1859469182
Short name T87
Test name
Test status
Simulation time 114001904939 ps
CPU time 311.9 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:37:44 PM PST 24
Peak memory 198240 kb
Host smart-7d60e5a5-4368-4a31-a3ef-e2ce772a5d75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859469182 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1859469182
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3524634208
Short name T270
Test name
Test status
Simulation time 525973197 ps
CPU time 0.63 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183288 kb
Host smart-acec893b-10a3-4001-8371-25bbd10d92c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524634208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3524634208
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3522028723
Short name T1
Test name
Test status
Simulation time 46802153982 ps
CPU time 61.93 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 183292 kb
Host smart-599b7e0f-595d-41ce-b2e3-f3c8cd8dbc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522028723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3522028723
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.3985781533
Short name T210
Test name
Test status
Simulation time 533418855 ps
CPU time 0.75 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:18 PM PST 24
Peak memory 183252 kb
Host smart-f2fd4463-4a5d-4f31-b55f-5f2ca3a819f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985781533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.3985781533
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.4293507427
Short name T271
Test name
Test status
Simulation time 9175012898 ps
CPU time 4.67 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:19 PM PST 24
Peak memory 191556 kb
Host smart-05bc7f41-a59e-45ce-ab3d-768b4d912337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293507427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.4293507427
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.1583131459
Short name T231
Test name
Test status
Simulation time 41350336300 ps
CPU time 66.76 seconds
Started Feb 21 12:32:34 PM PST 24
Finished Feb 21 12:33:42 PM PST 24
Peak memory 198244 kb
Host smart-1da49c1a-e6f1-480b-927b-b4595d4b96cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583131459 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.1583131459
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.1646151321
Short name T181
Test name
Test status
Simulation time 369515405 ps
CPU time 0.68 seconds
Started Feb 21 12:32:11 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183196 kb
Host smart-13cac529-f096-43f5-9c8c-4ff957623411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646151321 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.1646151321
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3094457341
Short name T120
Test name
Test status
Simulation time 13202650183 ps
CPU time 21.09 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:35 PM PST 24
Peak memory 183332 kb
Host smart-db414449-55f0-4e69-8aa4-95593768d6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094457341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3094457341
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.888935474
Short name T121
Test name
Test status
Simulation time 429159416 ps
CPU time 0.91 seconds
Started Feb 21 12:33:11 PM PST 24
Finished Feb 21 12:33:12 PM PST 24
Peak memory 182348 kb
Host smart-15ce86b7-13be-4173-b14d-4f9e98fdff3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888935474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.888935474
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3902030159
Short name T211
Test name
Test status
Simulation time 57621506841 ps
CPU time 22.27 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:40 PM PST 24
Peak memory 193316 kb
Host smart-57c607c6-06eb-47ea-a578-f9cf19ded21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902030159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3902030159
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.2605111845
Short name T68
Test name
Test status
Simulation time 111551132814 ps
CPU time 877.56 seconds
Started Feb 21 12:32:12 PM PST 24
Finished Feb 21 12:46:51 PM PST 24
Peak memory 202328 kb
Host smart-31ccd090-1304-4d2a-939c-da40e77e98fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605111845 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.2605111845
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.751962390
Short name T176
Test name
Test status
Simulation time 579174652 ps
CPU time 1.46 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:19 PM PST 24
Peak memory 183248 kb
Host smart-232d21d0-6bdb-4f56-a675-f653aa7d11bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751962390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.751962390
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3718333697
Short name T229
Test name
Test status
Simulation time 26506081842 ps
CPU time 4 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:22 PM PST 24
Peak memory 183024 kb
Host smart-a3befb78-a098-43dc-a6ab-21e290c86834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718333697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3718333697
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.431963886
Short name T126
Test name
Test status
Simulation time 469436660 ps
CPU time 1.29 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:32:13 PM PST 24
Peak memory 183152 kb
Host smart-ac796fdf-07a6-462c-b574-feb0f5f17a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431963886 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.431963886
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2892205094
Short name T203
Test name
Test status
Simulation time 152764852904 ps
CPU time 49.84 seconds
Started Feb 21 12:32:10 PM PST 24
Finished Feb 21 12:33:01 PM PST 24
Peak memory 193596 kb
Host smart-d1773dfd-2589-41c2-bbfe-26b097a36f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892205094 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2892205094
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2210609682
Short name T36
Test name
Test status
Simulation time 48277960280 ps
CPU time 172.8 seconds
Started Feb 21 12:32:37 PM PST 24
Finished Feb 21 12:35:30 PM PST 24
Peak memory 198264 kb
Host smart-b25fd338-ab8d-49d5-b134-b302a94ad009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210609682 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2210609682
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.4136744609
Short name T252
Test name
Test status
Simulation time 405391164 ps
CPU time 1.34 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:31:55 PM PST 24
Peak memory 183440 kb
Host smart-d3c462b2-f60a-4c1a-9bba-672c420e22b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136744609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.4136744609
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3653047657
Short name T235
Test name
Test status
Simulation time 47023658570 ps
CPU time 41.3 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:43 PM PST 24
Peak memory 183384 kb
Host smart-c65e8f7f-2e3a-4481-819c-3ba4f1301314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653047657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3653047657
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3063051392
Short name T19
Test name
Test status
Simulation time 4351763190 ps
CPU time 7.05 seconds
Started Feb 21 12:32:05 PM PST 24
Finished Feb 21 12:32:12 PM PST 24
Peak memory 215164 kb
Host smart-553e1138-64bd-4c48-8fdd-b8dd919cf91f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063051392 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3063051392
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.390031080
Short name T122
Test name
Test status
Simulation time 499260305 ps
CPU time 0.68 seconds
Started Feb 21 12:32:02 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183136 kb
Host smart-51e73207-baff-4865-a321-1edaa8355656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390031080 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.390031080
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.4168510093
Short name T215
Test name
Test status
Simulation time 153922958784 ps
CPU time 52.98 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:32:49 PM PST 24
Peak memory 193468 kb
Host smart-f9338ffe-ce68-4695-8453-4c64083250c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168510093 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.4168510093
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2095593931
Short name T70
Test name
Test status
Simulation time 89047619322 ps
CPU time 542.53 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:41:17 PM PST 24
Peak memory 197788 kb
Host smart-04714ae7-a1f5-4527-ac23-30d44688bff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095593931 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2095593931
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.549267156
Short name T2
Test name
Test status
Simulation time 588136281 ps
CPU time 0.65 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183308 kb
Host smart-6da0355e-e250-4a0c-a3fa-e0e6e17b80c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549267156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.549267156
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.480772733
Short name T119
Test name
Test status
Simulation time 30924940874 ps
CPU time 43.28 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:33:10 PM PST 24
Peak memory 183260 kb
Host smart-2ceffa98-f88d-4c74-be32-e991f6b7952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480772733 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.480772733
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.1198963234
Short name T8
Test name
Test status
Simulation time 557376716 ps
CPU time 1.5 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:32:10 PM PST 24
Peak memory 183268 kb
Host smart-e137d96d-2a29-43fe-b0a3-c70475cf3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198963234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.1198963234
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.3561097899
Short name T96
Test name
Test status
Simulation time 165601134942 ps
CPU time 247.4 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:36:15 PM PST 24
Peak memory 193344 kb
Host smart-d1ceb463-b231-4689-bd98-af30957c9b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561097899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.3561097899
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.190409407
Short name T14
Test name
Test status
Simulation time 582087788 ps
CPU time 1.31 seconds
Started Feb 21 12:32:12 PM PST 24
Finished Feb 21 12:32:14 PM PST 24
Peak memory 183292 kb
Host smart-7dd0b854-f104-4431-923a-7dec0e992052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190409407 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.190409407
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.2238675826
Short name T239
Test name
Test status
Simulation time 20115513220 ps
CPU time 8.28 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:16 PM PST 24
Peak memory 183248 kb
Host smart-fe2ddc87-f41c-45fb-9683-f81a8898a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238675826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.2238675826
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2208424055
Short name T160
Test name
Test status
Simulation time 548886098 ps
CPU time 0.73 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:14 PM PST 24
Peak memory 183256 kb
Host smart-b20d25c6-a1f2-465c-852f-cd276a6419b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208424055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2208424055
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.2443980896
Short name T38
Test name
Test status
Simulation time 85137611705 ps
CPU time 28.16 seconds
Started Feb 21 12:32:16 PM PST 24
Finished Feb 21 12:32:45 PM PST 24
Peak memory 183412 kb
Host smart-80809720-54b0-4c02-9799-9fe9178d132f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443980896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.2443980896
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.317785770
Short name T71
Test name
Test status
Simulation time 87782647969 ps
CPU time 803.04 seconds
Started Feb 21 12:32:17 PM PST 24
Finished Feb 21 12:45:41 PM PST 24
Peak memory 201776 kb
Host smart-d1ba5354-39b7-4a6c-92b8-ff54b46dfd51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317785770 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.317785770
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.1377436961
Short name T12
Test name
Test status
Simulation time 428891642 ps
CPU time 0.93 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:31 PM PST 24
Peak memory 182592 kb
Host smart-75e8bea6-8a68-4574-84e8-17722620ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377436961 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.1377436961
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1835695943
Short name T220
Test name
Test status
Simulation time 16190113049 ps
CPU time 6.49 seconds
Started Feb 21 12:32:14 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183280 kb
Host smart-87f3b771-b849-4319-8f10-96704866f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835695943 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1835695943
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1053218600
Short name T20
Test name
Test status
Simulation time 562776496 ps
CPU time 0.73 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:30 PM PST 24
Peak memory 183176 kb
Host smart-ea4bfee1-cfeb-4bc2-9a79-157aa6fa8b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053218600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1053218600
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3825925556
Short name T287
Test name
Test status
Simulation time 125198425311 ps
CPU time 96.96 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:33:58 PM PST 24
Peak memory 193648 kb
Host smart-9187b1d0-bf62-4a43-96d2-fd23d1a1f37e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825925556 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3825925556
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.1881703263
Short name T206
Test name
Test status
Simulation time 95301110505 ps
CPU time 163.18 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 206504 kb
Host smart-183899b7-c13d-4a9a-9127-f4706355a42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881703263 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.1881703263
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.4107569343
Short name T262
Test name
Test status
Simulation time 465038976 ps
CPU time 0.66 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183340 kb
Host smart-a47804ab-4570-441f-b2e5-85ade41eb618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107569343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.4107569343
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.4074110377
Short name T155
Test name
Test status
Simulation time 24660498012 ps
CPU time 38.65 seconds
Started Feb 21 12:32:15 PM PST 24
Finished Feb 21 12:32:54 PM PST 24
Peak memory 183392 kb
Host smart-10d612a6-64fd-42e8-930b-d29b09de7aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074110377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.4074110377
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1478169603
Short name T193
Test name
Test status
Simulation time 605009418 ps
CPU time 1.54 seconds
Started Feb 21 12:32:29 PM PST 24
Finished Feb 21 12:32:31 PM PST 24
Peak memory 182508 kb
Host smart-e0610015-ab1b-4acd-8b03-d58a6c5ab8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478169603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1478169603
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1158644205
Short name T3
Test name
Test status
Simulation time 147397198751 ps
CPU time 54.33 seconds
Started Feb 21 12:32:56 PM PST 24
Finished Feb 21 12:33:51 PM PST 24
Peak memory 193332 kb
Host smart-3097dea1-b410-4862-946a-8660dda910f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158644205 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1158644205
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.374012856
Short name T72
Test name
Test status
Simulation time 112250529179 ps
CPU time 254.87 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:36:42 PM PST 24
Peak memory 198204 kb
Host smart-5c7d9787-90b5-406f-9397-a462a9efa80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374012856 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.374012856
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.4070244420
Short name T228
Test name
Test status
Simulation time 469252816 ps
CPU time 0.88 seconds
Started Feb 21 12:33:05 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 183236 kb
Host smart-48aee994-5f3d-4a2b-bcb9-c52138935e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070244420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.4070244420
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3414190651
Short name T198
Test name
Test status
Simulation time 24370100993 ps
CPU time 32.76 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:33:00 PM PST 24
Peak memory 183296 kb
Host smart-e3105e23-922a-4b3d-b995-212898ab0dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414190651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3414190651
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.3623172063
Short name T214
Test name
Test status
Simulation time 565483183 ps
CPU time 1.49 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:32:30 PM PST 24
Peak memory 183160 kb
Host smart-81ade630-7099-4d59-9491-5615728f2840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623172063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.3623172063
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.4038383425
Short name T93
Test name
Test status
Simulation time 17665778950 ps
CPU time 15.76 seconds
Started Feb 21 12:32:28 PM PST 24
Finished Feb 21 12:32:44 PM PST 24
Peak memory 183364 kb
Host smart-cd0c6632-bfcd-42bf-9f68-5486c1875ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038383425 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.4038383425
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.4146060125
Short name T278
Test name
Test status
Simulation time 136603239258 ps
CPU time 687.86 seconds
Started Feb 21 12:32:27 PM PST 24
Finished Feb 21 12:43:55 PM PST 24
Peak memory 201212 kb
Host smart-c25a14c9-b25a-4ec0-8687-314ac73021dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146060125 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.4146060125
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1667280317
Short name T109
Test name
Test status
Simulation time 459797386 ps
CPU time 0.74 seconds
Started Feb 21 12:32:43 PM PST 24
Finished Feb 21 12:32:44 PM PST 24
Peak memory 183288 kb
Host smart-0aa878b0-0004-43dc-be21-6f6806ef7628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667280317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1667280317
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.2286222916
Short name T136
Test name
Test status
Simulation time 33187103888 ps
CPU time 47.51 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:33:08 PM PST 24
Peak memory 183316 kb
Host smart-4cfc2997-a33c-427a-acbd-f1d30db49e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286222916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.2286222916
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.598079396
Short name T135
Test name
Test status
Simulation time 597382864 ps
CPU time 1.47 seconds
Started Feb 21 12:32:31 PM PST 24
Finished Feb 21 12:32:33 PM PST 24
Peak memory 183200 kb
Host smart-b2915711-2920-40d2-9e05-fb4647e3304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598079396 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.598079396
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.745635540
Short name T104
Test name
Test status
Simulation time 395810754038 ps
CPU time 532.83 seconds
Started Feb 21 12:32:33 PM PST 24
Finished Feb 21 12:41:27 PM PST 24
Peak memory 183352 kb
Host smart-7baa24ae-281d-48dd-b66f-d3db73f0548c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745635540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.745635540
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.2177330872
Short name T78
Test name
Test status
Simulation time 179752934195 ps
CPU time 350.73 seconds
Started Feb 21 12:32:20 PM PST 24
Finished Feb 21 12:38:12 PM PST 24
Peak memory 198260 kb
Host smart-f97cf6d5-b6fa-420b-8dec-6b12930c03e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177330872 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.2177330872
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1666329238
Short name T209
Test name
Test status
Simulation time 373010007 ps
CPU time 0.72 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:33 PM PST 24
Peak memory 183252 kb
Host smart-f04e0ec0-8ad7-4836-a055-43a478695c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666329238 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1666329238
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2128979884
Short name T148
Test name
Test status
Simulation time 55788758143 ps
CPU time 21.62 seconds
Started Feb 21 12:32:31 PM PST 24
Finished Feb 21 12:32:53 PM PST 24
Peak memory 183328 kb
Host smart-4893f2b7-5b02-43b1-ad5c-ed6e49386497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128979884 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2128979884
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.429625840
Short name T154
Test name
Test status
Simulation time 410523536 ps
CPU time 0.7 seconds
Started Feb 21 12:32:36 PM PST 24
Finished Feb 21 12:32:38 PM PST 24
Peak memory 183144 kb
Host smart-4d3a516f-30c5-4c72-8268-6a6364a818be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429625840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.429625840
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2963179554
Short name T128
Test name
Test status
Simulation time 144572874976 ps
CPU time 202.52 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:35:43 PM PST 24
Peak memory 183412 kb
Host smart-f4236e45-7647-4a03-b906-782d52ff0392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963179554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2963179554
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.2717026238
Short name T202
Test name
Test status
Simulation time 145546858783 ps
CPU time 309.64 seconds
Started Feb 21 12:32:21 PM PST 24
Finished Feb 21 12:37:31 PM PST 24
Peak memory 198320 kb
Host smart-d25ccd1b-6cb6-41f7-beee-34bdc10a4c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717026238 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.2717026238
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.1286944822
Short name T259
Test name
Test status
Simulation time 485355543 ps
CPU time 0.67 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183284 kb
Host smart-afb34850-43a9-4bb6-8f84-34083eaefd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286944822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.1286944822
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.3250338420
Short name T285
Test name
Test status
Simulation time 5989315117 ps
CPU time 4.63 seconds
Started Feb 21 12:32:18 PM PST 24
Finished Feb 21 12:32:25 PM PST 24
Peak memory 183300 kb
Host smart-e091a56e-b581-4880-bfa6-adcdedca24b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250338420 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.3250338420
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3943749617
Short name T130
Test name
Test status
Simulation time 461865956 ps
CPU time 0.67 seconds
Started Feb 21 12:32:17 PM PST 24
Finished Feb 21 12:32:19 PM PST 24
Peak memory 183548 kb
Host smart-e93deb56-07ff-4459-bbd7-14f89bf1ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943749617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3943749617
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3103967846
Short name T240
Test name
Test status
Simulation time 188255994763 ps
CPU time 735.26 seconds
Started Feb 21 12:32:19 PM PST 24
Finished Feb 21 12:44:36 PM PST 24
Peak memory 200608 kb
Host smart-48a20fa8-2f98-4790-85fe-cbfc1e1cfe64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103967846 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3103967846
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.1669354191
Short name T250
Test name
Test status
Simulation time 501768953 ps
CPU time 0.73 seconds
Started Feb 21 12:32:13 PM PST 24
Finished Feb 21 12:32:15 PM PST 24
Peak memory 183256 kb
Host smart-ed16835c-16d3-4927-a9d0-48f984706b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669354191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.1669354191
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1811190729
Short name T281
Test name
Test status
Simulation time 35417815613 ps
CPU time 12.02 seconds
Started Feb 21 12:32:33 PM PST 24
Finished Feb 21 12:32:47 PM PST 24
Peak memory 183280 kb
Host smart-0b67a180-ca92-4eb8-a2c7-f082f53fc6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811190729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1811190729
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.33934810
Short name T147
Test name
Test status
Simulation time 515376810 ps
CPU time 0.96 seconds
Started Feb 21 12:32:25 PM PST 24
Finished Feb 21 12:32:26 PM PST 24
Peak memory 183144 kb
Host smart-24e2433a-231f-4845-87a5-1458dd0d2863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33934810 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.33934810
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1649672196
Short name T97
Test name
Test status
Simulation time 96844943774 ps
CPU time 146.61 seconds
Started Feb 21 12:32:24 PM PST 24
Finished Feb 21 12:34:51 PM PST 24
Peak memory 183372 kb
Host smart-38e072ae-c8db-4a67-a056-c183c2294c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649672196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1649672196
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1624672703
Short name T22
Test name
Test status
Simulation time 68634266433 ps
CPU time 322.33 seconds
Started Feb 21 12:32:19 PM PST 24
Finished Feb 21 12:37:43 PM PST 24
Peak memory 198228 kb
Host smart-f7e5c53e-c001-4720-984a-d6c45e1d8b2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624672703 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1624672703
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.3460851579
Short name T226
Test name
Test status
Simulation time 462429124 ps
CPU time 1.32 seconds
Started Feb 21 12:32:32 PM PST 24
Finished Feb 21 12:32:34 PM PST 24
Peak memory 183252 kb
Host smart-2e4a3c49-8d45-44d7-b396-5ec40ffafb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460851579 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.3460851579
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1258060543
Short name T217
Test name
Test status
Simulation time 61021303881 ps
CPU time 23.56 seconds
Started Feb 21 12:32:21 PM PST 24
Finished Feb 21 12:32:45 PM PST 24
Peak memory 183224 kb
Host smart-c6ee456d-2965-4a15-9ba7-b7d9c5b60a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258060543 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1258060543
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2477884915
Short name T125
Test name
Test status
Simulation time 585613061 ps
CPU time 0.83 seconds
Started Feb 21 12:32:19 PM PST 24
Finished Feb 21 12:32:21 PM PST 24
Peak memory 183284 kb
Host smart-8a0f984e-f42f-453b-aebc-275469032316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477884915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2477884915
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3712718915
Short name T237
Test name
Test status
Simulation time 92271619173 ps
CPU time 37.19 seconds
Started Feb 21 12:32:35 PM PST 24
Finished Feb 21 12:33:13 PM PST 24
Peak memory 193464 kb
Host smart-42a5a7e1-2a9d-4afa-8a65-d8136b000511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712718915 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3712718915
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_jump.120899405
Short name T212
Test name
Test status
Simulation time 547219028 ps
CPU time 0.78 seconds
Started Feb 21 12:31:56 PM PST 24
Finished Feb 21 12:31:57 PM PST 24
Peak memory 183272 kb
Host smart-9651302c-8dae-464d-9b50-8f139169fa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120899405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.120899405
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.168791916
Short name T255
Test name
Test status
Simulation time 22625548900 ps
CPU time 33.3 seconds
Started Feb 21 12:31:55 PM PST 24
Finished Feb 21 12:32:28 PM PST 24
Peak memory 183284 kb
Host smart-1be56f71-a9a2-4b7e-af8c-5edf08e2723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168791916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.168791916
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3048104953
Short name T184
Test name
Test status
Simulation time 546545693 ps
CPU time 0.91 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:01 PM PST 24
Peak memory 183164 kb
Host smart-5187a229-d502-469e-811d-84a3c5557f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048104953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3048104953
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.2842044406
Short name T153
Test name
Test status
Simulation time 165306561864 ps
CPU time 264.74 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:36:19 PM PST 24
Peak memory 193296 kb
Host smart-4f64ce16-6bcd-4b91-ba2a-134c9ebca016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842044406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.2842044406
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.39354116
Short name T234
Test name
Test status
Simulation time 95554776126 ps
CPU time 528.56 seconds
Started Feb 21 12:31:53 PM PST 24
Finished Feb 21 12:40:42 PM PST 24
Peak memory 198256 kb
Host smart-26636a20-1b3a-4181-93a0-3c18d152f1c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39354116 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.39354116
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3372563820
Short name T269
Test name
Test status
Simulation time 563475873 ps
CPU time 0.62 seconds
Started Feb 21 12:31:59 PM PST 24
Finished Feb 21 12:32:00 PM PST 24
Peak memory 183228 kb
Host smart-02ed7eca-1daf-479c-8b93-bc654fa2bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372563820 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3372563820
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1567796740
Short name T156
Test name
Test status
Simulation time 7588396814 ps
CPU time 5.83 seconds
Started Feb 21 12:32:04 PM PST 24
Finished Feb 21 12:32:10 PM PST 24
Peak memory 183364 kb
Host smart-4174c4b7-7349-4603-9fb7-20ac96971fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567796740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1567796740
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.169670330
Short name T151
Test name
Test status
Simulation time 584125340 ps
CPU time 0.94 seconds
Started Feb 21 12:32:00 PM PST 24
Finished Feb 21 12:32:01 PM PST 24
Peak memory 183160 kb
Host smart-196efe90-aa3c-4dba-8037-09db99ae0486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169670330 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.169670330
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3482045290
Short name T161
Test name
Test status
Simulation time 43613248714 ps
CPU time 29.35 seconds
Started Feb 21 12:31:55 PM PST 24
Finished Feb 21 12:32:25 PM PST 24
Peak memory 183212 kb
Host smart-a9357b69-b287-422c-a396-f09896a3522f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482045290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3482045290
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1860301703
Short name T101
Test name
Test status
Simulation time 534719287 ps
CPU time 1.33 seconds
Started Feb 21 12:31:59 PM PST 24
Finished Feb 21 12:32:01 PM PST 24
Peak memory 183224 kb
Host smart-903fb4e4-4dd1-4a10-9d05-22aa16e219df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860301703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1860301703
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2723476523
Short name T288
Test name
Test status
Simulation time 15251770128 ps
CPU time 13.83 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:16 PM PST 24
Peak memory 183272 kb
Host smart-ba9fb3f2-0866-40a9-9bf3-fc1c3d630d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723476523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2723476523
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.246763502
Short name T139
Test name
Test status
Simulation time 479713130 ps
CPU time 1.24 seconds
Started Feb 21 12:32:07 PM PST 24
Finished Feb 21 12:32:08 PM PST 24
Peak memory 183144 kb
Host smart-500f7e10-3aa1-4e50-bde0-679ad2236b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246763502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.246763502
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.1513930125
Short name T95
Test name
Test status
Simulation time 126590474721 ps
CPU time 85.57 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:33:28 PM PST 24
Peak memory 183424 kb
Host smart-3977e2a4-feb8-41da-bc2b-b6fba731a469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513930125 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.1513930125
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1252026615
Short name T286
Test name
Test status
Simulation time 100159647431 ps
CPU time 268.15 seconds
Started Feb 21 12:31:58 PM PST 24
Finished Feb 21 12:36:27 PM PST 24
Peak memory 198188 kb
Host smart-731a798b-9a2d-4c49-a94f-f53bcb2fe5f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252026615 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1252026615
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4292865443
Short name T149
Test name
Test status
Simulation time 549604103 ps
CPU time 0.69 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183364 kb
Host smart-3782729b-386e-4c32-a85c-f6b4c237562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292865443 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4292865443
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.459032185
Short name T179
Test name
Test status
Simulation time 40358914261 ps
CPU time 8.97 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:11 PM PST 24
Peak memory 183312 kb
Host smart-2391b02e-c098-4837-93ea-bfdc59181018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459032185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.459032185
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1237168976
Short name T64
Test name
Test status
Simulation time 519399042 ps
CPU time 0.71 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183180 kb
Host smart-6fe747bb-0315-48cf-ba8c-cf993f0c35eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237168976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1237168976
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.990228131
Short name T230
Test name
Test status
Simulation time 16041083591 ps
CPU time 23.95 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:32:22 PM PST 24
Peak memory 183324 kb
Host smart-a9d63609-f0c3-41bc-b16f-6cfe6d389a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990228131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.990228131
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2939738269
Short name T268
Test name
Test status
Simulation time 46571782662 ps
CPU time 306.83 seconds
Started Feb 21 12:32:04 PM PST 24
Finished Feb 21 12:37:11 PM PST 24
Peak memory 198308 kb
Host smart-375c3d2a-2b53-44ef-a073-bb48ddf05b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939738269 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2939738269
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.933524037
Short name T113
Test name
Test status
Simulation time 592839654 ps
CPU time 0.62 seconds
Started Feb 21 12:32:08 PM PST 24
Finished Feb 21 12:32:09 PM PST 24
Peak memory 183364 kb
Host smart-cd649bc2-1db0-4f50-a776-29142d21837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933524037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.933524037
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.1488734304
Short name T190
Test name
Test status
Simulation time 55643187307 ps
CPU time 40.9 seconds
Started Feb 21 12:31:57 PM PST 24
Finished Feb 21 12:32:39 PM PST 24
Peak memory 183280 kb
Host smart-c1c18094-30b0-4841-abac-b290066daf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488734304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.1488734304
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.484871777
Short name T175
Test name
Test status
Simulation time 385162340 ps
CPU time 0.88 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:32:03 PM PST 24
Peak memory 183180 kb
Host smart-3d087a7a-0896-41b0-b5a4-4aeff57b1917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484871777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.484871777
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.621236014
Short name T275
Test name
Test status
Simulation time 519331607374 ps
CPU time 856.21 seconds
Started Feb 21 12:32:01 PM PST 24
Finished Feb 21 12:46:18 PM PST 24
Peak memory 193404 kb
Host smart-80852028-7e84-4bd6-8cf0-21fec8645aee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621236014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.621236014
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.3824050394
Short name T35
Test name
Test status
Simulation time 23604637952 ps
CPU time 129.5 seconds
Started Feb 21 12:31:54 PM PST 24
Finished Feb 21 12:34:04 PM PST 24
Peak memory 198180 kb
Host smart-bbaff9a6-7e57-4f14-940a-0d9c364cdfc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824050394 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.3824050394
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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