Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 28768 1 T1 11 T3 11 T4 11
bark[1] 853 1 T39 16 T91 79 T92 26
bark[2] 378 1 T91 206 T93 22 T94 26
bark[3] 292 1 T13 22 T49 16 T95 16
bark[4] 378 1 T16 17 T47 12 T41 17
bark[5] 459 1 T2 12 T14 35 T96 12
bark[6] 324 1 T39 95 T41 17 T82 60
bark[7] 720 1 T10 16 T39 36 T49 30
bark[8] 668 1 T97 31 T76 204 T77 201
bark[9] 786 1 T16 353 T98 12 T43 197
bark[10] 251 1 T14 21 T95 17 T93 16
bark[11] 652 1 T14 190 T17 26 T49 36
bark[12] 270 1 T99 16 T100 12 T101 35
bark[13] 490 1 T43 236 T102 12 T103 12
bark[14] 487 1 T15 13 T76 71 T77 149
bark[15] 502 1 T38 102 T91 94 T26 12
bark[16] 570 1 T37 4 T38 4 T40 72
bark[17] 330 1 T10 16 T38 85 T82 46
bark[18] 292 1 T14 26 T41 35 T42 16
bark[19] 485 1 T16 253 T104 12 T76 6
bark[20] 350 1 T33 12 T105 16 T106 16
bark[21] 454 1 T13 31 T14 21 T105 17
bark[22] 415 1 T14 16 T16 21 T105 26
bark[23] 360 1 T14 12 T41 16 T95 16
bark[24] 225 1 T107 12 T50 16 T108 6
bark[25] 243 1 T6 26 T109 12 T31 16
bark[26] 533 1 T105 17 T102 17 T110 170
bark[27] 381 1 T41 27 T24 12 T111 12
bark[28] 350 1 T13 16 T14 16 T95 12
bark[29] 289 1 T6 25 T16 17 T105 16
bark[30] 456 1 T32 13 T40 10 T82 17
bark[31] 343 1 T37 21 T112 22 T76 4
bark_0 3374 1 T1 4 T2 4 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 28039 1 T1 10 T3 10 T4 10
bite[1] 280 1 T15 12 T113 11 T106 17
bite[2] 337 1 T14 34 T99 25 T110 25
bite[3] 488 1 T105 17 T102 17 T50 126
bite[4] 99 1 T114 11 T76 16 T29 11
bite[5] 556 1 T30 16 T115 12 T107 16
bite[6] 304 1 T14 16 T37 3 T40 10
bite[7] 241 1 T103 11 T82 62 T116 16
bite[8] 960 1 T14 21 T16 17 T41 17
bite[9] 334 1 T10 16 T16 3 T41 34
bite[10] 349 1 T76 203 T117 16 T118 16
bite[11] 434 1 T2 11 T6 25 T105 17
bite[12] 1007 1 T39 35 T41 16 T43 22
bite[13] 706 1 T6 26 T13 22 T16 17
bite[14] 387 1 T82 17 T119 11 T120 16
bite[15] 89 1 T33 11 T47 11 T84 17
bite[16] 710 1 T13 16 T16 203 T105 16
bite[17] 499 1 T32 12 T38 101 T39 16
bite[18] 399 1 T16 17 T38 84 T109 11
bite[19] 511 1 T14 11 T17 26 T39 94
bite[20] 398 1 T49 36 T97 31 T78 128
bite[21] 119 1 T76 70 T121 16 T122 17
bite[22] 268 1 T14 16 T95 16 T123 17
bite[23] 435 1 T10 16 T14 20 T41 16
bite[24] 247 1 T13 31 T124 11 T105 16
bite[25] 386 1 T14 172 T92 17 T83 34
bite[26] 409 1 T42 17 T95 11 T125 30
bite[27] 264 1 T37 20 T38 3 T99 16
bite[28] 647 1 T104 11 T105 16 T91 93
bite[29] 635 1 T14 17 T16 252 T42 17
bite[30] 413 1 T14 26 T91 78 T78 16
bite[31] 825 1 T43 235 T110 169 T31 16
bite_0 3953 1 T1 5 T2 5 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 45728 1 T1 15 T2 16 T3 15


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1220 1 T14 8 T16 106 T42 96
prescale[1] 1183 1 T6 59 T13 15 T38 15
prescale[2] 648 1 T16 15 T39 2 T99 21
prescale[3] 642 1 T13 15 T16 31 T17 2
prescale[4] 582 1 T13 31 T16 47 T105 21
prescale[5] 729 1 T13 8 T16 8 T38 77
prescale[6] 604 1 T38 2 T43 15 T76 29
prescale[7] 1009 1 T14 15 T16 24 T40 47
prescale[8] 714 1 T16 15 T39 2 T43 32
prescale[9] 964 1 T6 18 T16 36 T42 45
prescale[10] 802 1 T14 55 T39 2 T91 2
prescale[11] 621 1 T10 15 T38 34 T42 15
prescale[12] 457 1 T14 4 T38 2 T41 25
prescale[13] 430 1 T14 29 T17 2 T37 2
prescale[14] 890 1 T14 41 T16 8 T38 36
prescale[15] 435 1 T10 15 T16 15 T17 2
prescale[16] 855 1 T16 29 T97 15 T91 63
prescale[17] 858 1 T6 8 T16 43 T41 81
prescale[18] 893 1 T10 15 T13 15 T16 22
prescale[19] 304 1 T14 31 T16 89 T37 2
prescale[20] 585 1 T5 8 T14 8 T16 2
prescale[21] 701 1 T3 8 T4 8 T11 8
prescale[22] 654 1 T16 86 T38 2 T40 2
prescale[23] 1187 1 T6 24 T7 8 T16 87
prescale[24] 598 1 T16 2 T38 2 T39 2
prescale[25] 681 1 T14 42 T16 35 T40 35
prescale[26] 435 1 T13 15 T38 2 T39 2
prescale[27] 844 1 T10 23 T13 33 T16 29
prescale[28] 915 1 T14 17 T16 73 T17 2
prescale[29] 568 1 T10 24 T14 49 T16 15
prescale[30] 813 1 T17 2 T38 10 T42 47
prescale[31] 859 1 T9 8 T14 68 T40 15
prescale_0 22048 1 T1 15 T2 16 T3 7


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34271 1 T1 6 T2 16 T3 15
auto[1] 11457 1 T1 9 T4 9 T6 89


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 45728 1 T1 15 T2 16 T3 15


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 28184 1 T1 12 T3 12 T4 12
wkup[1] 478 1 T16 23 T105 17 T125 13
wkup[2] 533 1 T33 13 T39 5 T41 17
wkup[3] 493 1 T13 16 T14 17 T38 16
wkup[4] 505 1 T13 16 T16 16 T38 5
wkup[5] 458 1 T14 48 T16 16 T43 32
wkup[6] 502 1 T13 22 T16 16 T39 27
wkup[7] 410 1 T6 25 T16 16 T17 26
wkup[8] 570 1 T6 26 T14 26 T16 16
wkup[9] 607 1 T16 16 T17 16 T42 17
wkup[10] 378 1 T16 33 T47 13 T110 21
wkup[11] 394 1 T16 33 T105 26 T91 22
wkup[12] 412 1 T16 48 T40 33 T112 22
wkup[13] 691 1 T14 21 T17 26 T41 29
wkup[14] 505 1 T16 56 T40 16 T41 16
wkup[15] 496 1 T16 16 T32 14 T17 16
wkup[16] 424 1 T16 17 T38 26 T40 26
wkup[17] 501 1 T38 16 T39 13 T40 26
wkup[18] 525 1 T6 26 T16 5 T39 16
wkup[19] 409 1 T16 16 T37 5 T41 17
wkup[20] 487 1 T14 16 T16 16 T43 16
wkup[21] 513 1 T13 32 T16 16 T105 16
wkup[22] 476 1 T14 42 T16 13 T39 16
wkup[23] 480 1 T16 17 T42 32 T105 32
wkup[24] 385 1 T10 16 T49 13 T43 16
wkup[25] 460 1 T14 13 T16 16 T41 43
wkup[26] 359 1 T42 16 T76 16 T83 16
wkup[27] 484 1 T49 16 T43 16 T91 13
wkup[28] 517 1 T42 22 T43 37 T91 16
wkup[29] 606 1 T2 13 T14 21 T110 41
wkup[30] 392 1 T15 14 T14 16 T16 17
wkup[31] 251 1 T10 16 T38 39 T99 13
wkup_0 2843 1 T1 3 T2 3 T3 3

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