Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
8452 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
2 |
all_values[1] |
8452 |
1 |
|
T1 |
3 |
|
T2 |
2 |
|
T3 |
2 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15277 |
1 |
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
3 |
auto[1] |
1627 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12279 |
1 |
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
3 |
auto[1] |
4625 |
1 |
|
T1 |
2 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
5419 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
all_values[0] |
auto[0] |
auto[1] |
1735 |
1 |
|
T1 |
1 |
|
T6 |
10 |
|
T10 |
3 |
all_values[0] |
auto[1] |
auto[0] |
179 |
1 |
|
T1 |
1 |
|
T6 |
2 |
|
T10 |
2 |
all_values[0] |
auto[1] |
auto[1] |
1119 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
all_values[1] |
auto[0] |
auto[0] |
6529 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
2 |
all_values[1] |
auto[0] |
auto[1] |
1594 |
1 |
|
T1 |
1 |
|
T6 |
16 |
|
T10 |
3 |
all_values[1] |
auto[1] |
auto[0] |
152 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
2 |
all_values[1] |
auto[1] |
auto[1] |
177 |
1 |
|
T6 |
1 |
|
T10 |
1 |
|
T12 |
1 |