Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.82 95.31 100.00 99.35 100.00 96.64


Total test records in report: 430
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T280 /workspace/coverage/default/26.aon_timer_prescaler.1355826209 Feb 25 01:31:56 PM PST 24 Feb 25 01:32:07 PM PST 24 18332430027 ps
T281 /workspace/coverage/default/11.aon_timer_stress_all.330632259 Feb 25 01:31:37 PM PST 24 Feb 25 01:33:37 PM PST 24 289683096253 ps
T282 /workspace/coverage/default/38.aon_timer_jump.2388321601 Feb 25 01:32:04 PM PST 24 Feb 25 01:32:05 PM PST 24 428432483 ps
T283 /workspace/coverage/default/18.aon_timer_stress_all.2285736608 Feb 25 01:31:50 PM PST 24 Feb 25 01:33:53 PM PST 24 303277938154 ps
T284 /workspace/coverage/default/40.aon_timer_jump.2490301208 Feb 25 01:32:22 PM PST 24 Feb 25 01:32:23 PM PST 24 490487191 ps
T285 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2095772608 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 416658964 ps
T34 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1348650591 Feb 25 01:42:56 PM PST 24 Feb 25 01:43:01 PM PST 24 4482345237 ps
T286 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1858398836 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 336869118 ps
T287 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2955881293 Feb 25 01:42:50 PM PST 24 Feb 25 01:42:53 PM PST 24 897331620 ps
T35 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.435557182 Feb 25 01:42:52 PM PST 24 Feb 25 01:42:58 PM PST 24 3925987764 ps
T36 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.489302130 Feb 25 01:42:56 PM PST 24 Feb 25 01:43:03 PM PST 24 4017956081 ps
T88 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3833395091 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:59 PM PST 24 4449684397 ps
T288 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1260683716 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:54 PM PST 24 395032002 ps
T289 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1519956778 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:48 PM PST 24 759965014 ps
T290 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1460030998 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:49 PM PST 24 4062246009 ps
T291 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2478246290 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:50 PM PST 24 406257279 ps
T292 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3909270722 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 499963682 ps
T89 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2553712220 Feb 25 01:42:54 PM PST 24 Feb 25 01:42:57 PM PST 24 8412364086 ps
T293 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2367909135 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:55 PM PST 24 3940176974 ps
T294 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2400429962 Feb 25 01:43:11 PM PST 24 Feb 25 01:43:12 PM PST 24 430810823 ps
T51 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3420651114 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:50 PM PST 24 521515688 ps
T295 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3945373174 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:48 PM PST 24 743771668 ps
T296 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1626230509 Feb 25 01:42:31 PM PST 24 Feb 25 01:42:34 PM PST 24 8559618818 ps
T52 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1769201476 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:44 PM PST 24 659511311 ps
T297 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3408881322 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:53 PM PST 24 525798259 ps
T298 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.132593332 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:49 PM PST 24 391686161 ps
T65 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1491134343 Feb 25 01:42:31 PM PST 24 Feb 25 01:42:33 PM PST 24 1150240057 ps
T299 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1807792714 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:46 PM PST 24 497608692 ps
T300 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2904470180 Feb 25 01:42:52 PM PST 24 Feb 25 01:42:53 PM PST 24 386230351 ps
T53 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1569871102 Feb 25 01:42:32 PM PST 24 Feb 25 01:42:33 PM PST 24 735376096 ps
T301 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2469175491 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:46 PM PST 24 1114078835 ps
T302 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2457549995 Feb 25 01:42:32 PM PST 24 Feb 25 01:42:39 PM PST 24 4395693877 ps
T66 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3145876235 Feb 25 01:42:54 PM PST 24 Feb 25 01:42:57 PM PST 24 1665302011 ps
T303 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3654868172 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 313777298 ps
T54 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.785868246 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:48 PM PST 24 612464883 ps
T304 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.824796319 Feb 25 01:42:32 PM PST 24 Feb 25 01:42:33 PM PST 24 589350842 ps
T305 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1633417015 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 354876493 ps
T67 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2693197953 Feb 25 01:42:53 PM PST 24 Feb 25 01:42:55 PM PST 24 2055936202 ps
T306 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1714958628 Feb 25 01:42:59 PM PST 24 Feb 25 01:43:01 PM PST 24 482059701 ps
T307 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.863439949 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:48 PM PST 24 545803387 ps
T308 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2878050523 Feb 25 01:42:59 PM PST 24 Feb 25 01:43:01 PM PST 24 454631453 ps
T309 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3232541023 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:49 PM PST 24 569167756 ps
T68 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1556631982 Feb 25 01:42:50 PM PST 24 Feb 25 01:42:51 PM PST 24 887838556 ps
T310 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3645096081 Feb 25 01:42:41 PM PST 24 Feb 25 01:42:47 PM PST 24 8724229686 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1143258626 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:45 PM PST 24 486707302 ps
T312 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1197094997 Feb 25 01:43:05 PM PST 24 Feb 25 01:43:06 PM PST 24 348551381 ps
T313 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1419463721 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:46 PM PST 24 547111386 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1538696504 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:34 PM PST 24 330233701 ps
T55 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2342000908 Feb 25 01:42:54 PM PST 24 Feb 25 01:42:56 PM PST 24 344618541 ps
T315 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3677552764 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 468947873 ps
T316 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1476908714 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:47 PM PST 24 293062026 ps
T317 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.450327291 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 494205903 ps
T318 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2512700533 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 503586752 ps
T319 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3333185347 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 636425237 ps
T320 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3026487113 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 427016872 ps
T321 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1085834647 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 457852093 ps
T322 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2133084111 Feb 25 01:42:54 PM PST 24 Feb 25 01:43:01 PM PST 24 4206688717 ps
T323 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1575670920 Feb 25 01:42:34 PM PST 24 Feb 25 01:42:35 PM PST 24 288132793 ps
T56 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1791107830 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:47 PM PST 24 314139643 ps
T324 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3541837644 Feb 25 01:42:37 PM PST 24 Feb 25 01:42:40 PM PST 24 6108460850 ps
T325 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3070468965 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:51 PM PST 24 7893674899 ps
T326 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1447113780 Feb 25 01:42:59 PM PST 24 Feb 25 01:43:00 PM PST 24 394404141 ps
T69 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.987216793 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 972531882 ps
T327 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1562277648 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:51 PM PST 24 372586383 ps
T328 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.427437440 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:03 PM PST 24 508048710 ps
T329 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3799803495 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:34 PM PST 24 801143247 ps
T330 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3769299387 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:59 PM PST 24 479467846 ps
T331 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1535307319 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 270270830 ps
T332 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2033958898 Feb 25 01:42:34 PM PST 24 Feb 25 01:42:35 PM PST 24 479190796 ps
T333 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.252477648 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 366322781 ps
T334 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3196697465 Feb 25 01:43:02 PM PST 24 Feb 25 01:43:03 PM PST 24 297296192 ps
T335 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4100496044 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 349745976 ps
T336 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.35676215 Feb 25 01:43:05 PM PST 24 Feb 25 01:43:06 PM PST 24 526979193 ps
T337 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.610157208 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:43 PM PST 24 407643984 ps
T338 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.810067984 Feb 25 01:42:34 PM PST 24 Feb 25 01:42:37 PM PST 24 4688459796 ps
T339 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1360911253 Feb 25 01:43:03 PM PST 24 Feb 25 01:43:04 PM PST 24 306523153 ps
T340 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3813242450 Feb 25 01:42:53 PM PST 24 Feb 25 01:42:55 PM PST 24 427359769 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.900631423 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:47 PM PST 24 428751029 ps
T70 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.595589408 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:49 PM PST 24 2124176835 ps
T342 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2694688117 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:51 PM PST 24 8628794877 ps
T343 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3870029426 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 358559693 ps
T57 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2381146987 Feb 25 01:42:31 PM PST 24 Feb 25 01:42:32 PM PST 24 638746979 ps
T344 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3990320680 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 570255170 ps
T345 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3170197664 Feb 25 01:42:31 PM PST 24 Feb 25 01:42:32 PM PST 24 420203249 ps
T346 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2752251743 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 591769453 ps
T347 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1095243527 Feb 25 01:43:03 PM PST 24 Feb 25 01:43:05 PM PST 24 455314919 ps
T348 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2273215883 Feb 25 01:42:41 PM PST 24 Feb 25 01:42:42 PM PST 24 315693302 ps
T71 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3265425318 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:59 PM PST 24 1996903008 ps
T349 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2145470827 Feb 25 01:43:00 PM PST 24 Feb 25 01:43:01 PM PST 24 374499624 ps
T350 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1621386831 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:52 PM PST 24 491770321 ps
T58 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1763625328 Feb 25 01:42:45 PM PST 24 Feb 25 01:43:00 PM PST 24 11339640650 ps
T351 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3773766883 Feb 25 01:43:06 PM PST 24 Feb 25 01:43:07 PM PST 24 437517203 ps
T352 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2891787131 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:48 PM PST 24 306727049 ps
T353 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3864403136 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:03 PM PST 24 490175388 ps
T72 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.890177139 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:52 PM PST 24 1410137200 ps
T354 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2187751149 Feb 25 01:42:56 PM PST 24 Feb 25 01:42:56 PM PST 24 444748153 ps
T73 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1299700811 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 2015146695 ps
T355 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2819630260 Feb 25 01:43:02 PM PST 24 Feb 25 01:43:03 PM PST 24 442633153 ps
T356 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3138825149 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:34 PM PST 24 510270525 ps
T59 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1645840682 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:57 PM PST 24 11315087168 ps
T357 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3569477030 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:50 PM PST 24 2068182432 ps
T358 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1989310204 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:46 PM PST 24 310068022 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.973117826 Feb 25 01:42:53 PM PST 24 Feb 25 01:42:55 PM PST 24 587791686 ps
T360 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1290964176 Feb 25 01:43:02 PM PST 24 Feb 25 01:43:03 PM PST 24 427290722 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1371779356 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:48 PM PST 24 2092695462 ps
T63 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2032447274 Feb 25 01:42:36 PM PST 24 Feb 25 01:42:38 PM PST 24 992242769 ps
T362 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2075912358 Feb 25 01:42:53 PM PST 24 Feb 25 01:42:54 PM PST 24 474051161 ps
T363 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.228744688 Feb 25 01:42:56 PM PST 24 Feb 25 01:42:57 PM PST 24 446369958 ps
T364 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.239310112 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:52 PM PST 24 8539895778 ps
T365 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2647548522 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 1405717254 ps
T366 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2542707304 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:53 PM PST 24 622610805 ps
T367 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1246972822 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:54 PM PST 24 4361171516 ps
T368 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3628498074 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:46 PM PST 24 534797909 ps
T369 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.716612585 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 1125128777 ps
T90 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1341193759 Feb 25 01:42:52 PM PST 24 Feb 25 01:42:57 PM PST 24 7981420746 ps
T370 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3462262414 Feb 25 01:42:59 PM PST 24 Feb 25 01:43:00 PM PST 24 466993611 ps
T371 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2438490152 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:47 PM PST 24 1636795115 ps
T372 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2271079518 Feb 25 01:42:55 PM PST 24 Feb 25 01:42:56 PM PST 24 410174504 ps
T373 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3363475457 Feb 25 01:42:34 PM PST 24 Feb 25 01:42:35 PM PST 24 446599177 ps
T374 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2420637744 Feb 25 01:42:53 PM PST 24 Feb 25 01:43:05 PM PST 24 8163995924 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.668335721 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:44 PM PST 24 543704970 ps
T376 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1754956487 Feb 25 01:42:32 PM PST 24 Feb 25 01:42:34 PM PST 24 441397809 ps
T377 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3562256086 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 405344386 ps
T378 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3343390789 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 411092032 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1878607920 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 450710091 ps
T380 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3916741121 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:04 PM PST 24 347404175 ps
T60 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2528990373 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 541800165 ps
T381 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4113643644 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:52 PM PST 24 471656092 ps
T382 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.625835502 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:48 PM PST 24 5941402999 ps
T383 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1978505989 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:46 PM PST 24 543346706 ps
T384 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2465037221 Feb 25 01:43:05 PM PST 24 Feb 25 01:43:06 PM PST 24 490377828 ps
T385 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1104067099 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 585462531 ps
T386 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4230997521 Feb 25 01:42:30 PM PST 24 Feb 25 01:42:32 PM PST 24 433389090 ps
T64 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1025885203 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 393452093 ps
T387 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3267197968 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:49 PM PST 24 904701033 ps
T388 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2744620430 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 405782606 ps
T389 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3951574910 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:03 PM PST 24 513721577 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2770834298 Feb 25 01:42:42 PM PST 24 Feb 25 01:42:43 PM PST 24 536092462 ps
T391 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1234057794 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 571474897 ps
T392 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2841852380 Feb 25 01:42:45 PM PST 24 Feb 25 01:42:46 PM PST 24 603992328 ps
T393 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.289860226 Feb 25 01:42:54 PM PST 24 Feb 25 01:42:56 PM PST 24 556735153 ps
T394 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3328519000 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 478413057 ps
T395 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2054462565 Feb 25 01:42:36 PM PST 24 Feb 25 01:42:36 PM PST 24 538458792 ps
T396 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3812054945 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:50 PM PST 24 522516261 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.488394725 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:46 PM PST 24 1099359143 ps
T398 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2415157162 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 307865324 ps
T399 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1380939564 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:03 PM PST 24 543881212 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3272359023 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:44 PM PST 24 343505896 ps
T401 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.688584931 Feb 25 01:42:57 PM PST 24 Feb 25 01:42:58 PM PST 24 707807196 ps
T402 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3586449166 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:35 PM PST 24 704668359 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.803490929 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:48 PM PST 24 509878811 ps
T404 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1354337174 Feb 25 01:42:33 PM PST 24 Feb 25 01:42:35 PM PST 24 783171877 ps
T405 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2901412872 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:57 PM PST 24 1989648170 ps
T406 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.338321438 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 533026163 ps
T407 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3115702896 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:53 PM PST 24 449258907 ps
T408 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.422909013 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:49 PM PST 24 686512728 ps
T409 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1047637869 Feb 25 01:42:44 PM PST 24 Feb 25 01:42:45 PM PST 24 419222041 ps
T410 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1406472102 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:48 PM PST 24 406124667 ps
T411 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.961096551 Feb 25 01:43:00 PM PST 24 Feb 25 01:43:02 PM PST 24 461069730 ps
T412 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2440412442 Feb 25 01:42:59 PM PST 24 Feb 25 01:43:00 PM PST 24 517228582 ps
T413 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1247753624 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:50 PM PST 24 380915696 ps
T414 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3941047346 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:48 PM PST 24 562973725 ps
T61 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2777333871 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 438530651 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3196820206 Feb 25 01:42:51 PM PST 24 Feb 25 01:42:55 PM PST 24 8438093161 ps
T416 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3733710769 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:56 PM PST 24 2023006153 ps
T417 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3329660666 Feb 25 01:42:47 PM PST 24 Feb 25 01:43:01 PM PST 24 7645715032 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1983601548 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:48 PM PST 24 3648318637 ps
T418 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3890462638 Feb 25 01:42:43 PM PST 24 Feb 25 01:42:44 PM PST 24 959455979 ps
T419 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2929456857 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 439100991 ps
T420 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1286320598 Feb 25 01:42:48 PM PST 24 Feb 25 01:42:49 PM PST 24 484975583 ps
T421 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1852047375 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 417123410 ps
T422 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.894388637 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 488953079 ps
T423 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2694212145 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 466328027 ps
T424 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1053206462 Feb 25 01:43:01 PM PST 24 Feb 25 01:43:02 PM PST 24 427439225 ps
T425 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2056947234 Feb 25 01:42:47 PM PST 24 Feb 25 01:42:49 PM PST 24 527488665 ps
T426 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3978793479 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 379805858 ps
T427 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1208675363 Feb 25 01:42:49 PM PST 24 Feb 25 01:42:50 PM PST 24 486990122 ps
T428 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2632251642 Feb 25 01:42:36 PM PST 24 Feb 25 01:42:38 PM PST 24 498258297 ps
T429 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2925906602 Feb 25 01:42:46 PM PST 24 Feb 25 01:42:47 PM PST 24 1162279777 ps
T430 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2229932597 Feb 25 01:42:52 PM PST 24 Feb 25 01:42:54 PM PST 24 351098263 ps

Test location /workspace/coverage/default/25.aon_timer_stress_all.979422177
Short name T6
Test name
Test status
Simulation time 101874466513 ps
CPU time 76.47 seconds
Started Feb 25 01:31:58 PM PST 24
Finished Feb 25 01:33:14 PM PST 24
Peak memory 194788 kb
Host smart-e91af251-680d-44ad-8231-eac95b61d2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979422177 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_a
ll.979422177
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.878723325
Short name T16
Test name
Test status
Simulation time 49309922026 ps
CPU time 394.1 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:38:54 PM PST 24
Peak memory 198320 kb
Host smart-282c3d7b-7113-4576-84b2-b6e758e86968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878723325 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.878723325
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.14800452
Short name T14
Test name
Test status
Simulation time 111387234385 ps
CPU time 621.65 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:42:11 PM PST 24
Peak memory 198940 kb
Host smart-929ecb87-6572-491b-8771-39d513e01d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800452 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.14800452
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3833395091
Short name T88
Test name
Test status
Simulation time 4449684397 ps
CPU time 1.54 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:59 PM PST 24
Peak memory 195552 kb
Host smart-eedbbdc2-f891-4ee4-ae83-9941598b68b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833395091 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3833395091
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2823063430
Short name T76
Test name
Test status
Simulation time 246916904516 ps
CPU time 393.55 seconds
Started Feb 25 01:31:52 PM PST 24
Finished Feb 25 01:38:27 PM PST 24
Peak memory 198360 kb
Host smart-6ed90ddf-f633-4c76-ae28-6c97bcf184b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823063430 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2823063430
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.109471579
Short name T50
Test name
Test status
Simulation time 46900942739 ps
CPU time 384.75 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:38:21 PM PST 24
Peak memory 198372 kb
Host smart-16a83643-9f25-4d93-9359-59cf8e1dfe85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109471579 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.109471579
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.2266837772
Short name T118
Test name
Test status
Simulation time 146927896421 ps
CPU time 603.68 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:41:56 PM PST 24
Peak memory 199080 kb
Host smart-632ce52d-d145-4b4d-88de-6e1756f96bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266837772 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.2266837772
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.2597698418
Short name T39
Test name
Test status
Simulation time 78224168469 ps
CPU time 633.95 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:42:27 PM PST 24
Peak memory 198876 kb
Host smart-8df5ab11-3b92-477e-9ec7-e8b87212eba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597698418 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.2597698418
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.3505719929
Short name T22
Test name
Test status
Simulation time 4024229616 ps
CPU time 2.04 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:39 PM PST 24
Peak memory 215112 kb
Host smart-6e273cd6-79c1-4c22-bba3-f90ce303d1e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505719929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.3505719929
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.1341416309
Short name T79
Test name
Test status
Simulation time 58617303422 ps
CPU time 614.64 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:41:48 PM PST 24
Peak memory 198340 kb
Host smart-c92ae731-e417-4b16-97c8-8b46c6e1efc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341416309 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.1341416309
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.1426123968
Short name T189
Test name
Test status
Simulation time 138041788339 ps
CPU time 558.12 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:41:10 PM PST 24
Peak memory 199100 kb
Host smart-840e0d37-7134-4db9-b5da-d274f506b57d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426123968 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.1426123968
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.151473279
Short name T82
Test name
Test status
Simulation time 52351973420 ps
CPU time 395.86 seconds
Started Feb 25 01:31:40 PM PST 24
Finished Feb 25 01:38:16 PM PST 24
Peak memory 198352 kb
Host smart-12a26845-964e-45bd-89d5-5bc15f5d8e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151473279 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.151473279
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.604844095
Short name T49
Test name
Test status
Simulation time 344990501404 ps
CPU time 134.16 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:34:08 PM PST 24
Peak memory 194816 kb
Host smart-b1432709-19af-4158-8ae7-831393b98e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604844095 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_a
ll.604844095
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2381146987
Short name T57
Test name
Test status
Simulation time 638746979 ps
CPU time 0.94 seconds
Started Feb 25 01:42:31 PM PST 24
Finished Feb 25 01:42:32 PM PST 24
Peak memory 192604 kb
Host smart-5698363b-6de1-4245-bb39-e1ef207f601d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381146987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2381146987
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1491134343
Short name T65
Test name
Test status
Simulation time 1150240057 ps
CPU time 1.38 seconds
Started Feb 25 01:42:31 PM PST 24
Finished Feb 25 01:42:33 PM PST 24
Peak memory 192836 kb
Host smart-a7f34b02-50f7-45be-b68e-f4628be9fda3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491134343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1491134343
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1341193759
Short name T90
Test name
Test status
Simulation time 7981420746 ps
CPU time 4.68 seconds
Started Feb 25 01:42:52 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 197192 kb
Host smart-8e571b09-13c2-490a-a7d9-3f64ae880b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341193759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1341193759
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.435557182
Short name T35
Test name
Test status
Simulation time 3925987764 ps
CPU time 6.12 seconds
Started Feb 25 01:42:52 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 195656 kb
Host smart-2eafc2ee-9ac4-4cc2-b760-cc72a75b73a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435557182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.435557182
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.1645840682
Short name T59
Test name
Test status
Simulation time 11315087168 ps
CPU time 23.67 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 191764 kb
Host smart-c581df9b-c7d0-400f-8372-a8b937d21ef0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645840682 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.1645840682
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.3799803495
Short name T329
Test name
Test status
Simulation time 801143247 ps
CPU time 0.84 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:34 PM PST 24
Peak memory 183292 kb
Host smart-a995fa7a-cf6a-46dd-8aa3-aef7e2460ef6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799803495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.3799803495
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.1754956487
Short name T376
Test name
Test status
Simulation time 441397809 ps
CPU time 0.89 seconds
Started Feb 25 01:42:32 PM PST 24
Finished Feb 25 01:42:34 PM PST 24
Peak memory 195116 kb
Host smart-60a3c6f7-40bf-450d-a012-49e360284c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754956487 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.1754956487
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.1538696504
Short name T314
Test name
Test status
Simulation time 330233701 ps
CPU time 0.76 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:34 PM PST 24
Peak memory 183360 kb
Host smart-42edee2e-29b7-44ac-b162-9c0995d8e01c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538696504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.1538696504
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.2054462565
Short name T395
Test name
Test status
Simulation time 538458792 ps
CPU time 0.68 seconds
Started Feb 25 01:42:36 PM PST 24
Finished Feb 25 01:42:36 PM PST 24
Peak memory 183296 kb
Host smart-83af1415-338c-4c56-8a65-bf689f67e1df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054462565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.2054462565
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.824796319
Short name T304
Test name
Test status
Simulation time 589350842 ps
CPU time 0.61 seconds
Started Feb 25 01:42:32 PM PST 24
Finished Feb 25 01:42:33 PM PST 24
Peak memory 182960 kb
Host smart-d37ae4c1-bd5b-4d75-a153-8423d523b88a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824796319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_ti
mer_mem_partial_access.824796319
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3363475457
Short name T373
Test name
Test status
Simulation time 446599177 ps
CPU time 1.12 seconds
Started Feb 25 01:42:34 PM PST 24
Finished Feb 25 01:42:35 PM PST 24
Peak memory 183088 kb
Host smart-6456260f-9501-40d9-9573-403a0212fc73
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363475457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3363475457
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2632251642
Short name T428
Test name
Test status
Simulation time 498258297 ps
CPU time 2.14 seconds
Started Feb 25 01:42:36 PM PST 24
Finished Feb 25 01:42:38 PM PST 24
Peak memory 197232 kb
Host smart-36d57259-e296-464a-bbf1-a3839ece1c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632251642 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2632251642
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.810067984
Short name T338
Test name
Test status
Simulation time 4688459796 ps
CPU time 2.49 seconds
Started Feb 25 01:42:34 PM PST 24
Finished Feb 25 01:42:37 PM PST 24
Peak memory 196748 kb
Host smart-248bd0bd-a927-4b4e-bf6f-ba311e25beed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810067984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.810067984
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1569871102
Short name T53
Test name
Test status
Simulation time 735376096 ps
CPU time 0.78 seconds
Started Feb 25 01:42:32 PM PST 24
Finished Feb 25 01:42:33 PM PST 24
Peak memory 193360 kb
Host smart-30de6817-8751-4192-8d6a-17680a705fae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569871102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1569871102
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3541837644
Short name T324
Test name
Test status
Simulation time 6108460850 ps
CPU time 2.92 seconds
Started Feb 25 01:42:37 PM PST 24
Finished Feb 25 01:42:40 PM PST 24
Peak memory 191772 kb
Host smart-de42aba6-cb38-4eff-b746-b5ddca6ffa44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541837644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3541837644
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2032447274
Short name T63
Test name
Test status
Simulation time 992242769 ps
CPU time 2.16 seconds
Started Feb 25 01:42:36 PM PST 24
Finished Feb 25 01:42:38 PM PST 24
Peak memory 183324 kb
Host smart-ca169b7f-d4be-4267-8eb9-c0ffdb3ff3a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032447274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2032447274
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3170197664
Short name T345
Test name
Test status
Simulation time 420203249 ps
CPU time 0.89 seconds
Started Feb 25 01:42:31 PM PST 24
Finished Feb 25 01:42:32 PM PST 24
Peak memory 196324 kb
Host smart-087eee9f-5907-4356-9e93-68940a6cb9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170197664 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3170197664
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.4230997521
Short name T386
Test name
Test status
Simulation time 433389090 ps
CPU time 1.17 seconds
Started Feb 25 01:42:30 PM PST 24
Finished Feb 25 01:42:32 PM PST 24
Peak memory 183360 kb
Host smart-020b9f6e-f932-4e55-8151-3666d5752519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230997521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.4230997521
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3138825149
Short name T356
Test name
Test status
Simulation time 510270525 ps
CPU time 0.68 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:34 PM PST 24
Peak memory 183084 kb
Host smart-7753e6ec-457f-49b0-9370-0eb14b5ec1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138825149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3138825149
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.2033958898
Short name T332
Test name
Test status
Simulation time 479190796 ps
CPU time 0.67 seconds
Started Feb 25 01:42:34 PM PST 24
Finished Feb 25 01:42:35 PM PST 24
Peak memory 183236 kb
Host smart-af0ae28b-3847-48c5-8eb0-5f8de5d4f558
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033958898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.2033958898
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1575670920
Short name T323
Test name
Test status
Simulation time 288132793 ps
CPU time 0.62 seconds
Started Feb 25 01:42:34 PM PST 24
Finished Feb 25 01:42:35 PM PST 24
Peak memory 183292 kb
Host smart-1827b47b-790a-4e19-9173-95432a840273
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575670920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1575670920
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.488394725
Short name T397
Test name
Test status
Simulation time 1099359143 ps
CPU time 1.89 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 192884 kb
Host smart-1fa3587f-68f3-4c76-bdbf-acd8b1a51981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488394725 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.488394725
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.3586449166
Short name T402
Test name
Test status
Simulation time 704668359 ps
CPU time 2.05 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:35 PM PST 24
Peak memory 198064 kb
Host smart-4a58da92-d360-4935-81d7-544321b04041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586449166 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.3586449166
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2457549995
Short name T302
Test name
Test status
Simulation time 4395693877 ps
CPU time 7.04 seconds
Started Feb 25 01:42:32 PM PST 24
Finished Feb 25 01:42:39 PM PST 24
Peak memory 196556 kb
Host smart-aa53307f-b045-45d2-bcd7-1178504c9551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457549995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2457549995
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.4113643644
Short name T381
Test name
Test status
Simulation time 471656092 ps
CPU time 0.8 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 194044 kb
Host smart-50cddb7f-f3a5-4875-9dbf-e06da48314cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113643644 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.4113643644
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3813242450
Short name T340
Test name
Test status
Simulation time 427359769 ps
CPU time 1.27 seconds
Started Feb 25 01:42:53 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 183272 kb
Host smart-67e9bdbd-380e-436b-98aa-f58784697cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813242450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3813242450
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2904470180
Short name T300
Test name
Test status
Simulation time 386230351 ps
CPU time 0.7 seconds
Started Feb 25 01:42:52 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 183284 kb
Host smart-007253bb-a1f3-457b-a594-be11b30bb7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904470180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2904470180
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1556631982
Short name T68
Test name
Test status
Simulation time 887838556 ps
CPU time 1.06 seconds
Started Feb 25 01:42:50 PM PST 24
Finished Feb 25 01:42:51 PM PST 24
Peak memory 193812 kb
Host smart-70f3e437-9148-4f22-8709-d51428679f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556631982 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1556631982
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1562277648
Short name T327
Test name
Test status
Simulation time 372586383 ps
CPU time 2.66 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:51 PM PST 24
Peak memory 198184 kb
Host smart-0d285548-c976-4758-89c5-4843f901da3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562277648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1562277648
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.688584931
Short name T401
Test name
Test status
Simulation time 707807196 ps
CPU time 1.06 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 198008 kb
Host smart-cad8ad4a-baf3-4d63-9b10-d7002f90a910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688584931 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.688584931
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1234057794
Short name T391
Test name
Test status
Simulation time 571474897 ps
CPU time 0.79 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183348 kb
Host smart-db2cf11b-ba25-4ef3-a390-de7849a48e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234057794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1234057794
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3654868172
Short name T303
Test name
Test status
Simulation time 313777298 ps
CPU time 1.03 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 183068 kb
Host smart-e9814a5a-d2d7-4605-ab24-8fb4f426dd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654868172 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3654868172
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.3569477030
Short name T357
Test name
Test status
Simulation time 2068182432 ps
CPU time 1.06 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 194752 kb
Host smart-f825088d-ec06-43cc-8723-0747fb3fe40b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569477030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.3569477030
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2955881293
Short name T287
Test name
Test status
Simulation time 897331620 ps
CPU time 2.28 seconds
Started Feb 25 01:42:50 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 198156 kb
Host smart-0ad57221-68e5-4422-adb4-0e90ede46cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955881293 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2955881293
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.1348650591
Short name T34
Test name
Test status
Simulation time 4482345237 ps
CPU time 4.3 seconds
Started Feb 25 01:42:56 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 196860 kb
Host smart-f32de6ab-71dc-4210-b174-023c08a6ea7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348650591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.1348650591
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.338321438
Short name T406
Test name
Test status
Simulation time 533026163 ps
CPU time 0.97 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 194740 kb
Host smart-00268084-226c-4990-9cf9-6a9df10604b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338321438 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.338321438
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3677552764
Short name T315
Test name
Test status
Simulation time 468947873 ps
CPU time 1.21 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183308 kb
Host smart-b3435494-5dc2-4ac2-a414-868fc0dd8ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677552764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3677552764
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2187751149
Short name T354
Test name
Test status
Simulation time 444748153 ps
CPU time 0.61 seconds
Started Feb 25 01:42:56 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 183344 kb
Host smart-c04c65fe-d9ff-471c-a98f-724b037f49e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187751149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2187751149
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2693197953
Short name T67
Test name
Test status
Simulation time 2055936202 ps
CPU time 1.54 seconds
Started Feb 25 01:42:53 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 192760 kb
Host smart-a8b5c68c-8a0a-46e7-b631-7d2af250ba95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693197953 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2693197953
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.1621386831
Short name T350
Test name
Test status
Simulation time 491770321 ps
CPU time 1.97 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 198160 kb
Host smart-bca995f6-9b3f-4a73-83cf-a199768ab7d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621386831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.1621386831
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2420637744
Short name T374
Test name
Test status
Simulation time 8163995924 ps
CPU time 11.4 seconds
Started Feb 25 01:42:53 PM PST 24
Finished Feb 25 01:43:05 PM PST 24
Peak memory 197140 kb
Host smart-abaae911-3268-4c91-a98d-9738316b783a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420637744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2420637744
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.973117826
Short name T359
Test name
Test status
Simulation time 587791686 ps
CPU time 1.58 seconds
Started Feb 25 01:42:53 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 194900 kb
Host smart-5218fe1e-9253-43d0-ab60-43ab6ebd09e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973117826 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.973117826
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.4100496044
Short name T335
Test name
Test status
Simulation time 349745976 ps
CPU time 0.66 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 183408 kb
Host smart-81d92e99-a252-4870-8479-2c2097077ff2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100496044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.4100496044
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.2478246290
Short name T291
Test name
Test status
Simulation time 406257279 ps
CPU time 1.17 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183028 kb
Host smart-8990d0d7-ded3-44b3-922f-a55667fb209b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478246290 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.2478246290
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.716612585
Short name T369
Test name
Test status
Simulation time 1125128777 ps
CPU time 1.33 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 193764 kb
Host smart-dd917385-955e-45d9-aff5-0b7a607a5f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716612585 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon
_timer_same_csr_outstanding.716612585
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1260683716
Short name T288
Test name
Test status
Simulation time 395032002 ps
CPU time 2.8 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:54 PM PST 24
Peak memory 198112 kb
Host smart-eabd85cc-4eae-45ea-8327-3d459cc9df80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260683716 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1260683716
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.2553712220
Short name T89
Test name
Test status
Simulation time 8412364086 ps
CPU time 3.13 seconds
Started Feb 25 01:42:54 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 197352 kb
Host smart-c40f4bb2-4523-4b27-bc7b-30f2f27c7320
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553712220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.2553712220
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.2542707304
Short name T366
Test name
Test status
Simulation time 622610805 ps
CPU time 1.66 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 195408 kb
Host smart-cb1af633-9a80-4a70-92c7-8e9c671f06c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542707304 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.2542707304
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3978793479
Short name T426
Test name
Test status
Simulation time 379805858 ps
CPU time 1.24 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183304 kb
Host smart-810e554d-374d-4a9f-a110-ce75fcac8869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978793479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3978793479
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.1208675363
Short name T427
Test name
Test status
Simulation time 486990122 ps
CPU time 1.28 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183068 kb
Host smart-ff66c447-f803-44a0-bdef-9bb13e5e775b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208675363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.1208675363
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3733710769
Short name T416
Test name
Test status
Simulation time 2023006153 ps
CPU time 6.54 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 192896 kb
Host smart-33faed1f-d0f2-4dbb-ac5a-db564a56f6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733710769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3733710769
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.3232541023
Short name T309
Test name
Test status
Simulation time 569167756 ps
CPU time 1.45 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 198128 kb
Host smart-711f5d46-c25e-4177-86eb-5b1afe888e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232541023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.3232541023
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.2133084111
Short name T322
Test name
Test status
Simulation time 4206688717 ps
CPU time 7.02 seconds
Started Feb 25 01:42:54 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 197048 kb
Host smart-50f7c1b9-1503-4c79-aa5b-0b4309eaae73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133084111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.2133084111
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.1633417015
Short name T305
Test name
Test status
Simulation time 354876493 ps
CPU time 1.14 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 194220 kb
Host smart-3de3c124-2602-48bd-9d5f-7836715252a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633417015 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.1633417015
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.2929456857
Short name T419
Test name
Test status
Simulation time 439100991 ps
CPU time 0.66 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183348 kb
Host smart-0d4d7813-9601-4594-942e-7e4d86bf0872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929456857 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.2929456857
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3909270722
Short name T292
Test name
Test status
Simulation time 499963682 ps
CPU time 1.33 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 183068 kb
Host smart-e01ccfe0-9312-478b-a098-257b77b95360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909270722 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3909270722
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.987216793
Short name T69
Test name
Test status
Simulation time 972531882 ps
CPU time 1.02 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 192300 kb
Host smart-71be09c5-e235-4eec-a161-97b4147985c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987216793 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon
_timer_same_csr_outstanding.987216793
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.2056947234
Short name T425
Test name
Test status
Simulation time 527488665 ps
CPU time 1.76 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 198140 kb
Host smart-6b6ce8c7-a429-4cd6-8559-0629958f064e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056947234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.2056947234
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1104067099
Short name T385
Test name
Test status
Simulation time 585462531 ps
CPU time 1.14 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 196436 kb
Host smart-524d6715-7265-42ca-a8f8-103aa437a831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104067099 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1104067099
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.2229932597
Short name T430
Test name
Test status
Simulation time 351098263 ps
CPU time 1.06 seconds
Started Feb 25 01:42:52 PM PST 24
Finished Feb 25 01:42:54 PM PST 24
Peak memory 183352 kb
Host smart-eaa9ca98-ceeb-4fff-97c8-00aa21d9000e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229932597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.2229932597
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.450327291
Short name T317
Test name
Test status
Simulation time 494205903 ps
CPU time 0.56 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 183068 kb
Host smart-6d8cc800-f6a6-4c01-a8ee-c8b207a5e2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450327291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.450327291
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.3265425318
Short name T71
Test name
Test status
Simulation time 1996903008 ps
CPU time 1.72 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:59 PM PST 24
Peak memory 194848 kb
Host smart-e9bb0bae-5a4b-48f3-8f48-e3a409ecf11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265425318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.3265425318
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.289860226
Short name T393
Test name
Test status
Simulation time 556735153 ps
CPU time 2.32 seconds
Started Feb 25 01:42:54 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 198048 kb
Host smart-6b3452bd-d455-4510-9a67-558597619059
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289860226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.289860226
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2694688117
Short name T342
Test name
Test status
Simulation time 8628794877 ps
CPU time 2.23 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:51 PM PST 24
Peak memory 197288 kb
Host smart-93da7c80-840c-4d1e-b931-b65e5f565880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694688117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2694688117
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.228744688
Short name T363
Test name
Test status
Simulation time 446369958 ps
CPU time 1.24 seconds
Started Feb 25 01:42:56 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 195368 kb
Host smart-f78a8ba0-02b4-4003-ae07-dbee74a69521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228744688 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.228744688
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2777333871
Short name T61
Test name
Test status
Simulation time 438530651 ps
CPU time 0.65 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183460 kb
Host smart-62fba073-d67c-4128-b16c-9a4a628e296d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777333871 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2777333871
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.3026487113
Short name T320
Test name
Test status
Simulation time 427016872 ps
CPU time 0.76 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 183064 kb
Host smart-4f4390e9-4237-40e1-a378-668e08ac4fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026487113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.3026487113
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.890177139
Short name T72
Test name
Test status
Simulation time 1410137200 ps
CPU time 2.65 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 193716 kb
Host smart-f53fa1c8-b3de-49c7-9ece-4b8a6b08235c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890177139 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.890177139
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.1085834647
Short name T321
Test name
Test status
Simulation time 457852093 ps
CPU time 1.31 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:58 PM PST 24
Peak memory 198152 kb
Host smart-26bf0d5b-46b1-4b6f-80de-87f234b32bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085834647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.1085834647
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3196820206
Short name T415
Test name
Test status
Simulation time 8438093161 ps
CPU time 3.57 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 197260 kb
Host smart-45ad7d23-95e0-4d09-9030-ccc8b32bc160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196820206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3196820206
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1380939564
Short name T399
Test name
Test status
Simulation time 543881212 ps
CPU time 1.54 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 194932 kb
Host smart-20c380b9-612e-422e-965f-00da0ee0c4b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380939564 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1380939564
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.3115702896
Short name T407
Test name
Test status
Simulation time 449258907 ps
CPU time 1.18 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 182348 kb
Host smart-215669cb-0104-4815-adfb-ac7ef1fbe73a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115702896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.3115702896
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.1535307319
Short name T331
Test name
Test status
Simulation time 270270830 ps
CPU time 0.71 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 182404 kb
Host smart-ab2e03c7-421f-44e9-9e14-643433b82d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535307319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.1535307319
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.3145876235
Short name T66
Test name
Test status
Simulation time 1665302011 ps
CPU time 1.69 seconds
Started Feb 25 01:42:54 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 192796 kb
Host smart-8c4bf47c-b3d5-4a9c-8b4e-6d56044a259c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145876235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.3145876235
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.3769299387
Short name T330
Test name
Test status
Simulation time 479467846 ps
CPU time 1.78 seconds
Started Feb 25 01:42:57 PM PST 24
Finished Feb 25 01:42:59 PM PST 24
Peak memory 197992 kb
Host smart-830e2a10-9429-459a-b57c-ef423f4c03cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769299387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.3769299387
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.961096551
Short name T411
Test name
Test status
Simulation time 461069730 ps
CPU time 0.88 seconds
Started Feb 25 01:43:00 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 197352 kb
Host smart-18ba5c44-badd-4694-80f3-d4914218a0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961096551 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.961096551
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2342000908
Short name T55
Test name
Test status
Simulation time 344618541 ps
CPU time 0.74 seconds
Started Feb 25 01:42:54 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 183348 kb
Host smart-63d7a693-e6c2-4db3-a667-c3faf05e30ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342000908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2342000908
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2095772608
Short name T285
Test name
Test status
Simulation time 416658964 ps
CPU time 0.69 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 183072 kb
Host smart-41516c0c-f561-4c50-ae31-fd9e51e9d64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095772608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2095772608
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1299700811
Short name T73
Test name
Test status
Simulation time 2015146695 ps
CPU time 1.21 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 194440 kb
Host smart-99cca18e-4e08-4d0a-b6db-f14429346c45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299700811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1299700811
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.3916741121
Short name T380
Test name
Test status
Simulation time 347404175 ps
CPU time 2.35 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:04 PM PST 24
Peak memory 198108 kb
Host smart-16c7e687-36cb-4e8c-b468-202717f44de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916741121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.3916741121
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.489302130
Short name T36
Test name
Test status
Simulation time 4017956081 ps
CPU time 6.71 seconds
Started Feb 25 01:42:56 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 196676 kb
Host smart-77e5c7a9-0d99-4a8f-8912-de1b612a40db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489302130 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl
_intg_err.489302130
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1769201476
Short name T52
Test name
Test status
Simulation time 659511311 ps
CPU time 0.68 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:44 PM PST 24
Peak memory 192564 kb
Host smart-0519f813-5e21-4524-b547-54bccbb2670f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769201476 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1769201476
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1763625328
Short name T58
Test name
Test status
Simulation time 11339640650 ps
CPU time 15.17 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:43:00 PM PST 24
Peak memory 191768 kb
Host smart-78589bdd-6dc9-4a44-9304-69e2626171b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763625328 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1763625328
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2469175491
Short name T301
Test name
Test status
Simulation time 1114078835 ps
CPU time 2.23 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 183332 kb
Host smart-fac042ca-7a3d-4386-ac55-13bcc99ea00a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469175491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2469175491
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3408881322
Short name T297
Test name
Test status
Simulation time 525798259 ps
CPU time 1.06 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:53 PM PST 24
Peak memory 195304 kb
Host smart-26b574bc-be4d-4a76-a7cb-8e87c031e4d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408881322 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3408881322
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2512700533
Short name T318
Test name
Test status
Simulation time 503586752 ps
CPU time 0.89 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183372 kb
Host smart-0fd59612-b21e-480b-be4b-31946018e6c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512700533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2512700533
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3812054945
Short name T396
Test name
Test status
Simulation time 522516261 ps
CPU time 0.95 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 182976 kb
Host smart-194618d6-32cd-4063-9c34-6ad8c611ad64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812054945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3812054945
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.863439949
Short name T307
Test name
Test status
Simulation time 545803387 ps
CPU time 0.67 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 182968 kb
Host smart-deb7dd28-55e7-42cf-ae28-f5a0b8e63074
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863439949 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_ti
mer_mem_partial_access.863439949
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.2770834298
Short name T390
Test name
Test status
Simulation time 536092462 ps
CPU time 0.73 seconds
Started Feb 25 01:42:42 PM PST 24
Finished Feb 25 01:42:43 PM PST 24
Peak memory 183032 kb
Host smart-49cd1a07-16c0-48ad-8032-def1bc87a559
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770834298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.2770834298
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.2647548522
Short name T365
Test name
Test status
Simulation time 1405717254 ps
CPU time 0.81 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 193816 kb
Host smart-ff002be5-0ffa-49e7-952b-8f89543f7c28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647548522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.2647548522
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.1354337174
Short name T404
Test name
Test status
Simulation time 783171877 ps
CPU time 2 seconds
Started Feb 25 01:42:33 PM PST 24
Finished Feb 25 01:42:35 PM PST 24
Peak memory 198156 kb
Host smart-374d20d2-a4a4-40f3-8268-ab09a04f561b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354337174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.1354337174
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1626230509
Short name T296
Test name
Test status
Simulation time 8559618818 ps
CPU time 3.23 seconds
Started Feb 25 01:42:31 PM PST 24
Finished Feb 25 01:42:34 PM PST 24
Peak memory 197064 kb
Host smart-1dd74b13-c20c-490d-800b-94916d115334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626230509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1626230509
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.894388637
Short name T422
Test name
Test status
Simulation time 488953079 ps
CPU time 0.7 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183024 kb
Host smart-b450bead-ce23-4055-9ece-f8d3ac8336f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894388637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.894388637
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.1053206462
Short name T424
Test name
Test status
Simulation time 427439225 ps
CPU time 0.68 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183024 kb
Host smart-8cabd687-c322-41ab-a13c-eb0f7d1c87e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053206462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.1053206462
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2271079518
Short name T372
Test name
Test status
Simulation time 410174504 ps
CPU time 1.05 seconds
Started Feb 25 01:42:55 PM PST 24
Finished Feb 25 01:42:56 PM PST 24
Peak memory 183068 kb
Host smart-41c9f1af-27c5-44a6-9890-03a4bc25c2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271079518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2271079518
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.3870029426
Short name T343
Test name
Test status
Simulation time 358559693 ps
CPU time 0.99 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 182988 kb
Host smart-d63e44d5-d61f-428b-8819-2c7023049755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870029426 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.3870029426
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.2075912358
Short name T362
Test name
Test status
Simulation time 474051161 ps
CPU time 0.72 seconds
Started Feb 25 01:42:53 PM PST 24
Finished Feb 25 01:42:54 PM PST 24
Peak memory 183060 kb
Host smart-182bf8d0-b1e4-44de-a477-ff0bb722b7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075912358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.2075912358
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.3864403136
Short name T353
Test name
Test status
Simulation time 490175388 ps
CPU time 1.35 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183240 kb
Host smart-612e89a9-cea7-43ee-afdb-3b3b51136894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864403136 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.3864403136
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.252477648
Short name T333
Test name
Test status
Simulation time 366322781 ps
CPU time 0.67 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183084 kb
Host smart-cdf4b67c-ab44-469e-8edc-8723b5ae4fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252477648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.252477648
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.3462262414
Short name T370
Test name
Test status
Simulation time 466993611 ps
CPU time 1.25 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:00 PM PST 24
Peak memory 183300 kb
Host smart-72b94979-4c7e-4f68-900b-846323a17def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462262414 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.3462262414
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1197094997
Short name T312
Test name
Test status
Simulation time 348551381 ps
CPU time 0.63 seconds
Started Feb 25 01:43:05 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 183424 kb
Host smart-3370d12f-9003-4dbe-86aa-2e1b4764d9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197094997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1197094997
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.35676215
Short name T336
Test name
Test status
Simulation time 526979193 ps
CPU time 0.71 seconds
Started Feb 25 01:43:05 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 183260 kb
Host smart-afd28403-d992-4ea9-a42a-65196465041e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676215 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.35676215
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.785868246
Short name T54
Test name
Test status
Simulation time 612464883 ps
CPU time 0.97 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 193420 kb
Host smart-ba660070-02bb-448a-a48c-934108eb8376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785868246 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_al
iasing.785868246
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.625835502
Short name T382
Test name
Test status
Simulation time 5941402999 ps
CPU time 3.25 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 191764 kb
Host smart-ef0955fc-5054-432e-bb57-354bc3e073f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625835502 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_bi
t_bash.625835502
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3945373174
Short name T295
Test name
Test status
Simulation time 743771668 ps
CPU time 1.7 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 183208 kb
Host smart-94f57927-618f-4c55-9cab-aec7645a9a5f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945373174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3945373174
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.2752251743
Short name T346
Test name
Test status
Simulation time 591769453 ps
CPU time 0.73 seconds
Started Feb 25 01:42:49 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 194612 kb
Host smart-b93efd72-a134-4ca6-a4ff-790b322d536f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752251743 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.2752251743
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.668335721
Short name T375
Test name
Test status
Simulation time 543704970 ps
CPU time 0.96 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:44 PM PST 24
Peak memory 183360 kb
Host smart-dae1c9a1-3a0c-4fbf-ba9d-08e4365dea30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668335721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.668335721
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.132593332
Short name T298
Test name
Test status
Simulation time 391686161 ps
CPU time 1.01 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 183060 kb
Host smart-c98b558d-730d-4a38-8528-f8b6d93a4653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132593332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.132593332
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.1807792714
Short name T299
Test name
Test status
Simulation time 497608692 ps
CPU time 0.88 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 182968 kb
Host smart-475bd9e5-1928-4320-aaff-fd6cd3e5383a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807792714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.1807792714
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.3328519000
Short name T394
Test name
Test status
Simulation time 478413057 ps
CPU time 1.21 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183068 kb
Host smart-e53371c7-1f37-49c2-9b71-2ce24f139533
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328519000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.3328519000
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.2438490152
Short name T371
Test name
Test status
Simulation time 1636795115 ps
CPU time 2.23 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 191812 kb
Host smart-ec16fcea-e978-41b8-8121-970ccf875403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438490152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.2438490152
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1519956778
Short name T289
Test name
Test status
Simulation time 759965014 ps
CPU time 2.22 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 198156 kb
Host smart-766566c1-85cb-49fa-a030-2b048fd38882
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519956778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1519956778
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.3070468965
Short name T325
Test name
Test status
Simulation time 7893674899 ps
CPU time 4.05 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:51 PM PST 24
Peak memory 196960 kb
Host smart-e6567fe7-263d-48dc-b1ae-f2433e003499
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070468965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl
_intg_err.3070468965
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.3333185347
Short name T319
Test name
Test status
Simulation time 636425237 ps
CPU time 0.66 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183028 kb
Host smart-06fb4b36-ac5e-4ad8-ac74-8580db29142d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333185347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.3333185347
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.1858398836
Short name T286
Test name
Test status
Simulation time 336869118 ps
CPU time 1.01 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183024 kb
Host smart-8f591740-0227-4899-85f5-b9ce6209243a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858398836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.1858398836
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1290964176
Short name T360
Test name
Test status
Simulation time 427290722 ps
CPU time 1.13 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183068 kb
Host smart-ed7984ec-19f3-494b-ae83-eb1b205af2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290964176 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1290964176
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.3951574910
Short name T389
Test name
Test status
Simulation time 513721577 ps
CPU time 1.23 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183068 kb
Host smart-4021e7da-dc6d-4623-97e6-318db378a638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951574910 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.3951574910
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.427437440
Short name T328
Test name
Test status
Simulation time 508048710 ps
CPU time 1.32 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183060 kb
Host smart-c645a35d-acd9-49de-bdab-d83da94b2b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427437440 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.427437440
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2465037221
Short name T384
Test name
Test status
Simulation time 490377828 ps
CPU time 0.74 seconds
Started Feb 25 01:43:05 PM PST 24
Finished Feb 25 01:43:06 PM PST 24
Peak memory 183044 kb
Host smart-21bc0edd-5565-414e-ac36-15239f10d61d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465037221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2465037221
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3343390789
Short name T378
Test name
Test status
Simulation time 411092032 ps
CPU time 0.56 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183072 kb
Host smart-bffbd913-121c-4248-be8c-c9cc26bfd357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343390789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3343390789
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3773766883
Short name T351
Test name
Test status
Simulation time 437517203 ps
CPU time 1.24 seconds
Started Feb 25 01:43:06 PM PST 24
Finished Feb 25 01:43:07 PM PST 24
Peak memory 183068 kb
Host smart-5cfc6114-b73a-4531-8dda-9f5fe68371c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773766883 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3773766883
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.2878050523
Short name T308
Test name
Test status
Simulation time 454631453 ps
CPU time 1.11 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 183192 kb
Host smart-16e857eb-2086-4b1f-bfee-f3bb03182f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878050523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.2878050523
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.1714958628
Short name T306
Test name
Test status
Simulation time 482059701 ps
CPU time 1.23 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 183068 kb
Host smart-8b889b23-09a1-4c92-b77d-55624fc32063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714958628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.1714958628
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2841852380
Short name T392
Test name
Test status
Simulation time 603992328 ps
CPU time 0.84 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 192568 kb
Host smart-50ac9979-a125-486b-8ac1-f1171d755897
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841852380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2841852380
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1983601548
Short name T62
Test name
Test status
Simulation time 3648318637 ps
CPU time 2.02 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 191772 kb
Host smart-6e5391a5-d7c2-4856-8d32-b3596714efe2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983601548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1983601548
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3941047346
Short name T414
Test name
Test status
Simulation time 562973725 ps
CPU time 0.97 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 183252 kb
Host smart-ad274243-ca3c-40c0-ba90-3ed7bfa865e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941047346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3941047346
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1143258626
Short name T311
Test name
Test status
Simulation time 486707302 ps
CPU time 0.77 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:45 PM PST 24
Peak memory 194412 kb
Host smart-ebcf2abf-e59c-42de-accc-240f2c4e3fa2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143258626 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1143258626
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2528990373
Short name T60
Test name
Test status
Simulation time 541800165 ps
CPU time 0.67 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183372 kb
Host smart-b8e8b4ad-3cf6-4c00-b6d0-882c0c8878ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528990373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2528990373
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.3272359023
Short name T400
Test name
Test status
Simulation time 343505896 ps
CPU time 0.92 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:44 PM PST 24
Peak memory 183228 kb
Host smart-7d6320e4-0f98-43df-9a90-77fd1f8c6514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272359023 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.3272359023
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.1476908714
Short name T316
Test name
Test status
Simulation time 293062026 ps
CPU time 0.71 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183024 kb
Host smart-efc9bc1c-9101-4802-b96d-702b3d080ed0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476908714 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.1476908714
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1878607920
Short name T379
Test name
Test status
Simulation time 450710091 ps
CPU time 0.83 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183192 kb
Host smart-c51ea84b-f86a-4f21-a7fa-9bfce0527efc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878607920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1878607920
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3890462638
Short name T418
Test name
Test status
Simulation time 959455979 ps
CPU time 1.18 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:44 PM PST 24
Peak memory 193768 kb
Host smart-ae7af408-86d9-4669-9579-56c123d68800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890462638 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3890462638
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.1989310204
Short name T358
Test name
Test status
Simulation time 310068022 ps
CPU time 2.44 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 198120 kb
Host smart-a3396688-fca8-4a68-9187-dc0a09c5f5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989310204 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.1989310204
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3645096081
Short name T310
Test name
Test status
Simulation time 8724229686 ps
CPU time 5.21 seconds
Started Feb 25 01:42:41 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 197160 kb
Host smart-1b26a307-06e4-4139-bc19-637253eafa3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645096081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3645096081
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.3196697465
Short name T334
Test name
Test status
Simulation time 297296192 ps
CPU time 0.91 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183028 kb
Host smart-88dfe1ac-c7f1-495f-9c10-ec5de510bc5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196697465 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.3196697465
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1360911253
Short name T339
Test name
Test status
Simulation time 306523153 ps
CPU time 0.77 seconds
Started Feb 25 01:43:03 PM PST 24
Finished Feb 25 01:43:04 PM PST 24
Peak memory 183084 kb
Host smart-898f9ca1-2862-42b6-af44-c9183cb21273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360911253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1360911253
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.2145470827
Short name T349
Test name
Test status
Simulation time 374499624 ps
CPU time 0.59 seconds
Started Feb 25 01:43:00 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 183068 kb
Host smart-5dc97ef6-dc57-4565-b8a7-02d5884b82b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145470827 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.2145470827
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2400429962
Short name T294
Test name
Test status
Simulation time 430810823 ps
CPU time 0.7 seconds
Started Feb 25 01:43:11 PM PST 24
Finished Feb 25 01:43:12 PM PST 24
Peak memory 183024 kb
Host smart-7377fcee-e3bc-4ab0-9f30-443f8bf12282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400429962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2400429962
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1095243527
Short name T347
Test name
Test status
Simulation time 455314919 ps
CPU time 1.28 seconds
Started Feb 25 01:43:03 PM PST 24
Finished Feb 25 01:43:05 PM PST 24
Peak memory 183284 kb
Host smart-a983aa40-23be-4bf5-a3a6-ec4749725ea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095243527 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1095243527
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.3562256086
Short name T377
Test name
Test status
Simulation time 405344386 ps
CPU time 0.67 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183292 kb
Host smart-0059cac6-e985-48ce-b05f-f21417cb3fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562256086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.3562256086
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1852047375
Short name T421
Test name
Test status
Simulation time 417123410 ps
CPU time 0.63 seconds
Started Feb 25 01:43:01 PM PST 24
Finished Feb 25 01:43:02 PM PST 24
Peak memory 183076 kb
Host smart-8c6e718b-aedb-402f-a510-5e8ef9350c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852047375 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1852047375
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.2819630260
Short name T355
Test name
Test status
Simulation time 442633153 ps
CPU time 0.9 seconds
Started Feb 25 01:43:02 PM PST 24
Finished Feb 25 01:43:03 PM PST 24
Peak memory 183292 kb
Host smart-6ea13300-0fc6-47f5-afe0-c4472f9c1ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819630260 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.2819630260
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1447113780
Short name T326
Test name
Test status
Simulation time 394404141 ps
CPU time 0.65 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:00 PM PST 24
Peak memory 183084 kb
Host smart-e59ab622-5be0-4209-b76a-e35028166ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447113780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1447113780
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.2440412442
Short name T412
Test name
Test status
Simulation time 517228582 ps
CPU time 0.66 seconds
Started Feb 25 01:42:59 PM PST 24
Finished Feb 25 01:43:00 PM PST 24
Peak memory 182980 kb
Host smart-202ee795-1e25-4c55-b259-00c775fd617a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440412442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.2440412442
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.2273215883
Short name T348
Test name
Test status
Simulation time 315693302 ps
CPU time 0.83 seconds
Started Feb 25 01:42:41 PM PST 24
Finished Feb 25 01:42:42 PM PST 24
Peak memory 194668 kb
Host smart-c6f28dc6-bdc5-42e7-abf5-7afacd97c910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273215883 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.2273215883
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3628498074
Short name T368
Test name
Test status
Simulation time 534797909 ps
CPU time 0.65 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 183364 kb
Host smart-3ac3dbfd-ddd2-4e48-b7d7-3d297734e894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628498074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3628498074
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.1247753624
Short name T413
Test name
Test status
Simulation time 380915696 ps
CPU time 0.85 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183420 kb
Host smart-163984b4-31a3-4468-9cb7-bc8bbff253a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247753624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.1247753624
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.1371779356
Short name T361
Test name
Test status
Simulation time 2092695462 ps
CPU time 1.81 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 194848 kb
Host smart-176b75a5-5ebd-4622-8cc4-fb633043623f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371779356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.1371779356
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2891787131
Short name T352
Test name
Test status
Simulation time 306727049 ps
CPU time 2.2 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 198184 kb
Host smart-cf402255-0e7e-417f-b54d-19bcf6b27f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891787131 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2891787131
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.3329660666
Short name T417
Test name
Test status
Simulation time 7645715032 ps
CPU time 13.47 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:43:01 PM PST 24
Peak memory 197064 kb
Host smart-4b9fd432-5b49-4c7f-ad3d-25990246fd26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329660666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.3329660666
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1286320598
Short name T420
Test name
Test status
Simulation time 484975583 ps
CPU time 0.96 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 195712 kb
Host smart-9b120b5b-dd69-4540-ad61-b96dbceccfca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286320598 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1286320598
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2744620430
Short name T388
Test name
Test status
Simulation time 405782606 ps
CPU time 1.2 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183352 kb
Host smart-b35fc7ac-8194-4654-8569-40594ad7b28c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744620430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2744620430
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2694212145
Short name T423
Test name
Test status
Simulation time 466328027 ps
CPU time 1.25 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183116 kb
Host smart-961ca1b4-d845-4ee3-9329-6520cc672cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694212145 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2694212145
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2901412872
Short name T405
Test name
Test status
Simulation time 1989648170 ps
CPU time 5.48 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:57 PM PST 24
Peak memory 194260 kb
Host smart-ede290bb-be7e-4d81-99f1-4c6db0c2919e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901412872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2901412872
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.900631423
Short name T341
Test name
Test status
Simulation time 428751029 ps
CPU time 2.12 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 197608 kb
Host smart-bdcf8915-7517-4acd-adfe-1fbcf6f5a35a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900631423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.900631423
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.1460030998
Short name T290
Test name
Test status
Simulation time 4062246009 ps
CPU time 6.22 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 197012 kb
Host smart-2032e795-a43d-4a52-bd8c-61861f8622ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460030998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.1460030998
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.422909013
Short name T408
Test name
Test status
Simulation time 686512728 ps
CPU time 1.03 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 196200 kb
Host smart-3385cae6-9799-4785-bcab-3eb17253e488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422909013 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.422909013
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1025885203
Short name T64
Test name
Test status
Simulation time 393452093 ps
CPU time 0.86 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183384 kb
Host smart-09062664-859b-4da8-829c-7554140d3065
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025885203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1025885203
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.2415157162
Short name T398
Test name
Test status
Simulation time 307865324 ps
CPU time 0.75 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183096 kb
Host smart-2c875ff2-804f-4bbd-ac4c-a40a0cd59007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415157162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.2415157162
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.2925906602
Short name T429
Test name
Test status
Simulation time 1162279777 ps
CPU time 1.2 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 193172 kb
Host smart-be32342d-f6e9-47a8-a8c2-4febb11d3c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925906602 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.2925906602
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.1419463721
Short name T313
Test name
Test status
Simulation time 547111386 ps
CPU time 2.09 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 198216 kb
Host smart-103d90a9-5105-44cb-8cb4-c5cf03d90bbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419463721 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.1419463721
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.239310112
Short name T364
Test name
Test status
Simulation time 8539895778 ps
CPU time 8 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 197208 kb
Host smart-e523390e-7c9b-4c73-b4d8-502d6f7ca5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239310112 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.239310112
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1047637869
Short name T409
Test name
Test status
Simulation time 419222041 ps
CPU time 1.26 seconds
Started Feb 25 01:42:44 PM PST 24
Finished Feb 25 01:42:45 PM PST 24
Peak memory 195500 kb
Host smart-5e57eea7-5f34-450b-aa83-461c3e268bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047637869 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1047637869
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.1791107830
Short name T56
Test name
Test status
Simulation time 314139643 ps
CPU time 0.62 seconds
Started Feb 25 01:42:45 PM PST 24
Finished Feb 25 01:42:47 PM PST 24
Peak memory 183312 kb
Host smart-b3b8f62b-575f-4006-b7a4-2d9d36b71161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791107830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.1791107830
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.1406472102
Short name T410
Test name
Test status
Simulation time 406124667 ps
CPU time 0.58 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 183016 kb
Host smart-4528c69b-0455-4d99-802a-fb82379687c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406472102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.1406472102
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.3267197968
Short name T387
Test name
Test status
Simulation time 904701033 ps
CPU time 2.38 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 193740 kb
Host smart-ebd1e7c9-a925-4309-9952-99570dda5764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267197968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.3267197968
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1978505989
Short name T383
Test name
Test status
Simulation time 543346706 ps
CPU time 2.53 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:46 PM PST 24
Peak memory 198188 kb
Host smart-f38486bf-a8ce-49db-826f-614b6694262b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978505989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1978505989
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2367909135
Short name T293
Test name
Test status
Simulation time 3940176974 ps
CPU time 6 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:55 PM PST 24
Peak memory 195960 kb
Host smart-b26b3fb8-c0f3-4257-983d-f6f11d0d1f65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367909135 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2367909135
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3990320680
Short name T344
Test name
Test status
Simulation time 570255170 ps
CPU time 1.02 seconds
Started Feb 25 01:42:51 PM PST 24
Finished Feb 25 01:42:52 PM PST 24
Peak memory 195064 kb
Host smart-9c811402-db83-4e0c-8904-96a74f7e912a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990320680 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3990320680
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.3420651114
Short name T51
Test name
Test status
Simulation time 521515688 ps
CPU time 1.31 seconds
Started Feb 25 01:42:48 PM PST 24
Finished Feb 25 01:42:50 PM PST 24
Peak memory 183500 kb
Host smart-3446ce75-2ab2-4305-b42f-42cb79834813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420651114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.3420651114
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.610157208
Short name T337
Test name
Test status
Simulation time 407643984 ps
CPU time 0.59 seconds
Started Feb 25 01:42:43 PM PST 24
Finished Feb 25 01:42:43 PM PST 24
Peak memory 183068 kb
Host smart-c74f00a2-fe3b-43a7-abb5-7f328f4fddc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610157208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.610157208
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.595589408
Short name T70
Test name
Test status
Simulation time 2124176835 ps
CPU time 3.26 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:49 PM PST 24
Peak memory 193832 kb
Host smart-6f88eba7-02cd-4911-be48-6f4aad755a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595589408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_
timer_same_csr_outstanding.595589408
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.803490929
Short name T403
Test name
Test status
Simulation time 509878811 ps
CPU time 2.03 seconds
Started Feb 25 01:42:46 PM PST 24
Finished Feb 25 01:42:48 PM PST 24
Peak memory 198208 kb
Host smart-b996fcfe-ca3e-4816-a63b-abaad39b32cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803490929 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.803490929
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1246972822
Short name T367
Test name
Test status
Simulation time 4361171516 ps
CPU time 7.16 seconds
Started Feb 25 01:42:47 PM PST 24
Finished Feb 25 01:42:54 PM PST 24
Peak memory 196852 kb
Host smart-e5b95813-825c-458e-8be0-4d57f58b9841
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246972822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1246972822
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.3974438770
Short name T109
Test name
Test status
Simulation time 551967412 ps
CPU time 0.77 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 183336 kb
Host smart-24dbec11-2553-4196-9589-4991e8adfadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974438770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.3974438770
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2887292894
Short name T144
Test name
Test status
Simulation time 3885738608 ps
CPU time 2.2 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 183448 kb
Host smart-3a57a9fd-5239-4201-a3ff-138836c7c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887292894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2887292894
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3057702711
Short name T25
Test name
Test status
Simulation time 556498272 ps
CPU time 0.99 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 183228 kb
Host smart-0d02e6c2-09e5-4cb4-a927-3c1e33342683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057702711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3057702711
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.2269687625
Short name T116
Test name
Test status
Simulation time 71692491744 ps
CPU time 100.72 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:33:12 PM PST 24
Peak memory 183428 kb
Host smart-6b4853d0-4c6e-4cb4-8f57-c62d8827584e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269687625 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.2269687625
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1312250381
Short name T184
Test name
Test status
Simulation time 471018572 ps
CPU time 1.01 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 183336 kb
Host smart-a248783d-99ae-4fb8-b5ce-6492e0494ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312250381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1312250381
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2058427932
Short name T258
Test name
Test status
Simulation time 2881062100 ps
CPU time 1.07 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 183448 kb
Host smart-da078c44-3e64-4aef-884f-6ae404ca1abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058427932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2058427932
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3522410737
Short name T18
Test name
Test status
Simulation time 7369387414 ps
CPU time 3.4 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 215356 kb
Host smart-6eb60758-87f8-43e3-9f01-b06a6e490886
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522410737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3522410737
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.3110470865
Short name T194
Test name
Test status
Simulation time 443727307 ps
CPU time 0.72 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 183224 kb
Host smart-a19545e5-4d50-49b9-a55e-fbae3deddfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110470865 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.3110470865
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.2072310183
Short name T266
Test name
Test status
Simulation time 132783757289 ps
CPU time 181.73 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:34:35 PM PST 24
Peak memory 191776 kb
Host smart-c492bfeb-9b5e-45ae-a9e2-abae4e8a519b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072310183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.2072310183
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.2296425125
Short name T219
Test name
Test status
Simulation time 69775589160 ps
CPU time 304.77 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:36:35 PM PST 24
Peak memory 198324 kb
Host smart-99562cbb-cc47-4096-8674-77853e92d5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296425125 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.2296425125
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4079321218
Short name T231
Test name
Test status
Simulation time 409033204 ps
CPU time 1.15 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183424 kb
Host smart-81a56d6d-f592-4b4f-a63f-3fd481d80aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079321218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4079321218
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.2250348351
Short name T269
Test name
Test status
Simulation time 7499777141 ps
CPU time 10.53 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 183392 kb
Host smart-0ad39a2e-f5db-474e-9355-b81d7b6ca0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250348351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.2250348351
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.2125955596
Short name T271
Test name
Test status
Simulation time 543309467 ps
CPU time 1.29 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:31:48 PM PST 24
Peak memory 183276 kb
Host smart-7c33bc65-ceb5-4fdb-8ee2-7a9cccb1300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125955596 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.2125955596
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.1891106404
Short name T92
Test name
Test status
Simulation time 45447818792 ps
CPU time 14.59 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:32:06 PM PST 24
Peak memory 193516 kb
Host smart-2b5db509-0cf3-4e3b-a3c7-4d22433ae745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891106404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.1891106404
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.2094718741
Short name T233
Test name
Test status
Simulation time 225623700253 ps
CPU time 638.83 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:42:28 PM PST 24
Peak memory 200360 kb
Host smart-f8e8ce3f-57b3-491a-b46e-f955db47b4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094718741 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.2094718741
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.240124997
Short name T268
Test name
Test status
Simulation time 576320685 ps
CPU time 1.32 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 183104 kb
Host smart-bd67734f-a8ce-4da2-81ca-4c2f81334ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240124997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.240124997
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3907659138
Short name T27
Test name
Test status
Simulation time 28279514338 ps
CPU time 9.4 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:32:01 PM PST 24
Peak memory 183364 kb
Host smart-7ce10a09-bfbe-4e54-9585-c1653b8644cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907659138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3907659138
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.1178486794
Short name T131
Test name
Test status
Simulation time 388389816 ps
CPU time 0.69 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183176 kb
Host smart-f7d19803-7267-4fbc-bea0-ba4562cbdff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178486794 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.1178486794
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.330632259
Short name T281
Test name
Test status
Simulation time 289683096253 ps
CPU time 119.14 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:33:37 PM PST 24
Peak memory 183440 kb
Host smart-f2067055-6b23-463b-8af8-44aad11e968c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330632259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.330632259
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_jump.648213456
Short name T114
Test name
Test status
Simulation time 495957616 ps
CPU time 1.22 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183340 kb
Host smart-101f5c24-7ad1-4dd2-8a25-6d982b516bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648213456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.648213456
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3593297087
Short name T11
Test name
Test status
Simulation time 41456686374 ps
CPU time 67.31 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:33:00 PM PST 24
Peak memory 183292 kb
Host smart-effd87c4-98fd-4bff-8edf-e83e52418d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593297087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3593297087
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3559247014
Short name T208
Test name
Test status
Simulation time 460907259 ps
CPU time 0.9 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183172 kb
Host smart-59db46ec-bd1f-4bde-ba6a-9a9933dbcbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559247014 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3559247014
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2070150086
Short name T272
Test name
Test status
Simulation time 138685263285 ps
CPU time 114.08 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:33:45 PM PST 24
Peak memory 193460 kb
Host smart-b8224eb1-4ffe-4ace-924f-eb1318b8a097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070150086 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2070150086
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.562700791
Short name T2
Test name
Test status
Simulation time 581290910 ps
CPU time 1.47 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183280 kb
Host smart-e4e2ec8e-5a41-46b9-9e77-fcfd3bfa344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562700791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.562700791
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.2033361636
Short name T157
Test name
Test status
Simulation time 4813833040 ps
CPU time 2.68 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:40 PM PST 24
Peak memory 183404 kb
Host smart-dc3a89eb-c26c-4ab9-b064-d821c51e404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033361636 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.2033361636
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2409687148
Short name T274
Test name
Test status
Simulation time 545695292 ps
CPU time 0.74 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183176 kb
Host smart-3a0ecd81-ba7e-4ebb-b17c-19698a755db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409687148 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2409687148
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.4022651347
Short name T226
Test name
Test status
Simulation time 117288145842 ps
CPU time 43.56 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:32:36 PM PST 24
Peak memory 183328 kb
Host smart-2d48b5a0-a48c-4b62-8018-b23ca6186de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022651347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.4022651347
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2402451447
Short name T42
Test name
Test status
Simulation time 380574973137 ps
CPU time 804.23 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:45:16 PM PST 24
Peak memory 201268 kb
Host smart-c2e697c4-2b95-491e-b3a4-9d5aa5224cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402451447 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2402451447
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2620594574
Short name T178
Test name
Test status
Simulation time 359475439 ps
CPU time 1.09 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183424 kb
Host smart-9b5e1b22-2237-456f-b23c-28fdca6e829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620594574 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2620594574
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.3863012416
Short name T237
Test name
Test status
Simulation time 25514394874 ps
CPU time 10.17 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:32:00 PM PST 24
Peak memory 183392 kb
Host smart-3a53c618-37b5-4b7b-950e-5a3d658519e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863012416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.3863012416
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.2869363275
Short name T192
Test name
Test status
Simulation time 581739098 ps
CPU time 0.79 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183276 kb
Host smart-478f29df-6cd9-48cf-93d8-51c5e178ad08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869363275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.2869363275
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.3445132027
Short name T97
Test name
Test status
Simulation time 247640146012 ps
CPU time 194.1 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:35:05 PM PST 24
Peak memory 194912 kb
Host smart-d24c3931-3fa8-474f-8a0b-e49010d3583b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445132027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.3445132027
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2814720572
Short name T154
Test name
Test status
Simulation time 47399984028 ps
CPU time 400.17 seconds
Started Feb 25 01:31:41 PM PST 24
Finished Feb 25 01:38:21 PM PST 24
Peak memory 198348 kb
Host smart-5651ea6c-339e-469b-b26e-307fa59ef4ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814720572 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2814720572
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.2484951354
Short name T33
Test name
Test status
Simulation time 452247237 ps
CPU time 0.71 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183204 kb
Host smart-76def1fa-f60b-44f6-9e2d-960684ff6e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484951354 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.2484951354
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.3833276096
Short name T148
Test name
Test status
Simulation time 2297559665 ps
CPU time 0.95 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183348 kb
Host smart-b5689e95-5fea-4b65-be61-aef549be29a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833276096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.3833276096
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1884416214
Short name T139
Test name
Test status
Simulation time 603025736 ps
CPU time 0.65 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:31:48 PM PST 24
Peak memory 183248 kb
Host smart-6d4d733b-f891-4209-be96-9c3f2bc0ce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884416214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1884416214
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2697999286
Short name T106
Test name
Test status
Simulation time 49108381800 ps
CPU time 209.28 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:35:17 PM PST 24
Peak memory 198416 kb
Host smart-f2e7c3a9-7985-4979-ac7d-142678dbdcd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697999286 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2697999286
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.653760188
Short name T47
Test name
Test status
Simulation time 482269085 ps
CPU time 0.72 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:31:48 PM PST 24
Peak memory 183068 kb
Host smart-7e4b8c50-2e03-499d-8364-0896380713ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653760188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.653760188
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.839407304
Short name T253
Test name
Test status
Simulation time 35748798588 ps
CPU time 12.1 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:32:05 PM PST 24
Peak memory 183344 kb
Host smart-6b2271e6-272e-4afd-9f26-bc70a4f8fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839407304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.839407304
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.1618229697
Short name T28
Test name
Test status
Simulation time 539750718 ps
CPU time 0.89 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183288 kb
Host smart-5e4cc9ec-d605-40ec-a070-ef3569a7882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618229697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.1618229697
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3569342516
Short name T99
Test name
Test status
Simulation time 357619551631 ps
CPU time 140.73 seconds
Started Feb 25 01:31:42 PM PST 24
Finished Feb 25 01:34:03 PM PST 24
Peak memory 193632 kb
Host smart-65e46bbf-d610-436b-b1e0-98bf641359d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569342516 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3569342516
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_jump.45554651
Short name T24
Test name
Test status
Simulation time 553220187 ps
CPU time 0.72 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:31:51 PM PST 24
Peak memory 183372 kb
Host smart-15396d72-3d8d-432b-93c5-7b45856bb827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45554651 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.45554651
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1877775546
Short name T239
Test name
Test status
Simulation time 1430530123 ps
CPU time 2.71 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:55 PM PST 24
Peak memory 183276 kb
Host smart-9a4e61da-94b5-486b-803e-7534d11e748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877775546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1877775546
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.3494999303
Short name T252
Test name
Test status
Simulation time 592630347 ps
CPU time 0.81 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 183228 kb
Host smart-9cefdeb9-2ca1-4c73-b19b-d90c1ec72745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494999303 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.3494999303
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1289482234
Short name T30
Test name
Test status
Simulation time 102200239740 ps
CPU time 40.58 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:32:31 PM PST 24
Peak memory 183440 kb
Host smart-a21db327-4531-4361-805e-25c5bf29dbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289482234 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1289482234
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3623261857
Short name T217
Test name
Test status
Simulation time 42215413038 ps
CPU time 107.85 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:33:39 PM PST 24
Peak memory 198328 kb
Host smart-ab1cdfd0-1a23-461d-a665-bb35fe0fa86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623261857 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3623261857
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.100944030
Short name T152
Test name
Test status
Simulation time 545727443 ps
CPU time 0.95 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:31:47 PM PST 24
Peak memory 183336 kb
Host smart-c3b2f038-2c3d-4410-905f-5905e5d54be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100944030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.100944030
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2144228143
Short name T223
Test name
Test status
Simulation time 40541129322 ps
CPU time 57.11 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:32:50 PM PST 24
Peak memory 183364 kb
Host smart-965d4605-9dcf-441c-9445-b3e43dd77ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144228143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2144228143
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.1562315122
Short name T279
Test name
Test status
Simulation time 450338701 ps
CPU time 0.7 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:31:50 PM PST 24
Peak memory 183388 kb
Host smart-cb3bdf5e-db97-455a-a62a-925b285d7aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562315122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.1562315122
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.2285736608
Short name T283
Test name
Test status
Simulation time 303277938154 ps
CPU time 119.74 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:33:53 PM PST 24
Peak memory 183436 kb
Host smart-1ecdfa5d-a6b3-4843-b3d9-48a17d441503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285736608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.2285736608
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.2040302057
Short name T110
Test name
Test status
Simulation time 33094312570 ps
CPU time 174.77 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:34:44 PM PST 24
Peak memory 198344 kb
Host smart-bdbcbf25-53bc-4410-8737-e7aad0c02e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040302057 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.2040302057
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.1573060671
Short name T235
Test name
Test status
Simulation time 629908158 ps
CPU time 1.39 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:31:49 PM PST 24
Peak memory 183076 kb
Host smart-f837f3a2-612d-4e51-90a2-76a8e4df9233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573060671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.1573060671
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.2673097691
Short name T185
Test name
Test status
Simulation time 5365146764 ps
CPU time 2.08 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183360 kb
Host smart-73bcb1c3-ee9c-445b-97f4-e2791fe9fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673097691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.2673097691
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.2042771401
Short name T159
Test name
Test status
Simulation time 356367229 ps
CPU time 1.07 seconds
Started Feb 25 01:31:43 PM PST 24
Finished Feb 25 01:31:44 PM PST 24
Peak memory 183236 kb
Host smart-15e2b671-cece-4047-9800-c0fd43f87a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042771401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.2042771401
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2692374144
Short name T93
Test name
Test status
Simulation time 145837327333 ps
CPU time 50.75 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:32:44 PM PST 24
Peak memory 183372 kb
Host smart-edfc29d9-a175-4b40-ad10-e0dac49a2dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692374144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2692374144
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1197003775
Short name T215
Test name
Test status
Simulation time 48362819752 ps
CPU time 135.43 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:34:04 PM PST 24
Peak memory 198332 kb
Host smart-0419064e-2049-408e-8162-57f5e0eb20fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197003775 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1197003775
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.3393878581
Short name T141
Test name
Test status
Simulation time 485536271 ps
CPU time 0.72 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 183364 kb
Host smart-46b9b1bb-6f5d-4314-bc77-b79f37114a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393878581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.3393878581
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.3273479318
Short name T170
Test name
Test status
Simulation time 27946420475 ps
CPU time 7.13 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:41 PM PST 24
Peak memory 183484 kb
Host smart-f34a9003-1870-4a9e-a620-3e2b5cfaa2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273479318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.3273479318
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.463464498
Short name T19
Test name
Test status
Simulation time 7792092821 ps
CPU time 2.55 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 215420 kb
Host smart-73eefbe4-a0c2-42fc-aa6a-04b3b23a223d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463464498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.463464498
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1071776816
Short name T137
Test name
Test status
Simulation time 506650013 ps
CPU time 1.25 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 183412 kb
Host smart-51999a51-9422-4e00-a46f-2e7e592623f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071776816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1071776816
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.2187681141
Short name T123
Test name
Test status
Simulation time 394377621329 ps
CPU time 675.54 seconds
Started Feb 25 01:31:28 PM PST 24
Finished Feb 25 01:42:43 PM PST 24
Peak memory 183408 kb
Host smart-7c44a928-412d-4ae8-9eb0-71ec8da87276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187681141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.2187681141
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.3569536332
Short name T78
Test name
Test status
Simulation time 66887754028 ps
CPU time 541.7 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:40:36 PM PST 24
Peak memory 198416 kb
Host smart-c4e99a23-090e-42ca-9db2-8d2db751958d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569536332 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.3569536332
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2143311960
Short name T262
Test name
Test status
Simulation time 581107952 ps
CPU time 0.79 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:31:51 PM PST 24
Peak memory 183396 kb
Host smart-8cb99ed5-d5a5-47d5-b6dc-c983738529fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143311960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2143311960
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4140126098
Short name T200
Test name
Test status
Simulation time 31933261980 ps
CPU time 11.54 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:32:05 PM PST 24
Peak memory 183148 kb
Host smart-a71ef0d9-f46b-4eba-9c82-b39866913815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140126098 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4140126098
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3950158557
Short name T278
Test name
Test status
Simulation time 457894083 ps
CPU time 1.11 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183232 kb
Host smart-694c5118-626d-415f-94c9-0e74571725d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950158557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3950158557
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.3233007439
Short name T247
Test name
Test status
Simulation time 29299491254 ps
CPU time 12.44 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:32:06 PM PST 24
Peak memory 193748 kb
Host smart-c518c202-b14f-4d0c-aed8-daa6546801d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233007439 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.3233007439
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3199761859
Short name T43
Test name
Test status
Simulation time 193074520296 ps
CPU time 535.72 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:40:48 PM PST 24
Peak memory 198224 kb
Host smart-7c678d72-22d4-4791-973d-c0e5ca4fc1a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199761859 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3199761859
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.220084185
Short name T104
Test name
Test status
Simulation time 388280019 ps
CPU time 1.22 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183384 kb
Host smart-66321a08-d99f-41ed-9976-d48ec6006458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220084185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.220084185
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.4254477034
Short name T128
Test name
Test status
Simulation time 28265503168 ps
CPU time 8.32 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183404 kb
Host smart-a23bb81c-55a6-40d7-beae-17103743a10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254477034 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.4254477034
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2962607427
Short name T75
Test name
Test status
Simulation time 413858229 ps
CPU time 0.8 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:31:51 PM PST 24
Peak memory 183228 kb
Host smart-1b71b56f-2e15-4669-b6e9-57027bd1adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962607427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2962607427
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.820321561
Short name T181
Test name
Test status
Simulation time 14291380187 ps
CPU time 3.76 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 193504 kb
Host smart-1bf8bbd9-dbb0-4545-8081-9fb5fc07de13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820321561 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_a
ll.820321561
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.3250566629
Short name T87
Test name
Test status
Simulation time 50172470140 ps
CPU time 344.87 seconds
Started Feb 25 01:31:52 PM PST 24
Finished Feb 25 01:37:39 PM PST 24
Peak memory 198376 kb
Host smart-4187da00-59d8-44f2-b66c-13b588346503
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250566629 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.3250566629
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.2207872039
Short name T32
Test name
Test status
Simulation time 561687541 ps
CPU time 1.47 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:31:59 PM PST 24
Peak memory 183204 kb
Host smart-c62e112f-9ac3-4b5c-8249-0c36ce3fe752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207872039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.2207872039
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2665137299
Short name T9
Test name
Test status
Simulation time 40122560355 ps
CPU time 65.27 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:33:02 PM PST 24
Peak memory 183380 kb
Host smart-7dd89646-3ef9-43d0-8e44-5b45a6b6df1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665137299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2665137299
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.4084818411
Short name T126
Test name
Test status
Simulation time 564663011 ps
CPU time 0.64 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183272 kb
Host smart-ac50fd8f-ed12-4e9d-9e58-de45fa6b6939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084818411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.4084818411
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.115528670
Short name T218
Test name
Test status
Simulation time 153325846606 ps
CPU time 126.92 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:34:00 PM PST 24
Peak memory 193664 kb
Host smart-67732baf-e029-4788-80bc-abbaab262688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115528670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_a
ll.115528670
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3423587314
Short name T111
Test name
Test status
Simulation time 566097903 ps
CPU time 1.43 seconds
Started Feb 25 01:31:52 PM PST 24
Finished Feb 25 01:31:55 PM PST 24
Peak memory 183344 kb
Host smart-75d8822c-06b7-424f-9725-accfe3117906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423587314 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3423587314
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.300039859
Short name T46
Test name
Test status
Simulation time 4542707557 ps
CPU time 3.01 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:32:00 PM PST 24
Peak memory 183404 kb
Host smart-50165f2f-3fe2-46e9-918b-2517b65eb1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300039859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.300039859
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.1146154132
Short name T44
Test name
Test status
Simulation time 483431030 ps
CPU time 0.72 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 183276 kb
Host smart-ef44064b-c07c-4638-8b07-82ae59b920bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146154132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.1146154132
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2687540956
Short name T95
Test name
Test status
Simulation time 32015821733 ps
CPU time 48.01 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:32:44 PM PST 24
Peak memory 183392 kb
Host smart-063b580c-2a2c-413c-b12c-96de0bb469db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687540956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2687540956
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.3424227364
Short name T122
Test name
Test status
Simulation time 260081120322 ps
CPU time 447.49 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:39:24 PM PST 24
Peak memory 198328 kb
Host smart-16abaeff-da64-456a-a9fa-94fc286cd803
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424227364 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.3424227364
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.1511095203
Short name T115
Test name
Test status
Simulation time 580132372 ps
CPU time 0.76 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183380 kb
Host smart-c8cd3ec4-ab90-4aee-b842-235e4e110fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511095203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.1511095203
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1063846122
Short name T3
Test name
Test status
Simulation time 27994705372 ps
CPU time 9.8 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:32:06 PM PST 24
Peak memory 183388 kb
Host smart-3a196867-6c5f-42c5-8309-5b9a2792c99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063846122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1063846122
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2631861058
Short name T236
Test name
Test status
Simulation time 342081321 ps
CPU time 0.65 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183316 kb
Host smart-07703e18-b9b4-4062-926c-39a0771ab987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631861058 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2631861058
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3348052872
Short name T206
Test name
Test status
Simulation time 114837601460 ps
CPU time 165.05 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:34:49 PM PST 24
Peak memory 183392 kb
Host smart-3fd244f5-2892-4110-91bd-07bdc2f76ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348052872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3348052872
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.2881311107
Short name T85
Test name
Test status
Simulation time 382393385957 ps
CPU time 362.55 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:37:59 PM PST 24
Peak memory 198376 kb
Host smart-8f14ed7e-eb64-4de6-adbf-454788968734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881311107 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.2881311107
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2583324157
Short name T23
Test name
Test status
Simulation time 643211013 ps
CPU time 0.76 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183396 kb
Host smart-fcd1522e-635d-4280-ac16-bbe9ee76d686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583324157 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2583324157
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.3800970340
Short name T48
Test name
Test status
Simulation time 33658477803 ps
CPU time 4.42 seconds
Started Feb 25 01:31:52 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183412 kb
Host smart-2c392cfc-d1e9-4c9a-8104-5166650248ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800970340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.3800970340
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.3029052647
Short name T143
Test name
Test status
Simulation time 531342064 ps
CPU time 0.65 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 183276 kb
Host smart-661f18c2-d0ec-4099-ac66-1b69895baea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029052647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.3029052647
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.642387586
Short name T29
Test name
Test status
Simulation time 424302120 ps
CPU time 0.85 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183384 kb
Host smart-ff5df22f-9879-439e-9957-2d4c2e05760f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642387586 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.642387586
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1355826209
Short name T280
Test name
Test status
Simulation time 18332430027 ps
CPU time 9.99 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:32:07 PM PST 24
Peak memory 183408 kb
Host smart-bd4b2efe-19a0-4483-85f9-bf33dc574277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355826209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1355826209
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2795767370
Short name T251
Test name
Test status
Simulation time 382798033 ps
CPU time 0.92 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183288 kb
Host smart-98343e8a-dc6e-4401-9371-c5455bb314d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795767370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2795767370
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1656004835
Short name T175
Test name
Test status
Simulation time 307341375977 ps
CPU time 477.11 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:39:54 PM PST 24
Peak memory 193580 kb
Host smart-d37b68ab-8a17-4aed-a2bc-36581e5120b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656004835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1656004835
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.1896923580
Short name T37
Test name
Test status
Simulation time 72479289759 ps
CPU time 234.42 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:35:52 PM PST 24
Peak memory 206380 kb
Host smart-2f4adc35-ee09-456b-a5f7-a6901858a56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896923580 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.1896923580
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.607028802
Short name T198
Test name
Test status
Simulation time 537339131 ps
CPU time 0.74 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183380 kb
Host smart-64305b60-cf4f-4640-ad6e-87b7f3e7d994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607028802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.607028802
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.4285772809
Short name T191
Test name
Test status
Simulation time 18304754379 ps
CPU time 28.09 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:32:25 PM PST 24
Peak memory 183424 kb
Host smart-71d3ec6a-c416-4cc4-9f52-3fbebbf7efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285772809 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.4285772809
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.1692420859
Short name T270
Test name
Test status
Simulation time 491590949 ps
CPU time 1.25 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183292 kb
Host smart-f785f374-92ef-4344-8180-0d8cb2695da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692420859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.1692420859
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.3035835479
Short name T168
Test name
Test status
Simulation time 108318912695 ps
CPU time 46.71 seconds
Started Feb 25 01:31:53 PM PST 24
Finished Feb 25 01:32:41 PM PST 24
Peak memory 194708 kb
Host smart-b865f775-c060-4b52-b5c4-db22b2fbdbef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035835479 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.3035835479
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.4084492498
Short name T84
Test name
Test status
Simulation time 101411076199 ps
CPU time 727.42 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:44:04 PM PST 24
Peak memory 200400 kb
Host smart-84a75456-f610-4137-aac1-2eb22e4dc2b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084492498 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.4084492498
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.2114237618
Short name T171
Test name
Test status
Simulation time 374313441 ps
CPU time 1.08 seconds
Started Feb 25 01:31:58 PM PST 24
Finished Feb 25 01:32:00 PM PST 24
Peak memory 183328 kb
Host smart-5781bec9-6be7-40e4-8f4a-38484d83a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114237618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.2114237618
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.2646742045
Short name T265
Test name
Test status
Simulation time 7625669153 ps
CPU time 11.51 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:32:09 PM PST 24
Peak memory 183376 kb
Host smart-c83bccd2-285b-42ad-a71a-a0422f0ede41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646742045 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.2646742045
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.275624973
Short name T136
Test name
Test status
Simulation time 494666767 ps
CPU time 0.69 seconds
Started Feb 25 01:32:07 PM PST 24
Finished Feb 25 01:32:07 PM PST 24
Peak memory 183280 kb
Host smart-798cd109-9150-439b-bc28-2e93572e1748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275624973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.275624973
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1609438492
Short name T267
Test name
Test status
Simulation time 120575481457 ps
CPU time 10.3 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:32:08 PM PST 24
Peak memory 183452 kb
Host smart-c0e73033-16f2-4778-aa45-19cc842d578f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609438492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1609438492
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.2334541087
Short name T246
Test name
Test status
Simulation time 436535645129 ps
CPU time 971.05 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:48:15 PM PST 24
Peak memory 202788 kb
Host smart-407daff4-4c61-4e6f-bb9e-ce1fa7e797f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334541087 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.2334541087
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.956930743
Short name T214
Test name
Test status
Simulation time 478057343 ps
CPU time 0.72 seconds
Started Feb 25 01:31:59 PM PST 24
Finished Feb 25 01:32:00 PM PST 24
Peak memory 183324 kb
Host smart-4513c094-2a0b-41ab-90a8-a9807e76e643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956930743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.956930743
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.2954919400
Short name T147
Test name
Test status
Simulation time 7839283341 ps
CPU time 3.5 seconds
Started Feb 25 01:31:54 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 183408 kb
Host smart-f6640910-d190-40e7-85d8-6bdc32e8f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954919400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.2954919400
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2848908273
Short name T230
Test name
Test status
Simulation time 433849831 ps
CPU time 0.76 seconds
Started Feb 25 01:31:52 PM PST 24
Finished Feb 25 01:31:55 PM PST 24
Peak memory 183388 kb
Host smart-8d3b0636-7973-445c-9557-96b4e9cdabd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848908273 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2848908273
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.159961582
Short name T121
Test name
Test status
Simulation time 254702540233 ps
CPU time 93.01 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:33:30 PM PST 24
Peak memory 193708 kb
Host smart-d37d8389-4f66-4c95-a605-4a72df9ca887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159961582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.159961582
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.3891584391
Short name T140
Test name
Test status
Simulation time 11656255735 ps
CPU time 92.79 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:33:30 PM PST 24
Peak memory 198292 kb
Host smart-7822ce02-2473-4652-a03d-4a9e26193d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891584391 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.3891584391
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.524685765
Short name T222
Test name
Test status
Simulation time 363292373 ps
CPU time 0.64 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 183344 kb
Host smart-bf4b126d-9bcf-4cfd-a3ae-cc2b3a0324c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524685765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.524685765
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.1665964279
Short name T134
Test name
Test status
Simulation time 25735819269 ps
CPU time 38.39 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:32:12 PM PST 24
Peak memory 183412 kb
Host smart-1b9221bc-49f0-4517-8e9b-4f7f4ab7fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665964279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.1665964279
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.456685696
Short name T20
Test name
Test status
Simulation time 4500927063 ps
CPU time 3.51 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 215452 kb
Host smart-a4e0396f-53f1-4e50-ae03-e0c5c1fdcf2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456685696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.456685696
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2944449217
Short name T207
Test name
Test status
Simulation time 607859264 ps
CPU time 1.37 seconds
Started Feb 25 01:31:32 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 183268 kb
Host smart-2a452f21-2ed4-4186-bb49-62f179b05172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944449217 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2944449217
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1621963052
Short name T254
Test name
Test status
Simulation time 56208405326 ps
CPU time 33.67 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:32:07 PM PST 24
Peak memory 193800 kb
Host smart-2b5b13a9-e9f9-4c30-8a2c-22cb3714bad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621963052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1621963052
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1121961514
Short name T17
Test name
Test status
Simulation time 71647412367 ps
CPU time 200.24 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:34:52 PM PST 24
Peak memory 198348 kb
Host smart-0e34463a-3a5c-4484-a7c1-ed8bb7e43bcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121961514 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1121961514
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.2278184478
Short name T113
Test name
Test status
Simulation time 527918264 ps
CPU time 0.73 seconds
Started Feb 25 01:31:59 PM PST 24
Finished Feb 25 01:32:00 PM PST 24
Peak memory 183328 kb
Host smart-638633d3-0ba8-4889-8b15-f08001801ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278184478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.2278184478
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2203537291
Short name T221
Test name
Test status
Simulation time 9157698688 ps
CPU time 2.15 seconds
Started Feb 25 01:31:57 PM PST 24
Finished Feb 25 01:31:59 PM PST 24
Peak memory 183452 kb
Host smart-0f637e66-bd31-4b84-9b3d-6d8e8b330e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203537291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2203537291
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3700161536
Short name T135
Test name
Test status
Simulation time 570891592 ps
CPU time 1.5 seconds
Started Feb 25 01:32:00 PM PST 24
Finished Feb 25 01:32:02 PM PST 24
Peak memory 183220 kb
Host smart-a1bca595-22ca-4305-92a8-8d547a5c050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700161536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3700161536
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2969970657
Short name T10
Test name
Test status
Simulation time 242951031460 ps
CPU time 324.3 seconds
Started Feb 25 01:32:07 PM PST 24
Finished Feb 25 01:37:31 PM PST 24
Peak memory 193452 kb
Host smart-529ac503-e77d-4f5b-be36-b8e6beaab90a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969970657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2969970657
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2612587340
Short name T187
Test name
Test status
Simulation time 458402086 ps
CPU time 0.68 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183384 kb
Host smart-38443f63-4c80-4ca9-8a9d-670c2f971618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612587340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2612587340
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.2553358547
Short name T163
Test name
Test status
Simulation time 30955268842 ps
CPU time 24.28 seconds
Started Feb 25 01:31:53 PM PST 24
Finished Feb 25 01:32:18 PM PST 24
Peak memory 183436 kb
Host smart-eecbaaef-35bc-40da-bbf6-3dd3b893827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553358547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.2553358547
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.1783934428
Short name T158
Test name
Test status
Simulation time 429660401 ps
CPU time 0.71 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183372 kb
Host smart-30d1b0fd-a7ac-4797-843a-afe269d0521f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783934428 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.1783934428
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.864659096
Short name T149
Test name
Test status
Simulation time 47097682096 ps
CPU time 65.07 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:33:01 PM PST 24
Peak memory 183392 kb
Host smart-df43c449-7ea5-48e1-90e7-c741f2e774eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864659096 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.864659096
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.4158299942
Short name T101
Test name
Test status
Simulation time 16079600833 ps
CPU time 127.55 seconds
Started Feb 25 01:31:54 PM PST 24
Finished Feb 25 01:34:02 PM PST 24
Peak memory 198328 kb
Host smart-7fc3f4cd-1c53-4252-a86d-c1130148f012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158299942 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.4158299942
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.2445694670
Short name T96
Test name
Test status
Simulation time 497602394 ps
CPU time 1.17 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:31:56 PM PST 24
Peak memory 183388 kb
Host smart-b31ce8bc-09bd-48d2-9d46-daf687f7d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445694670 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.2445694670
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3182788562
Short name T151
Test name
Test status
Simulation time 30683600645 ps
CPU time 18.2 seconds
Started Feb 25 01:32:07 PM PST 24
Finished Feb 25 01:32:25 PM PST 24
Peak memory 183408 kb
Host smart-b2415eb1-bd11-4eef-b81a-eac8a2dd9218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182788562 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3182788562
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3111551519
Short name T153
Test name
Test status
Simulation time 406322247 ps
CPU time 0.67 seconds
Started Feb 25 01:31:54 PM PST 24
Finished Feb 25 01:31:55 PM PST 24
Peak memory 183380 kb
Host smart-44035f86-42b6-4baa-b515-cfceef612e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111551519 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3111551519
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.4247718878
Short name T205
Test name
Test status
Simulation time 20193607207 ps
CPU time 18.34 seconds
Started Feb 25 01:31:55 PM PST 24
Finished Feb 25 01:32:14 PM PST 24
Peak memory 194804 kb
Host smart-d2e1419e-f805-4826-b314-7feb5d3cdf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247718878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.4247718878
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.2682886006
Short name T201
Test name
Test status
Simulation time 386794931918 ps
CPU time 296.21 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:36:52 PM PST 24
Peak memory 198324 kb
Host smart-af3970c9-a4b0-408e-abdf-63b705951e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682886006 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.2682886006
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.226691388
Short name T250
Test name
Test status
Simulation time 584611951 ps
CPU time 1.5 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:58 PM PST 24
Peak memory 183384 kb
Host smart-3247314e-5a69-4cc1-a759-5dec92af0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226691388 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.226691388
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.1479817247
Short name T179
Test name
Test status
Simulation time 45835212798 ps
CPU time 70.48 seconds
Started Feb 25 01:32:07 PM PST 24
Finished Feb 25 01:33:17 PM PST 24
Peak memory 183412 kb
Host smart-209b2118-b47a-4d22-b659-6d824493a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479817247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.1479817247
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2438555989
Short name T259
Test name
Test status
Simulation time 457356132 ps
CPU time 0.91 seconds
Started Feb 25 01:31:56 PM PST 24
Finished Feb 25 01:31:57 PM PST 24
Peak memory 183328 kb
Host smart-bb7e74b3-b31d-459e-8b20-9b233a88fbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438555989 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2438555989
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.362289370
Short name T276
Test name
Test status
Simulation time 178379732579 ps
CPU time 67.54 seconds
Started Feb 25 01:32:11 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 193512 kb
Host smart-b3883271-9b79-46d9-a967-b53be647f2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362289370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_a
ll.362289370
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2845409688
Short name T176
Test name
Test status
Simulation time 18096188499 ps
CPU time 196.07 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:35:20 PM PST 24
Peak memory 198492 kb
Host smart-b90ef355-90fc-413a-aa55-394a73b8a5cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845409688 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2845409688
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1797985712
Short name T100
Test name
Test status
Simulation time 592175093 ps
CPU time 0.66 seconds
Started Feb 25 01:32:06 PM PST 24
Finished Feb 25 01:32:06 PM PST 24
Peak memory 183380 kb
Host smart-cf567e8f-dd4e-437c-911a-39957cd459ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797985712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1797985712
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2029520422
Short name T193
Test name
Test status
Simulation time 5156739013 ps
CPU time 4 seconds
Started Feb 25 01:32:16 PM PST 24
Finished Feb 25 01:32:20 PM PST 24
Peak memory 183412 kb
Host smart-ee848e72-4fe5-4461-af6f-e7111575064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029520422 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2029520422
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.597168406
Short name T12
Test name
Test status
Simulation time 406308868 ps
CPU time 1.16 seconds
Started Feb 25 01:32:02 PM PST 24
Finished Feb 25 01:32:03 PM PST 24
Peak memory 183392 kb
Host smart-81c9be6d-2f21-4f4b-a1c9-3bd9b8a1c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597168406 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.597168406
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3743613604
Short name T225
Test name
Test status
Simulation time 42662934289 ps
CPU time 11.02 seconds
Started Feb 25 01:32:03 PM PST 24
Finished Feb 25 01:32:14 PM PST 24
Peak memory 183432 kb
Host smart-682681b3-2626-4762-9525-a106e47cb1c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743613604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3743613604
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2003950557
Short name T232
Test name
Test status
Simulation time 53185281858 ps
CPU time 606.63 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:42:11 PM PST 24
Peak memory 198324 kb
Host smart-467760d9-d259-4d1d-84d1-56512ee82787
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003950557 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2003950557
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2357686363
Short name T248
Test name
Test status
Simulation time 626940993 ps
CPU time 0.66 seconds
Started Feb 25 01:32:03 PM PST 24
Finished Feb 25 01:32:04 PM PST 24
Peak memory 183396 kb
Host smart-c0e45b36-8e21-4244-8321-06c1b85be1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357686363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2357686363
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.1108080858
Short name T264
Test name
Test status
Simulation time 51922311375 ps
CPU time 19.59 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183412 kb
Host smart-3fc13dc4-52d4-496d-b6d3-100d9dfc0e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108080858 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.1108080858
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2712078555
Short name T1
Test name
Test status
Simulation time 453587207 ps
CPU time 0.95 seconds
Started Feb 25 01:32:03 PM PST 24
Finished Feb 25 01:32:04 PM PST 24
Peak memory 183272 kb
Host smart-d3ee245c-8122-4c4c-9639-6610c9010cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712078555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2712078555
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.249884523
Short name T117
Test name
Test status
Simulation time 57228252987 ps
CPU time 11.96 seconds
Started Feb 25 01:32:11 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183456 kb
Host smart-e14cd50e-047e-406c-9534-2fcc40bba58c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249884523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.249884523
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.168656299
Short name T86
Test name
Test status
Simulation time 34707182456 ps
CPU time 268.24 seconds
Started Feb 25 01:32:08 PM PST 24
Finished Feb 25 01:36:36 PM PST 24
Peak memory 198344 kb
Host smart-a1483b2c-606f-40b0-850f-b40003bdd077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168656299 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.168656299
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1547028155
Short name T26
Test name
Test status
Simulation time 436220448 ps
CPU time 1.3 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:32:05 PM PST 24
Peak memory 183340 kb
Host smart-65ab5a8a-f18d-445f-9534-c0fdf9f2fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547028155 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1547028155
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2346051480
Short name T183
Test name
Test status
Simulation time 23707524354 ps
CPU time 33.86 seconds
Started Feb 25 01:32:03 PM PST 24
Finished Feb 25 01:32:37 PM PST 24
Peak memory 183436 kb
Host smart-c4788809-470f-44d1-89f0-424979343291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346051480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2346051480
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.3628524895
Short name T162
Test name
Test status
Simulation time 545690473 ps
CPU time 1.33 seconds
Started Feb 25 01:32:08 PM PST 24
Finished Feb 25 01:32:10 PM PST 24
Peak memory 183288 kb
Host smart-8b066085-4930-4cbe-a1e9-b54579158095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628524895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.3628524895
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.4188640805
Short name T31
Test name
Test status
Simulation time 92380350567 ps
CPU time 127.91 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:34:12 PM PST 24
Peak memory 183436 kb
Host smart-8931c924-09f2-482e-8f57-194406a91b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188640805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.4188640805
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.3751458899
Short name T108
Test name
Test status
Simulation time 16895226089 ps
CPU time 182.86 seconds
Started Feb 25 01:32:03 PM PST 24
Finished Feb 25 01:35:06 PM PST 24
Peak memory 198320 kb
Host smart-359c4a4c-5341-44d5-9ae1-0bed12b88e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751458899 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.3751458899
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.4111498632
Short name T182
Test name
Test status
Simulation time 472678182 ps
CPU time 1.29 seconds
Started Feb 25 01:32:05 PM PST 24
Finished Feb 25 01:32:06 PM PST 24
Peak memory 183364 kb
Host smart-290ef293-283c-414a-a660-e307d9504bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111498632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.4111498632
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.3918704712
Short name T277
Test name
Test status
Simulation time 6836949023 ps
CPU time 3.19 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:32:07 PM PST 24
Peak memory 183392 kb
Host smart-51449870-4523-4249-9060-5b78d0a09f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918704712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.3918704712
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4256969557
Short name T172
Test name
Test status
Simulation time 379590063 ps
CPU time 1.08 seconds
Started Feb 25 01:32:09 PM PST 24
Finished Feb 25 01:32:11 PM PST 24
Peak memory 183212 kb
Host smart-40e79a43-e47e-46eb-b1e0-071e65d9971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256969557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4256969557
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.2869562755
Short name T94
Test name
Test status
Simulation time 148950547536 ps
CPU time 203.16 seconds
Started Feb 25 01:32:16 PM PST 24
Finished Feb 25 01:35:39 PM PST 24
Peak memory 183436 kb
Host smart-823d3e0b-1c5c-4ea0-b4c3-af0b0e96ec27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869562755 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.2869562755
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3184702813
Short name T241
Test name
Test status
Simulation time 53389708270 ps
CPU time 111.63 seconds
Started Feb 25 01:32:16 PM PST 24
Finished Feb 25 01:34:07 PM PST 24
Peak memory 198344 kb
Host smart-afb79ca1-db5a-4d84-aeee-7750a710d648
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184702813 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3184702813
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2388321601
Short name T282
Test name
Test status
Simulation time 428432483 ps
CPU time 1.2 seconds
Started Feb 25 01:32:04 PM PST 24
Finished Feb 25 01:32:05 PM PST 24
Peak memory 183384 kb
Host smart-b4fd078b-21f0-4b46-8781-fc6df39a1753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388321601 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2388321601
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.3824884075
Short name T130
Test name
Test status
Simulation time 28054372205 ps
CPU time 9.37 seconds
Started Feb 25 01:32:15 PM PST 24
Finished Feb 25 01:32:25 PM PST 24
Peak memory 183436 kb
Host smart-4130b9ab-9f1f-4b7a-be9c-02b9fd5493a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824884075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.3824884075
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.828113903
Short name T260
Test name
Test status
Simulation time 404998611 ps
CPU time 0.71 seconds
Started Feb 25 01:32:16 PM PST 24
Finished Feb 25 01:32:16 PM PST 24
Peak memory 183280 kb
Host smart-9210e00c-abd1-42b5-8735-53823807667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828113903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.828113903
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.287429213
Short name T146
Test name
Test status
Simulation time 186257733148 ps
CPU time 70.09 seconds
Started Feb 25 01:32:22 PM PST 24
Finished Feb 25 01:33:32 PM PST 24
Peak memory 193396 kb
Host smart-0e7ed635-07e6-4811-81dd-1784b454a8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287429213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_a
ll.287429213
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1223919945
Short name T41
Test name
Test status
Simulation time 20828407113 ps
CPU time 217.72 seconds
Started Feb 25 01:32:25 PM PST 24
Finished Feb 25 01:36:02 PM PST 24
Peak memory 198320 kb
Host smart-24e2e20a-4784-4064-8521-87dbc1d111f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223919945 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1223919945
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.2905469052
Short name T98
Test name
Test status
Simulation time 496624960 ps
CPU time 0.64 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183420 kb
Host smart-f77d91af-1fa2-4946-8b12-6f36affdb50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905469052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.2905469052
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.3330697529
Short name T243
Test name
Test status
Simulation time 56417657402 ps
CPU time 52.94 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:33:14 PM PST 24
Peak memory 183448 kb
Host smart-ef6d6e4f-7cac-48e5-a954-1fa8e07fd6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330697529 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.3330697529
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3492422875
Short name T273
Test name
Test status
Simulation time 382759703 ps
CPU time 0.68 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183276 kb
Host smart-b5a66067-2f2d-4da7-a274-71b77492ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492422875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3492422875
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.2318996347
Short name T105
Test name
Test status
Simulation time 70995065104 ps
CPU time 76.82 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:33:36 PM PST 24
Peak memory 183436 kb
Host smart-c01fe6d2-8f05-4572-bec1-950672d514a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318996347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.2318996347
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.3203694964
Short name T261
Test name
Test status
Simulation time 1120828568677 ps
CPU time 468.94 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:40:10 PM PST 24
Peak memory 198328 kb
Host smart-0f94f9e3-7cd9-493e-bfa6-e260e7e0f0d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203694964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.3203694964
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2363738002
Short name T213
Test name
Test status
Simulation time 593824216 ps
CPU time 0.71 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 183336 kb
Host smart-282b7c7a-c3be-40c3-adb4-955fc2b4c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363738002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2363738002
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2030750758
Short name T244
Test name
Test status
Simulation time 36344548234 ps
CPU time 3.47 seconds
Started Feb 25 01:31:27 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 183380 kb
Host smart-d34f19ed-3571-430c-b23a-f7457bf9cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030750758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2030750758
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.3605307025
Short name T21
Test name
Test status
Simulation time 4332001420 ps
CPU time 3.33 seconds
Started Feb 25 01:31:46 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 215284 kb
Host smart-632e489e-4d53-4bea-b33e-6c877a113317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605307025 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.3605307025
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.2597796544
Short name T127
Test name
Test status
Simulation time 562620928 ps
CPU time 1.22 seconds
Started Feb 25 01:31:32 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 183384 kb
Host smart-e3eb18c5-6feb-4760-b994-841950eedb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597796544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.2597796544
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.1571805306
Short name T180
Test name
Test status
Simulation time 273814187852 ps
CPU time 116.26 seconds
Started Feb 25 01:31:41 PM PST 24
Finished Feb 25 01:33:37 PM PST 24
Peak memory 183440 kb
Host smart-e82e587d-b0cb-4f1d-bdcd-f612df2f1590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571805306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.1571805306
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.3785474538
Short name T229
Test name
Test status
Simulation time 11186834052 ps
CPU time 52.96 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:32:45 PM PST 24
Peak memory 196976 kb
Host smart-7a330181-3b2f-48cf-a474-62f67e4bcaac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785474538 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.3785474538
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.2490301208
Short name T284
Test name
Test status
Simulation time 490487191 ps
CPU time 0.75 seconds
Started Feb 25 01:32:22 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183376 kb
Host smart-133f7834-4ba0-43cd-aa55-2e1e16590b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490301208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.2490301208
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4220509549
Short name T160
Test name
Test status
Simulation time 41867432706 ps
CPU time 60.6 seconds
Started Feb 25 01:32:18 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 183356 kb
Host smart-ac2d6c0d-a9ac-4fd8-8c8d-8160888ceabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220509549 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4220509549
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3577861142
Short name T173
Test name
Test status
Simulation time 377089247 ps
CPU time 0.68 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183232 kb
Host smart-8e7449ae-b5f0-4bc2-b5c8-e418c2d9f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577861142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3577861142
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2891843138
Short name T125
Test name
Test status
Simulation time 160569604426 ps
CPU time 221.63 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:36:02 PM PST 24
Peak memory 183396 kb
Host smart-c341fede-28dd-4016-a266-5b7db086c414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891843138 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2891843138
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2414296223
Short name T196
Test name
Test status
Simulation time 604052330 ps
CPU time 0.77 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183384 kb
Host smart-2b1a8c70-f289-4d23-8a7c-06168895a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414296223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2414296223
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3900339919
Short name T5
Test name
Test status
Simulation time 39014626929 ps
CPU time 29.15 seconds
Started Feb 25 01:32:24 PM PST 24
Finished Feb 25 01:32:54 PM PST 24
Peak memory 183388 kb
Host smart-0af339ad-b200-4745-8239-648b15f614b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900339919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3900339919
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2205821174
Short name T188
Test name
Test status
Simulation time 537012632 ps
CPU time 0.9 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:32:21 PM PST 24
Peak memory 183228 kb
Host smart-97adb53f-e39f-436f-9833-80995e0a910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205821174 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2205821174
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.1312351718
Short name T112
Test name
Test status
Simulation time 213522902493 ps
CPU time 254.22 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:36:33 PM PST 24
Peak memory 183452 kb
Host smart-9b2d0558-f26b-40da-98f6-7001b74e6def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312351718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.1312351718
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.4289262634
Short name T83
Test name
Test status
Simulation time 217842616141 ps
CPU time 421.48 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:39:22 PM PST 24
Peak memory 198348 kb
Host smart-4c00df4d-cd22-4d3c-8607-232f4fb76adf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289262634 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.4289262634
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.414628161
Short name T167
Test name
Test status
Simulation time 483721375 ps
CPU time 0.88 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183420 kb
Host smart-4a9f58b0-d715-461b-b715-12e54656b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414628161 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.414628161
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3360585589
Short name T190
Test name
Test status
Simulation time 59323133155 ps
CPU time 77.72 seconds
Started Feb 25 01:32:22 PM PST 24
Finished Feb 25 01:33:40 PM PST 24
Peak memory 183364 kb
Host smart-ab838b56-f805-41af-8338-09966277ea68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360585589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3360585589
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2657040213
Short name T8
Test name
Test status
Simulation time 443908560 ps
CPU time 0.7 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:32:20 PM PST 24
Peak memory 183224 kb
Host smart-8f2e2550-5b29-45ed-a8c7-43129e60e8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657040213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2657040213
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3795426128
Short name T245
Test name
Test status
Simulation time 57452988102 ps
CPU time 20.15 seconds
Started Feb 25 01:32:18 PM PST 24
Finished Feb 25 01:32:38 PM PST 24
Peak memory 193652 kb
Host smart-cff435c4-b9e2-4a22-a3d7-e03f7745eb07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795426128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3795426128
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.630005623
Short name T275
Test name
Test status
Simulation time 24989322837 ps
CPU time 261.63 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:36:50 PM PST 24
Peak memory 198376 kb
Host smart-900bda62-e00d-4240-9e64-58e3c82dd616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630005623 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.630005623
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.3779295830
Short name T138
Test name
Test status
Simulation time 601024591 ps
CPU time 0.74 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183384 kb
Host smart-13cd7424-cd29-4b04-a97a-3c6866ca7775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779295830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.3779295830
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.3217873797
Short name T212
Test name
Test status
Simulation time 52423251971 ps
CPU time 71.84 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:33:33 PM PST 24
Peak memory 183552 kb
Host smart-fd879b09-618e-40e4-8a37-56f37973fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217873797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.3217873797
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.1816036249
Short name T234
Test name
Test status
Simulation time 502182356 ps
CPU time 1.19 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183232 kb
Host smart-36a6a49d-f117-4ea5-9b12-8bdd2900bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816036249 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.1816036249
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.4206926490
Short name T240
Test name
Test status
Simulation time 181422741346 ps
CPU time 286.49 seconds
Started Feb 25 01:32:18 PM PST 24
Finished Feb 25 01:37:05 PM PST 24
Peak memory 193436 kb
Host smart-992088de-61d3-413c-a1f1-d93ffdde5cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206926490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.4206926490
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2477169530
Short name T249
Test name
Test status
Simulation time 11850300893 ps
CPU time 94.93 seconds
Started Feb 25 01:32:22 PM PST 24
Finished Feb 25 01:33:57 PM PST 24
Peak memory 198308 kb
Host smart-b1d678e5-88a8-46b7-a106-5198eeddf5d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477169530 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2477169530
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3907078274
Short name T133
Test name
Test status
Simulation time 546718817 ps
CPU time 1.39 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:32:22 PM PST 24
Peak memory 183396 kb
Host smart-8185309a-a7c7-47a6-b527-9e428e912684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907078274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3907078274
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3122893071
Short name T4
Test name
Test status
Simulation time 27249814741 ps
CPU time 6.34 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:28 PM PST 24
Peak memory 183432 kb
Host smart-bde8de0e-3675-471d-8b8b-ffa28d1a886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122893071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3122893071
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.807113004
Short name T165
Test name
Test status
Simulation time 612993224 ps
CPU time 0.74 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:32:20 PM PST 24
Peak memory 183376 kb
Host smart-3f2fc5dd-4b00-41fd-bfc6-fac3b7a56584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807113004 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.807113004
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1437618577
Short name T156
Test name
Test status
Simulation time 184977570397 ps
CPU time 47.16 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:33:07 PM PST 24
Peak memory 183436 kb
Host smart-de548289-99ba-4089-91d1-ce6e03cece18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437618577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1437618577
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.1378179900
Short name T211
Test name
Test status
Simulation time 212782893253 ps
CPU time 605.65 seconds
Started Feb 25 01:32:17 PM PST 24
Finished Feb 25 01:42:23 PM PST 24
Peak memory 199428 kb
Host smart-05bb26ca-6e2c-4920-b72d-ad177ca81df8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378179900 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.1378179900
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2272191035
Short name T150
Test name
Test status
Simulation time 567889843 ps
CPU time 0.91 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183368 kb
Host smart-b5b676f4-60b8-4f19-891d-6766e46728b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272191035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2272191035
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.1089985930
Short name T132
Test name
Test status
Simulation time 44172263419 ps
CPU time 15.97 seconds
Started Feb 25 01:32:18 PM PST 24
Finished Feb 25 01:32:34 PM PST 24
Peak memory 183408 kb
Host smart-8cd9bee9-712e-4fd9-95a2-1fa868aeca66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089985930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.1089985930
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.1091508593
Short name T216
Test name
Test status
Simulation time 582351505 ps
CPU time 1.48 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183360 kb
Host smart-f2376ac1-6a90-4971-9339-cef43abd3f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091508593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.1091508593
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.146668213
Short name T107
Test name
Test status
Simulation time 196191967907 ps
CPU time 166.07 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:35:06 PM PST 24
Peak memory 183396 kb
Host smart-5e016e71-3c13-4a87-9aed-6fb67f59b9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146668213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.146668213
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.68939450
Short name T81
Test name
Test status
Simulation time 26800086693 ps
CPU time 279.44 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:37:00 PM PST 24
Peak memory 198364 kb
Host smart-c4f842dc-a97a-4e1b-8e55-53983ee36adb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68939450 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.68939450
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.2056250546
Short name T197
Test name
Test status
Simulation time 594397649 ps
CPU time 1.41 seconds
Started Feb 25 01:32:18 PM PST 24
Finished Feb 25 01:32:20 PM PST 24
Peak memory 183368 kb
Host smart-13da6a66-b235-425a-ab9d-5eb6e7301048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056250546 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.2056250546
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.1513419737
Short name T227
Test name
Test status
Simulation time 655040203 ps
CPU time 1.49 seconds
Started Feb 25 01:32:19 PM PST 24
Finished Feb 25 01:32:21 PM PST 24
Peak memory 183324 kb
Host smart-7fcf8cad-97df-4082-9ac9-4f90910e3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513419737 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.1513419737
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.1449348345
Short name T186
Test name
Test status
Simulation time 400766824 ps
CPU time 0.65 seconds
Started Feb 25 01:32:29 PM PST 24
Finished Feb 25 01:32:30 PM PST 24
Peak memory 183276 kb
Host smart-e354ee36-c7af-4330-8c7b-e5a9035cecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449348345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.1449348345
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1796901784
Short name T169
Test name
Test status
Simulation time 108540854216 ps
CPU time 39.4 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:32:59 PM PST 24
Peak memory 183452 kb
Host smart-53ad0db8-66cf-458f-9ccc-653626e5ca78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796901784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1796901784
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1049764338
Short name T242
Test name
Test status
Simulation time 13693612775 ps
CPU time 102.84 seconds
Started Feb 25 01:32:21 PM PST 24
Finished Feb 25 01:34:05 PM PST 24
Peak memory 198324 kb
Host smart-807b896e-14c7-4b7d-979b-e56ab862e19e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049764338 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1049764338
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3185634705
Short name T103
Test name
Test status
Simulation time 384755779 ps
CPU time 0.88 seconds
Started Feb 25 01:32:33 PM PST 24
Finished Feb 25 01:32:34 PM PST 24
Peak memory 183392 kb
Host smart-279efbce-a6c7-4f06-80b4-d80ca9a34ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185634705 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3185634705
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.4149589385
Short name T195
Test name
Test status
Simulation time 27221714791 ps
CPU time 21.41 seconds
Started Feb 25 01:32:20 PM PST 24
Finished Feb 25 01:32:42 PM PST 24
Peak memory 183436 kb
Host smart-549516b3-e49e-45a7-9d18-82173eca87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149589385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.4149589385
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.655591887
Short name T177
Test name
Test status
Simulation time 567351646 ps
CPU time 1.44 seconds
Started Feb 25 01:32:22 PM PST 24
Finished Feb 25 01:32:23 PM PST 24
Peak memory 183280 kb
Host smart-8b64410c-fcd0-4c4a-a3f3-0ec928caa638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655591887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.655591887
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1633963170
Short name T210
Test name
Test status
Simulation time 120813261506 ps
CPU time 51.53 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:33:19 PM PST 24
Peak memory 193412 kb
Host smart-50afc67d-cea7-4b8f-8954-6427bc695031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633963170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1633963170
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3655996194
Short name T77
Test name
Test status
Simulation time 649471497015 ps
CPU time 129.29 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:34:47 PM PST 24
Peak memory 198276 kb
Host smart-880b4568-c986-4971-94e1-c11411cfc1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655996194 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3655996194
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.3481709822
Short name T145
Test name
Test status
Simulation time 358911104 ps
CPU time 1.07 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:33 PM PST 24
Peak memory 183384 kb
Host smart-c25f9def-0e6e-4617-a9e0-66115f9fadea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481709822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.3481709822
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3182931357
Short name T155
Test name
Test status
Simulation time 1188694519 ps
CPU time 1.25 seconds
Started Feb 25 01:32:27 PM PST 24
Finished Feb 25 01:32:28 PM PST 24
Peak memory 183248 kb
Host smart-6cd0e91f-1233-4940-8a2e-d0d8b2490243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182931357 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3182931357
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.2356308879
Short name T45
Test name
Test status
Simulation time 546941815 ps
CPU time 1.27 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:33 PM PST 24
Peak memory 183348 kb
Host smart-00c166a0-f20a-42d1-b106-fe60f61f9864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356308879 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.2356308879
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.1964607770
Short name T224
Test name
Test status
Simulation time 70914310957 ps
CPU time 98.76 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:34:17 PM PST 24
Peak memory 193604 kb
Host smart-3e82b75f-59b8-426d-9401-a72e5103f81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964607770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_
all.1964607770
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.2247209804
Short name T40
Test name
Test status
Simulation time 11163239308 ps
CPU time 74.91 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:33:46 PM PST 24
Peak memory 198336 kb
Host smart-48c08e5d-03c8-4a86-8f33-dc2c8ac8e08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247209804 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.2247209804
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.580184118
Short name T257
Test name
Test status
Simulation time 461522241 ps
CPU time 0.66 seconds
Started Feb 25 01:32:27 PM PST 24
Finished Feb 25 01:32:28 PM PST 24
Peak memory 183424 kb
Host smart-92876608-25e4-4bec-9cd9-8a82255368fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580184118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.580184118
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.2369967447
Short name T255
Test name
Test status
Simulation time 24275140750 ps
CPU time 34.34 seconds
Started Feb 25 01:32:31 PM PST 24
Finished Feb 25 01:33:06 PM PST 24
Peak memory 183424 kb
Host smart-03fffa56-ef04-4e30-ade2-7dd7b29d39a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369967447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.2369967447
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.387077604
Short name T202
Test name
Test status
Simulation time 507875497 ps
CPU time 0.67 seconds
Started Feb 25 01:32:32 PM PST 24
Finished Feb 25 01:32:33 PM PST 24
Peak memory 183288 kb
Host smart-cc5cc23c-a941-42ca-88e9-a08c396bedf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387077604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.387077604
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.388754920
Short name T199
Test name
Test status
Simulation time 4139085043 ps
CPU time 2.59 seconds
Started Feb 25 01:32:28 PM PST 24
Finished Feb 25 01:32:31 PM PST 24
Peak memory 183452 kb
Host smart-70b527a1-7b0c-423d-8ce7-896ad9fbc979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388754920 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_a
ll.388754920
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.90958525
Short name T161
Test name
Test status
Simulation time 151716514349 ps
CPU time 361.85 seconds
Started Feb 25 01:32:38 PM PST 24
Finished Feb 25 01:38:40 PM PST 24
Peak memory 198296 kb
Host smart-cc1de365-c064-455a-98f4-aac324e6ae6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90958525 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.90958525
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2386728261
Short name T124
Test name
Test status
Simulation time 424000730 ps
CPU time 0.7 seconds
Started Feb 25 01:31:44 PM PST 24
Finished Feb 25 01:31:46 PM PST 24
Peak memory 183396 kb
Host smart-87804025-e95b-4a2a-be7a-d155c267ed98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386728261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2386728261
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2269608026
Short name T228
Test name
Test status
Simulation time 27517192173 ps
CPU time 37.1 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:32:29 PM PST 24
Peak memory 183348 kb
Host smart-fb92154e-e4f5-4243-b4a0-fab5859f3d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269608026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2269608026
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.216774284
Short name T164
Test name
Test status
Simulation time 418449387 ps
CPU time 0.7 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 183272 kb
Host smart-02c09862-49ba-47bd-9f01-50eb9d76c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216774284 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.216774284
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1082637688
Short name T209
Test name
Test status
Simulation time 136734804360 ps
CPU time 106.04 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:33:36 PM PST 24
Peak memory 193880 kb
Host smart-5fd1dbfe-5478-4766-9354-6b10c0651c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082637688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1082637688
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1129575252
Short name T38
Test name
Test status
Simulation time 76170350677 ps
CPU time 307.68 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:36:59 PM PST 24
Peak memory 198252 kb
Host smart-715d0b46-84b9-4d18-945f-f60862e57975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129575252 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1129575252
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.3061146663
Short name T256
Test name
Test status
Simulation time 451021031 ps
CPU time 0.59 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183276 kb
Host smart-a7ea921a-be3c-4593-9526-58c84607d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061146663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.3061146663
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.1136980275
Short name T263
Test name
Test status
Simulation time 595562985 ps
CPU time 1.05 seconds
Started Feb 25 01:31:43 PM PST 24
Finished Feb 25 01:31:44 PM PST 24
Peak memory 183220 kb
Host smart-9fb7c1d8-e4f4-4393-86cd-1582d822f5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136980275 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.1136980275
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2211062085
Short name T220
Test name
Test status
Simulation time 400954253 ps
CPU time 0.78 seconds
Started Feb 25 01:31:49 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183168 kb
Host smart-f64f15f4-12bc-481e-b983-aca57f853801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211062085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2211062085
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1079543618
Short name T120
Test name
Test status
Simulation time 253513343629 ps
CPU time 91.74 seconds
Started Feb 25 01:31:44 PM PST 24
Finished Feb 25 01:33:17 PM PST 24
Peak memory 183408 kb
Host smart-fc65da27-0682-4b8b-b7e8-9c82037f1e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079543618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1079543618
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.513738386
Short name T80
Test name
Test status
Simulation time 57321611037 ps
CPU time 167.95 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:34:40 PM PST 24
Peak memory 198336 kb
Host smart-9cb75c99-3cea-4739-b462-22370dc2eb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513738386 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.513738386
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1524165074
Short name T15
Test name
Test status
Simulation time 513992047 ps
CPU time 1.05 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 183336 kb
Host smart-5bb3f58c-7f1c-4646-a4bf-3e88c3a4b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524165074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1524165074
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2892114335
Short name T7
Test name
Test status
Simulation time 44959068678 ps
CPU time 17.4 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:32:10 PM PST 24
Peak memory 181952 kb
Host smart-2d1afabc-751b-47d1-b7da-0445f10f254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892114335 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2892114335
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1873830470
Short name T129
Test name
Test status
Simulation time 517953962 ps
CPU time 0.66 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:53 PM PST 24
Peak memory 183116 kb
Host smart-bc1ad249-7548-4892-8fe0-f65ff95e5547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873830470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1873830470
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.2460870952
Short name T174
Test name
Test status
Simulation time 120115938390 ps
CPU time 200.41 seconds
Started Feb 25 01:31:39 PM PST 24
Finished Feb 25 01:35:00 PM PST 24
Peak memory 191652 kb
Host smart-d75f2b08-c154-451f-aff4-a86c05de7d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460870952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.2460870952
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2300849767
Short name T142
Test name
Test status
Simulation time 26050205964 ps
CPU time 278.89 seconds
Started Feb 25 01:31:39 PM PST 24
Finished Feb 25 01:36:19 PM PST 24
Peak memory 206524 kb
Host smart-df763bb8-85eb-4dc6-9d38-e3d0682b6d78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300849767 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2300849767
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.169761286
Short name T119
Test name
Test status
Simulation time 582135971 ps
CPU time 0.75 seconds
Started Feb 25 01:31:45 PM PST 24
Finished Feb 25 01:31:48 PM PST 24
Peak memory 183388 kb
Host smart-74387d56-4928-465d-a760-9a693e18d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169761286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.169761286
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.1416320170
Short name T203
Test name
Test status
Simulation time 24121201172 ps
CPU time 34.67 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:32:28 PM PST 24
Peak memory 183296 kb
Host smart-ecadb8a4-ca2c-4d36-823b-2034c73d88d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416320170 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.1416320170
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.4175581893
Short name T74
Test name
Test status
Simulation time 388531568 ps
CPU time 1.06 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:31:54 PM PST 24
Peak memory 183268 kb
Host smart-293137f9-5ff5-42c0-b76b-fe386a5f0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175581893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.4175581893
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.75072424
Short name T13
Test name
Test status
Simulation time 143714954700 ps
CPU time 108.01 seconds
Started Feb 25 01:31:47 PM PST 24
Finished Feb 25 01:33:39 PM PST 24
Peak memory 193836 kb
Host smart-519b7884-dbf6-45df-a749-021861df38df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75072424 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all
.75072424
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.692129983
Short name T91
Test name
Test status
Simulation time 64099929051 ps
CPU time 567.35 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:41:18 PM PST 24
Peak memory 198328 kb
Host smart-644adbf0-f164-4a74-bac1-6f20c6e619a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692129983 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.692129983
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2933043577
Short name T238
Test name
Test status
Simulation time 536747196 ps
CPU time 1.36 seconds
Started Feb 25 01:31:50 PM PST 24
Finished Feb 25 01:31:55 PM PST 24
Peak memory 183276 kb
Host smart-71f660e6-5eb7-4308-9cba-0adbc72454b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933043577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2933043577
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.2299469815
Short name T166
Test name
Test status
Simulation time 34938517482 ps
CPU time 55.4 seconds
Started Feb 25 01:31:51 PM PST 24
Finished Feb 25 01:32:49 PM PST 24
Peak memory 183304 kb
Host smart-2f68acf4-95e0-41f0-a0fa-2d35373530ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299469815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.2299469815
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3543196079
Short name T204
Test name
Test status
Simulation time 500780529 ps
CPU time 0.69 seconds
Started Feb 25 01:31:44 PM PST 24
Finished Feb 25 01:31:45 PM PST 24
Peak memory 183288 kb
Host smart-684ddd5a-c7c1-4cb9-8d97-6ee77d692870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543196079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3543196079
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.869817387
Short name T102
Test name
Test status
Simulation time 111922029707 ps
CPU time 174.83 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:34:45 PM PST 24
Peak memory 193596 kb
Host smart-63282d1d-49a9-47da-bb19-a6d61e28baac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869817387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.869817387
Directory /workspace/9.aon_timer_stress_all/latest
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