Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.45 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv


Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 141 5 136 96.45


Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
bark_thold_cp 34 1 33 97.06 100 1 1 0
bite_thold_cp 34 1 33 97.06 100 1 1 0
pause_in_sleep_cp 2 1 1 50.00 100 1 1 2
prescale_cp 34 1 33 97.06 100 1 1 0
wdog_regwen_cp 2 0 2 100.00 100 1 1 2
wkup_cause_cp 1 0 1 100.00 100 1 1 0
wkup_thold_cp 34 1 33 97.06 100 1 1 0


Summary for Variable bark_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bark_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bark_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bark[0] 27798 1 T1 10 T3 10 T4 358
bark[1] 421 1 T15 79 T45 97 T47 17
bark[2] 899 1 T11 26 T52 54 T47 17
bark[3] 631 1 T36 16 T52 16 T114 46
bark[4] 686 1 T2 13 T115 17 T61 16
bark[5] 677 1 T26 25 T114 229 T92 236
bark[6] 368 1 T17 21 T58 41 T116 51
bark[7] 258 1 T117 32 T47 36 T58 16
bark[8] 396 1 T10 13 T17 63 T21 41
bark[9] 456 1 T11 22 T50 12 T118 12
bark[10] 967 1 T15 21 T17 232 T45 109
bark[11] 332 1 T52 16 T47 17 T119 17
bark[12] 391 1 T120 25 T92 17 T121 16
bark[13] 179 1 T34 12 T107 13 T47 16
bark[14] 696 1 T117 21 T115 16 T114 174
bark[15] 203 1 T45 36 T22 16 T30 12
bark[16] 655 1 T4 173 T16 16 T17 16
bark[17] 248 1 T11 16 T105 26 T115 16
bark[18] 892 1 T6 22 T22 25 T122 32
bark[19] 234 1 T16 16 T32 22 T123 23
bark[20] 468 1 T53 12 T46 16 T124 36
bark[21] 475 1 T11 16 T21 16 T125 6
bark[22] 492 1 T6 16 T11 16 T126 12
bark[23] 735 1 T45 21 T52 16 T90 22
bark[24] 424 1 T32 16 T114 22 T123 16
bark[25] 247 1 T104 12 T98 16 T127 26
bark[26] 590 1 T4 17 T17 16 T124 32
bark[27] 387 1 T54 16 T125 17 T98 16
bark[28] 455 1 T105 32 T90 166 T116 51
bark[29] 387 1 T4 21 T122 46 T61 30
bark[30] 126 1 T16 16 T128 17 T129 32
bark[31] 1018 1 T4 43 T21 26 T130 12
bark_0 3607 1 T1 4 T2 4 T3 4


Summary for Variable bite_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for bite_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
bite_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
bite[0] 27340 1 T1 9 T3 9 T4 351
bite[1] 420 1 T6 16 T26 16 T129 16
bite[2] 658 1 T6 22 T90 21 T123 16
bite[3] 76 1 T50 11 T118 11 T125 5
bite[4] 307 1 T45 36 T47 16 T123 16
bite[5] 731 1 T47 17 T125 67 T97 5
bite[6] 893 1 T46 5 T117 38 T114 173
bite[7] 892 1 T2 12 T28 11 T114 54
bite[8] 559 1 T15 78 T52 54 T122 16
bite[9] 471 1 T16 16 T22 16 T122 16
bite[10] 307 1 T10 12 T32 16 T131 11
bite[11] 183 1 T17 16 T52 16 T114 20
bite[12] 405 1 T47 17 T123 22 T58 41
bite[13] 474 1 T4 59 T53 11 T132 22
bite[14] 222 1 T104 11 T105 25 T123 23
bite[15] 320 1 T4 20 T11 38 T133 11
bite[16] 416 1 T26 25 T126 11 T115 16
bite[17] 916 1 T15 20 T21 57 T52 16
bite[18] 474 1 T22 25 T32 22 T90 22
bite[19] 260 1 T11 38 T36 16 T114 45
bite[20] 280 1 T11 16 T45 108 T52 16
bite[21] 392 1 T124 32 T47 16 T123 16
bite[22] 498 1 T47 36 T32 16 T114 22
bite[23] 187 1 T32 17 T61 16 T116 50
bite[24] 499 1 T17 62 T21 26 T124 97
bite[25] 746 1 T60 11 T97 147 T134 12
bite[26] 674 1 T4 172 T107 12 T115 17
bite[27] 215 1 T11 26 T16 32 T17 21
bite[28] 694 1 T45 96 T105 32 T130 11
bite[29] 636 1 T34 11 T124 36 T54 16
bite[30] 443 1 T11 16 T17 236 T45 21
bite[31] 1000 1 T17 16 T46 16 T47 16
bite_0 4210 1 T1 5 T2 5 T3 5


Summary for Variable pause_in_sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 46798 1 T1 14 T2 17 T3 14


Summary for Variable prescale_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for prescale_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
prescale_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
prescale[0] 1089 1 T4 15 T36 31 T105 25
prescale[1] 862 1 T4 16 T6 16 T117 27
prescale[2] 721 1 T6 31 T15 84 T51 8
prescale[3] 967 1 T4 2 T52 47 T47 37
prescale[4] 847 1 T15 15 T17 38 T36 15
prescale[5] 916 1 T4 8 T21 31 T52 20
prescale[6] 748 1 T4 2 T44 8 T45 31
prescale[7] 636 1 T6 87 T7 8 T15 2
prescale[8] 549 1 T122 18 T26 21 T115 15
prescale[9] 668 1 T4 76 T47 39 T123 15
prescale[10] 806 1 T14 8 T26 41 T123 76
prescale[11] 674 1 T6 2 T15 31 T21 30
prescale[12] 1274 1 T17 15 T45 31 T47 18
prescale[13] 471 1 T52 18 T122 21 T25 8
prescale[14] 814 1 T6 2 T11 68 T17 141
prescale[15] 899 1 T4 2 T15 37 T45 241
prescale[16] 694 1 T15 15 T16 50 T17 89
prescale[17] 683 1 T17 140 T21 15 T47 16
prescale[18] 667 1 T17 2 T45 16 T22 39
prescale[19] 913 1 T21 15 T36 2 T45 206
prescale[20] 812 1 T4 78 T6 8 T16 20
prescale[21] 453 1 T15 2 T16 15 T21 28
prescale[22] 721 1 T4 20 T15 31 T45 10
prescale[23] 460 1 T6 69 T9 8 T45 4
prescale[24] 656 1 T45 18 T26 15 T115 15
prescale[25] 639 1 T4 2 T15 2 T17 15
prescale[26] 929 1 T11 8 T12 8 T36 16
prescale[27] 816 1 T15 46 T17 30 T45 2
prescale[28] 354 1 T4 2 T11 15 T26 2
prescale[29] 458 1 T36 2 T46 9 T117 30
prescale[30] 655 1 T135 8 T124 15 T47 2
prescale[31] 793 1 T4 113 T46 2 T117 18
prescale_0 23154 1 T1 14 T2 17 T3 14


Summary for Variable wdog_regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wdog_regwen_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35238 1 T1 14 T2 6 T3 14
auto[1] 11560 1 T2 11 T4 199 T6 65


Summary for Variable wkup_cause_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for wkup_cause_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup_cause_cleared 46798 1 T1 14 T2 17 T3 14


Summary for Variable wkup_thold_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 34 1 33 97.06


User Defined Bins for wkup_thold_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBER
wkup_max 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
wkup[0] 27786 1 T1 11 T3 11 T4 367
wkup[1] 600 1 T6 16 T11 22 T15 16
wkup[2] 352 1 T26 21 T32 17 T123 16
wkup[3] 522 1 T6 16 T15 32 T21 26
wkup[4] 508 1 T17 16 T45 16 T22 16
wkup[5] 496 1 T11 32 T36 16 T122 13
wkup[6] 677 1 T4 42 T124 16 T47 70
wkup[7] 339 1 T6 22 T11 16 T16 16
wkup[8] 708 1 T4 16 T11 26 T17 16
wkup[9] 593 1 T11 22 T17 39 T47 16
wkup[10] 569 1 T105 16 T26 22 T30 13
wkup[11] 485 1 T17 32 T46 7 T47 23
wkup[12] 507 1 T4 28 T11 16 T15 16
wkup[13] 457 1 T45 23 T124 16 T32 22
wkup[14] 669 1 T4 16 T15 42 T17 16
wkup[15] 726 1 T17 16 T45 32 T124 22
wkup[16] 434 1 T4 55 T6 16 T21 16
wkup[17] 497 1 T6 17 T45 16 T52 16
wkup[18] 350 1 T4 32 T6 16 T47 21
wkup[19] 442 1 T15 16 T45 42 T124 21
wkup[20] 630 1 T6 27 T36 38 T45 64
wkup[21] 615 1 T4 16 T6 41 T10 14
wkup[22] 551 1 T4 17 T17 16 T22 26
wkup[23] 420 1 T4 16 T45 16 T48 16
wkup[24] 484 1 T4 17 T6 16 T45 36
wkup[25] 515 1 T6 16 T45 53 T48 16
wkup[26] 534 1 T6 16 T45 16 T52 16
wkup[27] 559 1 T2 14 T45 42 T26 16
wkup[28] 416 1 T16 16 T17 21 T118 13
wkup[29] 430 1 T17 16 T50 13 T22 25
wkup[30] 343 1 T34 13 T54 16 T61 17
wkup[31] 516 1 T17 28 T45 16 T105 16
wkup_0 3068 1 T1 3 T2 3 T3 3

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