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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.82 95.31 100.00 99.35 100.00 96.64


Total test records in report: 429
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T290 /workspace/coverage/default/44.aon_timer_stress_all.1014880987 Feb 28 04:51:09 PM PST 24 Feb 28 04:51:49 PM PST 24 380943895655 ps
T291 /workspace/coverage/default/27.aon_timer_prescaler.2851248664 Feb 28 04:50:56 PM PST 24 Feb 28 04:51:11 PM PST 24 38039324529 ps
T292 /workspace/coverage/default/23.aon_timer_prescaler.3497607780 Feb 28 04:50:51 PM PST 24 Feb 28 04:51:56 PM PST 24 40935826907 ps
T293 /workspace/coverage/default/15.aon_timer_stress_all.2057675040 Feb 28 04:50:47 PM PST 24 Feb 28 04:54:31 PM PST 24 135767384134 ps
T37 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1516312803 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:46 PM PST 24 665407925 ps
T294 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2339554444 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:30 PM PST 24 491682021 ps
T38 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1009630202 Feb 28 04:51:27 PM PST 24 Feb 28 04:51:28 PM PST 24 523577111 ps
T39 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1633229147 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:14 PM PST 24 1161662689 ps
T43 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.768393052 Feb 28 04:51:23 PM PST 24 Feb 28 04:51:28 PM PST 24 1706039525 ps
T40 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3308782984 Feb 28 04:51:44 PM PST 24 Feb 28 04:51:49 PM PST 24 4410140889 ps
T64 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.210705740 Feb 28 04:51:29 PM PST 24 Feb 28 04:51:31 PM PST 24 540451405 ps
T65 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2227848122 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:30 PM PST 24 757162242 ps
T295 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2510024185 Feb 28 04:51:43 PM PST 24 Feb 28 04:51:44 PM PST 24 440368466 ps
T41 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2588063772 Feb 28 04:51:38 PM PST 24 Feb 28 04:51:55 PM PST 24 8393168503 ps
T296 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1367414712 Feb 28 04:51:17 PM PST 24 Feb 28 04:51:18 PM PST 24 468495336 ps
T297 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2770658612 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:32 PM PST 24 497918588 ps
T298 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2139026758 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:49 PM PST 24 494630856 ps
T299 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4144972164 Feb 28 04:51:54 PM PST 24 Feb 28 04:51:55 PM PST 24 423366076 ps
T83 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4256729339 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:36 PM PST 24 419068503 ps
T42 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.264590108 Feb 28 04:51:10 PM PST 24 Feb 28 04:51:24 PM PST 24 8489528322 ps
T300 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.455006720 Feb 28 04:51:20 PM PST 24 Feb 28 04:51:21 PM PST 24 636234082 ps
T66 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2671901141 Feb 28 04:51:19 PM PST 24 Feb 28 04:51:21 PM PST 24 407773850 ps
T301 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2054865184 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:50 PM PST 24 322648137 ps
T109 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1540654707 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:43 PM PST 24 4910735055 ps
T302 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.198997386 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:51 PM PST 24 522529248 ps
T303 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.212702574 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:56 PM PST 24 422588895 ps
T304 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.589994146 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:36 PM PST 24 469895934 ps
T84 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1942390162 Feb 28 04:51:34 PM PST 24 Feb 28 04:51:41 PM PST 24 2358354164 ps
T305 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.679464528 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:47 PM PST 24 477741339 ps
T306 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.912962511 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:14 PM PST 24 414131062 ps
T307 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1964011151 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:51 PM PST 24 566815797 ps
T308 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3425941332 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:43 PM PST 24 4752112362 ps
T85 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2188492521 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:33 PM PST 24 2343092190 ps
T309 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2274827221 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:51 PM PST 24 421373144 ps
T310 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2613630194 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:50 PM PST 24 469271269 ps
T67 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4250929991 Feb 28 04:51:40 PM PST 24 Feb 28 04:51:41 PM PST 24 424283953 ps
T108 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1409623468 Feb 28 04:51:27 PM PST 24 Feb 28 04:51:36 PM PST 24 8280756897 ps
T311 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3170267308 Feb 28 04:51:25 PM PST 24 Feb 28 04:51:28 PM PST 24 629867450 ps
T312 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1658800771 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:36 PM PST 24 4502455888 ps
T313 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2290014831 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:44 PM PST 24 7867313438 ps
T314 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2729925169 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:46 PM PST 24 458693930 ps
T315 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2374121041 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:48 PM PST 24 316330837 ps
T110 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.967286991 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:51 PM PST 24 8278129049 ps
T316 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1092665120 Feb 28 04:51:32 PM PST 24 Feb 28 04:51:34 PM PST 24 534052998 ps
T317 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2177534905 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:35 PM PST 24 359923856 ps
T318 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.903300717 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:50 PM PST 24 333912619 ps
T319 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1145876198 Feb 28 04:51:30 PM PST 24 Feb 28 04:51:32 PM PST 24 365690929 ps
T320 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2867222850 Feb 28 04:51:39 PM PST 24 Feb 28 04:51:41 PM PST 24 476091996 ps
T86 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4039150187 Feb 28 04:51:44 PM PST 24 Feb 28 04:51:48 PM PST 24 1488380838 ps
T321 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.205042494 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:14 PM PST 24 540169721 ps
T87 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1134071068 Feb 28 04:51:43 PM PST 24 Feb 28 04:51:44 PM PST 24 530956610 ps
T322 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.669208277 Feb 28 04:51:32 PM PST 24 Feb 28 04:51:34 PM PST 24 699313520 ps
T323 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2048078015 Feb 28 04:51:19 PM PST 24 Feb 28 04:51:22 PM PST 24 517108204 ps
T324 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2114174208 Feb 28 04:51:51 PM PST 24 Feb 28 04:51:52 PM PST 24 309410910 ps
T325 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3241525600 Feb 28 04:51:18 PM PST 24 Feb 28 04:51:19 PM PST 24 579245492 ps
T111 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2912627386 Feb 28 04:51:30 PM PST 24 Feb 28 04:51:38 PM PST 24 4536373880 ps
T88 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1143617719 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:47 PM PST 24 1051106195 ps
T89 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1209157947 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:43 PM PST 24 979423868 ps
T326 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2742610037 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:51 PM PST 24 1406493300 ps
T327 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3492923026 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:56 PM PST 24 420143718 ps
T328 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3853441216 Feb 28 04:51:44 PM PST 24 Feb 28 04:51:48 PM PST 24 8270769948 ps
T329 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1426396617 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:49 PM PST 24 348678478 ps
T330 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3142022528 Feb 28 04:51:38 PM PST 24 Feb 28 04:51:41 PM PST 24 893986373 ps
T331 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1957231703 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:35 PM PST 24 332802150 ps
T332 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1608527018 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:30 PM PST 24 578890062 ps
T333 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1229938028 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:35 PM PST 24 874835300 ps
T334 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1142376880 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:38 PM PST 24 4315168576 ps
T335 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1810902280 Feb 28 04:51:40 PM PST 24 Feb 28 04:51:41 PM PST 24 391787315 ps
T336 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1267958577 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:33 PM PST 24 439995944 ps
T337 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1904787757 Feb 28 04:51:27 PM PST 24 Feb 28 04:51:32 PM PST 24 1832171271 ps
T338 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3212966604 Feb 28 04:51:30 PM PST 24 Feb 28 04:51:31 PM PST 24 441766361 ps
T339 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2303437197 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:33 PM PST 24 402058786 ps
T340 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1471790649 Feb 28 04:51:42 PM PST 24 Feb 28 04:51:44 PM PST 24 355888266 ps
T341 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1299180677 Feb 28 04:51:42 PM PST 24 Feb 28 04:51:43 PM PST 24 417317702 ps
T112 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.538935448 Feb 28 04:51:30 PM PST 24 Feb 28 04:51:35 PM PST 24 8761709463 ps
T342 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1268904702 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:56 PM PST 24 442953026 ps
T343 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.866451146 Feb 28 04:51:20 PM PST 24 Feb 28 04:51:21 PM PST 24 406494898 ps
T344 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2915176421 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:51 PM PST 24 460922400 ps
T345 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.776146266 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:38 PM PST 24 563108410 ps
T346 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4242312565 Feb 28 04:51:44 PM PST 24 Feb 28 04:51:46 PM PST 24 386472943 ps
T347 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3347606279 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:28 PM PST 24 852388749 ps
T348 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2301589634 Feb 28 04:51:15 PM PST 24 Feb 28 04:51:18 PM PST 24 8926113587 ps
T349 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3969580013 Feb 28 04:51:21 PM PST 24 Feb 28 04:51:22 PM PST 24 490792962 ps
T350 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3080244417 Feb 28 04:51:40 PM PST 24 Feb 28 04:51:45 PM PST 24 4463316010 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1918510067 Feb 28 04:51:20 PM PST 24 Feb 28 04:51:22 PM PST 24 657089546 ps
T351 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1922152589 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:27 PM PST 24 420859658 ps
T352 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1401545945 Feb 28 04:51:51 PM PST 24 Feb 28 04:51:53 PM PST 24 298938339 ps
T69 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1768024902 Feb 28 04:51:23 PM PST 24 Feb 28 04:51:25 PM PST 24 2499660202 ps
T70 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.194927028 Feb 28 04:51:39 PM PST 24 Feb 28 04:51:41 PM PST 24 552353673 ps
T353 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1033928164 Feb 28 04:52:01 PM PST 24 Feb 28 04:52:02 PM PST 24 314322604 ps
T354 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2029987345 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:49 PM PST 24 616795449 ps
T71 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2793483069 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:47 PM PST 24 537055710 ps
T355 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1150583952 Feb 28 04:51:32 PM PST 24 Feb 28 04:51:37 PM PST 24 1965923598 ps
T356 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2481249224 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:51 PM PST 24 8176260078 ps
T357 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1963630189 Feb 28 04:51:48 PM PST 24 Feb 28 04:51:50 PM PST 24 276566200 ps
T358 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4017368387 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:29 PM PST 24 359418063 ps
T359 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1189452583 Feb 28 04:51:21 PM PST 24 Feb 28 04:51:22 PM PST 24 457451322 ps
T360 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1415220697 Feb 28 04:51:36 PM PST 24 Feb 28 04:51:37 PM PST 24 398739943 ps
T72 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2998477896 Feb 28 04:51:48 PM PST 24 Feb 28 04:51:49 PM PST 24 452566322 ps
T73 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3809691405 Feb 28 04:51:13 PM PST 24 Feb 28 04:51:17 PM PST 24 4622276067 ps
T361 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1720159370 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:30 PM PST 24 802800595 ps
T362 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3480292262 Feb 28 04:51:18 PM PST 24 Feb 28 04:51:21 PM PST 24 1969152209 ps
T363 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.898474409 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:26 PM PST 24 435782409 ps
T364 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3193942423 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:43 PM PST 24 422271781 ps
T365 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3669346815 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:30 PM PST 24 714097386 ps
T366 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2579762231 Feb 28 04:51:19 PM PST 24 Feb 28 04:51:21 PM PST 24 472995974 ps
T367 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.408979409 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:48 PM PST 24 1071049109 ps
T368 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3153871432 Feb 28 04:51:37 PM PST 24 Feb 28 04:51:38 PM PST 24 300845475 ps
T369 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1003952142 Feb 28 04:51:40 PM PST 24 Feb 28 04:51:41 PM PST 24 583909399 ps
T370 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3535727517 Feb 28 04:51:24 PM PST 24 Feb 28 04:51:25 PM PST 24 675039371 ps
T371 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1930608931 Feb 28 04:51:34 PM PST 24 Feb 28 04:51:36 PM PST 24 1919218253 ps
T74 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2114826933 Feb 28 04:51:30 PM PST 24 Feb 28 04:51:31 PM PST 24 290711119 ps
T372 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1163296324 Feb 28 04:51:38 PM PST 24 Feb 28 04:51:41 PM PST 24 514719321 ps
T75 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3296404506 Feb 28 04:51:37 PM PST 24 Feb 28 04:51:39 PM PST 24 426243409 ps
T373 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.759365274 Feb 28 04:51:38 PM PST 24 Feb 28 04:51:40 PM PST 24 489817320 ps
T374 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4028697353 Feb 28 04:51:14 PM PST 24 Feb 28 04:51:16 PM PST 24 780091332 ps
T375 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4196197504 Feb 28 04:51:15 PM PST 24 Feb 28 04:51:16 PM PST 24 364481760 ps
T376 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3400248664 Feb 28 04:51:51 PM PST 24 Feb 28 04:51:53 PM PST 24 465685688 ps
T377 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2095470955 Feb 28 04:51:31 PM PST 24 Feb 28 04:51:32 PM PST 24 361081542 ps
T378 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1210192129 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:34 PM PST 24 410606779 ps
T379 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3221578299 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:55 PM PST 24 418897080 ps
T380 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4141469620 Feb 28 04:51:20 PM PST 24 Feb 28 04:51:21 PM PST 24 552850752 ps
T381 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1518647931 Feb 28 04:51:18 PM PST 24 Feb 28 04:51:20 PM PST 24 527655963 ps
T382 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.372159771 Feb 28 04:51:18 PM PST 24 Feb 28 04:51:21 PM PST 24 1480336963 ps
T383 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2501756159 Feb 28 04:51:54 PM PST 24 Feb 28 04:51:57 PM PST 24 418964308 ps
T384 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1266508758 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:43 PM PST 24 483574973 ps
T385 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2941822269 Feb 28 04:51:27 PM PST 24 Feb 28 04:51:34 PM PST 24 6154842191 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1329104156 Feb 28 04:51:23 PM PST 24 Feb 28 04:51:25 PM PST 24 806687672 ps
T387 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.387725540 Feb 28 04:51:23 PM PST 24 Feb 28 04:51:23 PM PST 24 511469719 ps
T76 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1104547688 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:13 PM PST 24 657705109 ps
T388 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1847348408 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:27 PM PST 24 511925531 ps
T389 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2789611908 Feb 28 04:51:29 PM PST 24 Feb 28 04:51:31 PM PST 24 995959514 ps
T390 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2872418028 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:37 PM PST 24 562602506 ps
T391 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.392260641 Feb 28 04:51:46 PM PST 24 Feb 28 04:51:47 PM PST 24 520267033 ps
T77 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3273567387 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:38 PM PST 24 7527351840 ps
T392 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1554355800 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:50 PM PST 24 472197526 ps
T393 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1779198672 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:27 PM PST 24 395190959 ps
T394 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4254873592 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:13 PM PST 24 365130928 ps
T395 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1478222960 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:29 PM PST 24 320824988 ps
T396 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3929065860 Feb 28 04:51:34 PM PST 24 Feb 28 04:51:37 PM PST 24 499741694 ps
T397 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.545983087 Feb 28 04:51:46 PM PST 24 Feb 28 04:51:49 PM PST 24 392397228 ps
T398 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3431025262 Feb 28 04:51:38 PM PST 24 Feb 28 04:51:41 PM PST 24 507517720 ps
T399 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1464604024 Feb 28 04:51:55 PM PST 24 Feb 28 04:51:57 PM PST 24 373783157 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4149091701 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:27 PM PST 24 336245152 ps
T401 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.375306085 Feb 28 04:51:49 PM PST 24 Feb 28 04:51:51 PM PST 24 402194301 ps
T113 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1978080729 Feb 28 04:51:49 PM PST 24 Feb 28 04:52:04 PM PST 24 8394888745 ps
T402 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.571429634 Feb 28 04:51:21 PM PST 24 Feb 28 04:51:25 PM PST 24 8844247687 ps
T403 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1072533291 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:56 PM PST 24 391552826 ps
T404 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.325770468 Feb 28 04:51:51 PM PST 24 Feb 28 04:51:53 PM PST 24 406050313 ps
T405 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3633047637 Feb 28 04:51:55 PM PST 24 Feb 28 04:51:58 PM PST 24 445895356 ps
T406 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3916155661 Feb 28 04:51:39 PM PST 24 Feb 28 04:51:41 PM PST 24 416300565 ps
T407 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3338310822 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:49 PM PST 24 378666762 ps
T408 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1923185242 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:52 PM PST 24 492757945 ps
T78 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.61795257 Feb 28 04:51:14 PM PST 24 Feb 28 04:51:16 PM PST 24 371133184 ps
T409 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3965047409 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:51 PM PST 24 395750323 ps
T410 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2667544901 Feb 28 04:51:15 PM PST 24 Feb 28 04:51:16 PM PST 24 276637077 ps
T411 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.18798706 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:38 PM PST 24 8099587101 ps
T81 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.465062052 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:29 PM PST 24 529230082 ps
T79 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3667069916 Feb 28 04:51:24 PM PST 24 Feb 28 04:51:29 PM PST 24 5325116990 ps
T412 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3884922648 Feb 28 04:51:35 PM PST 24 Feb 28 04:51:35 PM PST 24 418801466 ps
T413 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2235476455 Feb 28 04:51:26 PM PST 24 Feb 28 04:51:27 PM PST 24 946688902 ps
T414 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.559825075 Feb 28 04:51:33 PM PST 24 Feb 28 04:51:35 PM PST 24 384019236 ps
T415 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2250821672 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:14 PM PST 24 548328812 ps
T416 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2926187998 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:42 PM PST 24 1760176230 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1578118570 Feb 28 04:51:28 PM PST 24 Feb 28 04:51:32 PM PST 24 3821477121 ps
T418 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3773484140 Feb 28 04:51:41 PM PST 24 Feb 28 04:51:42 PM PST 24 503628674 ps
T419 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2765053590 Feb 28 04:51:46 PM PST 24 Feb 28 04:51:47 PM PST 24 2555924562 ps
T420 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3273091475 Feb 28 04:51:45 PM PST 24 Feb 28 04:51:47 PM PST 24 2563312749 ps
T80 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1960194916 Feb 28 04:51:46 PM PST 24 Feb 28 04:51:48 PM PST 24 386771423 ps
T421 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2703825950 Feb 28 04:51:47 PM PST 24 Feb 28 04:51:48 PM PST 24 314235280 ps
T82 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1436852808 Feb 28 04:51:36 PM PST 24 Feb 28 04:51:37 PM PST 24 450515558 ps
T422 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1908711167 Feb 28 04:51:25 PM PST 24 Feb 28 04:51:26 PM PST 24 638465805 ps
T423 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.146988374 Feb 28 04:51:53 PM PST 24 Feb 28 04:51:56 PM PST 24 511654425 ps
T424 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2682280480 Feb 28 04:51:39 PM PST 24 Feb 28 04:51:41 PM PST 24 1293623697 ps
T425 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1721508434 Feb 28 04:51:50 PM PST 24 Feb 28 04:51:52 PM PST 24 1137879329 ps
T426 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1279073218 Feb 28 04:51:34 PM PST 24 Feb 28 04:51:35 PM PST 24 416903591 ps
T427 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3656309932 Feb 28 04:51:12 PM PST 24 Feb 28 04:51:14 PM PST 24 348327788 ps
T428 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2458713453 Feb 28 04:51:15 PM PST 24 Feb 28 04:51:16 PM PST 24 475088604 ps
T429 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4082363747 Feb 28 04:51:52 PM PST 24 Feb 28 04:51:54 PM PST 24 372504413 ps

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.416704144
Short name T6
Test name
Test status
Simulation time 39741458779 ps
CPU time 378.31 seconds
Started Feb 28 04:50:32 PM PST 24
Finished Feb 28 04:56:51 PM PST 24
Peak memory 197960 kb
Host smart-4a9d279c-4296-4189-bb29-ecf8400009c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416704144 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.416704144
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3852325838
Short name T47
Test name
Test status
Simulation time 217930795400 ps
CPU time 426.57 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:57:50 PM PST 24
Peak memory 198080 kb
Host smart-9df356a8-6e48-4f0a-9d61-6bf860e983c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852325838 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3852325838
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3308782984
Short name T40
Test name
Test status
Simulation time 4410140889 ps
CPU time 4.07 seconds
Started Feb 28 04:51:44 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 196832 kb
Host smart-b6a9d506-2d01-4686-b684-3b26933e0240
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308782984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3308782984
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2835171570
Short name T97
Test name
Test status
Simulation time 1528617847213 ps
CPU time 590.25 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 05:00:59 PM PST 24
Peak memory 198532 kb
Host smart-93cbb345-c592-4da7-a9f0-374ebe1e4570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835171570 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2835171570
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.680575150
Short name T92
Test name
Test status
Simulation time 89189470410 ps
CPU time 308.06 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:56:00 PM PST 24
Peak memory 198032 kb
Host smart-d0873ebd-7377-407d-9141-c35a5c1bee18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680575150 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.680575150
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.1780381500
Short name T17
Test name
Test status
Simulation time 379171701121 ps
CPU time 360.01 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:56:54 PM PST 24
Peak memory 198020 kb
Host smart-c5732f7f-631f-44b1-b629-3bd5c09abbcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780381500 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.1780381500
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1795357446
Short name T208
Test name
Test status
Simulation time 35497851532 ps
CPU time 217.01 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:54:38 PM PST 24
Peak memory 197908 kb
Host smart-0da7a154-de58-44cd-a25f-0c9e494598d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795357446 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1795357446
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2646091214
Short name T21
Test name
Test status
Simulation time 225509430389 ps
CPU time 184.2 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:54:02 PM PST 24
Peak memory 193380 kb
Host smart-85436adb-40fd-48c2-a01b-b69d37ea173e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646091214 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2646091214
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2671901141
Short name T66
Test name
Test status
Simulation time 407773850 ps
CPU time 0.96 seconds
Started Feb 28 04:51:19 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183440 kb
Host smart-f45f5de4-b6f7-477b-a3ba-04eaefa1ad95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671901141 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2671901141
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.867914441
Short name T18
Test name
Test status
Simulation time 8941621013 ps
CPU time 2.01 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 215236 kb
Host smart-24302877-71b8-4bdf-bb8d-e6e4a4430e3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867914441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.867914441
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.548084575
Short name T114
Test name
Test status
Simulation time 62673420598 ps
CPU time 332.14 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:56:35 PM PST 24
Peak memory 197984 kb
Host smart-9c209f05-c273-480d-9ed9-6607bef7be88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548084575 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.548084575
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.1753881780
Short name T11
Test name
Test status
Simulation time 84911045076 ps
CPU time 124.81 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:52:51 PM PST 24
Peak memory 183152 kb
Host smart-828a075e-7d6b-41f4-b6e5-d02f9298659b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753881780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_
all.1753881780
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.3856235156
Short name T101
Test name
Test status
Simulation time 64699039211 ps
CPU time 437.81 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:58:26 PM PST 24
Peak memory 197536 kb
Host smart-29cc85bb-84d2-4818-bc89-8e9a7f01393b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856235156 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.3856235156
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1978080729
Short name T113
Test name
Test status
Simulation time 8394888745 ps
CPU time 14.32 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:52:04 PM PST 24
Peak memory 197224 kb
Host smart-730be473-69b2-4c3b-ae47-0646d3c699ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978080729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1978080729
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2637326100
Short name T247
Test name
Test status
Simulation time 70671440935 ps
CPU time 30.57 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:51:23 PM PST 24
Peak memory 183140 kb
Host smart-c88965b2-2523-4b32-a512-cefd48db3226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637326100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2637326100
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.295233446
Short name T125
Test name
Test status
Simulation time 143380250576 ps
CPU time 314 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:56:15 PM PST 24
Peak memory 198144 kb
Host smart-b9fb7401-19cf-4c69-9444-8e20a7db6e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295233446 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.295233446
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.3809691405
Short name T73
Test name
Test status
Simulation time 4622276067 ps
CPU time 3.76 seconds
Started Feb 28 04:51:13 PM PST 24
Finished Feb 28 04:51:17 PM PST 24
Peak memory 191864 kb
Host smart-ff82ec44-9d0a-4891-996d-11fbb4164e66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809691405 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.3809691405
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.1633229147
Short name T39
Test name
Test status
Simulation time 1161662689 ps
CPU time 1.09 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 192912 kb
Host smart-a49e8fe1-043e-47b1-89ff-0fceb3421ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633229147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.1633229147
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.3638639051
Short name T227
Test name
Test status
Simulation time 66176139961 ps
CPU time 718.34 seconds
Started Feb 28 04:50:30 PM PST 24
Finished Feb 28 05:02:29 PM PST 24
Peak memory 199440 kb
Host smart-d44ee14b-5988-4d52-ba29-21fecc76d99e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638639051 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.3638639051
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2202598787
Short name T218
Test name
Test status
Simulation time 164008980749 ps
CPU time 618.18 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 05:01:02 PM PST 24
Peak memory 198936 kb
Host smart-797f419f-d5a0-41c6-a773-0925e1ce9b2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202598787 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2202598787
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1104547688
Short name T76
Test name
Test status
Simulation time 657705109 ps
CPU time 0.99 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 193292 kb
Host smart-3a3b5a1c-488c-4367-9671-a1e5f783d845
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104547688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1104547688
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.4028697353
Short name T374
Test name
Test status
Simulation time 780091332 ps
CPU time 1.06 seconds
Started Feb 28 04:51:14 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183384 kb
Host smart-a5aea736-6808-4c5f-9322-2068068bd039
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028697353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.4028697353
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2458713453
Short name T428
Test name
Test status
Simulation time 475088604 ps
CPU time 1.24 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 195356 kb
Host smart-2c1ced41-7d38-4bc6-bc15-6555ca370b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458713453 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2458713453
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.61795257
Short name T78
Test name
Test status
Simulation time 371133184 ps
CPU time 0.6 seconds
Started Feb 28 04:51:14 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183432 kb
Host smart-8dc9a497-72fc-41c1-ad51-38e554e389c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61795257 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.61795257
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3656309932
Short name T427
Test name
Test status
Simulation time 348327788 ps
CPU time 1.15 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 183176 kb
Host smart-02ab1453-952b-41b3-bb78-e80d7cbf2f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656309932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3656309932
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.2667544901
Short name T410
Test name
Test status
Simulation time 276637077 ps
CPU time 0.74 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183332 kb
Host smart-ce2b957c-ba17-44fa-ac64-9154c054dd9d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667544901 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.2667544901
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.4254873592
Short name T394
Test name
Test status
Simulation time 365130928 ps
CPU time 0.63 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 183116 kb
Host smart-4c5be2bb-bcd4-4866-83a6-aac0744f3762
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254873592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.4254873592
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.205042494
Short name T321
Test name
Test status
Simulation time 540169721 ps
CPU time 1.42 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 198168 kb
Host smart-08da5dfb-e5fc-49b1-89d1-8c4d0186c53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205042494 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.205042494
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.264590108
Short name T42
Test name
Test status
Simulation time 8489528322 ps
CPU time 14.37 seconds
Started Feb 28 04:51:10 PM PST 24
Finished Feb 28 04:51:24 PM PST 24
Peak memory 197156 kb
Host smart-3ff58f57-5b62-4253-a898-a171319c0f90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264590108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_
intg_err.264590108
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.1918510067
Short name T68
Test name
Test status
Simulation time 657089546 ps
CPU time 1.62 seconds
Started Feb 28 04:51:20 PM PST 24
Finished Feb 28 04:51:22 PM PST 24
Peak memory 183348 kb
Host smart-3f67fd04-8999-4532-adb8-48f4b161e4a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918510067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.1918510067
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.3273567387
Short name T77
Test name
Test status
Simulation time 7527351840 ps
CPU time 9.09 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 191844 kb
Host smart-f232bf72-f2f9-4313-a7c4-feaac13324c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273567387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.3273567387
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.372159771
Short name T382
Test name
Test status
Simulation time 1480336963 ps
CPU time 2.86 seconds
Started Feb 28 04:51:18 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183416 kb
Host smart-02b2f2ca-3789-470e-af93-5d56b0fb189b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372159771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.372159771
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.3241525600
Short name T325
Test name
Test status
Simulation time 579245492 ps
CPU time 1.05 seconds
Started Feb 28 04:51:18 PM PST 24
Finished Feb 28 04:51:19 PM PST 24
Peak memory 195480 kb
Host smart-8c0d1bd2-81e9-4f86-bef1-b0c522bb9ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241525600 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.3241525600
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1518647931
Short name T381
Test name
Test status
Simulation time 527655963 ps
CPU time 1.25 seconds
Started Feb 28 04:51:18 PM PST 24
Finished Feb 28 04:51:20 PM PST 24
Peak memory 183388 kb
Host smart-3fbdbbe5-0032-407e-b09b-e12990b44f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518647931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1518647931
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.4196197504
Short name T375
Test name
Test status
Simulation time 364481760 ps
CPU time 0.64 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183164 kb
Host smart-fe9d5cfa-6834-46c1-8f0a-3c430919281b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196197504 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.4196197504
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.1367414712
Short name T296
Test name
Test status
Simulation time 468495336 ps
CPU time 0.83 seconds
Started Feb 28 04:51:17 PM PST 24
Finished Feb 28 04:51:18 PM PST 24
Peak memory 183124 kb
Host smart-dc759c47-9339-4227-8b5a-49588cda2e1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367414712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.1367414712
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.912962511
Short name T306
Test name
Test status
Simulation time 414131062 ps
CPU time 1.07 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 183356 kb
Host smart-418e79ce-57b9-47dc-a3c9-748cc9fd2aa3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912962511 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wa
lk.912962511
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.3480292262
Short name T362
Test name
Test status
Simulation time 1969152209 ps
CPU time 3.31 seconds
Started Feb 28 04:51:18 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 191652 kb
Host smart-dc2cbeb9-9509-4f8b-be97-ac72faa363f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480292262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.3480292262
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.2250821672
Short name T415
Test name
Test status
Simulation time 548328812 ps
CPU time 1.51 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 198208 kb
Host smart-59b05d09-a72f-46fd-9fbf-0b0a11d14028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250821672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.2250821672
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2301589634
Short name T348
Test name
Test status
Simulation time 8926113587 ps
CPU time 2.6 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:18 PM PST 24
Peak memory 197200 kb
Host smart-0cd69a5b-b6d7-46be-a00e-121c8922d74e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301589634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2301589634
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.1516312803
Short name T37
Test name
Test status
Simulation time 665407925 ps
CPU time 0.98 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:46 PM PST 24
Peak memory 195252 kb
Host smart-c1a72449-d0d1-4b4c-83fd-8f4c758cdf85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516312803 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.1516312803
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.1436852808
Short name T82
Test name
Test status
Simulation time 450515558 ps
CPU time 0.93 seconds
Started Feb 28 04:51:36 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 183488 kb
Host smart-13833ef1-3628-4b35-ae7f-9b292468220b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436852808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.1436852808
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3193942423
Short name T364
Test name
Test status
Simulation time 422271781 ps
CPU time 1.11 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 183156 kb
Host smart-a50f5d1f-32a4-48a4-beac-0a22cf984914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193942423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3193942423
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1143617719
Short name T88
Test name
Test status
Simulation time 1051106195 ps
CPU time 1.31 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 192928 kb
Host smart-ea8953bd-d03f-4322-9c46-2d088570ef7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143617719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1143617719
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.2177534905
Short name T317
Test name
Test status
Simulation time 359923856 ps
CPU time 1.15 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 198008 kb
Host smart-a9b65647-e13c-411f-b43b-a9bf10178df3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177534905 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.2177534905
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1142376880
Short name T334
Test name
Test status
Simulation time 4315168576 ps
CPU time 2.48 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 196812 kb
Host smart-eaaa1975-a3cd-4786-9e2b-21a5a7ddfe33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142376880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1142376880
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.589994146
Short name T304
Test name
Test status
Simulation time 469895934 ps
CPU time 1.38 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:36 PM PST 24
Peak memory 196344 kb
Host smart-df7d6a44-26b0-4c42-bdee-ca87a1b12dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589994146 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.589994146
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1810902280
Short name T335
Test name
Test status
Simulation time 391787315 ps
CPU time 0.84 seconds
Started Feb 28 04:51:40 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 183404 kb
Host smart-1c5ccbc0-5ca9-451f-97bc-fbcfa70e25da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810902280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1810902280
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.3884922648
Short name T412
Test name
Test status
Simulation time 418801466 ps
CPU time 0.56 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 183168 kb
Host smart-eb81102d-d1ee-456c-b619-ca1c84201966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884922648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.3884922648
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1229938028
Short name T333
Test name
Test status
Simulation time 874835300 ps
CPU time 1.12 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 193888 kb
Host smart-a31ec399-752f-4298-a213-0f39b88850bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229938028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1229938028
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.2872418028
Short name T390
Test name
Test status
Simulation time 562602506 ps
CPU time 1.53 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 198376 kb
Host smart-0348495d-9907-4f16-b0e4-61d531064677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872418028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.2872418028
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.3425941332
Short name T308
Test name
Test status
Simulation time 4752112362 ps
CPU time 7.88 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 197052 kb
Host smart-5f14c80c-da05-4201-8d52-12b1c48bd1d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425941332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.3425941332
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.3431025262
Short name T398
Test name
Test status
Simulation time 507517720 ps
CPU time 1.46 seconds
Started Feb 28 04:51:38 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 195472 kb
Host smart-f6ef5a51-bd5f-4164-afee-ac39374384bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431025262 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.3431025262
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.4250929991
Short name T67
Test name
Test status
Simulation time 424283953 ps
CPU time 0.76 seconds
Started Feb 28 04:51:40 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 183368 kb
Host smart-5a0d2408-442b-4753-9a5f-c816cbbde0a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250929991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.4250929991
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.3153871432
Short name T368
Test name
Test status
Simulation time 300845475 ps
CPU time 0.65 seconds
Started Feb 28 04:51:37 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 183136 kb
Host smart-bab3de35-5108-4204-8b36-bbf3dbb65e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153871432 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.3153871432
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.2926187998
Short name T416
Test name
Test status
Simulation time 1760176230 ps
CPU time 1.26 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:42 PM PST 24
Peak memory 194732 kb
Host smart-3a9a1dd4-24b8-4f58-a026-dd65cdc48baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926187998 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.2926187998
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.776146266
Short name T345
Test name
Test status
Simulation time 563108410 ps
CPU time 1.81 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 198232 kb
Host smart-2c98bd51-8256-444c-80c3-80261d7d7579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776146266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.776146266
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.2588063772
Short name T41
Test name
Test status
Simulation time 8393168503 ps
CPU time 15.4 seconds
Started Feb 28 04:51:38 PM PST 24
Finished Feb 28 04:51:55 PM PST 24
Peak memory 197344 kb
Host smart-a2b0cce6-bc35-4aaa-abdf-174622d34f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588063772 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.2588063772
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1266508758
Short name T384
Test name
Test status
Simulation time 483574973 ps
CPU time 1.11 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 198084 kb
Host smart-31af07ec-0faf-41dc-a780-4019269292fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266508758 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1266508758
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1415220697
Short name T360
Test name
Test status
Simulation time 398739943 ps
CPU time 1.17 seconds
Started Feb 28 04:51:36 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 183428 kb
Host smart-602c3335-f1ea-431a-a090-6eb08a52f63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415220697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1415220697
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.3773484140
Short name T418
Test name
Test status
Simulation time 503628674 ps
CPU time 0.71 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:42 PM PST 24
Peak memory 183156 kb
Host smart-9de4b2dc-1639-4d83-9bd5-64a0a6b19f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773484140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.3773484140
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.3273091475
Short name T420
Test name
Test status
Simulation time 2563312749 ps
CPU time 1.66 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 191668 kb
Host smart-c4de1ed4-abd5-4d59-b02f-3eccf0fecd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273091475 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.3273091475
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1163296324
Short name T372
Test name
Test status
Simulation time 514719321 ps
CPU time 2.01 seconds
Started Feb 28 04:51:38 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 198236 kb
Host smart-51da35d8-6b19-4501-805d-3286d28747c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163296324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1163296324
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1540654707
Short name T109
Test name
Test status
Simulation time 4910735055 ps
CPU time 8.39 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 195500 kb
Host smart-84969cb4-bed4-4329-997c-87188a667ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540654707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1540654707
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.1003952142
Short name T369
Test name
Test status
Simulation time 583909399 ps
CPU time 1.01 seconds
Started Feb 28 04:51:40 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 196476 kb
Host smart-c9aaaf6b-4fde-4583-8a7f-0a0924330488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003952142 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.1003952142
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.194927028
Short name T70
Test name
Test status
Simulation time 552353673 ps
CPU time 0.76 seconds
Started Feb 28 04:51:39 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 183452 kb
Host smart-06272243-10f7-4f6d-a3ac-f8c706c9c40a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194927028 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.194927028
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.759365274
Short name T373
Test name
Test status
Simulation time 489817320 ps
CPU time 1.19 seconds
Started Feb 28 04:51:38 PM PST 24
Finished Feb 28 04:51:40 PM PST 24
Peak memory 183136 kb
Host smart-ee470a6b-9133-4ad8-ba86-d8d07432f4b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759365274 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.759365274
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.1209157947
Short name T89
Test name
Test status
Simulation time 979423868 ps
CPU time 1.08 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 192428 kb
Host smart-577de7dc-1bd1-46ed-9cc1-8f6f17549ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209157947 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.1209157947
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.408979409
Short name T367
Test name
Test status
Simulation time 1071049109 ps
CPU time 2.4 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 198272 kb
Host smart-43c198c8-5249-4d27-9a69-665b46e7a031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408979409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.408979409
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.3080244417
Short name T350
Test name
Test status
Simulation time 4463316010 ps
CPU time 4.74 seconds
Started Feb 28 04:51:40 PM PST 24
Finished Feb 28 04:51:45 PM PST 24
Peak memory 196948 kb
Host smart-837327d6-74b6-4879-9ca2-d37dc4cfa182
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080244417 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.3080244417
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2867222850
Short name T320
Test name
Test status
Simulation time 476091996 ps
CPU time 0.92 seconds
Started Feb 28 04:51:39 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 194952 kb
Host smart-b7e325d0-9d25-4f4e-99f7-f4192f93e0d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867222850 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2867222850
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.3296404506
Short name T75
Test name
Test status
Simulation time 426243409 ps
CPU time 0.64 seconds
Started Feb 28 04:51:37 PM PST 24
Finished Feb 28 04:51:39 PM PST 24
Peak memory 183412 kb
Host smart-f0c96a52-92cd-46c7-aa36-f3660f17f59c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296404506 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.3296404506
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3916155661
Short name T406
Test name
Test status
Simulation time 416300565 ps
CPU time 0.8 seconds
Started Feb 28 04:51:39 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 183172 kb
Host smart-85593a90-3bbf-4d2c-94b8-33261c342b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916155661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3916155661
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2682280480
Short name T424
Test name
Test status
Simulation time 1293623697 ps
CPU time 0.85 seconds
Started Feb 28 04:51:39 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 192996 kb
Host smart-e5c3256b-0f35-454a-97f7-5433ac42c73b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682280480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2682280480
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.3142022528
Short name T330
Test name
Test status
Simulation time 893986373 ps
CPU time 1.82 seconds
Started Feb 28 04:51:38 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 198304 kb
Host smart-71e47a77-6788-4be8-aeab-b828e0733e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142022528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.3142022528
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.967286991
Short name T110
Test name
Test status
Simulation time 8278129049 ps
CPU time 9.45 seconds
Started Feb 28 04:51:41 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 197300 kb
Host smart-541c7ac0-c3b5-4a96-9346-e26af3fb6078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967286991 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl
_intg_err.967286991
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.1471790649
Short name T340
Test name
Test status
Simulation time 355888266 ps
CPU time 1.18 seconds
Started Feb 28 04:51:42 PM PST 24
Finished Feb 28 04:51:44 PM PST 24
Peak memory 196556 kb
Host smart-7c9c3beb-9175-470d-98c9-b944d8de81ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471790649 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.1471790649
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1134071068
Short name T87
Test name
Test status
Simulation time 530956610 ps
CPU time 0.76 seconds
Started Feb 28 04:51:43 PM PST 24
Finished Feb 28 04:51:44 PM PST 24
Peak memory 183420 kb
Host smart-18b2229e-6f9a-4c64-9232-cc44beb8d1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134071068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1134071068
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.2729925169
Short name T314
Test name
Test status
Simulation time 458693930 ps
CPU time 0.91 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:46 PM PST 24
Peak memory 183396 kb
Host smart-37f4ac08-de77-431e-96d6-07c9b14f6c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729925169 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.2729925169
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.2742610037
Short name T326
Test name
Test status
Simulation time 1406493300 ps
CPU time 0.84 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 192924 kb
Host smart-37b4f603-5a22-4fb8-880d-9c3b35ff4546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742610037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.2742610037
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.545983087
Short name T397
Test name
Test status
Simulation time 392397228 ps
CPU time 2.1 seconds
Started Feb 28 04:51:46 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 198208 kb
Host smart-d2823510-eaa5-49e1-b802-0195f5b4c6a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545983087 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.545983087
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2481249224
Short name T356
Test name
Test status
Simulation time 8176260078 ps
CPU time 3.92 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 197076 kb
Host smart-94c4cdf0-a514-4ea6-a4b9-1827821cd532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481249224 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2481249224
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.4242312565
Short name T346
Test name
Test status
Simulation time 386472943 ps
CPU time 0.91 seconds
Started Feb 28 04:51:44 PM PST 24
Finished Feb 28 04:51:46 PM PST 24
Peak memory 194636 kb
Host smart-ba403195-6225-4efe-a64f-1a7639d35dc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242312565 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.4242312565
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.2793483069
Short name T71
Test name
Test status
Simulation time 537055710 ps
CPU time 0.76 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 183448 kb
Host smart-da5af702-a5a8-4852-a2d5-8ba553bf3190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793483069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.2793483069
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.1299180677
Short name T341
Test name
Test status
Simulation time 417317702 ps
CPU time 0.85 seconds
Started Feb 28 04:51:42 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 183180 kb
Host smart-16dfe214-1287-44ee-ac82-51915f0d257f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299180677 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.1299180677
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.2765053590
Short name T419
Test name
Test status
Simulation time 2555924562 ps
CPU time 1.2 seconds
Started Feb 28 04:51:46 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 194992 kb
Host smart-f6212b55-6a38-40ca-87c1-b49bdfbef408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765053590 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.ao
n_timer_same_csr_outstanding.2765053590
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.679464528
Short name T305
Test name
Test status
Simulation time 477741339 ps
CPU time 1.05 seconds
Started Feb 28 04:51:45 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 197892 kb
Host smart-7b282e7a-b9e6-4c17-9848-5e66339932d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679464528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.679464528
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.1964011151
Short name T307
Test name
Test status
Simulation time 566815797 ps
CPU time 1.41 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 195132 kb
Host smart-0fb03668-e3c9-46a6-af45-6960a4659540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964011151 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.1964011151
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.1960194916
Short name T80
Test name
Test status
Simulation time 386771423 ps
CPU time 1.1 seconds
Started Feb 28 04:51:46 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 183432 kb
Host smart-7526ed5d-4a08-49d8-9c1c-445a9a20d0ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960194916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.1960194916
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2139026758
Short name T298
Test name
Test status
Simulation time 494630856 ps
CPU time 1.3 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 183136 kb
Host smart-e2016d75-10ca-4c10-969b-aa43c5d59e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139026758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2139026758
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.4039150187
Short name T86
Test name
Test status
Simulation time 1488380838 ps
CPU time 4.52 seconds
Started Feb 28 04:51:44 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 194900 kb
Host smart-309d948c-6614-4a8a-81b0-58bb91c8e594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039150187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.4039150187
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2510024185
Short name T295
Test name
Test status
Simulation time 440368466 ps
CPU time 1.58 seconds
Started Feb 28 04:51:43 PM PST 24
Finished Feb 28 04:51:44 PM PST 24
Peak memory 198204 kb
Host smart-311db495-83ca-4df1-996e-deeabd47c45b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510024185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2510024185
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3853441216
Short name T328
Test name
Test status
Simulation time 8270769948 ps
CPU time 3.61 seconds
Started Feb 28 04:51:44 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 197288 kb
Host smart-120cbeb1-913f-49e9-ab73-97d3725c0dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853441216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3853441216
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.212702574
Short name T303
Test name
Test status
Simulation time 422588895 ps
CPU time 1.16 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 194420 kb
Host smart-fe043714-3566-4303-8908-ad4e292af2ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212702574 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.212702574
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.2998477896
Short name T72
Test name
Test status
Simulation time 452566322 ps
CPU time 1.22 seconds
Started Feb 28 04:51:48 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 183440 kb
Host smart-db07162c-fbd0-4446-87e6-25e1002dbba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998477896 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.2998477896
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2915176421
Short name T344
Test name
Test status
Simulation time 460922400 ps
CPU time 0.87 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 183184 kb
Host smart-cba8437b-9028-4042-9ed2-fd14b574bced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915176421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2915176421
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.1721508434
Short name T425
Test name
Test status
Simulation time 1137879329 ps
CPU time 1.45 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:52 PM PST 24
Peak memory 192460 kb
Host smart-7f7c72ef-ff29-42d4-b6e5-885adea20922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721508434 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.1721508434
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.2029987345
Short name T354
Test name
Test status
Simulation time 616795449 ps
CPU time 2.08 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 198228 kb
Host smart-490b4efa-bf79-43a8-8ee8-d9254c6b222a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029987345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.2029987345
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.455006720
Short name T300
Test name
Test status
Simulation time 636234082 ps
CPU time 0.75 seconds
Started Feb 28 04:51:20 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 192604 kb
Host smart-12cd76db-63f9-488f-a5aa-40194908cc84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455006720 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_al
iasing.455006720
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.3667069916
Short name T79
Test name
Test status
Simulation time 5325116990 ps
CPU time 5.56 seconds
Started Feb 28 04:51:24 PM PST 24
Finished Feb 28 04:51:29 PM PST 24
Peak memory 183776 kb
Host smart-4ba2892a-c8b0-4072-9476-6f0daeca934c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667069916 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.3667069916
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2227848122
Short name T65
Test name
Test status
Simulation time 757162242 ps
CPU time 1.67 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 183352 kb
Host smart-87ab5793-2226-4473-8d4f-54e4fc9a278e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227848122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2227848122
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.3969580013
Short name T349
Test name
Test status
Simulation time 490792962 ps
CPU time 0.81 seconds
Started Feb 28 04:51:21 PM PST 24
Finished Feb 28 04:51:22 PM PST 24
Peak memory 194616 kb
Host smart-27aedcb9-2ca4-4833-b81a-34cd3d73defe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969580013 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.3969580013
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.2579762231
Short name T366
Test name
Test status
Simulation time 472995974 ps
CPU time 0.63 seconds
Started Feb 28 04:51:19 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183308 kb
Host smart-5b9cf474-2dc8-4c69-a876-ae3533d9fc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579762231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.2579762231
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.1847348408
Short name T388
Test name
Test status
Simulation time 511925531 ps
CPU time 0.66 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 183092 kb
Host smart-f4fc232c-1c16-4861-97a7-c9dc2d1974ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847348408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.1847348408
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.4017368387
Short name T358
Test name
Test status
Simulation time 359418063 ps
CPU time 0.64 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:29 PM PST 24
Peak memory 183152 kb
Host smart-4342aa08-2429-48b2-b13e-2632059441e9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017368387 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.4017368387
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.768393052
Short name T43
Test name
Test status
Simulation time 1706039525 ps
CPU time 4.97 seconds
Started Feb 28 04:51:23 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 194704 kb
Host smart-f3a75840-6888-45de-afca-5cde3692ce0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768393052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.768393052
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2048078015
Short name T323
Test name
Test status
Simulation time 517108204 ps
CPU time 1.71 seconds
Started Feb 28 04:51:19 PM PST 24
Finished Feb 28 04:51:22 PM PST 24
Peak memory 198252 kb
Host smart-fe347ce7-98e0-49a0-a88a-37a271bc21eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048078015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2048078015
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1409623468
Short name T108
Test name
Test status
Simulation time 8280756897 ps
CPU time 7.76 seconds
Started Feb 28 04:51:27 PM PST 24
Finished Feb 28 04:51:36 PM PST 24
Peak memory 197268 kb
Host smart-94105ded-2157-41aa-af20-2f9c833f1d20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409623468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1409623468
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2054865184
Short name T301
Test name
Test status
Simulation time 322648137 ps
CPU time 0.81 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:50 PM PST 24
Peak memory 183152 kb
Host smart-1ede94a2-2b76-4b6b-978b-49504719b3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054865184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2054865184
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.375306085
Short name T401
Test name
Test status
Simulation time 402194301 ps
CPU time 1.22 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 183112 kb
Host smart-497954d2-394a-4d37-81dc-1f2377e61b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375306085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.375306085
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.3492923026
Short name T327
Test name
Test status
Simulation time 420143718 ps
CPU time 0.67 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 183316 kb
Host smart-d4f94c42-53ce-4dda-9f63-15f4460ae7f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492923026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.3492923026
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.1923185242
Short name T408
Test name
Test status
Simulation time 492757945 ps
CPU time 1 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:52 PM PST 24
Peak memory 183232 kb
Host smart-de0f9254-39ef-4e85-9de1-d0b80d1d54e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923185242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.1923185242
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.1963630189
Short name T357
Test name
Test status
Simulation time 276566200 ps
CPU time 0.8 seconds
Started Feb 28 04:51:48 PM PST 24
Finished Feb 28 04:51:50 PM PST 24
Peak memory 183104 kb
Host smart-95a4dc0f-b147-49ca-a9db-8bfcbaa5068a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963630189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.1963630189
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2501756159
Short name T383
Test name
Test status
Simulation time 418964308 ps
CPU time 1.21 seconds
Started Feb 28 04:51:54 PM PST 24
Finished Feb 28 04:51:57 PM PST 24
Peak memory 183152 kb
Host smart-a2f80eb2-1e1f-42ac-b609-aa27eceaed75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501756159 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2501756159
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.3338310822
Short name T407
Test name
Test status
Simulation time 378666762 ps
CPU time 1.11 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 183176 kb
Host smart-b28b9a1e-e0bd-4195-86ed-4f5e44a7cba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338310822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.3338310822
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.2703825950
Short name T421
Test name
Test status
Simulation time 314235280 ps
CPU time 0.72 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 183168 kb
Host smart-5fb1ec68-0185-40ac-a16b-e8e98a3ed3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703825950 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.2703825950
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1401545945
Short name T352
Test name
Test status
Simulation time 298938339 ps
CPU time 0.79 seconds
Started Feb 28 04:51:51 PM PST 24
Finished Feb 28 04:51:53 PM PST 24
Peak memory 183152 kb
Host smart-794cbb7f-ff5e-491d-931b-49a405cf964c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401545945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1401545945
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2613630194
Short name T310
Test name
Test status
Simulation time 469271269 ps
CPU time 0.73 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:50 PM PST 24
Peak memory 183364 kb
Host smart-3c7de421-88a3-469a-9659-ff84e149ebcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613630194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2613630194
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3535727517
Short name T370
Test name
Test status
Simulation time 675039371 ps
CPU time 0.83 seconds
Started Feb 28 04:51:24 PM PST 24
Finished Feb 28 04:51:25 PM PST 24
Peak memory 193500 kb
Host smart-4460ba07-047d-4e2a-97d5-54811d109944
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535727517 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3535727517
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.2941822269
Short name T385
Test name
Test status
Simulation time 6154842191 ps
CPU time 6.86 seconds
Started Feb 28 04:51:27 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 195112 kb
Host smart-37551f6a-8fba-427f-9da7-e5f75186e270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941822269 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.2941822269
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.3347606279
Short name T347
Test name
Test status
Simulation time 852388749 ps
CPU time 1.84 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 183324 kb
Host smart-4f3a5e6a-3aee-42c8-be65-eab5d568506f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347606279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_h
w_reset.3347606279
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1009630202
Short name T38
Test name
Test status
Simulation time 523577111 ps
CPU time 1.13 seconds
Started Feb 28 04:51:27 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 195712 kb
Host smart-28809454-128e-4825-b8a8-565359f5a543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009630202 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1009630202
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.465062052
Short name T81
Test name
Test status
Simulation time 529230082 ps
CPU time 0.76 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:29 PM PST 24
Peak memory 183404 kb
Host smart-865d03c0-5939-42f6-8e76-19815eb932e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465062052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.465062052
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.4141469620
Short name T380
Test name
Test status
Simulation time 552850752 ps
CPU time 0.6 seconds
Started Feb 28 04:51:20 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183384 kb
Host smart-8d09b810-0036-48b5-bae3-8d81c74c82f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141469620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.4141469620
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.866451146
Short name T343
Test name
Test status
Simulation time 406494898 ps
CPU time 1.15 seconds
Started Feb 28 04:51:20 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183132 kb
Host smart-53f90edc-2cf7-4daa-9295-9bea6b77fef1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866451146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_ti
mer_mem_partial_access.866451146
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.1189452583
Short name T359
Test name
Test status
Simulation time 457451322 ps
CPU time 1.18 seconds
Started Feb 28 04:51:21 PM PST 24
Finished Feb 28 04:51:22 PM PST 24
Peak memory 183436 kb
Host smart-03543325-8af7-42eb-b3e5-b921a6f4aeba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189452583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.1189452583
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.1904787757
Short name T337
Test name
Test status
Simulation time 1832171271 ps
CPU time 4.78 seconds
Started Feb 28 04:51:27 PM PST 24
Finished Feb 28 04:51:32 PM PST 24
Peak memory 192324 kb
Host smart-3aa9b4d9-07ea-433a-8aa0-8e6d2c60058b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904787757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.1904787757
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1329104156
Short name T386
Test name
Test status
Simulation time 806687672 ps
CPU time 2.61 seconds
Started Feb 28 04:51:23 PM PST 24
Finished Feb 28 04:51:25 PM PST 24
Peak memory 198248 kb
Host smart-6d1edeaf-70c5-4928-bd4b-aa1be6b616c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329104156 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1329104156
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.571429634
Short name T402
Test name
Test status
Simulation time 8844247687 ps
CPU time 3.03 seconds
Started Feb 28 04:51:21 PM PST 24
Finished Feb 28 04:51:25 PM PST 24
Peak memory 197272 kb
Host smart-05dde11a-cc2a-4b66-b023-703cb20c1aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571429634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.571429634
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1554355800
Short name T392
Test name
Test status
Simulation time 472197526 ps
CPU time 0.68 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:50 PM PST 24
Peak memory 183112 kb
Host smart-6f88569b-5c53-460d-9cda-aa190638db46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554355800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1554355800
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.198997386
Short name T302
Test name
Test status
Simulation time 522529248 ps
CPU time 0.87 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 183324 kb
Host smart-0d58f945-0cc9-4e02-a9fc-32f7989902a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198997386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.198997386
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.1426396617
Short name T329
Test name
Test status
Simulation time 348678478 ps
CPU time 1.03 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 183140 kb
Host smart-dcbd25b7-c4ae-4234-9f18-44b716563734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426396617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.1426396617
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.903300717
Short name T318
Test name
Test status
Simulation time 333912619 ps
CPU time 0.67 seconds
Started Feb 28 04:51:49 PM PST 24
Finished Feb 28 04:51:50 PM PST 24
Peak memory 183384 kb
Host smart-3bb5b108-f689-4286-a181-0f78df684982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903300717 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.903300717
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2374121041
Short name T315
Test name
Test status
Simulation time 316330837 ps
CPU time 1.01 seconds
Started Feb 28 04:51:47 PM PST 24
Finished Feb 28 04:51:48 PM PST 24
Peak memory 183368 kb
Host smart-7889dc1a-0c98-45c1-aae9-a0e6161a9745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374121041 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2374121041
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.2274827221
Short name T309
Test name
Test status
Simulation time 421373144 ps
CPU time 0.64 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 183124 kb
Host smart-aca12443-1b03-43fc-96a1-acf415890a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274827221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.2274827221
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.392260641
Short name T391
Test name
Test status
Simulation time 520267033 ps
CPU time 0.75 seconds
Started Feb 28 04:51:46 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 183116 kb
Host smart-9aacf1e8-1e13-4f56-acc4-9bf29ad15dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392260641 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.392260641
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.3633047637
Short name T405
Test name
Test status
Simulation time 445895356 ps
CPU time 1.12 seconds
Started Feb 28 04:51:55 PM PST 24
Finished Feb 28 04:51:58 PM PST 24
Peak memory 183316 kb
Host smart-449e95ef-1c2b-4618-8296-54a923aa21ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633047637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.3633047637
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.146988374
Short name T423
Test name
Test status
Simulation time 511654425 ps
CPU time 1.36 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 183152 kb
Host smart-cf07850a-078c-4050-afcd-ebe4aefe6362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146988374 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.146988374
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3965047409
Short name T409
Test name
Test status
Simulation time 395750323 ps
CPU time 0.64 seconds
Started Feb 28 04:51:50 PM PST 24
Finished Feb 28 04:51:51 PM PST 24
Peak memory 183136 kb
Host smart-69c7dacd-2f54-408f-97d3-5e57070db7b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965047409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3965047409
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1908711167
Short name T422
Test name
Test status
Simulation time 638465805 ps
CPU time 0.85 seconds
Started Feb 28 04:51:25 PM PST 24
Finished Feb 28 04:51:26 PM PST 24
Peak memory 183352 kb
Host smart-64d85660-8c82-4ea0-ac29-a653ed860070
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908711167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1908711167
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1768024902
Short name T69
Test name
Test status
Simulation time 2499660202 ps
CPU time 1.44 seconds
Started Feb 28 04:51:23 PM PST 24
Finished Feb 28 04:51:25 PM PST 24
Peak memory 191868 kb
Host smart-32e53ce7-14f6-4499-80fc-d7ff74e5e3f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768024902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1768024902
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1720159370
Short name T361
Test name
Test status
Simulation time 802800595 ps
CPU time 1.68 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 183412 kb
Host smart-dac71382-9d7d-4d6b-87d0-c607f10bff71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720159370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1720159370
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1922152589
Short name T351
Test name
Test status
Simulation time 420859658 ps
CPU time 0.98 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 194352 kb
Host smart-474173a3-67a3-4fb5-b2c8-248691f7ef22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922152589 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1922152589
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.1779198672
Short name T393
Test name
Test status
Simulation time 395190959 ps
CPU time 0.91 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 183476 kb
Host smart-47d78350-2ed6-416b-8991-f672a00a074e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779198672 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.1779198672
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.387725540
Short name T387
Test name
Test status
Simulation time 511469719 ps
CPU time 0.64 seconds
Started Feb 28 04:51:23 PM PST 24
Finished Feb 28 04:51:23 PM PST 24
Peak memory 183108 kb
Host smart-69bd8ac4-f44c-41fe-b6c0-426c61d9bc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387725540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.387725540
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.4149091701
Short name T400
Test name
Test status
Simulation time 336245152 ps
CPU time 0.66 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 183044 kb
Host smart-c1774e47-9fa5-4f7d-a5cc-c059e05c85b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149091701 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.4149091701
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.898474409
Short name T363
Test name
Test status
Simulation time 435782409 ps
CPU time 0.72 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:26 PM PST 24
Peak memory 183356 kb
Host smart-8d56bb9c-04d4-426d-9c52-edc6622cfcdd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898474409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_wa
lk.898474409
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.2235476455
Short name T413
Test name
Test status
Simulation time 946688902 ps
CPU time 1.16 seconds
Started Feb 28 04:51:26 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 192876 kb
Host smart-782d50fd-040d-4d01-852e-cda7ce307dff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235476455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.2235476455
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.3669346815
Short name T365
Test name
Test status
Simulation time 714097386 ps
CPU time 2.04 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 198296 kb
Host smart-5d263228-e05e-4673-aea9-ca2530f0921e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669346815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.3669346815
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.1578118570
Short name T417
Test name
Test status
Simulation time 3821477121 ps
CPU time 3.83 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:32 PM PST 24
Peak memory 197012 kb
Host smart-e29cd15f-2815-456a-bd79-6800dcb680cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578118570 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.1578118570
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1464604024
Short name T399
Test name
Test status
Simulation time 373783157 ps
CPU time 0.6 seconds
Started Feb 28 04:51:55 PM PST 24
Finished Feb 28 04:51:57 PM PST 24
Peak memory 183324 kb
Host smart-8ba53b12-681c-437f-9ed4-2545beda1742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464604024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1464604024
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.3400248664
Short name T376
Test name
Test status
Simulation time 465685688 ps
CPU time 1.18 seconds
Started Feb 28 04:51:51 PM PST 24
Finished Feb 28 04:51:53 PM PST 24
Peak memory 183160 kb
Host smart-0fe91914-de89-4f9e-9c85-933b04864488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400248664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.3400248664
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.1072533291
Short name T403
Test name
Test status
Simulation time 391552826 ps
CPU time 1.17 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 183184 kb
Host smart-521840c7-e39c-4cf5-81d2-00bed5d69a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072533291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.1072533291
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.4082363747
Short name T429
Test name
Test status
Simulation time 372504413 ps
CPU time 0.69 seconds
Started Feb 28 04:51:52 PM PST 24
Finished Feb 28 04:51:54 PM PST 24
Peak memory 183164 kb
Host smart-0eccbf1d-35dd-4dd5-86da-746c2cafdab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082363747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.4082363747
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.1268904702
Short name T342
Test name
Test status
Simulation time 442953026 ps
CPU time 1.21 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 183184 kb
Host smart-a710d353-22e8-431c-8de5-d93cbd963d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268904702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.1268904702
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.325770468
Short name T404
Test name
Test status
Simulation time 406050313 ps
CPU time 0.87 seconds
Started Feb 28 04:51:51 PM PST 24
Finished Feb 28 04:51:53 PM PST 24
Peak memory 183140 kb
Host smart-f1e60ab5-7dee-4d66-9d40-ed9e02a55642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325770468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.325770468
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1033928164
Short name T353
Test name
Test status
Simulation time 314322604 ps
CPU time 0.63 seconds
Started Feb 28 04:52:01 PM PST 24
Finished Feb 28 04:52:02 PM PST 24
Peak memory 183336 kb
Host smart-d2c9f32a-a7cd-4526-8587-54c698a3606a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033928164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1033928164
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3221578299
Short name T379
Test name
Test status
Simulation time 418897080 ps
CPU time 1.14 seconds
Started Feb 28 04:51:53 PM PST 24
Finished Feb 28 04:51:55 PM PST 24
Peak memory 183184 kb
Host smart-9e3bdc7e-dadc-4f82-b2bd-85ce1bb3368a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221578299 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3221578299
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.2114174208
Short name T324
Test name
Test status
Simulation time 309410910 ps
CPU time 0.63 seconds
Started Feb 28 04:51:51 PM PST 24
Finished Feb 28 04:51:52 PM PST 24
Peak memory 183184 kb
Host smart-cc743b92-9d29-498d-99ea-f40cc2a306ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114174208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.2114174208
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.4144972164
Short name T299
Test name
Test status
Simulation time 423366076 ps
CPU time 0.86 seconds
Started Feb 28 04:51:54 PM PST 24
Finished Feb 28 04:51:55 PM PST 24
Peak memory 183168 kb
Host smart-2158f31a-28c8-475f-9962-c4eb68116946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144972164 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.4144972164
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.1608527018
Short name T332
Test name
Test status
Simulation time 578890062 ps
CPU time 1.06 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 194660 kb
Host smart-90292dc2-9631-4d7b-9158-f60ee2064787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608527018 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.1608527018
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.210705740
Short name T64
Test name
Test status
Simulation time 540451405 ps
CPU time 1.47 seconds
Started Feb 28 04:51:29 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 183556 kb
Host smart-b7402179-a98d-4dee-9442-3103b8ea339c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210705740 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.210705740
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.559825075
Short name T414
Test name
Test status
Simulation time 384019236 ps
CPU time 1.16 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 183184 kb
Host smart-e15b5897-b5ce-4cf3-a926-e743a322c0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559825075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.559825075
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2789611908
Short name T389
Test name
Test status
Simulation time 995959514 ps
CPU time 1 seconds
Started Feb 28 04:51:29 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 193804 kb
Host smart-5a2d58b5-2df3-4c68-8d99-71255269e1cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789611908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2789611908
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.3170267308
Short name T311
Test name
Test status
Simulation time 629867450 ps
CPU time 2.15 seconds
Started Feb 28 04:51:25 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 198140 kb
Host smart-9355afbb-c389-483e-89a6-b0109bdb806b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170267308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.3170267308
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1658800771
Short name T312
Test name
Test status
Simulation time 4502455888 ps
CPU time 4.42 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:36 PM PST 24
Peak memory 196816 kb
Host smart-98360515-8d04-41c4-a376-288365d93551
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658800771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1658800771
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.3212966604
Short name T338
Test name
Test status
Simulation time 441766361 ps
CPU time 1.25 seconds
Started Feb 28 04:51:30 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 194792 kb
Host smart-70c26549-10f5-4533-95f1-f98f550a27e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212966604 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.3212966604
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.1478222960
Short name T395
Test name
Test status
Simulation time 320824988 ps
CPU time 0.78 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:29 PM PST 24
Peak memory 183452 kb
Host smart-e7bf194b-195b-4e47-a82d-af8cc1037c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478222960 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.1478222960
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.1267958577
Short name T336
Test name
Test status
Simulation time 439995944 ps
CPU time 1.21 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:33 PM PST 24
Peak memory 183312 kb
Host smart-2e94bf80-55c3-430f-8115-287ed3fd4138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267958577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.1267958577
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.2188492521
Short name T85
Test name
Test status
Simulation time 2343092190 ps
CPU time 1.59 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:33 PM PST 24
Peak memory 194016 kb
Host smart-d517f4e8-eba5-495a-8fa4-9831bbc19521
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188492521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon
_timer_same_csr_outstanding.2188492521
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.1145876198
Short name T319
Test name
Test status
Simulation time 365690929 ps
CPU time 1.79 seconds
Started Feb 28 04:51:30 PM PST 24
Finished Feb 28 04:51:32 PM PST 24
Peak memory 198260 kb
Host smart-d1b35bcb-99ad-4617-9872-395f7638857b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145876198 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.1145876198
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2912627386
Short name T111
Test name
Test status
Simulation time 4536373880 ps
CPU time 7.22 seconds
Started Feb 28 04:51:30 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 197036 kb
Host smart-c1941f70-c55b-4106-9f54-cfecacf2e2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912627386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2912627386
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2770658612
Short name T297
Test name
Test status
Simulation time 497918588 ps
CPU time 0.94 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:32 PM PST 24
Peak memory 196856 kb
Host smart-8e8ff20c-f677-43e3-8d47-ed2101b431bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770658612 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2770658612
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.1210192129
Short name T378
Test name
Test status
Simulation time 410606779 ps
CPU time 0.71 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 183420 kb
Host smart-b54b242d-17fe-438e-8efc-ad67a13057f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210192129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.1210192129
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1957231703
Short name T331
Test name
Test status
Simulation time 332802150 ps
CPU time 1.04 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 183092 kb
Host smart-c46482e2-6214-441c-84fa-fb743f39eeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957231703 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1957231703
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1942390162
Short name T84
Test name
Test status
Simulation time 2358354164 ps
CPU time 6.62 seconds
Started Feb 28 04:51:34 PM PST 24
Finished Feb 28 04:51:41 PM PST 24
Peak memory 194968 kb
Host smart-fff7b065-7934-4089-9037-36f5d330bbfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942390162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1942390162
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.2339554444
Short name T294
Test name
Test status
Simulation time 491682021 ps
CPU time 1.34 seconds
Started Feb 28 04:51:28 PM PST 24
Finished Feb 28 04:51:30 PM PST 24
Peak memory 198036 kb
Host smart-1b987c78-a140-4efa-99b3-5c5cce0fb910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339554444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.2339554444
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.538935448
Short name T112
Test name
Test status
Simulation time 8761709463 ps
CPU time 4.55 seconds
Started Feb 28 04:51:30 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 197304 kb
Host smart-6c7ea8ea-2974-4ea3-85fb-43a5b8cbc3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538935448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_
intg_err.538935448
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1279073218
Short name T426
Test name
Test status
Simulation time 416903591 ps
CPU time 0.74 seconds
Started Feb 28 04:51:34 PM PST 24
Finished Feb 28 04:51:35 PM PST 24
Peak memory 195224 kb
Host smart-a20da0bd-75dc-4484-905f-aba3742de622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279073218 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1279073218
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2114826933
Short name T74
Test name
Test status
Simulation time 290711119 ps
CPU time 0.78 seconds
Started Feb 28 04:51:30 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 183392 kb
Host smart-6bcbc206-b503-4e57-b975-87f9f9d40cda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114826933 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2114826933
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.2303437197
Short name T339
Test name
Test status
Simulation time 402058786 ps
CPU time 1.05 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:33 PM PST 24
Peak memory 183180 kb
Host smart-90bb3fe3-0533-4721-9428-a25c2ca2d625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303437197 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.2303437197
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1930608931
Short name T371
Test name
Test status
Simulation time 1919218253 ps
CPU time 1.24 seconds
Started Feb 28 04:51:34 PM PST 24
Finished Feb 28 04:51:36 PM PST 24
Peak memory 192392 kb
Host smart-c11ab073-1ee8-4bb8-a5c8-6cbd6c6844c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930608931 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1930608931
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3929065860
Short name T396
Test name
Test status
Simulation time 499741694 ps
CPU time 2.12 seconds
Started Feb 28 04:51:34 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 198260 kb
Host smart-bcea6479-58b0-48f9-9184-33fc95290f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929065860 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3929065860
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.18798706
Short name T411
Test name
Test status
Simulation time 8099587101 ps
CPU time 4.32 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:38 PM PST 24
Peak memory 197156 kb
Host smart-30021a74-2d07-4c3f-8650-65940a9d620c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_i
ntg_err.18798706
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.1092665120
Short name T316
Test name
Test status
Simulation time 534052998 ps
CPU time 1.34 seconds
Started Feb 28 04:51:32 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 194432 kb
Host smart-29415828-4453-41df-90ed-04c382d80033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092665120 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.1092665120
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.4256729339
Short name T83
Test name
Test status
Simulation time 419068503 ps
CPU time 1.41 seconds
Started Feb 28 04:51:35 PM PST 24
Finished Feb 28 04:51:36 PM PST 24
Peak memory 183552 kb
Host smart-9132813e-4610-4547-bd72-b9d7cbed62ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256729339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.4256729339
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2095470955
Short name T377
Test name
Test status
Simulation time 361081542 ps
CPU time 1.03 seconds
Started Feb 28 04:51:31 PM PST 24
Finished Feb 28 04:51:32 PM PST 24
Peak memory 183168 kb
Host smart-a259aa5e-2866-48a9-9a72-ad229ef25ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095470955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2095470955
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.1150583952
Short name T355
Test name
Test status
Simulation time 1965923598 ps
CPU time 4.06 seconds
Started Feb 28 04:51:32 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 194932 kb
Host smart-ff23b3f9-eb37-4abe-bffb-402d6272d4d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150583952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.1150583952
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.669208277
Short name T322
Test name
Test status
Simulation time 699313520 ps
CPU time 1.85 seconds
Started Feb 28 04:51:32 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 198276 kb
Host smart-4fdda8a4-6e2e-4092-ab26-48a6e8048306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669208277 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.669208277
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2290014831
Short name T313
Test name
Test status
Simulation time 7867313438 ps
CPU time 10.79 seconds
Started Feb 28 04:51:33 PM PST 24
Finished Feb 28 04:51:44 PM PST 24
Peak memory 197424 kb
Host smart-db495147-860b-45aa-a961-8295894556bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290014831 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2290014831
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.1258011759
Short name T28
Test name
Test status
Simulation time 648176862 ps
CPU time 0.72 seconds
Started Feb 28 04:50:30 PM PST 24
Finished Feb 28 04:50:31 PM PST 24
Peak memory 183008 kb
Host smart-3185c441-94ff-414a-bfe9-abfeb3a04204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258011759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.1258011759
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.2765626711
Short name T27
Test name
Test status
Simulation time 32437145402 ps
CPU time 12.08 seconds
Started Feb 28 04:50:32 PM PST 24
Finished Feb 28 04:50:45 PM PST 24
Peak memory 183036 kb
Host smart-36cafb1c-27ce-46a2-937c-d1b4fd15186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765626711 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.2765626711
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3377961956
Short name T280
Test name
Test status
Simulation time 527496050 ps
CPU time 1.1 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:39 PM PST 24
Peak memory 183032 kb
Host smart-a316b71e-49c8-482e-8c04-d845cd89732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377961956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3377961956
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.934737606
Short name T271
Test name
Test status
Simulation time 6173093057 ps
CPU time 3.39 seconds
Started Feb 28 04:50:31 PM PST 24
Finished Feb 28 04:50:35 PM PST 24
Peak memory 183068 kb
Host smart-54eb2f87-a884-4d8f-acc4-f0d391712921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934737606 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_al
l.934737606
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1725699331
Short name T152
Test name
Test status
Simulation time 357680445 ps
CPU time 1.18 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 182964 kb
Host smart-81a2c35d-0589-4441-8a92-a8b8a7e6cfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725699331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1725699331
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.4238218597
Short name T206
Test name
Test status
Simulation time 8513938273 ps
CPU time 9.04 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:44 PM PST 24
Peak memory 183072 kb
Host smart-22899c99-93a1-4e9e-a6cb-647bc99f302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238218597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.4238218597
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.399110580
Short name T20
Test name
Test status
Simulation time 7901973050 ps
CPU time 6.63 seconds
Started Feb 28 04:50:33 PM PST 24
Finished Feb 28 04:50:40 PM PST 24
Peak memory 215208 kb
Host smart-f9e17542-dce3-4b4a-870b-edb67c961f3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399110580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.399110580
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.2333216868
Short name T235
Test name
Test status
Simulation time 500851766 ps
CPU time 1.18 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 182900 kb
Host smart-eca1a2a6-964c-4b77-8c97-484a9c9493ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333216868 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.2333216868
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.1827510213
Short name T22
Test name
Test status
Simulation time 159037932200 ps
CPU time 133.95 seconds
Started Feb 28 04:50:32 PM PST 24
Finished Feb 28 04:52:46 PM PST 24
Peak memory 193136 kb
Host smart-a0251da8-caee-4514-bdfd-039d763d1962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827510213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.1827510213
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.4226954497
Short name T167
Test name
Test status
Simulation time 424617725 ps
CPU time 1.23 seconds
Started Feb 28 04:50:44 PM PST 24
Finished Feb 28 04:50:45 PM PST 24
Peak memory 183008 kb
Host smart-bed75cf8-584f-4b08-9f64-708bd74a5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226954497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.4226954497
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1200344325
Short name T164
Test name
Test status
Simulation time 3097271869 ps
CPU time 5.48 seconds
Started Feb 28 04:50:44 PM PST 24
Finished Feb 28 04:50:50 PM PST 24
Peak memory 183064 kb
Host smart-be105711-e6a1-416b-a520-79672c8d5984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200344325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1200344325
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4088529027
Short name T138
Test name
Test status
Simulation time 461712041 ps
CPU time 1.24 seconds
Started Feb 28 04:50:39 PM PST 24
Finished Feb 28 04:50:40 PM PST 24
Peak memory 183088 kb
Host smart-9dfd540c-dadc-4be3-871b-6580e3815922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088529027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4088529027
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2503819102
Short name T220
Test name
Test status
Simulation time 241738569871 ps
CPU time 85.13 seconds
Started Feb 28 04:50:44 PM PST 24
Finished Feb 28 04:52:11 PM PST 24
Peak memory 194288 kb
Host smart-9cb04bdf-b226-40c2-9fc7-ec46aa281a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503819102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2503819102
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.1076514262
Short name T189
Test name
Test status
Simulation time 107346645052 ps
CPU time 376.21 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:57:08 PM PST 24
Peak memory 198092 kb
Host smart-817d44df-c3c3-42d2-9fca-2538517ba9db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076514262 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.1076514262
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.351492015
Short name T186
Test name
Test status
Simulation time 566481067 ps
CPU time 1.5 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183008 kb
Host smart-9336be7b-25c7-4de9-a162-58522c5004e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351492015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.351492015
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.235984005
Short name T166
Test name
Test status
Simulation time 34567734490 ps
CPU time 11.95 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:50:59 PM PST 24
Peak memory 182984 kb
Host smart-16892a46-38aa-4c7a-b2e2-940ab49e6419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235984005 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.235984005
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.2006512667
Short name T246
Test name
Test status
Simulation time 514374233 ps
CPU time 1.09 seconds
Started Feb 28 04:50:42 PM PST 24
Finished Feb 28 04:50:43 PM PST 24
Peak memory 182984 kb
Host smart-d364ab8a-e42b-4bc5-9d63-99152068c37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006512667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.2006512667
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.609608253
Short name T185
Test name
Test status
Simulation time 96796938861 ps
CPU time 141.94 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:53:09 PM PST 24
Peak memory 183148 kb
Host smart-51c6c79b-85e7-47e4-8dc4-a5b469d2b3cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609608253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.609608253
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3311434423
Short name T91
Test name
Test status
Simulation time 198356295500 ps
CPU time 570.81 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 05:00:14 PM PST 24
Peak memory 197944 kb
Host smart-81313a42-8510-41c3-94e4-3b8aeee04615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311434423 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3311434423
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2693800049
Short name T198
Test name
Test status
Simulation time 556815556 ps
CPU time 1.5 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:50:45 PM PST 24
Peak memory 183072 kb
Host smart-b82ce509-b52a-4bab-8e9f-7212d5786d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693800049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2693800049
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.750321908
Short name T62
Test name
Test status
Simulation time 37123048049 ps
CPU time 52.54 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 183172 kb
Host smart-4c2bf367-d1ed-4161-b6ea-e571ded6b136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750321908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.750321908
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3752258588
Short name T219
Test name
Test status
Simulation time 440781506 ps
CPU time 0.72 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:50:44 PM PST 24
Peak memory 182940 kb
Host smart-1f4d1e61-6b2f-4799-ba88-e3213ce06330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752258588 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3752258588
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.2775954311
Short name T231
Test name
Test status
Simulation time 42877970637 ps
CPU time 12.22 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:51:04 PM PST 24
Peak memory 194412 kb
Host smart-26c09224-0de6-427b-af0c-4e8227ea6c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775954311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.2775954311
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_jump.2264066603
Short name T230
Test name
Test status
Simulation time 461939085 ps
CPU time 1.22 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183068 kb
Host smart-355d0d46-a216-446b-8c31-9999f61545f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264066603 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.2264066603
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.303829997
Short name T191
Test name
Test status
Simulation time 32885933636 ps
CPU time 45.13 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:51:37 PM PST 24
Peak memory 183116 kb
Host smart-33a244ff-a21e-41f8-9c26-2875c3b555e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303829997 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.303829997
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.4005657840
Short name T173
Test name
Test status
Simulation time 452357671 ps
CPU time 0.73 seconds
Started Feb 28 04:50:44 PM PST 24
Finished Feb 28 04:50:46 PM PST 24
Peak memory 182920 kb
Host smart-d8f8c7ed-e810-4644-9349-8c1fabe86b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005657840 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.4005657840
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1138187037
Short name T141
Test name
Test status
Simulation time 32326188730 ps
CPU time 23.31 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 183152 kb
Host smart-a767a83d-c109-4291-90fb-d9278f7efd2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138187037 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1138187037
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_jump.3451443822
Short name T254
Test name
Test status
Simulation time 359962790 ps
CPU time 1.15 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:50:48 PM PST 24
Peak memory 182948 kb
Host smart-3985063e-3a2f-4611-a32d-d167c163ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451443822 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.3451443822
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.1391661316
Short name T263
Test name
Test status
Simulation time 13835476697 ps
CPU time 2.7 seconds
Started Feb 28 04:50:45 PM PST 24
Finished Feb 28 04:50:49 PM PST 24
Peak memory 183096 kb
Host smart-37a841ce-f2c9-46e2-acde-846641c35890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391661316 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.1391661316
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3930984075
Short name T63
Test name
Test status
Simulation time 480742400 ps
CPU time 0.75 seconds
Started Feb 28 04:50:45 PM PST 24
Finished Feb 28 04:50:47 PM PST 24
Peak memory 182960 kb
Host smart-2b150de7-2387-4958-88ec-c87ced2e40f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930984075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3930984075
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2700543695
Short name T264
Test name
Test status
Simulation time 41039918977 ps
CPU time 321.94 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:56:05 PM PST 24
Peak memory 197804 kb
Host smart-7f873daf-228e-4a76-b404-e17770b48388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700543695 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2700543695
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.987547999
Short name T126
Test name
Test status
Simulation time 465430461 ps
CPU time 0.75 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:50:44 PM PST 24
Peak memory 182944 kb
Host smart-66a2357e-4752-45cd-a3e5-f26672c3e230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987547999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.987547999
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1699717033
Short name T238
Test name
Test status
Simulation time 4470835566 ps
CPU time 3.63 seconds
Started Feb 28 04:50:42 PM PST 24
Finished Feb 28 04:50:45 PM PST 24
Peak memory 183108 kb
Host smart-d40f5795-6917-4271-beee-e405215159e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699717033 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1699717033
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2756851767
Short name T31
Test name
Test status
Simulation time 710220345 ps
CPU time 0.59 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 182976 kb
Host smart-6e277146-d39a-463d-8b4b-70985d61cc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756851767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2756851767
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.2057675040
Short name T293
Test name
Test status
Simulation time 135767384134 ps
CPU time 221.68 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:54:31 PM PST 24
Peak memory 194424 kb
Host smart-f049e3be-2b65-4b08-8fa3-efc1785aa4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057675040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.2057675040
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2613959411
Short name T96
Test name
Test status
Simulation time 317396593779 ps
CPU time 249.87 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:55:10 PM PST 24
Peak memory 197964 kb
Host smart-d2b27d5d-371b-4129-8bea-5d33715f74e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613959411 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2613959411
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.1581792493
Short name T131
Test name
Test status
Simulation time 517280605 ps
CPU time 1.37 seconds
Started Feb 28 04:50:49 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 182920 kb
Host smart-ebde6c66-2228-479c-96f1-bec8ec7effc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581792493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.1581792493
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.3304227252
Short name T12
Test name
Test status
Simulation time 51120728524 ps
CPU time 71.31 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:52:03 PM PST 24
Peak memory 183060 kb
Host smart-44c9f834-107d-4502-b490-ea4f4e9b4f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304227252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.3304227252
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3862528850
Short name T137
Test name
Test status
Simulation time 489250473 ps
CPU time 0.69 seconds
Started Feb 28 04:50:48 PM PST 24
Finished Feb 28 04:50:51 PM PST 24
Peak memory 182916 kb
Host smart-29d5a497-9359-4ea7-8c27-a0fcec10cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862528850 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3862528850
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.4106014667
Short name T215
Test name
Test status
Simulation time 206112565262 ps
CPU time 310.95 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:56:01 PM PST 24
Peak memory 183128 kb
Host smart-5edd34c5-9fe0-4733-a443-cfba29ce8582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106014667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.4106014667
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.424568781
Short name T94
Test name
Test status
Simulation time 91188367201 ps
CPU time 167.64 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:53:37 PM PST 24
Peak memory 198184 kb
Host smart-5eb46967-9d1b-4b6d-acc6-76011fb48732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424568781 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.424568781
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.3667193816
Short name T162
Test name
Test status
Simulation time 395883495 ps
CPU time 0.75 seconds
Started Feb 28 04:50:48 PM PST 24
Finished Feb 28 04:50:52 PM PST 24
Peak memory 183148 kb
Host smart-f719d090-d2d5-4c87-9094-c8b2b02e8dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667193816 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.3667193816
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.1906565917
Short name T239
Test name
Test status
Simulation time 29141293488 ps
CPU time 43.27 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 183100 kb
Host smart-55018060-1313-48b5-a008-9257545d2562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906565917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.1906565917
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.4277747973
Short name T224
Test name
Test status
Simulation time 451319274 ps
CPU time 0.65 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:50:55 PM PST 24
Peak memory 182992 kb
Host smart-c32f520f-39ea-455d-8eb0-5a552d29026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277747973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.4277747973
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.3308905913
Short name T54
Test name
Test status
Simulation time 99189091284 ps
CPU time 857.7 seconds
Started Feb 28 04:50:48 PM PST 24
Finished Feb 28 05:05:08 PM PST 24
Peak memory 201296 kb
Host smart-525bed92-ca3e-4897-aa9f-2ed585732ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308905913 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.3308905913
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.2908999691
Short name T2
Test name
Test status
Simulation time 517553897 ps
CPU time 0.99 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:50:48 PM PST 24
Peak memory 183008 kb
Host smart-d060096a-bc23-4a9e-8f48-b9f12d07102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908999691 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.2908999691
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.900395117
Short name T193
Test name
Test status
Simulation time 20217600142 ps
CPU time 31.48 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183036 kb
Host smart-d3a870f4-fd65-4dd1-9bd2-864944af8d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900395117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.900395117
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.2838653194
Short name T283
Test name
Test status
Simulation time 530635639 ps
CPU time 1.4 seconds
Started Feb 28 04:50:48 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183052 kb
Host smart-58cb708b-1778-41b9-9573-3d6d509f8f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838653194 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.2838653194
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.3953588088
Short name T242
Test name
Test status
Simulation time 146441823708 ps
CPU time 25.27 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:51:19 PM PST 24
Peak memory 183064 kb
Host smart-9e8271dc-3a4a-4649-b21a-64aa4eb379d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953588088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_
all.3953588088
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2417029568
Short name T176
Test name
Test status
Simulation time 412246464 ps
CPU time 1.06 seconds
Started Feb 28 04:50:48 PM PST 24
Finished Feb 28 04:50:52 PM PST 24
Peak memory 183020 kb
Host smart-4967108b-e33a-4815-8ebc-3bc7a0f63ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417029568 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2417029568
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.3802055285
Short name T181
Test name
Test status
Simulation time 33451727277 ps
CPU time 37.82 seconds
Started Feb 28 04:50:47 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 183004 kb
Host smart-91449cf5-1c6e-4d5f-aeb1-b1afd7edce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802055285 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.3802055285
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1531166450
Short name T197
Test name
Test status
Simulation time 487567573 ps
CPU time 1.27 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 182936 kb
Host smart-21607a7c-66ad-4ec4-8a6a-9663415aa655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531166450 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1531166450
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2531699282
Short name T115
Test name
Test status
Simulation time 168535707748 ps
CPU time 12.53 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:51:00 PM PST 24
Peak memory 183132 kb
Host smart-bfc3d105-d3ae-4da3-a572-3924221eb7c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531699282 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2531699282
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.3132320713
Short name T95
Test name
Test status
Simulation time 82738426477 ps
CPU time 600.73 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 05:00:53 PM PST 24
Peak memory 197880 kb
Host smart-f9363fb0-9886-493a-84d9-f25c64599ed2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132320713 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.3132320713
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.1904760668
Short name T147
Test name
Test status
Simulation time 462745517 ps
CPU time 1.44 seconds
Started Feb 28 04:50:33 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 183008 kb
Host smart-a89253c6-abb5-4a87-a681-7219415b32e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904760668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.1904760668
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.2492304347
Short name T163
Test name
Test status
Simulation time 27146858576 ps
CPU time 19.29 seconds
Started Feb 28 04:50:33 PM PST 24
Finished Feb 28 04:50:52 PM PST 24
Peak memory 183148 kb
Host smart-85c65b1b-9835-4018-9333-5db3f5b7a3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492304347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.2492304347
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.2668781251
Short name T24
Test name
Test status
Simulation time 8279877970 ps
CPU time 11.92 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:50:49 PM PST 24
Peak memory 215332 kb
Host smart-7bbc964a-729e-4ab1-b296-b80a20e1abdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668781251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.2668781251
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1392470101
Short name T199
Test name
Test status
Simulation time 350410292 ps
CPU time 1.02 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:35 PM PST 24
Peak memory 182912 kb
Host smart-3f42d55d-06b9-4d05-b9cd-a8b0d346683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392470101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1392470101
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.1024397175
Short name T274
Test name
Test status
Simulation time 64082263964 ps
CPU time 21.91 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:58 PM PST 24
Peak memory 183104 kb
Host smart-19a19e5c-fe55-4849-92b1-4a607a48578f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024397175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.1024397175
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.2746623782
Short name T102
Test name
Test status
Simulation time 175210852456 ps
CPU time 327.01 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:56:01 PM PST 24
Peak memory 198024 kb
Host smart-874facc6-e581-4035-89d3-9b912078be83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746623782 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.2746623782
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.4157389291
Short name T177
Test name
Test status
Simulation time 373629471 ps
CPU time 1.19 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183080 kb
Host smart-203afcca-6c5d-4063-a41f-a971be1eb4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157389291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.4157389291
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.4161353430
Short name T106
Test name
Test status
Simulation time 42729152728 ps
CPU time 35.85 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:51:28 PM PST 24
Peak memory 182952 kb
Host smart-60680ae6-2a67-46e2-847b-42bc1ecdbd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161353430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.4161353430
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.4139856144
Short name T143
Test name
Test status
Simulation time 363842452 ps
CPU time 1.13 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:50:48 PM PST 24
Peak memory 182832 kb
Host smart-b7115c45-7dc7-4671-a26f-92c9a9416458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139856144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.4139856144
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.312883089
Short name T122
Test name
Test status
Simulation time 244666147787 ps
CPU time 96.34 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:52:29 PM PST 24
Peak memory 194460 kb
Host smart-9bdeb5a7-11cc-4957-aa49-d2298edbe366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312883089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_a
ll.312883089
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.3530779251
Short name T4
Test name
Test status
Simulation time 95161973518 ps
CPU time 413.59 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:57:45 PM PST 24
Peak memory 206176 kb
Host smart-7a70156d-b464-4a92-9d80-83dd870ff725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530779251 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.3530779251
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3560740412
Short name T168
Test name
Test status
Simulation time 627811992 ps
CPU time 0.62 seconds
Started Feb 28 04:50:52 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 182988 kb
Host smart-46821d96-2d22-499b-8978-e9b7ccb9f4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560740412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3560740412
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3515631210
Short name T140
Test name
Test status
Simulation time 56108038122 ps
CPU time 27.89 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:51:27 PM PST 24
Peak memory 183176 kb
Host smart-4410dbc4-eaf4-4af7-9ee3-fe99b34a85d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515631210 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3515631210
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2945808325
Short name T139
Test name
Test status
Simulation time 610517723 ps
CPU time 0.62 seconds
Started Feb 28 04:50:46 PM PST 24
Finished Feb 28 04:50:47 PM PST 24
Peak memory 182992 kb
Host smart-2b3b5252-da8b-4e7f-9176-a24b70e8077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945808325 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2945808325
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.2638062140
Short name T119
Test name
Test status
Simulation time 225488961288 ps
CPU time 69.18 seconds
Started Feb 28 04:50:55 PM PST 24
Finished Feb 28 04:52:05 PM PST 24
Peak memory 183304 kb
Host smart-9132a930-ede3-4cea-8c7a-2b3a4e0cf3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638062140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.2638062140
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3620339975
Short name T222
Test name
Test status
Simulation time 513174257 ps
CPU time 1.36 seconds
Started Feb 28 04:50:49 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 182968 kb
Host smart-1fe69f21-73c1-4635-8447-9ccbeb30d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620339975 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3620339975
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2417277801
Short name T51
Test name
Test status
Simulation time 4880220939 ps
CPU time 4.84 seconds
Started Feb 28 04:50:52 PM PST 24
Finished Feb 28 04:50:59 PM PST 24
Peak memory 183132 kb
Host smart-149d8183-a90c-478c-a47c-e4b6d21366c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417277801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2417277801
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.3587949895
Short name T175
Test name
Test status
Simulation time 602350909 ps
CPU time 1.43 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:50:58 PM PST 24
Peak memory 182920 kb
Host smart-c54c3075-0b3a-4ce2-b38d-7509b965ba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587949895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.3587949895
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.1079098897
Short name T61
Test name
Test status
Simulation time 25854710892 ps
CPU time 20.52 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 183040 kb
Host smart-e5fad0af-6cbc-4580-9c3f-b4935fbcee4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079098897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.1079098897
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.3119262394
Short name T129
Test name
Test status
Simulation time 48270743912 ps
CPU time 190.9 seconds
Started Feb 28 04:50:55 PM PST 24
Finished Feb 28 04:54:06 PM PST 24
Peak memory 198148 kb
Host smart-344c4661-f0bf-439b-ade3-726487ce610c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119262394 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.3119262394
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.900747779
Short name T285
Test name
Test status
Simulation time 358010203 ps
CPU time 0.76 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183088 kb
Host smart-329829c5-f44e-4b1c-935c-5e52e78db1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900747779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.900747779
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.3497607780
Short name T292
Test name
Test status
Simulation time 40935826907 ps
CPU time 63.74 seconds
Started Feb 28 04:50:51 PM PST 24
Finished Feb 28 04:51:56 PM PST 24
Peak memory 183052 kb
Host smart-7e883d63-c6e9-4aa3-9bfe-7b78f9004196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497607780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.3497607780
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3622364253
Short name T226
Test name
Test status
Simulation time 352081047 ps
CPU time 0.68 seconds
Started Feb 28 04:50:50 PM PST 24
Finished Feb 28 04:50:53 PM PST 24
Peak memory 183076 kb
Host smart-35ea2522-f7ad-4b4a-9103-ba3a05950a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622364253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3622364253
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.181895864
Short name T286
Test name
Test status
Simulation time 31559065651 ps
CPU time 108.9 seconds
Started Feb 28 04:50:57 PM PST 24
Finished Feb 28 04:52:46 PM PST 24
Peak memory 198020 kb
Host smart-334ff183-9e5e-4c26-8ad8-a0c326edacc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181895864 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.181895864
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.551331923
Short name T190
Test name
Test status
Simulation time 591640004 ps
CPU time 0.74 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:50:56 PM PST 24
Peak memory 182940 kb
Host smart-baa1ddd8-4161-45fe-93a6-454b5d23f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551331923 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.551331923
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.279187031
Short name T157
Test name
Test status
Simulation time 47209090614 ps
CPU time 17.28 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 183108 kb
Host smart-583b6cee-4993-4f13-9f3b-4c0f679c8099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279187031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.279187031
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.877153076
Short name T260
Test name
Test status
Simulation time 370851844 ps
CPU time 0.82 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:50:58 PM PST 24
Peak memory 182428 kb
Host smart-70b45dc4-307e-44d9-af63-773b785d364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877153076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.877153076
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1349475661
Short name T16
Test name
Test status
Simulation time 157260590539 ps
CPU time 260.69 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:55:17 PM PST 24
Peak memory 183080 kb
Host smart-e6cad9ff-0d74-49a4-a0c6-99bf4e2c66fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349475661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1349475661
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3081303853
Short name T127
Test name
Test status
Simulation time 30975980657 ps
CPU time 321.4 seconds
Started Feb 28 04:50:57 PM PST 24
Finished Feb 28 04:56:18 PM PST 24
Peak memory 198056 kb
Host smart-cba342ce-e422-4425-9374-6953c81853b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081303853 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3081303853
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.4235393053
Short name T130
Test name
Test status
Simulation time 377077841 ps
CPU time 0.64 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:50:58 PM PST 24
Peak memory 182624 kb
Host smart-1d68ad16-a6aa-463c-829e-ade5b85e1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235393053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.4235393053
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.1653066617
Short name T7
Test name
Test status
Simulation time 10437203567 ps
CPU time 5.53 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 183076 kb
Host smart-4498f37c-4471-4849-967e-ae1ed5093b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653066617 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.1653066617
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.133185928
Short name T262
Test name
Test status
Simulation time 564914641 ps
CPU time 1.36 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:50:55 PM PST 24
Peak memory 182924 kb
Host smart-86755349-0599-420e-9297-a4268c22b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133185928 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.133185928
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.3190436668
Short name T132
Test name
Test status
Simulation time 95320544565 ps
CPU time 65.76 seconds
Started Feb 28 04:50:53 PM PST 24
Finished Feb 28 04:52:00 PM PST 24
Peak memory 183140 kb
Host smart-a15f27d3-08c6-454a-9dd1-7f9a5f349301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190436668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.3190436668
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.2464627382
Short name T116
Test name
Test status
Simulation time 25197693206 ps
CPU time 209.06 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:54:30 PM PST 24
Peak memory 197992 kb
Host smart-453a87c2-15fc-42e1-80b9-08989a731a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464627382 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.2464627382
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.159381710
Short name T134
Test name
Test status
Simulation time 435343094 ps
CPU time 0.69 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:51:01 PM PST 24
Peak memory 183016 kb
Host smart-c325a42c-0d54-4197-a8f8-ab9a7a4c3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159381710 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.159381710
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1688133132
Short name T55
Test name
Test status
Simulation time 12609494284 ps
CPU time 1.93 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:51:00 PM PST 24
Peak memory 183204 kb
Host smart-9c6c9fed-91ed-4add-8b9e-5ceed8178510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688133132 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1688133132
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.3689930063
Short name T148
Test name
Test status
Simulation time 556531966 ps
CPU time 1.44 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:50:59 PM PST 24
Peak memory 183032 kb
Host smart-ac8172fb-c646-448e-99ba-7a1e62a18676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689930063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.3689930063
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.1545960120
Short name T265
Test name
Test status
Simulation time 133555478358 ps
CPU time 210.28 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:54:28 PM PST 24
Peak memory 183028 kb
Host smart-02301047-30b0-4b02-93ba-fded4cc4c90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545960120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.1545960120
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.739898579
Short name T253
Test name
Test status
Simulation time 48317079988 ps
CPU time 341.13 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:56:39 PM PST 24
Peak memory 197984 kb
Host smart-19ca0f8c-8c68-41a4-9274-61d59cabf63e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739898579 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.739898579
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3192499956
Short name T266
Test name
Test status
Simulation time 464516260 ps
CPU time 0.6 seconds
Started Feb 28 04:50:57 PM PST 24
Finished Feb 28 04:50:57 PM PST 24
Peak memory 183040 kb
Host smart-2092cd05-b889-4973-93c5-a94c6d127bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192499956 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3192499956
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2851248664
Short name T291
Test name
Test status
Simulation time 38039324529 ps
CPU time 15.47 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 183136 kb
Host smart-aee56e6f-74cb-40f8-aaea-69b873320693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851248664 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2851248664
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3949316974
Short name T153
Test name
Test status
Simulation time 546952152 ps
CPU time 0.9 seconds
Started Feb 28 04:50:56 PM PST 24
Finished Feb 28 04:50:57 PM PST 24
Peak memory 182972 kb
Host smart-694be761-1893-402a-8438-4be7ced58331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949316974 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3949316974
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.100291347
Short name T128
Test name
Test status
Simulation time 139704251616 ps
CPU time 193.3 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:54:13 PM PST 24
Peak memory 194632 kb
Host smart-4fe44d7c-8085-468c-a239-039914982c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100291347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.100291347
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.3628344507
Short name T46
Test name
Test status
Simulation time 24435514357 ps
CPU time 173.15 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:53:52 PM PST 24
Peak memory 198000 kb
Host smart-bbdb9d32-cc99-435d-ab28-f514da5a4783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628344507 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.3628344507
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.3527494645
Short name T194
Test name
Test status
Simulation time 471969169 ps
CPU time 0.72 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:51:00 PM PST 24
Peak memory 183008 kb
Host smart-f68a622d-0154-47a8-bf00-00bdc6d4e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527494645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.3527494645
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1652975306
Short name T240
Test name
Test status
Simulation time 55750440681 ps
CPU time 22.53 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:24 PM PST 24
Peak memory 183112 kb
Host smart-524b0c7f-c178-41f4-9550-29a8308c7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652975306 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1652975306
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.766140587
Short name T180
Test name
Test status
Simulation time 376669093 ps
CPU time 1.17 seconds
Started Feb 28 04:50:57 PM PST 24
Finished Feb 28 04:50:58 PM PST 24
Peak memory 182980 kb
Host smart-71ac2dab-97a1-4e45-8184-8651529a5102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766140587 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.766140587
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.1433885007
Short name T121
Test name
Test status
Simulation time 136772061098 ps
CPU time 180.57 seconds
Started Feb 28 04:50:57 PM PST 24
Finished Feb 28 04:53:58 PM PST 24
Peak memory 183064 kb
Host smart-b99c8cb6-3349-4e61-b47e-6bcf08483e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433885007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.1433885007
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.929906576
Short name T244
Test name
Test status
Simulation time 10992896564 ps
CPU time 86.92 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:52:26 PM PST 24
Peak memory 198116 kb
Host smart-0103611a-c7d4-4fef-9438-b8e94c20502d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929906576 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.929906576
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.1391115597
Short name T255
Test name
Test status
Simulation time 402606970 ps
CPU time 1.1 seconds
Started Feb 28 04:50:55 PM PST 24
Finished Feb 28 04:50:56 PM PST 24
Peak memory 183076 kb
Host smart-704fa058-8a1d-4a6a-8c03-0fe21d3dd0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391115597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.1391115597
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.677473445
Short name T273
Test name
Test status
Simulation time 44582810815 ps
CPU time 32.17 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:51:31 PM PST 24
Peak memory 183128 kb
Host smart-4007d488-f880-4d5c-8a50-64441365e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677473445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.677473445
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.4238424462
Short name T248
Test name
Test status
Simulation time 444323669 ps
CPU time 1.15 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:50:59 PM PST 24
Peak memory 182912 kb
Host smart-278382d9-e21b-4182-9de4-7e3b3f1876fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238424462 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.4238424462
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2706250188
Short name T201
Test name
Test status
Simulation time 50330532886 ps
CPU time 21.34 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:51:20 PM PST 24
Peak memory 193520 kb
Host smart-820a0e33-aa9f-4205-bff0-632dfda41068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706250188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2706250188
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1448661090
Short name T123
Test name
Test status
Simulation time 17987173726 ps
CPU time 181.77 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:54:01 PM PST 24
Peak memory 198000 kb
Host smart-39b9a397-17d9-419d-909b-ed4a47d1c359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448661090 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1448661090
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.1827140813
Short name T213
Test name
Test status
Simulation time 439418550 ps
CPU time 0.73 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 183000 kb
Host smart-2ba3957a-6d81-4d18-ad0b-e28a6474d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827140813 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.1827140813
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2321468524
Short name T25
Test name
Test status
Simulation time 17365160096 ps
CPU time 3.1 seconds
Started Feb 28 04:50:33 PM PST 24
Finished Feb 28 04:50:37 PM PST 24
Peak memory 183068 kb
Host smart-fbda616e-87fb-4b69-ace1-1fd49074f9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321468524 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2321468524
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.112234671
Short name T19
Test name
Test status
Simulation time 8047488967 ps
CPU time 3.65 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:38 PM PST 24
Peak memory 215320 kb
Host smart-435db878-b437-48ad-88c8-3a80923f841f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112234671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.112234671
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.2363823887
Short name T151
Test name
Test status
Simulation time 574580669 ps
CPU time 0.99 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 182828 kb
Host smart-83c581cb-61b0-4224-8bb0-7d0d44f29265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363823887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.2363823887
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.1891509828
Short name T229
Test name
Test status
Simulation time 144183141658 ps
CPU time 195.02 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:53:50 PM PST 24
Peak memory 183140 kb
Host smart-a952d714-6b6f-4853-8968-a5b58a707a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891509828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.1891509828
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.2111133884
Short name T48
Test name
Test status
Simulation time 49723951494 ps
CPU time 330.3 seconds
Started Feb 28 04:50:39 PM PST 24
Finished Feb 28 04:56:09 PM PST 24
Peak memory 198148 kb
Host smart-61eedbd8-5e14-4034-8fc7-65fa566c7593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111133884 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.2111133884
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.4236936742
Short name T53
Test name
Test status
Simulation time 419745059 ps
CPU time 0.68 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:51:00 PM PST 24
Peak memory 183016 kb
Host smart-ac7c1d05-e476-49d5-ba4a-b4a94e6a5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236936742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.4236936742
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.4254032464
Short name T192
Test name
Test status
Simulation time 33655277825 ps
CPU time 41.19 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 183088 kb
Host smart-00679cc2-20f9-41c3-8228-4a0902a87fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254032464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.4254032464
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.4143577114
Short name T169
Test name
Test status
Simulation time 343300335 ps
CPU time 1.08 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 182932 kb
Host smart-4a835be6-1d72-4dbc-9d2c-f5765646def8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143577114 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.4143577114
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.1309964078
Short name T217
Test name
Test status
Simulation time 168917643757 ps
CPU time 79.51 seconds
Started Feb 28 04:50:59 PM PST 24
Finished Feb 28 04:52:19 PM PST 24
Peak memory 183076 kb
Host smart-e5a02eb2-30ce-46eb-bc50-eef1ce79d3d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309964078 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.1309964078
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.604261632
Short name T45
Test name
Test status
Simulation time 180676046899 ps
CPU time 617.32 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 05:01:19 PM PST 24
Peak memory 199564 kb
Host smart-5d35e5f9-0af6-4bee-a2ed-05d94b995c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604261632 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.604261632
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.555457731
Short name T149
Test name
Test status
Simulation time 395641982 ps
CPU time 0.86 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:51:01 PM PST 24
Peak memory 183044 kb
Host smart-f06b2eec-cda1-4cd9-91d4-313393f3e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555457731 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.555457731
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.1491062766
Short name T272
Test name
Test status
Simulation time 24377656891 ps
CPU time 10.83 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 183180 kb
Host smart-0357b9e5-19d5-4c53-9ae1-8c332fa5dfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491062766 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.1491062766
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.3552695032
Short name T277
Test name
Test status
Simulation time 447096414 ps
CPU time 0.72 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:01 PM PST 24
Peak memory 182976 kb
Host smart-6f978c79-ae99-4628-a52e-dbf3406e95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552695032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.3552695032
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.320259669
Short name T182
Test name
Test status
Simulation time 125577685917 ps
CPU time 60.31 seconds
Started Feb 28 04:51:05 PM PST 24
Finished Feb 28 04:52:05 PM PST 24
Peak memory 183068 kb
Host smart-1a9d3911-3b38-4674-8cd6-13da4aa531fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320259669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_a
ll.320259669
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_jump.4103918557
Short name T178
Test name
Test status
Simulation time 528447981 ps
CPU time 1.07 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 183068 kb
Host smart-572943e2-6839-4926-88c8-f0cc757da505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103918557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.4103918557
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3767269333
Short name T14
Test name
Test status
Simulation time 19743237579 ps
CPU time 8.42 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 183096 kb
Host smart-8ae48b18-c32d-4167-9549-45b1fb97ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767269333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3767269333
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.2275402251
Short name T257
Test name
Test status
Simulation time 480983756 ps
CPU time 1.16 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:03 PM PST 24
Peak memory 182908 kb
Host smart-dbf643bc-d787-4a4f-b31b-3d4a3271c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275402251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.2275402251
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.2168201267
Short name T237
Test name
Test status
Simulation time 50652120451 ps
CPU time 71.73 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:52:14 PM PST 24
Peak memory 183080 kb
Host smart-a38ef06f-53d5-4bad-9716-2fd1bff9ca0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168201267 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.2168201267
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_jump.716381657
Short name T34
Test name
Test status
Simulation time 390800554 ps
CPU time 0.73 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:03 PM PST 24
Peak memory 183080 kb
Host smart-70fccc03-e171-4f43-b962-40c0a3800661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716381657 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.716381657
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.3666832409
Short name T252
Test name
Test status
Simulation time 21286182717 ps
CPU time 7.77 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:51:08 PM PST 24
Peak memory 183124 kb
Host smart-cb9ade17-90cd-4fcf-b613-7c195bb08f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666832409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.3666832409
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2673524769
Short name T279
Test name
Test status
Simulation time 640101070 ps
CPU time 0.61 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 182988 kb
Host smart-aa4239d1-63f7-4945-8a96-ee64bce1826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673524769 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2673524769
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1307314565
Short name T32
Test name
Test status
Simulation time 159561397919 ps
CPU time 224.26 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:54:45 PM PST 24
Peak memory 183064 kb
Host smart-d47c7601-7227-4224-aec4-d2ad8f13df0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307314565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1307314565
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3917007270
Short name T276
Test name
Test status
Simulation time 173232191254 ps
CPU time 198.7 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:54:23 PM PST 24
Peak memory 198076 kb
Host smart-15c60400-1ec3-4d5f-a763-57f8e27df269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917007270 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3917007270
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.739276226
Short name T104
Test name
Test status
Simulation time 617051297 ps
CPU time 0.74 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 183032 kb
Host smart-a6b526ce-2a38-41e6-a47e-dbc3c502eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739276226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.739276226
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.3728362191
Short name T144
Test name
Test status
Simulation time 19295932157 ps
CPU time 29.91 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:51:33 PM PST 24
Peak memory 183148 kb
Host smart-d1ed7e82-eaf5-47c1-ad4b-bb2e8d7dc6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728362191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.3728362191
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.196470849
Short name T184
Test name
Test status
Simulation time 462112079 ps
CPU time 1.12 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:50:59 PM PST 24
Peak memory 182856 kb
Host smart-79903a4c-d66c-42e5-9377-502560ff4589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196470849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.196470849
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.3438379741
Short name T250
Test name
Test status
Simulation time 234953420228 ps
CPU time 44.56 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:47 PM PST 24
Peak memory 191280 kb
Host smart-c89624e2-9902-4950-b1a7-acfa804af0e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438379741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.3438379741
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.2960076421
Short name T26
Test name
Test status
Simulation time 1010945152772 ps
CPU time 868.36 seconds
Started Feb 28 04:51:05 PM PST 24
Finished Feb 28 05:05:33 PM PST 24
Peak memory 213452 kb
Host smart-b81bf8da-73c3-4e7a-bf19-4369ff17b8be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960076421 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.2960076421
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1271330326
Short name T10
Test name
Test status
Simulation time 375428432 ps
CPU time 1.08 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:51:04 PM PST 24
Peak memory 183064 kb
Host smart-de1d2d6d-35ff-463d-99f6-6e1342fdef35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271330326 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1271330326
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3181307955
Short name T171
Test name
Test status
Simulation time 4618748022 ps
CPU time 3.83 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:51:04 PM PST 24
Peak memory 183096 kb
Host smart-65e140ea-0087-4e38-8021-4dadf04d0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181307955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3181307955
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.3570801007
Short name T196
Test name
Test status
Simulation time 399072294 ps
CPU time 0.62 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 182908 kb
Host smart-03c2c0ef-c85e-4355-92d3-b862a090566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570801007 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.3570801007
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.84150649
Short name T287
Test name
Test status
Simulation time 50970387920 ps
CPU time 34.88 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:51:43 PM PST 24
Peak memory 193176 kb
Host smart-f9c84238-4c27-44cf-9bc0-bd9a89310868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84150649 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_al
l.84150649
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.3260040165
Short name T98
Test name
Test status
Simulation time 64171692697 ps
CPU time 493.85 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:59:14 PM PST 24
Peak memory 198036 kb
Host smart-77131def-e591-4ccf-b503-cbdb3ba05d58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260040165 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.3260040165
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1434890385
Short name T50
Test name
Test status
Simulation time 597660310 ps
CPU time 0.67 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 183012 kb
Host smart-b7848311-0484-41b5-8ccb-ef40bc4ad69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434890385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1434890385
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.730514470
Short name T187
Test name
Test status
Simulation time 4818304985 ps
CPU time 1.08 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 183120 kb
Host smart-b7d80b00-8cde-49ca-b8b4-07295e9ff99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730514470 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.730514470
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1454301698
Short name T29
Test name
Test status
Simulation time 451873432 ps
CPU time 0.6 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 182892 kb
Host smart-b04d6cbf-4d44-41d4-b614-bc758fe6e33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454301698 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1454301698
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2263983544
Short name T278
Test name
Test status
Simulation time 57981710582 ps
CPU time 18.75 seconds
Started Feb 28 04:50:58 PM PST 24
Finished Feb 28 04:51:17 PM PST 24
Peak memory 191120 kb
Host smart-6ff7a2c7-e073-478e-a23b-591f2fc62e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263983544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2263983544
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1010766919
Short name T268
Test name
Test status
Simulation time 436640209 ps
CPU time 0.74 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 183072 kb
Host smart-d8466c4f-a027-482f-88e3-f2f2d47686fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010766919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1010766919
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1848014491
Short name T150
Test name
Test status
Simulation time 967541783 ps
CPU time 0.88 seconds
Started Feb 28 04:51:01 PM PST 24
Finished Feb 28 04:51:02 PM PST 24
Peak memory 182996 kb
Host smart-8b7c1942-41de-4710-8f7f-da55d604562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848014491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1848014491
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.2675741747
Short name T204
Test name
Test status
Simulation time 403909671 ps
CPU time 0.76 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 182944 kb
Host smart-4c162bcc-dc3a-4bba-b2ed-fe5882102f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675741747 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.2675741747
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.1769520489
Short name T105
Test name
Test status
Simulation time 4114979001 ps
CPU time 3.61 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:51:07 PM PST 24
Peak memory 183048 kb
Host smart-0b3d7632-74af-4058-a18a-0f14a57d3594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769520489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.1769520489
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.57969087
Short name T232
Test name
Test status
Simulation time 57819829108 ps
CPU time 124.31 seconds
Started Feb 28 04:51:00 PM PST 24
Finished Feb 28 04:53:04 PM PST 24
Peak memory 197992 kb
Host smart-5f6d5cbb-f11f-40f0-a71f-20f15da3b6a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57969087 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.57969087
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2847232024
Short name T159
Test name
Test status
Simulation time 582781354 ps
CPU time 0.92 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:03 PM PST 24
Peak memory 183108 kb
Host smart-b4de78bf-f256-47af-9d52-8be4ebd26cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847232024 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2847232024
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.2886161990
Short name T282
Test name
Test status
Simulation time 58123967346 ps
CPU time 21.13 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:51:24 PM PST 24
Peak memory 183052 kb
Host smart-89bd805c-89cd-477f-bc39-19831f8aa3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886161990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.2886161990
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.2952676451
Short name T212
Test name
Test status
Simulation time 525919037 ps
CPU time 0.67 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 182992 kb
Host smart-74a0de0d-0120-4ace-9e8e-aeda4e81e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952676451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.2952676451
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3431283075
Short name T133
Test name
Test status
Simulation time 423310123228 ps
CPU time 70.48 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:52:13 PM PST 24
Peak memory 193268 kb
Host smart-ac6f73b0-5f66-4020-b2d5-088c34188aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431283075 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3431283075
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.976636449
Short name T36
Test name
Test status
Simulation time 88748419586 ps
CPU time 289.85 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:55:54 PM PST 24
Peak memory 197996 kb
Host smart-5f3c16c7-e7de-492a-9c1b-94e749f5c27b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976636449 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.976636449
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.aon_timer_jump.1815612841
Short name T118
Test name
Test status
Simulation time 383153476 ps
CPU time 0.68 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 183136 kb
Host smart-4f98f5b2-f82c-4bf8-ad17-2b54c2ade41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815612841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.1815612841
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.122039665
Short name T9
Test name
Test status
Simulation time 29704768286 ps
CPU time 10.3 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:15 PM PST 24
Peak memory 183056 kb
Host smart-c269df7b-d54c-4925-8608-43fd37e5f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122039665 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.122039665
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3920565791
Short name T267
Test name
Test status
Simulation time 368723372 ps
CPU time 1.13 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:04 PM PST 24
Peak memory 182988 kb
Host smart-a1e7f97d-461f-4de5-976c-b923255b9a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920565791 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3920565791
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.738226938
Short name T188
Test name
Test status
Simulation time 243217989863 ps
CPU time 169.48 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:53:54 PM PST 24
Peak memory 193364 kb
Host smart-4935c4db-97f7-4794-88b8-88aa370c1a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738226938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.738226938
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.2653424756
Short name T233
Test name
Test status
Simulation time 76526727846 ps
CPU time 826.13 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 05:04:49 PM PST 24
Peak memory 201648 kb
Host smart-2f869ad7-0607-4613-b6b9-0095ee1897a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653424756 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.2653424756
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.711370399
Short name T142
Test name
Test status
Simulation time 506371867 ps
CPU time 0.92 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 183056 kb
Host smart-e0892c29-512d-4661-8f08-e137f1e3ebdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711370399 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.711370399
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3245863708
Short name T210
Test name
Test status
Simulation time 4999298270 ps
CPU time 4.94 seconds
Started Feb 28 04:50:36 PM PST 24
Finished Feb 28 04:50:41 PM PST 24
Peak memory 183136 kb
Host smart-fa43f575-a6e8-4352-b9b1-ef04ea076744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245863708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3245863708
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.4284748841
Short name T23
Test name
Test status
Simulation time 4467595133 ps
CPU time 1.4 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:39 PM PST 24
Peak memory 215208 kb
Host smart-f2c3fab8-f818-4206-ba67-d5794f9fa66c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284748841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.4284748841
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.4285379565
Short name T160
Test name
Test status
Simulation time 509264622 ps
CPU time 0.94 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:50:35 PM PST 24
Peak memory 182916 kb
Host smart-f5a9b785-6c03-4b2f-9d3a-aeaab0ccaece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285379565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.4285379565
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.3156036109
Short name T52
Test name
Test status
Simulation time 56902998137 ps
CPU time 94.33 seconds
Started Feb 28 04:50:34 PM PST 24
Finished Feb 28 04:52:09 PM PST 24
Peak memory 183056 kb
Host smart-e33140d7-f51c-4267-b94d-6f845fbe5382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156036109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.3156036109
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.1113788922
Short name T203
Test name
Test status
Simulation time 37861866307 ps
CPU time 393.73 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 04:57:14 PM PST 24
Peak memory 206208 kb
Host smart-8e771060-72f3-40e8-b117-77ea189a42cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113788922 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.1113788922
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.1209245547
Short name T56
Test name
Test status
Simulation time 546079848 ps
CPU time 0.72 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:51:04 PM PST 24
Peak memory 183060 kb
Host smart-f7b725bd-ab7f-47c2-b8b9-6c030f63a0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209245547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.1209245547
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4056128395
Short name T251
Test name
Test status
Simulation time 688577463 ps
CPU time 0.84 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:03 PM PST 24
Peak memory 182868 kb
Host smart-ba1b092b-f2e2-43b1-9a18-cde6da5728ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056128395 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4056128395
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.488584433
Short name T209
Test name
Test status
Simulation time 488265557 ps
CPU time 1.17 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:05 PM PST 24
Peak memory 183060 kb
Host smart-4b9e4102-b0fd-4939-afbb-25b585425870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488584433 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.488584433
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.595975049
Short name T228
Test name
Test status
Simulation time 286332580308 ps
CPU time 391.01 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:57:34 PM PST 24
Peak memory 193160 kb
Host smart-6910b0c2-d624-4510-bcb0-7775cb25fef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595975049 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.595975049
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3085348327
Short name T165
Test name
Test status
Simulation time 63975855820 ps
CPU time 401.8 seconds
Started Feb 28 04:51:03 PM PST 24
Finished Feb 28 04:57:45 PM PST 24
Peak memory 198000 kb
Host smart-a10c81d1-8406-4992-913b-72b1d1d2abb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085348327 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3085348327
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.aon_timer_jump.1487385620
Short name T170
Test name
Test status
Simulation time 395241835 ps
CPU time 1.23 seconds
Started Feb 28 04:51:02 PM PST 24
Finished Feb 28 04:51:03 PM PST 24
Peak memory 183084 kb
Host smart-1b32a06f-2a7c-4718-b00e-80fb0e2f7633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487385620 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.1487385620
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.484923497
Short name T57
Test name
Test status
Simulation time 38043579462 ps
CPU time 15.17 seconds
Started Feb 28 04:51:05 PM PST 24
Finished Feb 28 04:51:21 PM PST 24
Peak memory 183140 kb
Host smart-af97769b-9e5e-402d-a758-b220abc0bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484923497 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.484923497
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.1871602006
Short name T3
Test name
Test status
Simulation time 370967243 ps
CPU time 1.12 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:51:07 PM PST 24
Peak memory 182992 kb
Host smart-6be1731c-fc23-4d89-9830-86bab88e8432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871602006 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.1871602006
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3332394758
Short name T117
Test name
Test status
Simulation time 128657082821 ps
CPU time 63.78 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:52:08 PM PST 24
Peak memory 194456 kb
Host smart-df183b3d-920b-4f32-aeba-ab71ae61bf07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332394758 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3332394758
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.1828419709
Short name T93
Test name
Test status
Simulation time 318800419297 ps
CPU time 825.84 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 05:04:50 PM PST 24
Peak memory 202092 kb
Host smart-3db147ba-1c0d-46a8-861e-ee2a3ff48a96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828419709 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.1828419709
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.299493723
Short name T243
Test name
Test status
Simulation time 589733809 ps
CPU time 0.6 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 182992 kb
Host smart-33f9ceb0-4b86-479b-8030-f8b240cadef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299493723 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.299493723
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.3959207897
Short name T202
Test name
Test status
Simulation time 15411264660 ps
CPU time 22.37 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:51:29 PM PST 24
Peak memory 183044 kb
Host smart-1126fbd5-4ce4-4f04-b361-63d4b4b79ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959207897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.3959207897
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.2436356053
Short name T245
Test name
Test status
Simulation time 501041854 ps
CPU time 0.94 seconds
Started Feb 28 04:51:04 PM PST 24
Finished Feb 28 04:51:06 PM PST 24
Peak memory 183000 kb
Host smart-87c4420e-d015-4862-ae05-ea018040ff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436356053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.2436356053
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.74726384
Short name T179
Test name
Test status
Simulation time 32781645329 ps
CPU time 13.11 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:51:22 PM PST 24
Peak memory 183064 kb
Host smart-56abe4cd-f248-4537-81d3-e49910047de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74726384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_al
l.74726384
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2215913055
Short name T288
Test name
Test status
Simulation time 432188194 ps
CPU time 1.19 seconds
Started Feb 28 04:51:07 PM PST 24
Finished Feb 28 04:51:08 PM PST 24
Peak memory 183092 kb
Host smart-d44564f3-e2f2-4a47-af04-6c3c6f0aed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215913055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2215913055
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2144427802
Short name T145
Test name
Test status
Simulation time 37549136233 ps
CPU time 62.05 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:52:12 PM PST 24
Peak memory 183036 kb
Host smart-bc229af1-5877-4602-8fe6-9cdcbfc947c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144427802 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2144427802
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.820372592
Short name T13
Test name
Test status
Simulation time 560362046 ps
CPU time 1.27 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:51:08 PM PST 24
Peak memory 183076 kb
Host smart-80db4d1c-7a02-4f86-ba48-cbbf5e4968f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820372592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.820372592
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2621232977
Short name T120
Test name
Test status
Simulation time 127128441226 ps
CPU time 46.32 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:51:54 PM PST 24
Peak memory 191236 kb
Host smart-0c0bca8c-cfff-45c0-9cb5-5d325a76d902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621232977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2621232977
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.1929407350
Short name T211
Test name
Test status
Simulation time 7892369647 ps
CPU time 54.97 seconds
Started Feb 28 04:51:11 PM PST 24
Finished Feb 28 04:52:07 PM PST 24
Peak memory 198028 kb
Host smart-43d55ac1-0f01-45f1-8536-58a363035618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929407350 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.1929407350
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3548390792
Short name T261
Test name
Test status
Simulation time 606241375 ps
CPU time 1.46 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 183020 kb
Host smart-dd8f5529-663b-447d-9eec-78cf2c21a7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548390792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3548390792
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.3705515062
Short name T214
Test name
Test status
Simulation time 19615508732 ps
CPU time 8.7 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:51:17 PM PST 24
Peak memory 183248 kb
Host smart-813c9fd2-52af-4225-9bd4-d14978946f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705515062 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.3705515062
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.33787976
Short name T5
Test name
Test status
Simulation time 473406897 ps
CPU time 0.88 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 182900 kb
Host smart-a68cdd18-f190-4fec-99f8-7f655cd55773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33787976 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.33787976
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1014880987
Short name T290
Test name
Test status
Simulation time 380943895655 ps
CPU time 40.45 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:49 PM PST 24
Peak memory 183072 kb
Host smart-e3445d29-8f05-4b5e-811e-cdb91a27c47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014880987 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1014880987
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.956181489
Short name T99
Test name
Test status
Simulation time 50059689662 ps
CPU time 398.03 seconds
Started Feb 28 04:51:07 PM PST 24
Finished Feb 28 04:57:45 PM PST 24
Peak memory 197936 kb
Host smart-ab82d39b-0dc9-44d4-aa79-5b9fb7a65c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956181489 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.956181489
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.2315799143
Short name T30
Test name
Test status
Simulation time 356220199 ps
CPU time 0.85 seconds
Started Feb 28 04:51:07 PM PST 24
Finished Feb 28 04:51:08 PM PST 24
Peak memory 183056 kb
Host smart-12d31749-24c8-438e-8a3c-06e389af3a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315799143 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.2315799143
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.3416426152
Short name T269
Test name
Test status
Simulation time 38114293727 ps
CPU time 52.15 seconds
Started Feb 28 04:51:07 PM PST 24
Finished Feb 28 04:52:00 PM PST 24
Peak memory 183076 kb
Host smart-d37b63f3-ec7b-453b-8a25-94a58e98afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416426152 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.3416426152
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.3613558812
Short name T284
Test name
Test status
Simulation time 503543954 ps
CPU time 1.34 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 182844 kb
Host smart-4b37ad55-3f5b-4a20-960c-99094f0a51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613558812 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.3613558812
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1297290167
Short name T221
Test name
Test status
Simulation time 243959933201 ps
CPU time 350.95 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:56:57 PM PST 24
Peak memory 183056 kb
Host smart-ee9ac931-0f84-49e9-9700-b7bc03f4e219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297290167 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1297290167
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1466505248
Short name T107
Test name
Test status
Simulation time 529885415 ps
CPU time 0.76 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:51:07 PM PST 24
Peak memory 182996 kb
Host smart-4fb3b57c-7c12-4a72-bb57-48c57377dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466505248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1466505248
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2358553558
Short name T183
Test name
Test status
Simulation time 51648927299 ps
CPU time 67.81 seconds
Started Feb 28 04:51:08 PM PST 24
Finished Feb 28 04:52:16 PM PST 24
Peak memory 182624 kb
Host smart-c3ce69a5-58fc-4ba5-b6e2-21f66d940583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358553558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2358553558
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.3182049397
Short name T270
Test name
Test status
Simulation time 338768070 ps
CPU time 1.03 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:10 PM PST 24
Peak memory 182844 kb
Host smart-b59ea5ba-3736-4584-ad25-3dce404d721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182049397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.3182049397
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.2469192754
Short name T281
Test name
Test status
Simulation time 120730273708 ps
CPU time 184.54 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:54:13 PM PST 24
Peak memory 193056 kb
Host smart-2e3ed45d-f6ca-4d30-845c-7604e4788d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469192754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.2469192754
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.1189897283
Short name T223
Test name
Test status
Simulation time 13223529689 ps
CPU time 145.38 seconds
Started Feb 28 04:51:06 PM PST 24
Finished Feb 28 04:53:31 PM PST 24
Peak memory 198092 kb
Host smart-269147aa-38b5-457e-acc5-3a1cf2ecacbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189897283 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.1189897283
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3295172401
Short name T158
Test name
Test status
Simulation time 451154281 ps
CPU time 1.28 seconds
Started Feb 28 04:51:13 PM PST 24
Finished Feb 28 04:51:14 PM PST 24
Peak memory 183016 kb
Host smart-1e1f0c15-0dd4-4013-9831-a1a5750881f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295172401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3295172401
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.1208429055
Short name T44
Test name
Test status
Simulation time 8965358025 ps
CPU time 1.16 seconds
Started Feb 28 04:51:09 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 183056 kb
Host smart-308516e5-2102-40e8-b6fe-461f3a733e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208429055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.1208429055
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3839860851
Short name T59
Test name
Test status
Simulation time 597168396 ps
CPU time 0.75 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 182992 kb
Host smart-ee26b1fc-3039-4d68-b954-15bde68c8509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839860851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3839860851
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2433383409
Short name T249
Test name
Test status
Simulation time 124298117826 ps
CPU time 190.88 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:54:23 PM PST 24
Peak memory 194536 kb
Host smart-805c0485-978c-4ccc-994b-6595ee17da96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433383409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2433383409
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.2665012959
Short name T259
Test name
Test status
Simulation time 70310366352 ps
CPU time 288.15 seconds
Started Feb 28 04:51:10 PM PST 24
Finished Feb 28 04:55:59 PM PST 24
Peak memory 197976 kb
Host smart-8b77cc4b-44bd-40af-8d2c-58a6e0870b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665012959 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.2665012959
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2514623903
Short name T241
Test name
Test status
Simulation time 634801784 ps
CPU time 1.53 seconds
Started Feb 28 04:51:10 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 182980 kb
Host smart-8262ae09-1ab8-46d3-9e75-a26e8d698b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514623903 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2514623903
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.3265624209
Short name T156
Test name
Test status
Simulation time 14318913579 ps
CPU time 20.46 seconds
Started Feb 28 04:51:13 PM PST 24
Finished Feb 28 04:51:34 PM PST 24
Peak memory 183056 kb
Host smart-e7a6e258-bc93-488b-a1b9-5c96b20efaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265624209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.3265624209
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.388904743
Short name T136
Test name
Test status
Simulation time 495582524 ps
CPU time 1.29 seconds
Started Feb 28 04:51:10 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 182912 kb
Host smart-fa547fc0-e115-4670-8dfb-b870132cc6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388904743 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.388904743
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.855721555
Short name T216
Test name
Test status
Simulation time 47001666983 ps
CPU time 399.69 seconds
Started Feb 28 04:51:13 PM PST 24
Finished Feb 28 04:57:53 PM PST 24
Peak memory 214336 kb
Host smart-5bad2167-da45-42d7-8659-4aa9688c2f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855721555 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.855721555
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.229789501
Short name T195
Test name
Test status
Simulation time 415858844 ps
CPU time 1.27 seconds
Started Feb 28 04:51:11 PM PST 24
Finished Feb 28 04:51:13 PM PST 24
Peak memory 182944 kb
Host smart-62068011-f978-4e2a-bee3-d20859cf1715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229789501 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.229789501
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1021981162
Short name T155
Test name
Test status
Simulation time 8301303293 ps
CPU time 3.3 seconds
Started Feb 28 04:51:12 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183048 kb
Host smart-056e2c94-10a8-4b1a-b124-194624f39eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021981162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1021981162
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.35788360
Short name T35
Test name
Test status
Simulation time 501496392 ps
CPU time 1.31 seconds
Started Feb 28 04:51:15 PM PST 24
Finished Feb 28 04:51:16 PM PST 24
Peak memory 183088 kb
Host smart-39da548c-2975-4cff-abac-82700e187520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35788360 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.35788360
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.2706156377
Short name T154
Test name
Test status
Simulation time 304021176533 ps
CPU time 112.88 seconds
Started Feb 28 04:51:14 PM PST 24
Finished Feb 28 04:53:07 PM PST 24
Peak memory 183068 kb
Host smart-ffdf4030-6a21-435d-a950-b745c0691fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706156377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.2706156377
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1454841735
Short name T15
Test name
Test status
Simulation time 59604368478 ps
CPU time 629.56 seconds
Started Feb 28 04:51:14 PM PST 24
Finished Feb 28 05:01:43 PM PST 24
Peak memory 198212 kb
Host smart-0e445ea7-3caa-40b9-a40c-ef020415e1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454841735 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1454841735
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.1790951880
Short name T289
Test name
Test status
Simulation time 458417714 ps
CPU time 0.85 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:36 PM PST 24
Peak memory 182860 kb
Host smart-fad7ff53-2069-4402-91d2-4837e669a6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790951880 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.1790951880
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.3020279656
Short name T135
Test name
Test status
Simulation time 38678808648 ps
CPU time 11.52 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:50 PM PST 24
Peak memory 183064 kb
Host smart-9b4bc028-ce29-493b-94df-517c0e8e8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020279656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.3020279656
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2266083483
Short name T49
Test name
Test status
Simulation time 459036661 ps
CPU time 1.36 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:50:38 PM PST 24
Peak memory 182908 kb
Host smart-fab6a893-26f8-4a85-8d6b-ba4c9dd31e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266083483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2266083483
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3019379341
Short name T236
Test name
Test status
Simulation time 449606433421 ps
CPU time 639.13 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 05:01:17 PM PST 24
Peak memory 183140 kb
Host smart-e7c64b30-fdcd-4456-8c8b-05acd3e383dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019379341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3019379341
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1022193018
Short name T90
Test name
Test status
Simulation time 180617210844 ps
CPU time 491.76 seconds
Started Feb 28 04:50:36 PM PST 24
Finished Feb 28 04:58:48 PM PST 24
Peak memory 198108 kb
Host smart-50a8ca84-f69d-48e0-8199-640b6f8528d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022193018 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1022193018
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.2334582580
Short name T60
Test name
Test status
Simulation time 430477899 ps
CPU time 0.9 seconds
Started Feb 28 04:50:36 PM PST 24
Finished Feb 28 04:50:37 PM PST 24
Peak memory 183036 kb
Host smart-7cc73e1c-12ad-4af4-b73c-94a1161f6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334582580 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.2334582580
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.4245037518
Short name T234
Test name
Test status
Simulation time 53821446644 ps
CPU time 9.52 seconds
Started Feb 28 04:50:36 PM PST 24
Finished Feb 28 04:50:45 PM PST 24
Peak memory 183044 kb
Host smart-733444f1-e1be-4765-9fbb-4c4e2c9540a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245037518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.4245037518
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.3172900298
Short name T258
Test name
Test status
Simulation time 524119467 ps
CPU time 1.38 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:50:38 PM PST 24
Peak memory 182976 kb
Host smart-8bb2f53b-1ed8-4aa3-8ab3-c697dada8d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172900298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.3172900298
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.3956812190
Short name T58
Test name
Test status
Simulation time 93521968567 ps
CPU time 35.01 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:51:12 PM PST 24
Peak memory 183060 kb
Host smart-becea8bd-35df-4cdd-9503-9fe1f8ed3572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956812190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.3956812190
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.2011929692
Short name T205
Test name
Test status
Simulation time 81262863889 ps
CPU time 916.19 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 05:05:57 PM PST 24
Peak memory 202424 kb
Host smart-98c47679-d41c-4bcc-950a-4d5ae11483b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011929692 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.2011929692
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.1158717102
Short name T256
Test name
Test status
Simulation time 617019022 ps
CPU time 0.81 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:50:38 PM PST 24
Peak memory 182916 kb
Host smart-cdc1054e-2079-4edc-b2ea-be0dcd20110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158717102 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.1158717102
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2211740535
Short name T33
Test name
Test status
Simulation time 33119616388 ps
CPU time 25.29 seconds
Started Feb 28 04:50:41 PM PST 24
Finished Feb 28 04:51:06 PM PST 24
Peak memory 183060 kb
Host smart-6aaee7a8-fb57-425d-8757-2b3a307bde0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211740535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2211740535
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.1584554364
Short name T8
Test name
Test status
Simulation time 375568001 ps
CPU time 1.09 seconds
Started Feb 28 04:50:35 PM PST 24
Finished Feb 28 04:50:37 PM PST 24
Peak memory 182756 kb
Host smart-9cd38355-21a6-468d-b946-f1558e0cfe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584554364 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.1584554364
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3110742356
Short name T174
Test name
Test status
Simulation time 267013936536 ps
CPU time 113.79 seconds
Started Feb 28 04:50:41 PM PST 24
Finished Feb 28 04:52:35 PM PST 24
Peak memory 193072 kb
Host smart-786839aa-968c-402e-b6a7-c11392140034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110742356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3110742356
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.1792444561
Short name T172
Test name
Test status
Simulation time 158205663809 ps
CPU time 246.95 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 04:54:48 PM PST 24
Peak memory 198004 kb
Host smart-0b9c00fe-6836-4a2e-800f-4af7118865c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792444561 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.1792444561
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.4240665067
Short name T200
Test name
Test status
Simulation time 586420161 ps
CPU time 0.8 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:39 PM PST 24
Peak memory 182992 kb
Host smart-6fa7392f-7ff7-4027-8d0b-e8eac3ebcb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240665067 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.4240665067
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2615629423
Short name T146
Test name
Test status
Simulation time 52604161853 ps
CPU time 75.85 seconds
Started Feb 28 04:50:37 PM PST 24
Finished Feb 28 04:51:53 PM PST 24
Peak memory 183132 kb
Host smart-2733b67d-24cb-4251-8ad3-5bb0f643a3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615629423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2615629423
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.3233667591
Short name T1
Test name
Test status
Simulation time 584288431 ps
CPU time 1.5 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:40 PM PST 24
Peak memory 182900 kb
Host smart-ad594026-9893-4ca2-adec-f6188f9d94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233667591 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.3233667591
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.3640988946
Short name T124
Test name
Test status
Simulation time 75525462902 ps
CPU time 28 seconds
Started Feb 28 04:50:43 PM PST 24
Finished Feb 28 04:51:11 PM PST 24
Peak memory 183156 kb
Host smart-a1acf5f7-73a4-4fa4-b64d-32b227ddc37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640988946 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.3640988946
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.2938606372
Short name T103
Test name
Test status
Simulation time 117971296141 ps
CPU time 227.35 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:54:26 PM PST 24
Peak memory 198096 kb
Host smart-4fb7ba6c-897d-4460-886f-5d8d8458eca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938606372 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.2938606372
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.1256555350
Short name T207
Test name
Test status
Simulation time 369524261 ps
CPU time 0.71 seconds
Started Feb 28 04:50:38 PM PST 24
Finished Feb 28 04:50:39 PM PST 24
Peak memory 183064 kb
Host smart-e8c93244-ceda-460d-81ac-c61371bf6b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256555350 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.1256555350
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.982130182
Short name T161
Test name
Test status
Simulation time 25808137631 ps
CPU time 10.98 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 04:50:52 PM PST 24
Peak memory 183144 kb
Host smart-c9fb53c5-3b1b-438d-a89c-0a1687f9286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982130182 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.982130182
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3365434283
Short name T275
Test name
Test status
Simulation time 359179870 ps
CPU time 1.08 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 04:50:42 PM PST 24
Peak memory 183076 kb
Host smart-6da8ff5f-e9f0-4e4d-bb3b-3e9ddcc199c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365434283 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3365434283
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1776317200
Short name T225
Test name
Test status
Simulation time 242806159734 ps
CPU time 317.75 seconds
Started Feb 28 04:50:40 PM PST 24
Finished Feb 28 04:55:58 PM PST 24
Peak memory 194228 kb
Host smart-ad38d7ac-6985-43b9-8336-e1e11fb839df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776317200 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1776317200
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2623212486
Short name T100
Test name
Test status
Simulation time 103917415770 ps
CPU time 399.8 seconds
Started Feb 28 04:50:36 PM PST 24
Finished Feb 28 04:57:16 PM PST 24
Peak memory 198068 kb
Host smart-5e01e058-2edd-48f2-a5e9-be6e4908edb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623212486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2623212486
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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