Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

---

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	141	4	137	97.16

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	1	33	97.06	100	1	1	0
bite_thold_cp	34	1	33	97.06	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	0	34	100.00	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	34	1	33	97.06	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	26242	1		T1	116		T2	11		T3	10
bark[1]	948	1		T8	16		T71	12		T32	176
bark[2]	352	1		T26	83		T87	17		T74	117
bark[3]	757	1		T30	26		T88	16		T89	12
bark[4]	374	1		T8	17		T33	16		T90	17
bark[5]	441	1		T33	163		T91	16		T74	21
bark[6]	299	1		T1	16		T32	41		T33	81
bark[7]	486	1		T31	6		T88	16		T92	16
bark[8]	359	1		T31	17		T33	21		T93	211
bark[9]	656	1		T7	12		T15	16		T29	16
bark[10]	618	1		T15	16		T17	48		T38	12
bark[11]	628	1		T1	16		T13	12		T28	31
bark[12]	559	1		T10	16		T88	19		T91	16
bark[13]	560	1		T6	12		T17	16		T26	123
bark[14]	150	1		T26	12		T33	16		T94	16
bark[15]	190	1		T10	30		T29	17		T41	61
bark[16]	461	1		T10	16		T28	74		T95	12
bark[17]	520	1		T30	55		T96	17		T97	16
bark[18]	304	1		T8	37		T10	16		T15	17
bark[19]	222	1		T29	17		T40	29		T43	60
bark[20]	554	1		T28	65		T96	16		T98	12
bark[21]	294	1		T9	16		T40	16		T92	32
bark[22]	652	1		T8	6		T99	41		T96	57
bark[23]	280	1		T17	16		T26	16		T32	81
bark[24]	335	1		T10	32		T16	16		T28	17
bark[25]	895	1		T1	33		T28	16		T29	121
bark[26]	177	1		T5	16		T46	12		T100	26
bark[27]	697	1		T8	82		T14	13		T26	16
bark[28]	1100	1		T35	13		T31	16		T101	12
bark[29]	1258	1		T8	95		T17	165		T87	17
bark[30]	578	1		T26	41		T28	16		T33	218
bark[31]	1117	1		T10	22		T36	16		T41	12
bark_0	3866	1		T1	4		T2	4		T3	4

---

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	25576	1		T1	104		T2	10		T3	9
bite[1]	215	1		T89	11		T32	80		T87	17
bite[2]	467	1		T72	17		T102	12		T97	16
bite[3]	480	1		T8	81		T14	12		T78	17
bite[4]	614	1		T28	73		T29	17		T93	17
bite[5]	444	1		T41	11		T100	26		T93	16
bite[6]	214	1		T28	64		T36	32		T33	16
bite[7]	803	1		T15	17		T40	56		T43	60
bite[8]	537	1		T1	16		T8	5		T17	164
bite[9]	395	1		T26	40		T30	65		T88	16
bite[10]	556	1		T7	11		T26	11		T31	16
bite[11]	859	1		T9	16		T10	30		T17	16
bite[12]	489	1		T42	11		T92	17		T91	16
bite[13]	363	1		T1	44		T8	36		T35	12
bite[14]	836	1		T97	17		T74	34		T103	11
bite[15]	554	1		T10	16		T28	16		T43	17
bite[16]	351	1		T10	16		T33	16		T97	16
bite[17]	197	1		T8	16		T10	48		T79	23
bite[18]	708	1		T26	82		T28	31		T87	17
bite[19]	436	1		T8	17		T32	175		T99	16
bite[20]	848	1		T16	16		T71	11		T88	30
bite[21]	835	1		T38	11		T104	11		T90	17
bite[22]	1041	1		T5	16		T17	47		T36	32
bite[23]	370	1		T6	11		T26	16		T32	20
bite[24]	400	1		T1	16		T13	11		T28	17
bite[25]	420	1		T43	47		T96	17		T97	16
bite[26]	591	1		T8	94		T17	16		T26	122
bite[27]	394	1		T88	17		T32	36		T105	16
bite[28]	763	1		T15	32		T26	16		T28	16
bite[29]	485	1		T28	51		T30	26		T88	18
bite[30]	784	1		T10	22		T28	184		T40	16
bite[31]	430	1		T29	17		T99	31		T96	16
bite_0	4474	1		T1	5		T2	5		T3	5

---

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	46929	1		T1	185		T2	15		T3	14

---

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	0	34	100.00

User Defined Bins for prescale_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale_max	2	1		T106	2		-	-		-	-
prescale[0]	859	1		T5	51		T8	71		T17	14
prescale[1]	944	1		T8	53		T17	122		T28	40
prescale[2]	1067	1		T15	15		T28	111		T32	93
prescale[3]	706	1		T5	15		T8	45		T12	8
prescale[4]	784	1		T5	15		T16	22		T17	2
prescale[5]	966	1		T5	54		T8	2		T17	16
prescale[6]	514	1		T8	16		T16	46		T17	60
prescale[7]	671	1		T36	8		T31	2		T33	123
prescale[8]	559	1		T5	25		T16	31		T17	53
prescale[9]	695	1		T5	15		T8	2		T9	15
prescale[10]	1110	1		T15	18		T28	29		T29	30
prescale[11]	1077	1		T1	18		T5	25		T10	18
prescale[12]	466	1		T8	15		T17	31		T29	40
prescale[13]	541	1		T17	2		T91	15		T93	35
prescale[14]	977	1		T16	15		T17	57		T31	15
prescale[15]	432	1		T5	29		T17	15		T26	2
prescale[16]	334	1		T92	2		T72	18		T93	29
prescale[17]	896	1		T5	86		T28	76		T31	47
prescale[18]	503	1		T5	2		T29	2		T32	2
prescale[19]	526	1		T8	15		T9	18		T26	2
prescale[20]	1245	1		T28	132		T31	2		T40	18
prescale[21]	754	1		T8	80		T10	38		T26	2
prescale[22]	548	1		T8	2		T17	2		T31	2
prescale[23]	641	1		T5	40		T8	8		T15	15
prescale[24]	509	1		T26	4		T29	2		T39	8
prescale[25]	563	1		T5	2		T10	15		T16	15
prescale[26]	369	1		T8	2		T17	23		T28	126
prescale[27]	754	1		T16	25		T17	15		T28	61
prescale[28]	448	1		T8	2		T17	15		T29	39
prescale[29]	528	1		T5	36		T8	39		T9	15
prescale[30]	766	1		T5	38		T8	15		T17	15
prescale[31]	802	1		T1	18		T17	54		T26	40
prescale_0	24375	1		T1	149		T2	15		T3	14

---

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34200	1		T1	90		T2	6		T3	6
auto[1]	12729	1		T1	95		T2	9		T3	8

---

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	46929	1		T1	185		T2	15		T3	14

---

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	27360	1		T1	88		T2	12		T3	11
wkup[1]	719	1		T15	17		T17	84		T28	16
wkup[2]	635	1		T6	13		T8	37		T13	13
wkup[3]	453	1		T28	13		T31	16		T88	20
wkup[4]	440	1		T30	16		T33	53		T72	16
wkup[5]	465	1		T26	16		T28	16		T38	13
wkup[6]	756	1		T5	16		T8	16		T17	27
wkup[7]	549	1		T8	51		T26	21		T28	21
wkup[8]	440	1		T5	21		T8	16		T10	16
wkup[9]	461	1		T8	16		T10	16		T34	13
wkup[10]	645	1		T1	33		T26	33		T28	16
wkup[11]	498	1		T8	37		T15	16		T36	16
wkup[12]	425	1		T10	16		T26	13		T28	16
wkup[13]	593	1		T1	16		T5	16		T17	16
wkup[14]	553	1		T7	13		T16	16		T26	17
wkup[15]	488	1		T26	34		T31	16		T41	16
wkup[16]	473	1		T1	16		T5	26		T17	16
wkup[17]	535	1		T28	32		T35	14		T99	16
wkup[18]	494	1		T5	13		T8	16		T40	34
wkup[19]	669	1		T1	13		T5	16		T17	16
wkup[20]	427	1		T1	16		T17	16		T26	16
wkup[21]	439	1		T8	7		T32	16		T100	26
wkup[22]	529	1		T5	16		T10	22		T17	27
wkup[23]	340	1		T10	16		T32	16		T33	17
wkup[24]	446	1		T26	16		T28	16		T88	16
wkup[25]	597	1		T15	16		T36	36		T29	17
wkup[26]	759	1		T8	33		T26	32		T28	47
wkup[27]	502	1		T9	16		T10	16		T26	16
wkup[28]	675	1		T9	16		T17	16		T28	48
wkup[29]	283	1		T10	16		T17	13		T32	13
wkup[30]	486	1		T14	14		T28	32		T36	16
wkup[31]	474	1		T16	16		T30	16		T31	16
wkup_0	3321	1		T1	3		T2	3		T3	3