Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.56 99.82 95.31 100.00 99.35 100.00 96.90


Total test records in report: 430
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T283 /workspace/coverage/default/7.aon_timer_smoke.3659947356 Feb 29 12:42:14 PM PST 24 Feb 29 12:42:15 PM PST 24 535267727 ps
T284 /workspace/coverage/default/44.aon_timer_prescaler.730686509 Feb 29 12:42:15 PM PST 24 Feb 29 12:43:11 PM PST 24 38723039410 ps
T285 /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3981579527 Feb 29 12:42:19 PM PST 24 Feb 29 12:52:13 PM PST 24 111848494074 ps
T286 /workspace/coverage/default/9.aon_timer_stress_all.212551694 Feb 29 12:41:48 PM PST 24 Feb 29 12:44:32 PM PST 24 217487880252 ps
T287 /workspace/coverage/default/21.aon_timer_jump.3189205128 Feb 29 12:42:11 PM PST 24 Feb 29 12:42:12 PM PST 24 352565254 ps
T23 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3201736441 Feb 29 12:41:09 PM PST 24 Feb 29 12:41:14 PM PST 24 7942842880 ps
T24 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1310967547 Feb 29 12:40:41 PM PST 24 Feb 29 12:40:49 PM PST 24 8190947733 ps
T27 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.98199113 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:47 PM PST 24 481754236 ps
T25 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3896205134 Feb 29 12:40:41 PM PST 24 Feb 29 12:40:49 PM PST 24 4661168365 ps
T83 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4218213365 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:54 PM PST 24 4479560508 ps
T288 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3390042108 Feb 29 12:41:18 PM PST 24 Feb 29 12:41:19 PM PST 24 271690989 ps
T62 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2303847551 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:50 PM PST 24 1927298389 ps
T289 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4200381031 Feb 29 12:40:59 PM PST 24 Feb 29 12:41:01 PM PST 24 652742905 ps
T290 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3603335697 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:07 PM PST 24 465272044 ps
T48 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4246878378 Feb 29 12:40:35 PM PST 24 Feb 29 12:40:41 PM PST 24 521235524 ps
T49 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2999431279 Feb 29 12:40:36 PM PST 24 Feb 29 12:40:37 PM PST 24 326046830 ps
T291 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1828395370 Feb 29 12:40:42 PM PST 24 Feb 29 12:40:43 PM PST 24 309709339 ps
T292 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2822525300 Feb 29 12:41:05 PM PST 24 Feb 29 12:41:06 PM PST 24 314966162 ps
T293 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2859165970 Feb 29 12:41:14 PM PST 24 Feb 29 12:41:16 PM PST 24 492636479 ps
T294 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3611271183 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:52 PM PST 24 449694562 ps
T295 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.968370451 Feb 29 12:41:18 PM PST 24 Feb 29 12:41:19 PM PST 24 484149478 ps
T84 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2150286800 Feb 29 12:40:49 PM PST 24 Feb 29 12:41:05 PM PST 24 8794741186 ps
T50 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3083886171 Feb 29 12:41:20 PM PST 24 Feb 29 12:41:22 PM PST 24 297951057 ps
T296 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2835308589 Feb 29 12:41:02 PM PST 24 Feb 29 12:41:03 PM PST 24 276708389 ps
T297 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.488327210 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:45 PM PST 24 544457147 ps
T298 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2737981963 Feb 29 12:41:26 PM PST 24 Feb 29 12:41:27 PM PST 24 340190854 ps
T63 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3746281778 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:54 PM PST 24 2047501890 ps
T51 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4120905744 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:51 PM PST 24 522488495 ps
T107 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.703812416 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:52 PM PST 24 4517646752 ps
T64 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3286562461 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:59 PM PST 24 1944177982 ps
T299 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3247753567 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:07 PM PST 24 304289215 ps
T300 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1538078471 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:57 PM PST 24 445891238 ps
T52 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3571521964 Feb 29 12:40:54 PM PST 24 Feb 29 12:40:56 PM PST 24 274725357 ps
T301 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4149897779 Feb 29 12:41:04 PM PST 24 Feb 29 12:41:06 PM PST 24 472458489 ps
T65 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1204392031 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:55 PM PST 24 2703025458 ps
T302 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1092572605 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:07 PM PST 24 522294390 ps
T53 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4272100134 Feb 29 12:40:54 PM PST 24 Feb 29 12:40:55 PM PST 24 315922871 ps
T303 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.741415727 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:53 PM PST 24 809509105 ps
T304 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1328780825 Feb 29 12:40:54 PM PST 24 Feb 29 12:40:55 PM PST 24 495902583 ps
T305 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1028774085 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:26 PM PST 24 433389960 ps
T306 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4234761442 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:12 PM PST 24 7964059481 ps
T66 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1824565071 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:48 PM PST 24 2212983978 ps
T67 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.307408708 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 1203548674 ps
T54 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1968034431 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:49 PM PST 24 333691883 ps
T307 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2082021252 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:08 PM PST 24 383534136 ps
T308 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3053177297 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:50 PM PST 24 402833210 ps
T68 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.323827808 Feb 29 12:40:38 PM PST 24 Feb 29 12:40:41 PM PST 24 1204690257 ps
T309 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.614559280 Feb 29 12:41:16 PM PST 24 Feb 29 12:41:17 PM PST 24 281461354 ps
T69 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.571091878 Feb 29 12:41:17 PM PST 24 Feb 29 12:41:18 PM PST 24 494473059 ps
T55 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2620148598 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:57 PM PST 24 534521049 ps
T70 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3128716748 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:52 PM PST 24 1420071787 ps
T310 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1898238487 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:52 PM PST 24 1050809937 ps
T311 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2634266522 Feb 29 12:41:11 PM PST 24 Feb 29 12:41:14 PM PST 24 437499216 ps
T56 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2205594697 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:47 PM PST 24 3700651538 ps
T312 /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2153460674 Feb 29 12:40:58 PM PST 24 Feb 29 12:40:59 PM PST 24 459069075 ps
T85 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1187398891 Feb 29 12:40:57 PM PST 24 Feb 29 12:40:59 PM PST 24 4578044309 ps
T313 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2042960347 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 460257541 ps
T314 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.188331047 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 1001654828 ps
T315 /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1817177069 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:53 PM PST 24 1333383709 ps
T316 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3778205739 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:53 PM PST 24 355250034 ps
T317 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3234918081 Feb 29 12:41:18 PM PST 24 Feb 29 12:41:20 PM PST 24 427509552 ps
T318 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.463758318 Feb 29 12:40:27 PM PST 24 Feb 29 12:40:28 PM PST 24 339060952 ps
T319 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3414791397 Feb 29 12:40:33 PM PST 24 Feb 29 12:40:34 PM PST 24 389706456 ps
T320 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.282898814 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:57 PM PST 24 456670933 ps
T321 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3341227846 Feb 29 12:40:54 PM PST 24 Feb 29 12:40:55 PM PST 24 628133818 ps
T322 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3382129901 Feb 29 12:40:43 PM PST 24 Feb 29 12:40:44 PM PST 24 356787027 ps
T323 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1163010951 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:49 PM PST 24 8894832150 ps
T324 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4013990492 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:57 PM PST 24 664954973 ps
T325 /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4154556782 Feb 29 12:41:06 PM PST 24 Feb 29 12:41:07 PM PST 24 341777954 ps
T326 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3694663467 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:54 PM PST 24 444388020 ps
T327 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1205714548 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:49 PM PST 24 529490592 ps
T328 /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1285718201 Feb 29 12:41:10 PM PST 24 Feb 29 12:41:12 PM PST 24 495489942 ps
T329 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2388150563 Feb 29 12:41:12 PM PST 24 Feb 29 12:41:13 PM PST 24 446189775 ps
T330 /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.22186369 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:45 PM PST 24 273560635 ps
T331 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4263006877 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:48 PM PST 24 1230263941 ps
T332 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3312147524 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:49 PM PST 24 419849560 ps
T57 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2589879500 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:56 PM PST 24 360977349 ps
T333 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2554327615 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:03 PM PST 24 441465283 ps
T334 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2170033338 Feb 29 12:41:04 PM PST 24 Feb 29 12:41:12 PM PST 24 577892699 ps
T335 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.389327066 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:51 PM PST 24 1338234420 ps
T58 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1992965900 Feb 29 12:40:57 PM PST 24 Feb 29 12:40:58 PM PST 24 534500998 ps
T336 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1461714380 Feb 29 12:41:05 PM PST 24 Feb 29 12:41:07 PM PST 24 280800237 ps
T337 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.34560415 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:52 PM PST 24 492856953 ps
T338 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3204652965 Feb 29 12:40:56 PM PST 24 Feb 29 12:41:02 PM PST 24 3681736301 ps
T86 /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.801087615 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:51 PM PST 24 8381895482 ps
T339 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2299390539 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:50 PM PST 24 462455000 ps
T340 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3574757554 Feb 29 12:40:42 PM PST 24 Feb 29 12:40:43 PM PST 24 1147662363 ps
T59 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3278038231 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:46 PM PST 24 454133178 ps
T341 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2510707381 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:57 PM PST 24 3989150574 ps
T342 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2850667147 Feb 29 12:40:41 PM PST 24 Feb 29 12:40:42 PM PST 24 431965187 ps
T343 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3351297841 Feb 29 12:40:58 PM PST 24 Feb 29 12:40:59 PM PST 24 320977285 ps
T344 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3151782996 Feb 29 12:40:43 PM PST 24 Feb 29 12:40:44 PM PST 24 665639308 ps
T345 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2023327885 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:50 PM PST 24 798559409 ps
T346 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3914159292 Feb 29 12:40:40 PM PST 24 Feb 29 12:40:41 PM PST 24 388886269 ps
T347 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2743369952 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:55 PM PST 24 1012599135 ps
T348 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1992463109 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 469171234 ps
T349 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1973603229 Feb 29 12:40:59 PM PST 24 Feb 29 12:41:02 PM PST 24 2034654214 ps
T350 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3111178663 Feb 29 12:41:18 PM PST 24 Feb 29 12:41:20 PM PST 24 453398356 ps
T351 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3019391940 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:45 PM PST 24 458106741 ps
T352 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1847625345 Feb 29 12:40:54 PM PST 24 Feb 29 12:40:56 PM PST 24 392876635 ps
T60 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.684117592 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:57 PM PST 24 420725572 ps
T353 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4223148635 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 496750946 ps
T354 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1161865777 Feb 29 12:41:02 PM PST 24 Feb 29 12:41:04 PM PST 24 455835038 ps
T355 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.925885662 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:03 PM PST 24 454982400 ps
T356 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2064842993 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:47 PM PST 24 441471914 ps
T357 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1910181196 Feb 29 12:41:11 PM PST 24 Feb 29 12:41:16 PM PST 24 8931156925 ps
T358 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1086618351 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:03 PM PST 24 340678786 ps
T61 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3530743142 Feb 29 12:40:54 PM PST 24 Feb 29 12:41:09 PM PST 24 11594321842 ps
T359 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3607290445 Feb 29 12:40:59 PM PST 24 Feb 29 12:41:01 PM PST 24 437325994 ps
T360 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1912941040 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:54 PM PST 24 4321301523 ps
T361 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4110211999 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:49 PM PST 24 589307733 ps
T362 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3887755358 Feb 29 12:40:53 PM PST 24 Feb 29 12:41:00 PM PST 24 8074734315 ps
T363 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1498682191 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:54 PM PST 24 493946679 ps
T364 /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1027420979 Feb 29 12:40:58 PM PST 24 Feb 29 12:40:59 PM PST 24 919542175 ps
T365 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4001097048 Feb 29 12:41:15 PM PST 24 Feb 29 12:41:16 PM PST 24 306488332 ps
T366 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1119554085 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:51 PM PST 24 378860082 ps
T367 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2042725331 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:56 PM PST 24 471380649 ps
T368 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1987660653 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 373447228 ps
T369 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.794970945 Feb 29 12:41:13 PM PST 24 Feb 29 12:41:14 PM PST 24 533896100 ps
T370 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2619267808 Feb 29 12:40:32 PM PST 24 Feb 29 12:40:33 PM PST 24 434807394 ps
T371 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3335664243 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:53 PM PST 24 4511936461 ps
T372 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3353175855 Feb 29 12:40:57 PM PST 24 Feb 29 12:40:58 PM PST 24 656849445 ps
T373 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2526955560 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:46 PM PST 24 399964283 ps
T374 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3553608488 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:03 PM PST 24 453841431 ps
T375 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3274399823 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:50 PM PST 24 550953467 ps
T376 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.25832077 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:50 PM PST 24 317998345 ps
T377 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.894535386 Feb 29 12:41:15 PM PST 24 Feb 29 12:41:18 PM PST 24 1246514661 ps
T378 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4161550661 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:56 PM PST 24 490260096 ps
T379 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2182667051 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:51 PM PST 24 455566846 ps
T380 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3826089160 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:59 PM PST 24 4710491330 ps
T381 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.782293099 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:58 PM PST 24 4123410977 ps
T382 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.865619626 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:45 PM PST 24 567144455 ps
T383 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1684011229 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:49 PM PST 24 472359764 ps
T384 /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1009898727 Feb 29 12:41:15 PM PST 24 Feb 29 12:41:17 PM PST 24 295279443 ps
T385 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1044293926 Feb 29 12:40:58 PM PST 24 Feb 29 12:40:59 PM PST 24 533746282 ps
T386 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.740610070 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:59 PM PST 24 2218409144 ps
T387 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2919203085 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 408433305 ps
T388 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.739257756 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:49 PM PST 24 1176473195 ps
T389 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.654450400 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:48 PM PST 24 410738636 ps
T390 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2811365727 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:50 PM PST 24 484385130 ps
T391 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2974333126 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 454056426 ps
T392 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1716334209 Feb 29 12:40:55 PM PST 24 Feb 29 12:41:01 PM PST 24 524221477 ps
T393 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2993758917 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:57 PM PST 24 678058544 ps
T394 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1946689843 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:56 PM PST 24 331091442 ps
T395 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2780250207 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:04 PM PST 24 2385910551 ps
T396 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2068276343 Feb 29 12:40:47 PM PST 24 Feb 29 12:40:49 PM PST 24 1340653559 ps
T397 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.832729687 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:54 PM PST 24 595089331 ps
T398 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4192583782 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:56 PM PST 24 356457947 ps
T399 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1568525412 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 341400187 ps
T400 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.435682008 Feb 29 12:40:43 PM PST 24 Feb 29 12:40:44 PM PST 24 317499981 ps
T401 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.252155618 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:05 PM PST 24 345855184 ps
T402 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2337293789 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:49 PM PST 24 306793997 ps
T403 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2180074126 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:51 PM PST 24 302757943 ps
T404 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1766783729 Feb 29 12:40:46 PM PST 24 Feb 29 12:40:47 PM PST 24 460654426 ps
T405 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3287308401 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:46 PM PST 24 492903659 ps
T406 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3413987607 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:47 PM PST 24 462390619 ps
T407 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1407232412 Feb 29 12:41:16 PM PST 24 Feb 29 12:41:17 PM PST 24 316996234 ps
T408 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2222491327 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:55 PM PST 24 522037744 ps
T409 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.387790471 Feb 29 12:40:59 PM PST 24 Feb 29 12:41:01 PM PST 24 528283537 ps
T410 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3393216811 Feb 29 12:40:55 PM PST 24 Feb 29 12:40:56 PM PST 24 573240681 ps
T411 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3505052065 Feb 29 12:40:58 PM PST 24 Feb 29 12:40:59 PM PST 24 605826263 ps
T412 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1131121437 Feb 29 12:41:00 PM PST 24 Feb 29 12:41:01 PM PST 24 518771365 ps
T413 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2317986149 Feb 29 12:40:58 PM PST 24 Feb 29 12:41:00 PM PST 24 483997019 ps
T414 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3117306480 Feb 29 12:41:13 PM PST 24 Feb 29 12:41:15 PM PST 24 980140138 ps
T415 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1911761286 Feb 29 12:40:55 PM PST 24 Feb 29 12:41:01 PM PST 24 10590432932 ps
T416 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1503512184 Feb 29 12:40:55 PM PST 24 Feb 29 12:41:03 PM PST 24 4418974197 ps
T417 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.528742190 Feb 29 12:40:56 PM PST 24 Feb 29 12:40:58 PM PST 24 648954014 ps
T418 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2727471383 Feb 29 12:40:59 PM PST 24 Feb 29 12:41:00 PM PST 24 405295921 ps
T419 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1914445583 Feb 29 12:40:44 PM PST 24 Feb 29 12:40:45 PM PST 24 427150346 ps
T420 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1498607151 Feb 29 12:40:49 PM PST 24 Feb 29 12:40:53 PM PST 24 4313522610 ps
T421 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3494036320 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 511985165 ps
T422 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4222972777 Feb 29 12:40:41 PM PST 24 Feb 29 12:40:43 PM PST 24 424032529 ps
T423 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1987850221 Feb 29 12:40:51 PM PST 24 Feb 29 12:40:52 PM PST 24 278170831 ps
T424 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2152203067 Feb 29 12:40:45 PM PST 24 Feb 29 12:40:47 PM PST 24 576769711 ps
T425 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.327232111 Feb 29 12:40:52 PM PST 24 Feb 29 12:40:54 PM PST 24 349234220 ps
T426 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2288656448 Feb 29 12:40:50 PM PST 24 Feb 29 12:40:54 PM PST 24 574095145 ps
T427 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3211083902 Feb 29 12:40:53 PM PST 24 Feb 29 12:40:54 PM PST 24 1954323899 ps
T428 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.115426558 Feb 29 12:41:01 PM PST 24 Feb 29 12:41:04 PM PST 24 337917125 ps
T429 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3387042826 Feb 29 12:40:41 PM PST 24 Feb 29 12:40:42 PM PST 24 370423662 ps
T430 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2340227207 Feb 29 12:40:48 PM PST 24 Feb 29 12:40:57 PM PST 24 3154347517 ps

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.4067715187
Short name T8
Test name
Test status
Simulation time 161015614486 ps
CPU time 873.8 seconds
Started Feb 29 12:41:53 PM PST 24
Finished Feb 29 12:56:28 PM PST 24
Peak memory 202864 kb
Host smart-35c14db7-3356-4fd5-9506-2af534bf47e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067715187 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.4067715187
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.4060713053
Short name T10
Test name
Test status
Simulation time 167280942191 ps
CPU time 34.39 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 183052 kb
Host smart-bda771a9-1d22-434d-8a73-0d35fef51cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060713053 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.4060713053
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all_with_rand_reset.3534325431
Short name T28
Test name
Test status
Simulation time 28545705890 ps
CPU time 198.86 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:45:27 PM PST 24
Peak memory 198224 kb
Host smart-cefc684b-5d3e-4dc8-ab09-5b0c4bf77ad7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534325431 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_all_with_rand_reset.3534325431
Directory /workspace/40.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.3201736441
Short name T23
Test name
Test status
Simulation time 7942842880 ps
CPU time 4.3 seconds
Started Feb 29 12:41:09 PM PST 24
Finished Feb 29 12:41:14 PM PST 24
Peak memory 197172 kb
Host smart-807cff49-f388-4f3f-ba67-8787476c19b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201736441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_t
l_intg_err.3201736441
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.4258288761
Short name T33
Test name
Test status
Simulation time 281705710108 ps
CPU time 353.33 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:47:52 PM PST 24
Peak memory 197912 kb
Host smart-bc4b387a-9b3c-439f-af55-a391ff4c6a2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258288761 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.4258288761
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all_with_rand_reset.1322491229
Short name T32
Test name
Test status
Simulation time 96201193792 ps
CPU time 516.49 seconds
Started Feb 29 12:42:19 PM PST 24
Finished Feb 29 12:50:55 PM PST 24
Peak memory 197956 kb
Host smart-bb60ce60-6449-4291-93e2-cb1f45a99f5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322491229 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_all_with_rand_reset.1322491229
Directory /workspace/38.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.2942868486
Short name T93
Test name
Test status
Simulation time 20049327466 ps
CPU time 101.21 seconds
Started Feb 29 12:42:09 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 197932 kb
Host smart-c5932135-8061-4556-96ae-d5e78ed5febe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942868486 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.2942868486
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.4163445051
Short name T81
Test name
Test status
Simulation time 117644186505 ps
CPU time 474.08 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:50:10 PM PST 24
Peak memory 197932 kb
Host smart-1a3179b2-0ca9-4869-98b1-283fb334c11e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163445051 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.4163445051
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1757132610
Short name T21
Test name
Test status
Simulation time 4329053681 ps
CPU time 2.39 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 215164 kb
Host smart-81987933-54ce-4f34-9ae2-27cb8390e138
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757132610 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1757132610
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.3615818955
Short name T97
Test name
Test status
Simulation time 275462920150 ps
CPU time 239.73 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:46:10 PM PST 24
Peak memory 182936 kb
Host smart-801e003a-3774-4473-bff2-bd89d99bda7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615818955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_
all.3615818955
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.790561948
Short name T17
Test name
Test status
Simulation time 331115312803 ps
CPU time 582.8 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:51:45 PM PST 24
Peak memory 198556 kb
Host smart-0f2cb2fe-e101-4b32-9af7-8454622a1fc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790561948 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.790561948
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.1968034431
Short name T54
Test name
Test status
Simulation time 333691883 ps
CPU time 1.06 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 190336 kb
Host smart-16227534-bc29-41e6-a376-1cbb3a31fd69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968034431 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.1968034431
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all.1010729770
Short name T197
Test name
Test status
Simulation time 216314034664 ps
CPU time 39.19 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:54 PM PST 24
Peak memory 182976 kb
Host smart-12c90631-bb79-4607-ba44-2acf67af92e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010729770 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_
all.1010729770
Directory /workspace/25.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.2303847551
Short name T62
Test name
Test status
Simulation time 1927298389 ps
CPU time 2.22 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 191760 kb
Host smart-54537806-ad2f-4369-9e29-cd5f8bf40451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303847551 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon
_timer_same_csr_outstanding.2303847551
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.1912941040
Short name T360
Test name
Test status
Simulation time 4321301523 ps
CPU time 2.73 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 195376 kb
Host smart-0016fd40-0c38-456d-95fd-5c34c078b18d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912941040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.1912941040
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all_with_rand_reset.724091621
Short name T222
Test name
Test status
Simulation time 103900696275 ps
CPU time 235.05 seconds
Started Feb 29 12:41:51 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 198020 kb
Host smart-32e095d0-1293-4f95-b318-3c95b6431e66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724091621 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_all_with_rand_reset.724091621
Directory /workspace/0.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.26709209
Short name T106
Test name
Test status
Simulation time 69976224038 ps
CPU time 741.32 seconds
Started Feb 29 12:42:09 PM PST 24
Finished Feb 29 12:54:31 PM PST 24
Peak memory 205980 kb
Host smart-6362345b-9333-42b3-b3ae-a8b196b5b867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709209 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.26709209
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.281493358
Short name T155
Test name
Test status
Simulation time 33558492764 ps
CPU time 271.69 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:46:50 PM PST 24
Peak memory 197832 kb
Host smart-d00d1d42-dc73-4e03-aa40-f805fe4b24bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281493358 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.281493358
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.4120905744
Short name T51
Test name
Test status
Simulation time 522488495 ps
CPU time 2.41 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 183008 kb
Host smart-e0631133-a9c5-4c39-a4dc-427b1037a416
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120905744 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_b
it_bash.4120905744
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.2023327885
Short name T345
Test name
Test status
Simulation time 798559409 ps
CPU time 0.82 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 183004 kb
Host smart-3cd5d558-fe6f-4f70-8530-8bc3aea95f47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023327885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_h
w_reset.2023327885
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.98199113
Short name T27
Test name
Test status
Simulation time 481754236 ps
CPU time 1.25 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 194752 kb
Host smart-a6b69c90-f7cb-4397-9cae-bbebafc97fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98199113 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.98199113
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.2811365727
Short name T390
Test name
Test status
Simulation time 484385130 ps
CPU time 0.92 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 183368 kb
Host smart-1a98a425-763e-483a-a9b7-6dd16b4ed5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811365727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.2811365727
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.463758318
Short name T318
Test name
Test status
Simulation time 339060952 ps
CPU time 0.76 seconds
Started Feb 29 12:40:27 PM PST 24
Finished Feb 29 12:40:28 PM PST 24
Peak memory 183268 kb
Host smart-eb24f5e2-8488-48ed-b48a-b3d44316274c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463758318 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.463758318
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.1766783729
Short name T404
Test name
Test status
Simulation time 460654426 ps
CPU time 0.83 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 183032 kb
Host smart-87ecbe7d-e4c4-41f8-8827-93cad9731c5b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766783729 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.1766783729
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.3414791397
Short name T319
Test name
Test status
Simulation time 389706456 ps
CPU time 0.66 seconds
Started Feb 29 12:40:33 PM PST 24
Finished Feb 29 12:40:34 PM PST 24
Peak memory 183036 kb
Host smart-55fcd286-961f-44aa-ad48-0d45d36bcf3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414791397 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.3414791397
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.2288656448
Short name T426
Test name
Test status
Simulation time 574095145 ps
CPU time 2.88 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 198148 kb
Host smart-336c75cb-7c6e-4f34-b863-7d1a1d4af17a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288656448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.2288656448
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.3896205134
Short name T25
Test name
Test status
Simulation time 4661168365 ps
CPU time 7.34 seconds
Started Feb 29 12:40:41 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 196268 kb
Host smart-81d7a9ed-e57a-4867-af26-37eebe6a6dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896205134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.3896205134
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.4246878378
Short name T48
Test name
Test status
Simulation time 521235524 ps
CPU time 1.06 seconds
Started Feb 29 12:40:35 PM PST 24
Finished Feb 29 12:40:41 PM PST 24
Peak memory 183384 kb
Host smart-c4cee2f6-e960-44d7-aebf-d1c93e74b08b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246878378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.4246878378
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.2205594697
Short name T56
Test name
Test status
Simulation time 3700651538 ps
CPU time 3.86 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 183596 kb
Host smart-9ceb3b4f-9571-4f2d-8d22-a7eb19f155f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205594697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.2205594697
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.2068276343
Short name T396
Test name
Test status
Simulation time 1340653559 ps
CPU time 1.69 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 180952 kb
Host smart-6dd16fb0-1e50-4311-bc48-4b7073da26e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068276343 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_h
w_reset.2068276343
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.2619267808
Short name T370
Test name
Test status
Simulation time 434807394 ps
CPU time 0.79 seconds
Started Feb 29 12:40:32 PM PST 24
Finished Feb 29 12:40:33 PM PST 24
Peak memory 195112 kb
Host smart-6cd19c52-aabf-438b-9c47-169f56da076c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619267808 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.2619267808
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.2337293789
Short name T402
Test name
Test status
Simulation time 306793997 ps
CPU time 0.72 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 183424 kb
Host smart-87902266-77c2-4092-833e-9f07d0f8885a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337293789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.2337293789
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.2850667147
Short name T342
Test name
Test status
Simulation time 431965187 ps
CPU time 0.68 seconds
Started Feb 29 12:40:41 PM PST 24
Finished Feb 29 12:40:42 PM PST 24
Peak memory 182972 kb
Host smart-1f25fb60-d22f-49e3-a605-a7e7cecbf7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850667147 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.2850667147
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.865619626
Short name T382
Test name
Test status
Simulation time 567144455 ps
CPU time 0.58 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:45 PM PST 24
Peak memory 182912 kb
Host smart-733793b4-fe8e-4414-b098-0b7ba06f0d1f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865619626 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_ti
mer_mem_partial_access.865619626
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.25832077
Short name T376
Test name
Test status
Simulation time 317998345 ps
CPU time 0.99 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 183324 kb
Host smart-80dfc29d-c707-48ea-bf7a-d5e7549cb262
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25832077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_wal
k.25832077
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.323827808
Short name T68
Test name
Test status
Simulation time 1204690257 ps
CPU time 2.44 seconds
Started Feb 29 12:40:38 PM PST 24
Finished Feb 29 12:40:41 PM PST 24
Peak memory 193824 kb
Host smart-4aa3eba1-dbaf-418e-8bb5-44bcfd18ad66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323827808 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_
timer_same_csr_outstanding.323827808
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.739257756
Short name T388
Test name
Test status
Simulation time 1176473195 ps
CPU time 2.37 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 198484 kb
Host smart-52b9d2ef-9af7-405e-ae16-ae9fb693cdc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739257756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.739257756
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.3335664243
Short name T371
Test name
Test status
Simulation time 4511936461 ps
CPU time 2.58 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:53 PM PST 24
Peak memory 196816 kb
Host smart-fa359748-d2ed-4ffa-91e8-13c5b5c3c2c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335664243 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.3335664243
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.3312147524
Short name T332
Test name
Test status
Simulation time 419849560 ps
CPU time 1.18 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 194312 kb
Host smart-66b476d7-b98c-4d77-9795-5f17eb2cfc33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312147524 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.3312147524
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.3019391940
Short name T351
Test name
Test status
Simulation time 458106741 ps
CPU time 0.76 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:45 PM PST 24
Peak memory 183352 kb
Host smart-2710cf1a-4e4a-41d7-acb8-5082dda2e981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019391940 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.3019391940
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.3778205739
Short name T316
Test name
Test status
Simulation time 355250034 ps
CPU time 1.09 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:53 PM PST 24
Peak memory 182996 kb
Host smart-46a1e2ef-2e20-4389-8748-26a2b9e04893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778205739 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.3778205739
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1204392031
Short name T65
Test name
Test status
Simulation time 2703025458 ps
CPU time 2.44 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 194812 kb
Host smart-8d87194e-d178-44da-8dce-a5249e9f2928
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204392031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1204392031
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.3413987607
Short name T406
Test name
Test status
Simulation time 462390619 ps
CPU time 2.21 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 198032 kb
Host smart-597931bf-0d6b-4ee3-b4af-20d0372f2f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413987607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.3413987607
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.1131121437
Short name T412
Test name
Test status
Simulation time 518771365 ps
CPU time 0.84 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 195072 kb
Host smart-7fffe201-6693-4a6a-83fa-86a5d1bd393a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131121437 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.1131121437
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.1992463109
Short name T348
Test name
Test status
Simulation time 469171234 ps
CPU time 1.28 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 183332 kb
Host smart-aa6615b4-d534-471a-a360-6887b3d91701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992463109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.1992463109
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.4192583782
Short name T398
Test name
Test status
Simulation time 356457947 ps
CPU time 1.07 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183032 kb
Host smart-c65adcfc-8737-4312-a9c3-247ef03b66e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192583782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.4192583782
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.1898238487
Short name T310
Test name
Test status
Simulation time 1050809937 ps
CPU time 2.43 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 193736 kb
Host smart-87c6d4f7-a185-4ba3-a0bf-06734edc0d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898238487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.1898238487
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.3053177297
Short name T308
Test name
Test status
Simulation time 402833210 ps
CPU time 2.04 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 198208 kb
Host smart-d7db81d1-098b-4f63-8118-2f4bf800fe47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053177297 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.3053177297
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.4218213365
Short name T83
Test name
Test status
Simulation time 4479560508 ps
CPU time 7.73 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 196800 kb
Host smart-6e57ea8d-78e5-433d-9a5f-42c0f60d0e40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218213365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.4218213365
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.34560415
Short name T337
Test name
Test status
Simulation time 492856953 ps
CPU time 0.99 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 194896 kb
Host smart-6f508a5d-d10d-49d9-bc8c-a46a7c611717
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560415 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.34560415
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.3278038231
Short name T59
Test name
Test status
Simulation time 454133178 ps
CPU time 0.93 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:46 PM PST 24
Peak memory 183440 kb
Host smart-f107c92f-e8a5-457b-af68-32f49ecc3a21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278038231 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.3278038231
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.654450400
Short name T389
Test name
Test status
Simulation time 410738636 ps
CPU time 0.69 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:48 PM PST 24
Peak memory 183124 kb
Host smart-a7f4cf3b-e18c-4bac-8735-5bd4055931c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654450400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.654450400
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3574757554
Short name T340
Test name
Test status
Simulation time 1147662363 ps
CPU time 1.14 seconds
Started Feb 29 12:40:42 PM PST 24
Finished Feb 29 12:40:43 PM PST 24
Peak memory 192644 kb
Host smart-8438fee8-4d53-47f0-aca3-9aebc7da59ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574757554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3574757554
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2993758917
Short name T393
Test name
Test status
Simulation time 678058544 ps
CPU time 1.34 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 198028 kb
Host smart-62009aae-68f2-44be-8426-f4043a18fa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993758917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2993758917
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.1187398891
Short name T85
Test name
Test status
Simulation time 4578044309 ps
CPU time 2.64 seconds
Started Feb 29 12:40:57 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 196836 kb
Host smart-f66252df-fec0-442f-b81b-87a88b2c7247
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187398891 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_t
l_intg_err.1187398891
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.3505052065
Short name T411
Test name
Test status
Simulation time 605826263 ps
CPU time 0.91 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 196492 kb
Host smart-e41de623-1d43-40e6-beea-a21c35470783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505052065 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.3505052065
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1716334209
Short name T392
Test name
Test status
Simulation time 524221477 ps
CPU time 0.76 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 183384 kb
Host smart-69f33906-8b09-4fcc-a6f5-e4f91e5293aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716334209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1716334209
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1946689843
Short name T394
Test name
Test status
Simulation time 331091442 ps
CPU time 0.63 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 182984 kb
Host smart-e785313e-ddc8-4eab-aa13-07aff5046cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946689843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1946689843
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.1027420979
Short name T364
Test name
Test status
Simulation time 919542175 ps
CPU time 0.66 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 193536 kb
Host smart-df822749-c930-4de8-91f9-d70d7a8b3224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027420979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.1027420979
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.1568525412
Short name T399
Test name
Test status
Simulation time 341400187 ps
CPU time 1.78 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 198224 kb
Host smart-628170ac-bd3c-4495-a191-f8d7f86ade6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568525412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.1568525412
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.1503512184
Short name T416
Test name
Test status
Simulation time 4418974197 ps
CPU time 7.66 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 196516 kb
Host smart-bf8296df-d789-4f39-ad1a-c6c583840319
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503512184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_t
l_intg_err.1503512184
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.3694663467
Short name T326
Test name
Test status
Simulation time 444388020 ps
CPU time 0.85 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 196712 kb
Host smart-a55d6152-c193-4332-9b3f-f3b75f4eeb4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694663467 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.3694663467
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.4272100134
Short name T53
Test name
Test status
Simulation time 315922871 ps
CPU time 1.08 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 183400 kb
Host smart-99ef4925-2e21-4c84-a521-45bcaf50b0f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272100134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.4272100134
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.2737981963
Short name T298
Test name
Test status
Simulation time 340190854 ps
CPU time 1.05 seconds
Started Feb 29 12:41:26 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 183352 kb
Host smart-ead28d9f-ec3d-406f-8a07-1bb12bc4eb6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737981963 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.2737981963
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3286562461
Short name T64
Test name
Test status
Simulation time 1944177982 ps
CPU time 5.46 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 192740 kb
Host smart-373757ee-5448-4d8c-b987-ed5a15808a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286562461 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3286562461
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.2170033338
Short name T334
Test name
Test status
Simulation time 577892699 ps
CPU time 2.35 seconds
Started Feb 29 12:41:04 PM PST 24
Finished Feb 29 12:41:12 PM PST 24
Peak memory 198192 kb
Host smart-0260c054-3a30-4fde-90df-20d84f6d95fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170033338 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.2170033338
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.4234761442
Short name T306
Test name
Test status
Simulation time 7964059481 ps
CPU time 6.42 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:12 PM PST 24
Peak memory 196956 kb
Host smart-7d3b23e0-0de9-439a-8a10-a17c5b3d2ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234761442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.4234761442
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.2153460674
Short name T312
Test name
Test status
Simulation time 459069075 ps
CPU time 0.83 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 194884 kb
Host smart-d3d3ae11-1fbf-4188-95e2-ba72a62760b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153460674 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.2153460674
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1992965900
Short name T58
Test name
Test status
Simulation time 534500998 ps
CPU time 0.79 seconds
Started Feb 29 12:40:57 PM PST 24
Finished Feb 29 12:40:58 PM PST 24
Peak memory 183312 kb
Host smart-1464a77c-9534-4eff-8d46-79b642e579ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992965900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1992965900
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.3611271183
Short name T294
Test name
Test status
Simulation time 449694562 ps
CPU time 1.15 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 182968 kb
Host smart-9dcd0dcd-bac7-4773-9654-5575486877b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611271183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.3611271183
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.3128716748
Short name T70
Test name
Test status
Simulation time 1420071787 ps
CPU time 2.44 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 193620 kb
Host smart-66620923-24d0-48f7-ae3c-59a9b649eba8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128716748 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.3128716748
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.4013990492
Short name T324
Test name
Test status
Simulation time 664954973 ps
CPU time 2.15 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 197876 kb
Host smart-19416e10-8129-4ec3-b5b6-201ef27db27e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013990492 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.4013990492
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.2150286800
Short name T84
Test name
Test status
Simulation time 8794741186 ps
CPU time 15.23 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:41:05 PM PST 24
Peak memory 197332 kb
Host smart-2dd57307-9f56-4d3e-a4f1-b3f508455fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150286800 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.2150286800
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.3382129901
Short name T322
Test name
Test status
Simulation time 356787027 ps
CPU time 0.77 seconds
Started Feb 29 12:40:43 PM PST 24
Finished Feb 29 12:40:44 PM PST 24
Peak memory 194444 kb
Host smart-d6955519-7de1-419d-ae8c-6497f4089616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382129901 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.3382129901
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.794970945
Short name T369
Test name
Test status
Simulation time 533896100 ps
CPU time 1.38 seconds
Started Feb 29 12:41:13 PM PST 24
Finished Feb 29 12:41:14 PM PST 24
Peak memory 183340 kb
Host smart-1b028763-4f83-4b00-966e-e9a79d91f40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794970945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.794970945
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.282898814
Short name T320
Test name
Test status
Simulation time 456670933 ps
CPU time 0.59 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 183128 kb
Host smart-47b6327e-4e63-4ece-9eae-2fc68c856bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282898814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.282898814
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.1824565071
Short name T66
Test name
Test status
Simulation time 2212983978 ps
CPU time 3.39 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:48 PM PST 24
Peak memory 191660 kb
Host smart-4616ab87-9791-4bf1-8172-325199a2e332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824565071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ao
n_timer_same_csr_outstanding.1824565071
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.2317986149
Short name T413
Test name
Test status
Simulation time 483997019 ps
CPU time 1.78 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:41:00 PM PST 24
Peak memory 198024 kb
Host smart-96ab1b33-f724-45c0-a84c-101fb868495e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317986149 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.2317986149
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.2510707381
Short name T341
Test name
Test status
Simulation time 3989150574 ps
CPU time 6.84 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 196604 kb
Host smart-233f6fba-67ce-4ec0-83e5-fb332fd1b962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510707381 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.2510707381
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.3353175855
Short name T372
Test name
Test status
Simulation time 656849445 ps
CPU time 1.27 seconds
Started Feb 29 12:40:57 PM PST 24
Finished Feb 29 12:40:58 PM PST 24
Peak memory 198016 kb
Host smart-34297f58-a9be-498a-a04a-a46a7d63d2c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353175855 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.3353175855
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.684117592
Short name T60
Test name
Test status
Simulation time 420725572 ps
CPU time 0.7 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 183500 kb
Host smart-280cf938-8372-40fd-aa10-767cfce78383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684117592 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.684117592
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2974333126
Short name T391
Test name
Test status
Simulation time 454056426 ps
CPU time 1.24 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 183068 kb
Host smart-2969bad2-4551-4211-9a24-066895c94707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974333126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2974333126
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.389327066
Short name T335
Test name
Test status
Simulation time 1338234420 ps
CPU time 1.11 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 192820 kb
Host smart-c5034d07-c89a-4b47-bf1d-b12ef677bda3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389327066 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon
_timer_same_csr_outstanding.389327066
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.528742190
Short name T417
Test name
Test status
Simulation time 648954014 ps
CPU time 1.84 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:58 PM PST 24
Peak memory 198216 kb
Host smart-b508abc1-b1dd-4fc1-ad44-b8740de4acc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528742190 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.528742190
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.3204652965
Short name T338
Test name
Test status
Simulation time 3681736301 ps
CPU time 6.29 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:41:02 PM PST 24
Peak memory 196544 kb
Host smart-7dc217ba-c66c-4bf3-b4f7-973c23c5eb30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204652965 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.3204652965
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.115426558
Short name T428
Test name
Test status
Simulation time 337917125 ps
CPU time 0.87 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 194428 kb
Host smart-ba5359b2-8965-4409-91cd-7d4f177f326e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115426558 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.115426558
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.571091878
Short name T69
Test name
Test status
Simulation time 494473059 ps
CPU time 0.93 seconds
Started Feb 29 12:41:17 PM PST 24
Finished Feb 29 12:41:18 PM PST 24
Peak memory 183340 kb
Host smart-c68d74fd-622a-47ff-8280-6f7b29abf891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571091878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.571091878
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.2822525300
Short name T292
Test name
Test status
Simulation time 314966162 ps
CPU time 0.63 seconds
Started Feb 29 12:41:05 PM PST 24
Finished Feb 29 12:41:06 PM PST 24
Peak memory 183112 kb
Host smart-33ad221f-a89c-4cbe-acb5-3c1d529551c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822525300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.2822525300
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.1973603229
Short name T349
Test name
Test status
Simulation time 2034654214 ps
CPU time 2.01 seconds
Started Feb 29 12:40:59 PM PST 24
Finished Feb 29 12:41:02 PM PST 24
Peak memory 193716 kb
Host smart-bd7d0dae-45c7-4aaf-92b6-c2cbf517b653
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973603229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.1973603229
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.252155618
Short name T401
Test name
Test status
Simulation time 345855184 ps
CPU time 2.3 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:05 PM PST 24
Peak memory 198080 kb
Host smart-62ad044b-176b-438b-9b14-490b71184a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252155618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.252155618
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.387790471
Short name T409
Test name
Test status
Simulation time 528283537 ps
CPU time 1.46 seconds
Started Feb 29 12:40:59 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 195092 kb
Host smart-56cabe00-7eaf-46e7-b229-e9989db5b0d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387790471 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.387790471
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.3083886171
Short name T50
Test name
Test status
Simulation time 297951057 ps
CPU time 1.01 seconds
Started Feb 29 12:41:20 PM PST 24
Finished Feb 29 12:41:22 PM PST 24
Peak memory 183324 kb
Host smart-25ec52b6-f1e6-4bc0-9320-ff48bfc790f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083886171 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.3083886171
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.1028774085
Short name T305
Test name
Test status
Simulation time 433389960 ps
CPU time 0.69 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 183260 kb
Host smart-eb488bdf-0e87-47b9-9e9b-323732866c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028774085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.1028774085
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.3117306480
Short name T414
Test name
Test status
Simulation time 980140138 ps
CPU time 1.36 seconds
Started Feb 29 12:41:13 PM PST 24
Finished Feb 29 12:41:15 PM PST 24
Peak memory 193800 kb
Host smart-c064c59d-6780-48bb-9b32-c6e814dfba9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117306480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.3117306480
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.4200381031
Short name T289
Test name
Test status
Simulation time 652742905 ps
CPU time 1.67 seconds
Started Feb 29 12:40:59 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 198000 kb
Host smart-4c03e799-9946-477b-9b01-320e030afde1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200381031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.4200381031
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.1910181196
Short name T357
Test name
Test status
Simulation time 8931156925 ps
CPU time 4.74 seconds
Started Feb 29 12:41:11 PM PST 24
Finished Feb 29 12:41:16 PM PST 24
Peak memory 197112 kb
Host smart-97424372-d605-49b6-b146-81f271bfa9c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910181196 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.1910181196
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.1914445583
Short name T419
Test name
Test status
Simulation time 427150346 ps
CPU time 0.76 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:45 PM PST 24
Peak memory 192464 kb
Host smart-aef38de1-c347-4edc-8cd4-e0c0b30610e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914445583 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.1914445583
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.2340227207
Short name T430
Test name
Test status
Simulation time 3154347517 ps
CPU time 8.36 seconds
Started Feb 29 12:40:48 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 193484 kb
Host smart-e6359d8a-dc77-4539-884c-924b759a2028
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340227207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.2340227207
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.4263006877
Short name T331
Test name
Test status
Simulation time 1230263941 ps
CPU time 1.03 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:48 PM PST 24
Peak memory 183340 kb
Host smart-efa8bffc-ab13-4b4b-bdc2-194f129f69e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263006877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.4263006877
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.832729687
Short name T397
Test name
Test status
Simulation time 595089331 ps
CPU time 0.88 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 194264 kb
Host smart-d860b003-1b9d-4059-850a-03c9456f228d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832729687 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.832729687
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.2999431279
Short name T49
Test name
Test status
Simulation time 326046830 ps
CPU time 0.99 seconds
Started Feb 29 12:40:36 PM PST 24
Finished Feb 29 12:40:37 PM PST 24
Peak memory 183256 kb
Host smart-a2ef455f-6b68-4085-ab32-a832f4396ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999431279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.2999431279
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.3387042826
Short name T429
Test name
Test status
Simulation time 370423662 ps
CPU time 0.71 seconds
Started Feb 29 12:40:41 PM PST 24
Finished Feb 29 12:40:42 PM PST 24
Peak memory 183184 kb
Host smart-b124290f-b275-42df-aa55-08d190fc465c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387042826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.3387042826
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.3914159292
Short name T346
Test name
Test status
Simulation time 388886269 ps
CPU time 1.14 seconds
Started Feb 29 12:40:40 PM PST 24
Finished Feb 29 12:40:41 PM PST 24
Peak memory 183052 kb
Host smart-91223092-bac5-4724-9277-ab117de9982c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914159292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.3914159292
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1828395370
Short name T291
Test name
Test status
Simulation time 309709339 ps
CPU time 0.63 seconds
Started Feb 29 12:40:42 PM PST 24
Finished Feb 29 12:40:43 PM PST 24
Peak memory 182976 kb
Host smart-22634df4-b116-4ce9-b7d0-b63d72f2c563
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828395370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1828395370
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.307408708
Short name T67
Test name
Test status
Simulation time 1203548674 ps
CPU time 1.52 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 192836 kb
Host smart-bcc23126-50c1-4908-80a6-1a9f3737faa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307408708 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_
timer_same_csr_outstanding.307408708
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.4110211999
Short name T361
Test name
Test status
Simulation time 589307733 ps
CPU time 2.84 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 198212 kb
Host smart-5825ef70-263a-4c42-8557-1353931a3eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110211999 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.4110211999
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.703812416
Short name T107
Test name
Test status
Simulation time 4517646752 ps
CPU time 2.84 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 196796 kb
Host smart-8c6ac79c-5735-4c8c-88a9-fa5307a88c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703812416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_
intg_err.703812416
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.925885662
Short name T355
Test name
Test status
Simulation time 454982400 ps
CPU time 0.79 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 183112 kb
Host smart-8289c9e7-7792-4ff6-8f53-738cc14d6f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925885662 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.925885662
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.2859165970
Short name T293
Test name
Test status
Simulation time 492636479 ps
CPU time 1.25 seconds
Started Feb 29 12:41:14 PM PST 24
Finished Feb 29 12:41:16 PM PST 24
Peak memory 183076 kb
Host smart-5703407f-b613-4b75-a193-db2449b4bb4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859165970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.2859165970
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.2727471383
Short name T418
Test name
Test status
Simulation time 405295921 ps
CPU time 0.65 seconds
Started Feb 29 12:40:59 PM PST 24
Finished Feb 29 12:41:00 PM PST 24
Peak memory 183112 kb
Host smart-9c022678-fad7-45c8-87eb-58404d09fe93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727471383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.2727471383
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.968370451
Short name T295
Test name
Test status
Simulation time 484149478 ps
CPU time 0.67 seconds
Started Feb 29 12:41:18 PM PST 24
Finished Feb 29 12:41:19 PM PST 24
Peak memory 182988 kb
Host smart-02783c2d-286c-4b01-8b5e-d5d08114e73b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968370451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.968370451
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.4223148635
Short name T353
Test name
Test status
Simulation time 496750946 ps
CPU time 1.29 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 183136 kb
Host smart-a1dcb365-5874-4298-9ff3-d0b05654a475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223148635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.4223148635
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.1538078471
Short name T300
Test name
Test status
Simulation time 445891238 ps
CPU time 0.86 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 183108 kb
Host smart-53b9af57-dab6-496d-8ffd-04ec63d35c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538078471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.1538078471
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.1092572605
Short name T302
Test name
Test status
Simulation time 522294390 ps
CPU time 0.75 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:07 PM PST 24
Peak memory 183068 kb
Host smart-656b48e1-c0b0-4174-ac24-8c1769d10f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092572605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.1092572605
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.1161865777
Short name T354
Test name
Test status
Simulation time 455835038 ps
CPU time 1.17 seconds
Started Feb 29 12:41:02 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 183104 kb
Host smart-2d83f7e7-7c20-48fc-a045-ded40e6f3983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161865777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.1161865777
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.4149897779
Short name T301
Test name
Test status
Simulation time 472458489 ps
CPU time 1.15 seconds
Started Feb 29 12:41:04 PM PST 24
Finished Feb 29 12:41:06 PM PST 24
Peak memory 183068 kb
Host smart-ce299f47-f225-461e-a05f-42f49308b4e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149897779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.4149897779
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2554327615
Short name T333
Test name
Test status
Simulation time 441465283 ps
CPU time 0.7 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 183112 kb
Host smart-2d701724-e979-4ec3-a366-0fc24ae2899f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554327615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2554327615
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.3274399823
Short name T375
Test name
Test status
Simulation time 550953467 ps
CPU time 0.83 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 183408 kb
Host smart-386a0192-c93f-4ef0-83ea-9d1b47ea9329
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274399823 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.3274399823
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3530743142
Short name T61
Test name
Test status
Simulation time 11594321842 ps
CPU time 15.31 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:41:09 PM PST 24
Peak memory 191648 kb
Host smart-8aefea7b-9195-43e2-a574-6f6b1a6bddd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530743142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3530743142
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.741415727
Short name T303
Test name
Test status
Simulation time 809509105 ps
CPU time 0.85 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:53 PM PST 24
Peak memory 183092 kb
Host smart-53b7c722-e43f-47e2-8e98-4e42b234ad6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741415727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.741415727
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1119554085
Short name T366
Test name
Test status
Simulation time 378860082 ps
CPU time 0.78 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 194588 kb
Host smart-367a1ac0-e378-4b3c-b3b0-12c1d4a655a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119554085 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1119554085
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3553608488
Short name T374
Test name
Test status
Simulation time 453841431 ps
CPU time 0.69 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 183396 kb
Host smart-6819b9f5-7707-4346-8180-ba963bb68f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553608488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3553608488
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.1987850221
Short name T423
Test name
Test status
Simulation time 278170831 ps
CPU time 0.99 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:52 PM PST 24
Peak memory 182196 kb
Host smart-bd8c831c-d3e7-41b3-80a7-89abaf9f1b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987850221 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.1987850221
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2526955560
Short name T373
Test name
Test status
Simulation time 399964283 ps
CPU time 1.1 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:46 PM PST 24
Peak memory 183292 kb
Host smart-8daabb2c-973f-4f4f-a94e-86119fbf9f8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526955560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2526955560
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.2919203085
Short name T387
Test name
Test status
Simulation time 408433305 ps
CPU time 1.17 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 183116 kb
Host smart-e2a1c116-34e0-4a2e-bdfa-b10a1c34c484
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919203085 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_w
alk.2919203085
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.3211083902
Short name T427
Test name
Test status
Simulation time 1954323899 ps
CPU time 1.27 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 194772 kb
Host smart-6983abac-101a-47f7-956b-c595a90cdf7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211083902 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon
_timer_same_csr_outstanding.3211083902
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.1498682191
Short name T363
Test name
Test status
Simulation time 493946679 ps
CPU time 2.39 seconds
Started Feb 29 12:40:51 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 198148 kb
Host smart-92779407-3ec1-45fe-9b5f-0dd74349410e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498682191 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.1498682191
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.801087615
Short name T86
Test name
Test status
Simulation time 8381895482 ps
CPU time 7.02 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 197488 kb
Host smart-1f4baf86-b338-4ebe-bce6-d6ba510f3735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801087615 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.801087615
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.1086618351
Short name T358
Test name
Test status
Simulation time 340678786 ps
CPU time 0.97 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 183112 kb
Host smart-5c070316-4205-4669-b07f-defe68a93eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086618351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.1086618351
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.3111178663
Short name T350
Test name
Test status
Simulation time 453398356 ps
CPU time 1.18 seconds
Started Feb 29 12:41:18 PM PST 24
Finished Feb 29 12:41:20 PM PST 24
Peak memory 183160 kb
Host smart-4d057b14-2776-4b67-944a-9397b1126c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111178663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.3111178663
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.3603335697
Short name T290
Test name
Test status
Simulation time 465272044 ps
CPU time 0.83 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:07 PM PST 24
Peak memory 183248 kb
Host smart-7b9437b9-13ad-49c2-8ea8-af4113f417fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603335697 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.3603335697
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2042725331
Short name T367
Test name
Test status
Simulation time 471380649 ps
CPU time 0.7 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183080 kb
Host smart-8eb72508-854f-4f74-bc79-7b7a1b762c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042725331 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2042725331
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.2042960347
Short name T313
Test name
Test status
Simulation time 460257541 ps
CPU time 0.71 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 183516 kb
Host smart-8215eeb2-5208-421e-928a-d8314dcc3f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042960347 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.2042960347
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.1407232412
Short name T407
Test name
Test status
Simulation time 316996234 ps
CPU time 0.76 seconds
Started Feb 29 12:41:16 PM PST 24
Finished Feb 29 12:41:17 PM PST 24
Peak memory 183076 kb
Host smart-ae3d3fd7-e17b-46e9-93f8-048a04caebf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407232412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.1407232412
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.3247753567
Short name T299
Test name
Test status
Simulation time 304289215 ps
CPU time 0.62 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:07 PM PST 24
Peak memory 183068 kb
Host smart-3fb03937-df68-446b-8cca-db5596843b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247753567 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.3247753567
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1328780825
Short name T304
Test name
Test status
Simulation time 495902583 ps
CPU time 0.92 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 183072 kb
Host smart-77862788-8bf5-4e21-b3fa-bb87d25b0e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328780825 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1328780825
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.1009898727
Short name T384
Test name
Test status
Simulation time 295279443 ps
CPU time 1.06 seconds
Started Feb 29 12:41:15 PM PST 24
Finished Feb 29 12:41:17 PM PST 24
Peak memory 182212 kb
Host smart-0d01305d-04ef-4230-b0b4-2a7444b83d51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009898727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.1009898727
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.3351297841
Short name T343
Test name
Test status
Simulation time 320977285 ps
CPU time 1.01 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 182996 kb
Host smart-3b66f406-f807-4ea4-84b9-1f538ac95857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351297841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.3351297841
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.2620148598
Short name T55
Test name
Test status
Simulation time 534521049 ps
CPU time 1.09 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:57 PM PST 24
Peak memory 192544 kb
Host smart-1438cc70-abc7-4091-a61b-6bb255cb242a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620148598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.2620148598
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.1911761286
Short name T415
Test name
Test status
Simulation time 10590432932 ps
CPU time 5.88 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 183504 kb
Host smart-4786cf23-0855-4b62-a4aa-338fca65d9e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911761286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.1911761286
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.1817177069
Short name T315
Test name
Test status
Simulation time 1333383709 ps
CPU time 2.59 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:53 PM PST 24
Peak memory 183324 kb
Host smart-21e352de-9146-4bab-8e57-58e10e36a9cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817177069 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.1817177069
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.3341227846
Short name T321
Test name
Test status
Simulation time 628133818 ps
CPU time 1.38 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 197896 kb
Host smart-3bf33228-eaf9-4fa4-a0ba-4ad7461a33d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341227846 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.3341227846
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.2064842993
Short name T356
Test name
Test status
Simulation time 441471914 ps
CPU time 0.74 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 183292 kb
Host smart-5410ff5c-0588-4ba5-8c4f-6570eb19a3ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064842993 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.2064842993
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.435682008
Short name T400
Test name
Test status
Simulation time 317499981 ps
CPU time 1.06 seconds
Started Feb 29 12:40:43 PM PST 24
Finished Feb 29 12:40:44 PM PST 24
Peak memory 183068 kb
Host smart-685600f9-dbed-4dff-85ba-4f328ba008f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435682008 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.435682008
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.2182667051
Short name T379
Test name
Test status
Simulation time 455566846 ps
CPU time 1.26 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 183032 kb
Host smart-ad7b9e75-1c4a-417d-8c0e-8ecd101c624f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182667051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.2182667051
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.1205714548
Short name T327
Test name
Test status
Simulation time 529490592 ps
CPU time 0.62 seconds
Started Feb 29 12:40:47 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 182196 kb
Host smart-41f4e8b8-d863-41ce-b1b3-430632af3ed2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205714548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.1205714548
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3746281778
Short name T63
Test name
Test status
Simulation time 2047501890 ps
CPU time 1.11 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 192368 kb
Host smart-69eff8f2-5e6c-4aa5-a297-7520cfe30cab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746281778 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3746281778
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2634266522
Short name T311
Test name
Test status
Simulation time 437499216 ps
CPU time 2.39 seconds
Started Feb 29 12:41:11 PM PST 24
Finished Feb 29 12:41:14 PM PST 24
Peak memory 198080 kb
Host smart-09c9dc79-53e4-4359-9c20-18f0d02d400e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634266522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2634266522
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.782293099
Short name T381
Test name
Test status
Simulation time 4123410977 ps
CPU time 2.34 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:58 PM PST 24
Peak memory 196644 kb
Host smart-fe5d9314-7418-4491-ade3-48784d67425b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782293099 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_
intg_err.782293099
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1987660653
Short name T368
Test name
Test status
Simulation time 373447228 ps
CPU time 0.78 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 183304 kb
Host smart-196735db-26f8-48f7-a509-40cfb5031d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987660653 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1987660653
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.1285718201
Short name T328
Test name
Test status
Simulation time 495489942 ps
CPU time 1.2 seconds
Started Feb 29 12:41:10 PM PST 24
Finished Feb 29 12:41:12 PM PST 24
Peak memory 183068 kb
Host smart-c201ca01-758c-47e0-affa-8a81b6a03165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285718201 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.1285718201
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.3390042108
Short name T288
Test name
Test status
Simulation time 271690989 ps
CPU time 0.9 seconds
Started Feb 29 12:41:18 PM PST 24
Finished Feb 29 12:41:19 PM PST 24
Peak memory 183060 kb
Host smart-878669b1-b3bf-4f6d-b4c6-c348916abd23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390042108 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.3390042108
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.2835308589
Short name T296
Test name
Test status
Simulation time 276708389 ps
CPU time 0.68 seconds
Started Feb 29 12:41:02 PM PST 24
Finished Feb 29 12:41:03 PM PST 24
Peak memory 183316 kb
Host smart-28cbc0b7-04d3-4c25-b97a-1f1edc2333d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835308589 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.2835308589
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.4001097048
Short name T365
Test name
Test status
Simulation time 306488332 ps
CPU time 0.65 seconds
Started Feb 29 12:41:15 PM PST 24
Finished Feb 29 12:41:16 PM PST 24
Peak memory 182048 kb
Host smart-36f3dca2-f556-4a23-a3f2-f207ab87dff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001097048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.4001097048
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2388150563
Short name T329
Test name
Test status
Simulation time 446189775 ps
CPU time 0.7 seconds
Started Feb 29 12:41:12 PM PST 24
Finished Feb 29 12:41:13 PM PST 24
Peak memory 183068 kb
Host smart-0737218f-2b79-4546-ae98-b85bbfd7cd36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388150563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2388150563
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.614559280
Short name T309
Test name
Test status
Simulation time 281461354 ps
CPU time 0.91 seconds
Started Feb 29 12:41:16 PM PST 24
Finished Feb 29 12:41:17 PM PST 24
Peak memory 183068 kb
Host smart-38d72bee-d3cd-4b4a-924e-722a1d6b3968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614559280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.614559280
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.1461714380
Short name T336
Test name
Test status
Simulation time 280800237 ps
CPU time 0.97 seconds
Started Feb 29 12:41:05 PM PST 24
Finished Feb 29 12:41:07 PM PST 24
Peak memory 183280 kb
Host smart-e251b18e-2a96-447c-8e39-7d1f1a55e643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461714380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.1461714380
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.4154556782
Short name T325
Test name
Test status
Simulation time 341777954 ps
CPU time 0.9 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:07 PM PST 24
Peak memory 183068 kb
Host smart-309788bf-83b2-405e-b3c2-3ed114f36d7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154556782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.4154556782
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3234918081
Short name T317
Test name
Test status
Simulation time 427509552 ps
CPU time 0.59 seconds
Started Feb 29 12:41:18 PM PST 24
Finished Feb 29 12:41:20 PM PST 24
Peak memory 183160 kb
Host smart-69d544c4-4257-42f3-a7f2-af4566d27467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234918081 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3234918081
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.3393216811
Short name T410
Test name
Test status
Simulation time 573240681 ps
CPU time 0.96 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 193968 kb
Host smart-08de001e-df83-4309-ae04-37004288563b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393216811 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.3393216811
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.1847625345
Short name T352
Test name
Test status
Simulation time 392876635 ps
CPU time 0.77 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183180 kb
Host smart-788e3548-04ae-4c91-8d7d-2fac10ecea6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847625345 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.1847625345
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.4161550661
Short name T378
Test name
Test status
Simulation time 490260096 ps
CPU time 0.87 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183120 kb
Host smart-3bf5620f-ebda-4c90-96ab-748edb734778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161550661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.4161550661
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.188331047
Short name T314
Test name
Test status
Simulation time 1001654828 ps
CPU time 1.98 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 192184 kb
Host smart-959ddde0-3b6c-4559-909b-a8861483665b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188331047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_
timer_same_csr_outstanding.188331047
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.2222491327
Short name T408
Test name
Test status
Simulation time 522037744 ps
CPU time 2.03 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 198144 kb
Host smart-167fa7f6-528c-4cf6-b95d-b6b0d173fed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222491327 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.2222491327
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.1163010951
Short name T323
Test name
Test status
Simulation time 8894832150 ps
CPU time 3.02 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 197364 kb
Host smart-0602b635-d56f-4f6a-b8f7-830fa94cf6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163010951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.1163010951
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.2152203067
Short name T424
Test name
Test status
Simulation time 576769711 ps
CPU time 1.52 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:47 PM PST 24
Peak memory 194376 kb
Host smart-3de7c5ef-7059-42e2-9fc4-5d5fd0e41a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152203067 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.2152203067
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.4222972777
Short name T422
Test name
Test status
Simulation time 424032529 ps
CPU time 1.17 seconds
Started Feb 29 12:40:41 PM PST 24
Finished Feb 29 12:40:43 PM PST 24
Peak memory 183392 kb
Host smart-eb804971-2751-4af7-9ba2-257ebf90e535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222972777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.4222972777
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.2299390539
Short name T339
Test name
Test status
Simulation time 462455000 ps
CPU time 0.84 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:50 PM PST 24
Peak memory 183136 kb
Host smart-d2f6fb4d-90c4-4389-b688-25ff33376a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299390539 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.2299390539
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.740610070
Short name T386
Test name
Test status
Simulation time 2218409144 ps
CPU time 6.06 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 192860 kb
Host smart-763e5fb1-7d74-4340-b02e-cfccdc1dee1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740610070 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_
timer_same_csr_outstanding.740610070
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3494036320
Short name T421
Test name
Test status
Simulation time 511985165 ps
CPU time 1.71 seconds
Started Feb 29 12:41:01 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 198236 kb
Host smart-52b31cad-7a31-42a1-8869-01e666494e96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494036320 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3494036320
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.3887755358
Short name T362
Test name
Test status
Simulation time 8074734315 ps
CPU time 7.12 seconds
Started Feb 29 12:40:53 PM PST 24
Finished Feb 29 12:41:00 PM PST 24
Peak memory 197164 kb
Host smart-54e168d5-a13b-488b-8b4f-293d8bbfb2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887755358 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.3887755358
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.488327210
Short name T297
Test name
Test status
Simulation time 544457147 ps
CPU time 1.13 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:45 PM PST 24
Peak memory 197940 kb
Host smart-c060e23f-9c99-485e-bff9-16590347b6d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488327210 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.488327210
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3571521964
Short name T52
Test name
Test status
Simulation time 274725357 ps
CPU time 0.94 seconds
Started Feb 29 12:40:54 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183048 kb
Host smart-6e55e170-ab6f-49c0-b724-1b1cde0830b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571521964 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3571521964
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.22186369
Short name T330
Test name
Test status
Simulation time 273560635 ps
CPU time 1.01 seconds
Started Feb 29 12:40:44 PM PST 24
Finished Feb 29 12:40:45 PM PST 24
Peak memory 183324 kb
Host smart-c876c862-7699-4d1d-91d5-c6a338df84fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186369 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.22186369
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.894535386
Short name T377
Test name
Test status
Simulation time 1246514661 ps
CPU time 1.86 seconds
Started Feb 29 12:41:15 PM PST 24
Finished Feb 29 12:41:18 PM PST 24
Peak memory 193796 kb
Host smart-c36dd6ed-679d-45b8-adb2-63b14d1dc8ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894535386 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_
timer_same_csr_outstanding.894535386
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.327232111
Short name T425
Test name
Test status
Simulation time 349234220 ps
CPU time 1.89 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:54 PM PST 24
Peak memory 198036 kb
Host smart-d168d3aa-ea94-43cf-9fde-6b5099a12396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327232111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.327232111
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1310967547
Short name T24
Test name
Test status
Simulation time 8190947733 ps
CPU time 7.99 seconds
Started Feb 29 12:40:41 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 197172 kb
Host smart-b5cd0a05-5d36-4564-82f8-24c16285d73f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310967547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1310967547
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.1044293926
Short name T385
Test name
Test status
Simulation time 533746282 ps
CPU time 1.42 seconds
Started Feb 29 12:40:58 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 194296 kb
Host smart-1cebb858-4e12-45e1-bc84-c08a4f128fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044293926 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.1044293926
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.2589879500
Short name T57
Test name
Test status
Simulation time 360977349 ps
CPU time 0.68 seconds
Started Feb 29 12:40:55 PM PST 24
Finished Feb 29 12:40:56 PM PST 24
Peak memory 183208 kb
Host smart-c00fd628-d678-4272-b264-db1f62d18ef6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589879500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.2589879500
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.3287308401
Short name T405
Test name
Test status
Simulation time 492903659 ps
CPU time 0.92 seconds
Started Feb 29 12:40:45 PM PST 24
Finished Feb 29 12:40:46 PM PST 24
Peak memory 182932 kb
Host smart-1a041e06-f896-4a62-a202-ff3d5e3c3560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287308401 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.3287308401
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.2780250207
Short name T395
Test name
Test status
Simulation time 2385910551 ps
CPU time 2.14 seconds
Started Feb 29 12:41:00 PM PST 24
Finished Feb 29 12:41:04 PM PST 24
Peak memory 195012 kb
Host smart-ca0f8653-74fa-4d1d-ae77-c6c4238e25a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780250207 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.2780250207
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.3151782996
Short name T344
Test name
Test status
Simulation time 665639308 ps
CPU time 1.26 seconds
Started Feb 29 12:40:43 PM PST 24
Finished Feb 29 12:40:44 PM PST 24
Peak memory 198136 kb
Host smart-ef01b57c-8e60-4994-99a1-a58cae3935a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151782996 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.3151782996
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.3826089160
Short name T380
Test name
Test status
Simulation time 4710491330 ps
CPU time 2.69 seconds
Started Feb 29 12:40:56 PM PST 24
Finished Feb 29 12:40:59 PM PST 24
Peak memory 196832 kb
Host smart-d757a679-bfc2-4cc3-bb0c-1e9cc939ac7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826089160 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.3826089160
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.3607290445
Short name T359
Test name
Test status
Simulation time 437325994 ps
CPU time 1.03 seconds
Started Feb 29 12:40:59 PM PST 24
Finished Feb 29 12:41:01 PM PST 24
Peak memory 195520 kb
Host smart-b6efd58e-2872-4c11-b68b-f6998a0c71b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607290445 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.3607290445
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.2082021252
Short name T307
Test name
Test status
Simulation time 383534136 ps
CPU time 0.82 seconds
Started Feb 29 12:41:06 PM PST 24
Finished Feb 29 12:41:08 PM PST 24
Peak memory 183264 kb
Host smart-508f6777-9e01-4c64-ac82-37f624147a94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082021252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.2082021252
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2180074126
Short name T403
Test name
Test status
Simulation time 302757943 ps
CPU time 0.66 seconds
Started Feb 29 12:40:50 PM PST 24
Finished Feb 29 12:40:51 PM PST 24
Peak memory 183068 kb
Host smart-a28fac26-d4ce-49d7-bf31-ac6dd9fd6e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180074126 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2180074126
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2743369952
Short name T347
Test name
Test status
Simulation time 1012599135 ps
CPU time 2.32 seconds
Started Feb 29 12:40:52 PM PST 24
Finished Feb 29 12:40:55 PM PST 24
Peak memory 192260 kb
Host smart-322ae67e-b84c-4890-9d04-5e5d8fe30527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743369952 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2743369952
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.1684011229
Short name T383
Test name
Test status
Simulation time 472359764 ps
CPU time 2.28 seconds
Started Feb 29 12:40:46 PM PST 24
Finished Feb 29 12:40:49 PM PST 24
Peak memory 198132 kb
Host smart-7df920bb-230e-4cb2-8947-aabaf02e80c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684011229 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.1684011229
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.1498607151
Short name T420
Test name
Test status
Simulation time 4313522610 ps
CPU time 3.83 seconds
Started Feb 29 12:40:49 PM PST 24
Finished Feb 29 12:40:53 PM PST 24
Peak memory 195448 kb
Host smart-ac142517-ddcb-41cb-9675-0362fb9f12a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498607151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.1498607151
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.154691352
Short name T226
Test name
Test status
Simulation time 455005917 ps
CPU time 0.71 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 182916 kb
Host smart-0cb2ad76-21a6-4cec-ae55-250548e0b5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154691352 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.154691352
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.738713342
Short name T152
Test name
Test status
Simulation time 8483210599 ps
CPU time 3.92 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 182924 kb
Host smart-5be5e04a-4033-488f-9dda-df8771bfd356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738713342 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.738713342
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.4279633355
Short name T4
Test name
Test status
Simulation time 469029152 ps
CPU time 0.72 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 182932 kb
Host smart-271d6357-402d-4dcf-b24d-a5c8f80486bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279633355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.4279633355
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_jump.1488345097
Short name T227
Test name
Test status
Simulation time 576700239 ps
CPU time 1.46 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 182900 kb
Host smart-7caad044-9ec4-435a-b7ad-b25149fa7b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488345097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.1488345097
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.3906317656
Short name T221
Test name
Test status
Simulation time 23579707157 ps
CPU time 10.35 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:42:08 PM PST 24
Peak memory 182908 kb
Host smart-b8ba1f3b-722f-4b13-a876-8ed44684a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906317656 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.3906317656
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.3487499460
Short name T20
Test name
Test status
Simulation time 8200845586 ps
CPU time 2.34 seconds
Started Feb 29 12:41:51 PM PST 24
Finished Feb 29 12:41:54 PM PST 24
Peak memory 215208 kb
Host smart-5ed40284-6511-4aa8-9b9c-327aa62b57a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487499460 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.3487499460
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.739389121
Short name T111
Test name
Test status
Simulation time 401886912 ps
CPU time 1.16 seconds
Started Feb 29 12:42:04 PM PST 24
Finished Feb 29 12:42:05 PM PST 24
Peak memory 182984 kb
Host smart-1671d687-0917-47e6-9bf2-6bbb87aa5fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739389121 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.739389121
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.3009430968
Short name T87
Test name
Test status
Simulation time 133070382444 ps
CPU time 104.34 seconds
Started Feb 29 12:41:52 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 182976 kb
Host smart-5e477dd0-16b8-4ba3-8316-be5854ef82b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009430968 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.3009430968
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_jump.2662720518
Short name T207
Test name
Test status
Simulation time 609113999 ps
CPU time 1.44 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 182920 kb
Host smart-1306dbe5-e442-40e7-9ee2-e6d2de6ba2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662720518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.2662720518
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1308056979
Short name T210
Test name
Test status
Simulation time 4606826575 ps
CPU time 3.5 seconds
Started Feb 29 12:42:05 PM PST 24
Finished Feb 29 12:42:08 PM PST 24
Peak memory 182956 kb
Host smart-bcc6374a-9517-4025-b05b-33a38ba81371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308056979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1308056979
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.3218610185
Short name T139
Test name
Test status
Simulation time 401197617 ps
CPU time 0.67 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 182748 kb
Host smart-e1bedb11-cab9-43a2-b1da-9ce22727894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218610185 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.3218610185
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2968427218
Short name T149
Test name
Test status
Simulation time 5331814268 ps
CPU time 4.76 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 182980 kb
Host smart-77c96437-d411-411f-a200-ff340603eb6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968427218 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2968427218
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_jump.3774810921
Short name T137
Test name
Test status
Simulation time 472360512 ps
CPU time 1.32 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:04 PM PST 24
Peak memory 183020 kb
Host smart-d558eaf3-06ef-4610-b854-da80cf7bcbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774810921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.3774810921
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.3351540379
Short name T270
Test name
Test status
Simulation time 13480467356 ps
CPU time 9.7 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 182936 kb
Host smart-9a910c12-1421-410f-bf2c-5cf1ab348787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351540379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.3351540379
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.3992448981
Short name T175
Test name
Test status
Simulation time 564128808 ps
CPU time 0.76 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 182864 kb
Host smart-cb3e82af-5ee6-477b-848d-3945103d28cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992448981 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.3992448981
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.1258075044
Short name T99
Test name
Test status
Simulation time 109152643402 ps
CPU time 39.2 seconds
Started Feb 29 12:42:53 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 182916 kb
Host smart-6b217a73-8837-406b-a2ea-e3e951fcd701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258075044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_
all.1258075044
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3856299958
Short name T77
Test name
Test status
Simulation time 29023118202 ps
CPU time 299.46 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 197904 kb
Host smart-f5cdfbdd-c8a9-4ac7-97d7-fa387a8aaf8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856299958 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3856299958
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.3759899168
Short name T281
Test name
Test status
Simulation time 348877006 ps
CPU time 1.35 seconds
Started Feb 29 12:42:00 PM PST 24
Finished Feb 29 12:42:01 PM PST 24
Peak memory 182920 kb
Host smart-25f2aa54-14ac-4eb3-aaa3-4cea5aceadee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759899168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.3759899168
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.1349457719
Short name T240
Test name
Test status
Simulation time 34449759239 ps
CPU time 55.49 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:43:11 PM PST 24
Peak memory 182988 kb
Host smart-15587157-21ae-4b31-b9c9-b053cb845fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349457719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.1349457719
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.2823860340
Short name T124
Test name
Test status
Simulation time 449468819 ps
CPU time 0.72 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 182884 kb
Host smart-8f0d9849-53a9-4a86-a7aa-0bd9c3e33730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823860340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.2823860340
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1209426849
Short name T277
Test name
Test status
Simulation time 72230026224 ps
CPU time 26.5 seconds
Started Feb 29 12:42:03 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 193240 kb
Host smart-374701bb-45ce-4a6b-8d32-802fbb5b339f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209426849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1209426849
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.1378454281
Short name T211
Test name
Test status
Simulation time 279437530938 ps
CPU time 311.84 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:47:07 PM PST 24
Peak memory 197908 kb
Host smart-9a35641a-c1c1-4bef-a83f-96671f821fba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378454281 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.1378454281
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.3883635281
Short name T242
Test name
Test status
Simulation time 607552254 ps
CPU time 0.8 seconds
Started Feb 29 12:41:53 PM PST 24
Finished Feb 29 12:41:54 PM PST 24
Peak memory 182940 kb
Host smart-0a3e3e75-5c80-44ca-939f-e84dc6bcbca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883635281 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.3883635281
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.337594557
Short name T130
Test name
Test status
Simulation time 35141869494 ps
CPU time 13.72 seconds
Started Feb 29 12:41:50 PM PST 24
Finished Feb 29 12:42:04 PM PST 24
Peak memory 183028 kb
Host smart-d3cc8594-286a-4bc0-9f5b-5ac4d4514ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337594557 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.337594557
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.2529473311
Short name T147
Test name
Test status
Simulation time 563613508 ps
CPU time 0.98 seconds
Started Feb 29 12:42:07 PM PST 24
Finished Feb 29 12:42:08 PM PST 24
Peak memory 182796 kb
Host smart-5f5a6a45-f8d1-49f0-9b95-0d660902cc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529473311 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.2529473311
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1859415696
Short name T95
Test name
Test status
Simulation time 129996463405 ps
CPU time 42 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:42:54 PM PST 24
Peak memory 194156 kb
Host smart-da845219-b302-4345-a655-fd70abf5ec63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859415696 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1859415696
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.2111326791
Short name T5
Test name
Test status
Simulation time 46769024812 ps
CPU time 331.79 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:47:55 PM PST 24
Peak memory 197908 kb
Host smart-33c2d30f-d912-44ce-88bf-0c1ceca861b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111326791 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.2111326791
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.2508290835
Short name T241
Test name
Test status
Simulation time 445298378 ps
CPU time 0.85 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 182924 kb
Host smart-18c8e435-aeb5-492b-a2ad-54455a52124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508290835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.2508290835
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.86232887
Short name T188
Test name
Test status
Simulation time 30903131631 ps
CPU time 11.08 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:13 PM PST 24
Peak memory 183004 kb
Host smart-66ce4d13-2b33-4d5a-a0fd-2893a96825c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86232887 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.86232887
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.4204663658
Short name T135
Test name
Test status
Simulation time 475203745 ps
CPU time 1.18 seconds
Started Feb 29 12:41:53 PM PST 24
Finished Feb 29 12:41:54 PM PST 24
Peak memory 182824 kb
Host smart-e417e080-88b0-4c33-87ff-541642777c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204663658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.4204663658
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.396415084
Short name T40
Test name
Test status
Simulation time 43451884881 ps
CPU time 17.4 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:42:06 PM PST 24
Peak memory 183012 kb
Host smart-468fef98-a2db-4167-a3b6-a588fff1fee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396415084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.396415084
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.2997855387
Short name T82
Test name
Test status
Simulation time 72598845021 ps
CPU time 426.33 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:48:52 PM PST 24
Peak memory 206104 kb
Host smart-dfa09428-8c2a-4c6e-a5ba-4bdc4fc70be1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997855387 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.2997855387
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.1063151611
Short name T262
Test name
Test status
Simulation time 445563187 ps
CPU time 0.64 seconds
Started Feb 29 12:42:01 PM PST 24
Finished Feb 29 12:42:02 PM PST 24
Peak memory 183016 kb
Host smart-a40954fc-d67f-466a-8287-ebc9aee5eb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063151611 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.1063151611
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.4272782944
Short name T251
Test name
Test status
Simulation time 58408518528 ps
CPU time 46.61 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 182896 kb
Host smart-9755b369-bec1-4db9-8c05-12072fc360b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272782944 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.4272782944
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.1264296101
Short name T192
Test name
Test status
Simulation time 441580774 ps
CPU time 0.78 seconds
Started Feb 29 12:42:01 PM PST 24
Finished Feb 29 12:42:02 PM PST 24
Peak memory 182940 kb
Host smart-12f3d1d8-d5b4-4357-90d0-e76f75a54210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264296101 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.1264296101
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.3503910789
Short name T127
Test name
Test status
Simulation time 509029567516 ps
CPU time 757.3 seconds
Started Feb 29 12:42:04 PM PST 24
Finished Feb 29 12:54:41 PM PST 24
Peak memory 193020 kb
Host smart-d1ed7d24-fa88-4589-804c-8bc703a0766c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503910789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.3503910789
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.1055097570
Short name T74
Test name
Test status
Simulation time 91205059137 ps
CPU time 868.92 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:56:39 PM PST 24
Peak memory 202124 kb
Host smart-8958b2f1-de02-449b-bb9f-93ad24a59f61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055097570 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.1055097570
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2669302261
Short name T71
Test name
Test status
Simulation time 636817918 ps
CPU time 0.67 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:42:22 PM PST 24
Peak memory 182900 kb
Host smart-5ad12e19-daa0-4401-b9ea-7f5eed1d45be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669302261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2669302261
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.1784261544
Short name T258
Test name
Test status
Simulation time 2327829532 ps
CPU time 2.98 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 182968 kb
Host smart-6eb92b3a-9745-4089-b2b1-b5c4f345b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784261544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.1784261544
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.3888110247
Short name T267
Test name
Test status
Simulation time 549216577 ps
CPU time 0.89 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:41:55 PM PST 24
Peak memory 182800 kb
Host smart-76914c40-aaf8-4de0-bc7b-4278e6701a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888110247 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.3888110247
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.3787755256
Short name T183
Test name
Test status
Simulation time 46973736934 ps
CPU time 17.82 seconds
Started Feb 29 12:42:03 PM PST 24
Finished Feb 29 12:42:21 PM PST 24
Peak memory 193312 kb
Host smart-0db571ff-0cff-4595-871d-5824833c166e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787755256 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.3787755256
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3855608799
Short name T76
Test name
Test status
Simulation time 167369328382 ps
CPU time 445.16 seconds
Started Feb 29 12:42:09 PM PST 24
Finished Feb 29 12:49:34 PM PST 24
Peak memory 197932 kb
Host smart-2212a87a-2139-43e0-8da3-71279106bd86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855608799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3855608799
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1332805759
Short name T46
Test name
Test status
Simulation time 602291571 ps
CPU time 1.59 seconds
Started Feb 29 12:42:05 PM PST 24
Finished Feb 29 12:42:07 PM PST 24
Peak memory 181236 kb
Host smart-8be8f103-d2ec-4035-8ac0-ceaa67fb2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332805759 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1332805759
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.2350151230
Short name T272
Test name
Test status
Simulation time 14960470573 ps
CPU time 4.88 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182940 kb
Host smart-17107f89-43b0-45a4-83c8-683f5235e6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350151230 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.2350151230
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.2101256924
Short name T178
Test name
Test status
Simulation time 409584873 ps
CPU time 0.67 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 182836 kb
Host smart-b3d3a8b7-538b-459e-800f-df6aa1d7936f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101256924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.2101256924
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.1935608117
Short name T271
Test name
Test status
Simulation time 201236181786 ps
CPU time 279.28 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:46:49 PM PST 24
Peak memory 182968 kb
Host smart-d0e59154-b0fd-4464-9178-8698e8e7b7f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935608117 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.1935608117
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all_with_rand_reset.936412266
Short name T248
Test name
Test status
Simulation time 181855106184 ps
CPU time 1038.01 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:59:31 PM PST 24
Peak memory 204400 kb
Host smart-6066537d-c97e-4564-9787-2cb6c3e31586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936412266 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_all_with_rand_reset.936412266
Directory /workspace/17.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.aon_timer_jump.3112189951
Short name T193
Test name
Test status
Simulation time 382524845 ps
CPU time 0.68 seconds
Started Feb 29 12:41:56 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 182920 kb
Host smart-e08ea680-9eac-473d-9d8e-3f0517effbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112189951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.3112189951
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.1284766687
Short name T223
Test name
Test status
Simulation time 5192048195 ps
CPU time 1.34 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 182964 kb
Host smart-f77fa118-0e42-42e3-8e09-4f178262e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284766687 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.1284766687
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.3388986962
Short name T121
Test name
Test status
Simulation time 357985947 ps
CPU time 1.09 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 182908 kb
Host smart-0807ce9c-8d50-481b-acf4-0468158db6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388986962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.3388986962
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all.759944491
Short name T247
Test name
Test status
Simulation time 291062895965 ps
CPU time 383.26 seconds
Started Feb 29 12:42:07 PM PST 24
Finished Feb 29 12:48:30 PM PST 24
Peak memory 182736 kb
Host smart-1238db6a-4981-45f6-b914-a090c542615a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759944491 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_a
ll.759944491
Directory /workspace/18.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.3456853576
Short name T26
Test name
Test status
Simulation time 164407166414 ps
CPU time 328.75 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:47:36 PM PST 24
Peak memory 197916 kb
Host smart-9601ad91-eec7-45ea-a6f7-1acdfee7ade1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456853576 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.3456853576
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.4276796732
Short name T153
Test name
Test status
Simulation time 468301902 ps
CPU time 0.61 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 182920 kb
Host smart-744fb29f-db08-4d67-8b68-e3126b7546c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276796732 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.4276796732
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.1424866493
Short name T280
Test name
Test status
Simulation time 30145326958 ps
CPU time 9.58 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 182928 kb
Host smart-be6b5d58-f182-494e-abf8-27ee38705314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424866493 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.1424866493
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.250038047
Short name T176
Test name
Test status
Simulation time 547041792 ps
CPU time 0.64 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:12 PM PST 24
Peak memory 182916 kb
Host smart-b8c1bccc-0a3d-412f-928d-698975e42a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250038047 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.250038047
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.2619356371
Short name T185
Test name
Test status
Simulation time 116077785292 ps
CPU time 154.77 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:44:52 PM PST 24
Peak memory 182980 kb
Host smart-483b9fc4-0326-4544-bd26-9b64b72ca4ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619356371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_
all.2619356371
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.1647299098
Short name T253
Test name
Test status
Simulation time 125216648393 ps
CPU time 344.01 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:47:39 PM PST 24
Peak memory 197908 kb
Host smart-7fec253b-2104-4f88-8f38-7391a76e9603
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647299098 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.1647299098
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.539516741
Short name T266
Test name
Test status
Simulation time 498274492 ps
CPU time 0.69 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 182940 kb
Host smart-eb253b77-6423-422f-8b8b-93ec8a621144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539516741 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.539516741
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.742497536
Short name T179
Test name
Test status
Simulation time 29152431044 ps
CPU time 11.88 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 183024 kb
Host smart-b2c9815d-79c4-4729-af93-b5714c0756ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742497536 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.742497536
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.1349819276
Short name T11
Test name
Test status
Simulation time 7414114409 ps
CPU time 11.11 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:53 PM PST 24
Peak memory 215180 kb
Host smart-d61c9569-cd55-4566-94ac-290fe97840f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349819276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.1349819276
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.3003590409
Short name T136
Test name
Test status
Simulation time 571039018 ps
CPU time 0.9 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 182860 kb
Host smart-0a05b383-94d7-483b-a65d-b30221600a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003590409 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.3003590409
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all.4110588340
Short name T238
Test name
Test status
Simulation time 208882893484 ps
CPU time 62.04 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:42:49 PM PST 24
Peak memory 183024 kb
Host smart-24e9c25c-48e6-4acb-830f-7e822539abee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110588340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_a
ll.4110588340
Directory /workspace/2.aon_timer_stress_all/latest

Test location /workspace/coverage/default/2.aon_timer_stress_all_with_rand_reset.825606419
Short name T80
Test name
Test status
Simulation time 148568551523 ps
CPU time 287.77 seconds
Started Feb 29 12:41:51 PM PST 24
Finished Feb 29 12:46:39 PM PST 24
Peak memory 198032 kb
Host smart-f6d06923-4468-4be3-9526-149d431e7fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825606419 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_stress_all_with_rand_reset.825606419
Directory /workspace/2.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.aon_timer_jump.2015235784
Short name T168
Test name
Test status
Simulation time 498902175 ps
CPU time 1.27 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:16 PM PST 24
Peak memory 182860 kb
Host smart-19d40b81-274a-4aa6-a7a7-29b8d1f19677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015235784 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.2015235784
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.3382593707
Short name T119
Test name
Test status
Simulation time 22569124084 ps
CPU time 23.7 seconds
Started Feb 29 12:42:09 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 182828 kb
Host smart-91855518-59e4-4b67-9194-bca64da9e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382593707 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.3382593707
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3941621572
Short name T201
Test name
Test status
Simulation time 563449001 ps
CPU time 0.98 seconds
Started Feb 29 12:42:05 PM PST 24
Finished Feb 29 12:42:07 PM PST 24
Peak memory 181152 kb
Host smart-5901c756-b13e-4187-971a-7aab3d6f58f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941621572 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3941621572
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all.1783800228
Short name T187
Test name
Test status
Simulation time 78187804910 ps
CPU time 26.97 seconds
Started Feb 29 12:42:06 PM PST 24
Finished Feb 29 12:42:33 PM PST 24
Peak memory 183052 kb
Host smart-89062539-f050-4f64-9c19-3ead3d3d8761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783800228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_
all.1783800228
Directory /workspace/20.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_jump.3189205128
Short name T287
Test name
Test status
Simulation time 352565254 ps
CPU time 0.91 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:12 PM PST 24
Peak memory 182796 kb
Host smart-910f57c1-7a21-41bf-82bd-f338cc4794d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189205128 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.3189205128
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.1382515515
Short name T112
Test name
Test status
Simulation time 20684932666 ps
CPU time 9.19 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 182996 kb
Host smart-45b8bc9e-a260-4c2d-9623-5f08e3ebfe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382515515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.1382515515
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.2082054092
Short name T275
Test name
Test status
Simulation time 452355637 ps
CPU time 1.18 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:12 PM PST 24
Peak memory 182912 kb
Host smart-2a579e32-75d1-439b-87f1-b4fa358e655e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082054092 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.2082054092
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1019326600
Short name T143
Test name
Test status
Simulation time 64587951713 ps
CPU time 27.17 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:46 PM PST 24
Peak memory 193068 kb
Host smart-2e521e50-fba0-4856-b8a2-588012da2d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019326600 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1019326600
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_jump.4052330362
Short name T89
Test name
Test status
Simulation time 440098201 ps
CPU time 0.84 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 182920 kb
Host smart-3d01464b-e951-407a-afe9-7aa3bf960d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052330362 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.4052330362
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.2408959609
Short name T239
Test name
Test status
Simulation time 15638534294 ps
CPU time 23.12 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182828 kb
Host smart-5a72c8e2-d134-48b8-bf37-776ddbddb6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408959609 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.2408959609
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.1479771030
Short name T195
Test name
Test status
Simulation time 398568049 ps
CPU time 0.85 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:42:10 PM PST 24
Peak memory 182788 kb
Host smart-baf41143-267a-4ee5-b4b8-263137c4f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479771030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.1479771030
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3922226990
Short name T96
Test name
Test status
Simulation time 101404912854 ps
CPU time 138.22 seconds
Started Feb 29 12:41:50 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 183076 kb
Host smart-9d0bbcef-4d70-4db0-b9c8-149f8b4f44bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922226990 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3922226990
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.746250527
Short name T73
Test name
Test status
Simulation time 181656580953 ps
CPU time 351.44 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:48:04 PM PST 24
Peak memory 197936 kb
Host smart-7c49a249-80ea-4105-a62a-bdad1229df58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746250527 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.746250527
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.299715456
Short name T13
Test name
Test status
Simulation time 501870843 ps
CPU time 1.22 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182852 kb
Host smart-0b84f470-985e-43aa-8985-b4d857560fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299715456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.299715456
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.555026296
Short name T224
Test name
Test status
Simulation time 34458166661 ps
CPU time 50.31 seconds
Started Feb 29 12:41:56 PM PST 24
Finished Feb 29 12:42:47 PM PST 24
Peak memory 182980 kb
Host smart-5788babd-ee4d-4990-8d73-5529ca144dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555026296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.555026296
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.494014035
Short name T256
Test name
Test status
Simulation time 556662211 ps
CPU time 0.89 seconds
Started Feb 29 12:42:05 PM PST 24
Finished Feb 29 12:42:06 PM PST 24
Peak memory 182924 kb
Host smart-9209d4c8-a3a5-492c-b388-dc325e43f448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494014035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.494014035
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.1892346084
Short name T91
Test name
Test status
Simulation time 341418232624 ps
CPU time 469.08 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:50:00 PM PST 24
Peak memory 194140 kb
Host smart-b42f7122-b49b-41e1-a16f-313fdcdaa823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892346084 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.1892346084
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.2284708829
Short name T200
Test name
Test status
Simulation time 161910993146 ps
CPU time 547.46 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:51:21 PM PST 24
Peak memory 197972 kb
Host smart-ae7c2e0d-c88c-4f94-a445-1e9b6932cb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284708829 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.2284708829
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.998123317
Short name T42
Test name
Test status
Simulation time 512902716 ps
CPU time 1.21 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 182916 kb
Host smart-1039f999-de0e-4835-8439-18974eb46e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998123317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.998123317
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.1862387040
Short name T233
Test name
Test status
Simulation time 41282478657 ps
CPU time 32.44 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:53 PM PST 24
Peak memory 183340 kb
Host smart-29fc90c6-4fcd-4c0e-a491-97276483e28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862387040 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.1862387040
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.2683513851
Short name T263
Test name
Test status
Simulation time 338181448 ps
CPU time 1.08 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:42:23 PM PST 24
Peak memory 182920 kb
Host smart-8d7841d6-0265-400f-94d6-1d346a3b726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683513851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.2683513851
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.1731384984
Short name T144
Test name
Test status
Simulation time 62909418811 ps
CPU time 45.92 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:43:00 PM PST 24
Peak memory 183048 kb
Host smart-1d6ee37b-5f59-4c26-b920-97a4e8e4d6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731384984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.1731384984
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/25.aon_timer_jump.2651643113
Short name T131
Test name
Test status
Simulation time 536208279 ps
CPU time 1.4 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:23 PM PST 24
Peak memory 182856 kb
Host smart-3980c48f-349f-48ff-a90e-806b73410180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651643113 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.2651643113
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.412440970
Short name T166
Test name
Test status
Simulation time 13873146486 ps
CPU time 4.87 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:42:15 PM PST 24
Peak memory 182956 kb
Host smart-2f0c8e76-b9e9-44b4-a5da-77b8c92483ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412440970 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.412440970
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.1180295582
Short name T203
Test name
Test status
Simulation time 517940257 ps
CPU time 0.6 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:42:16 PM PST 24
Peak memory 182928 kb
Host smart-37a31811-b441-437f-9ebd-cc2a380be74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180295582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.1180295582
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_jump.361140253
Short name T102
Test name
Test status
Simulation time 537871052 ps
CPU time 0.63 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:42:13 PM PST 24
Peak memory 182900 kb
Host smart-21096a71-9078-4e1e-b43b-8b74f2ba2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361140253 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.361140253
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.1254498056
Short name T172
Test name
Test status
Simulation time 23998713966 ps
CPU time 18.09 seconds
Started Feb 29 12:42:19 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 182996 kb
Host smart-57cc25a4-7e0f-4c10-911d-cc11c9a18407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254498056 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.1254498056
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.4157163986
Short name T108
Test name
Test status
Simulation time 525378417 ps
CPU time 1.22 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:27 PM PST 24
Peak memory 182940 kb
Host smart-c723109e-6182-43e8-ae35-62960f094d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157163986 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.4157163986
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2748739571
Short name T257
Test name
Test status
Simulation time 12219293070 ps
CPU time 5.51 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:26 PM PST 24
Peak memory 193048 kb
Host smart-9bfc7e14-be21-4ef9-a27c-7caf66b7b57f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748739571 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2748739571
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.3858280963
Short name T29
Test name
Test status
Simulation time 102005108973 ps
CPU time 209.46 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:45:58 PM PST 24
Peak memory 197920 kb
Host smart-52f07623-e1f9-413d-a477-729df4c3a6f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858280963 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.3858280963
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3671204015
Short name T6
Test name
Test status
Simulation time 373367675 ps
CPU time 0.82 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:42:18 PM PST 24
Peak memory 182948 kb
Host smart-9d4a5566-2419-482d-9b26-a5c09c5f88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671204015 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3671204015
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.1924445474
Short name T182
Test name
Test status
Simulation time 13341520752 ps
CPU time 5.76 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:14 PM PST 24
Peak memory 183060 kb
Host smart-a9ac59c1-8727-400f-9a50-4d476c3a0f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924445474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.1924445474
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.811951412
Short name T259
Test name
Test status
Simulation time 571391917 ps
CPU time 0.78 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182848 kb
Host smart-1a4d2e8a-4595-4c2e-b177-3d04265b07f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811951412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.811951412
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.1538677192
Short name T36
Test name
Test status
Simulation time 20522001757 ps
CPU time 3.28 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 182984 kb
Host smart-f60ede71-22c8-4758-b639-ca438430069e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538677192 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_
all.1538677192
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.430299956
Short name T145
Test name
Test status
Simulation time 578399225636 ps
CPU time 882.74 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 202764 kb
Host smart-29db69fe-293f-4aa7-a948-7fb37af1bec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430299956 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.430299956
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.1283910528
Short name T189
Test name
Test status
Simulation time 498210033 ps
CPU time 0.56 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 183276 kb
Host smart-d65eb0e8-dd45-4f09-8698-8a90d337210b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283910528 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.1283910528
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.130231340
Short name T194
Test name
Test status
Simulation time 28753247885 ps
CPU time 42.01 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:43:12 PM PST 24
Peak memory 183068 kb
Host smart-8cf9be62-6211-436d-912e-6dae550b7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130231340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.130231340
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.1532897368
Short name T150
Test name
Test status
Simulation time 487540742 ps
CPU time 0.62 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:42:13 PM PST 24
Peak memory 182816 kb
Host smart-de06bc18-013c-4886-ba81-779bb023fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532897368 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.1532897368
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.3990250859
Short name T16
Test name
Test status
Simulation time 114319552212 ps
CPU time 24.81 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:42:41 PM PST 24
Peak memory 193172 kb
Host smart-41a9cbfa-7e91-41f8-84dd-a57dbe3c26ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990250859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_
all.3990250859
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.1138657010
Short name T209
Test name
Test status
Simulation time 84247203181 ps
CPU time 656.8 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:53:15 PM PST 24
Peak memory 198984 kb
Host smart-af737787-ce21-459e-a9d6-e2f0e2294d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138657010 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.1138657010
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.aon_timer_jump.3348955521
Short name T151
Test name
Test status
Simulation time 434106890 ps
CPU time 0.72 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:15 PM PST 24
Peak memory 183000 kb
Host smart-62ba57ae-ca05-45c2-bf07-897482bed4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348955521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.3348955521
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.3651326068
Short name T220
Test name
Test status
Simulation time 44906467423 ps
CPU time 70.4 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 182896 kb
Host smart-b2c898a8-140f-45de-a3cb-0add0f479fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651326068 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.3651326068
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.2181012400
Short name T261
Test name
Test status
Simulation time 376655029 ps
CPU time 0.74 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:12 PM PST 24
Peak memory 182892 kb
Host smart-87a4a989-4aa1-4b2e-87d2-2a585af876a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181012400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.2181012400
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.410072695
Short name T268
Test name
Test status
Simulation time 182236672730 ps
CPU time 121.41 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 183340 kb
Host smart-36235552-24f0-4362-802e-1f9e84d5a884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410072695 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_a
ll.410072695
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.1933495082
Short name T92
Test name
Test status
Simulation time 169315449932 ps
CPU time 468.12 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:49:59 PM PST 24
Peak memory 197956 kb
Host smart-86cbe5e4-d83b-4c12-b1b9-91a8c5ad7ae6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933495082 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.1933495082
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.4102834668
Short name T7
Test name
Test status
Simulation time 549418534 ps
CPU time 0.74 seconds
Started Feb 29 12:41:50 PM PST 24
Finished Feb 29 12:41:51 PM PST 24
Peak memory 183012 kb
Host smart-89fc06bd-f3a1-42e9-ba44-06fc03c2c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102834668 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.4102834668
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.2859303844
Short name T156
Test name
Test status
Simulation time 17639897379 ps
CPU time 9.35 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:51 PM PST 24
Peak memory 182980 kb
Host smart-b3a62314-5eb4-4628-843d-c10ef0684665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859303844 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.2859303844
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.719911026
Short name T18
Test name
Test status
Simulation time 7122266963 ps
CPU time 12.79 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:42:01 PM PST 24
Peak memory 215156 kb
Host smart-c1b665b8-3336-49ff-b37c-ed19b84f5c9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719911026 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.719911026
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.551640621
Short name T118
Test name
Test status
Simulation time 434578332 ps
CPU time 0.73 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:41:50 PM PST 24
Peak memory 182816 kb
Host smart-b4575da3-ff8e-412e-9f8e-b74366c4c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551640621 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.551640621
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.4061430709
Short name T88
Test name
Test status
Simulation time 196208115007 ps
CPU time 81.78 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:43:07 PM PST 24
Peak memory 193176 kb
Host smart-6b466472-5a5e-4eef-9925-7b235bd15ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061430709 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_a
ll.4061430709
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1136999964
Short name T79
Test name
Test status
Simulation time 243380275608 ps
CPU time 907.25 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:57:05 PM PST 24
Peak memory 202388 kb
Host smart-31ecc940-7cc4-403f-bc56-679e95bc19cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136999964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1136999964
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.830765995
Short name T125
Test name
Test status
Simulation time 483271579 ps
CPU time 0.77 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:42:11 PM PST 24
Peak memory 182928 kb
Host smart-42a7a956-24a3-4348-86e4-fe2f3377fe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830765995 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.830765995
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.2829118688
Short name T47
Test name
Test status
Simulation time 39005128897 ps
CPU time 11.54 seconds
Started Feb 29 12:42:05 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182960 kb
Host smart-e85c36db-68a8-475d-95d5-5e8aa3f6aa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829118688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.2829118688
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.3121225144
Short name T174
Test name
Test status
Simulation time 353508284 ps
CPU time 0.8 seconds
Started Feb 29 12:42:19 PM PST 24
Finished Feb 29 12:42:20 PM PST 24
Peak memory 182820 kb
Host smart-7822b46b-01fc-4929-89d1-2aa338d14c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121225144 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.3121225144
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.71427118
Short name T212
Test name
Test status
Simulation time 172104044847 ps
CPU time 267.33 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:46:40 PM PST 24
Peak memory 183016 kb
Host smart-b10de764-9423-46fa-829d-cf1a163a8394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71427118 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_al
l.71427118
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.2584773654
Short name T90
Test name
Test status
Simulation time 78467684439 ps
CPU time 166.41 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:45:08 PM PST 24
Peak memory 198032 kb
Host smart-e5176079-7fd8-4f81-99cc-8cc66137ef5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584773654 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.2584773654
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.2210424390
Short name T35
Test name
Test status
Simulation time 572398894 ps
CPU time 0.76 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 183000 kb
Host smart-31d18e1d-0869-4a57-bbb1-2d7efc958c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210424390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.2210424390
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.971317503
Short name T44
Test name
Test status
Simulation time 29774868842 ps
CPU time 42.97 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:43:01 PM PST 24
Peak memory 182880 kb
Host smart-e96b0fa8-b8be-4eb8-ad61-e90d811f18f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971317503 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.971317503
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.497004286
Short name T216
Test name
Test status
Simulation time 476879957 ps
CPU time 0.68 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:27 PM PST 24
Peak memory 182852 kb
Host smart-1ae026ce-69a8-4fd6-8149-e5b8d08b9e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497004286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.497004286
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.2438733948
Short name T173
Test name
Test status
Simulation time 144398400570 ps
CPU time 109.32 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:43:49 PM PST 24
Peak memory 182988 kb
Host smart-caa600db-7c1f-41f6-913d-81117b1031d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438733948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.2438733948
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.174369834
Short name T78
Test name
Test status
Simulation time 83770726504 ps
CPU time 185.19 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:45:16 PM PST 24
Peak memory 197976 kb
Host smart-0b8a4485-50e5-4779-9685-047948d4d9a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174369834 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.174369834
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3048404262
Short name T14
Test name
Test status
Simulation time 457204679 ps
CPU time 0.9 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 182948 kb
Host smart-28eee041-f5f2-489c-9993-5a59f8fc53d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048404262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3048404262
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.3537925909
Short name T254
Test name
Test status
Simulation time 6652011632 ps
CPU time 9.74 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:36 PM PST 24
Peak memory 183004 kb
Host smart-17a1e6c7-1311-4f69-a580-f30fdf9b29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537925909 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.3537925909
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.3040992111
Short name T146
Test name
Test status
Simulation time 463936845 ps
CPU time 0.78 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:42:13 PM PST 24
Peak memory 182860 kb
Host smart-6d06d461-af52-4d64-985d-f5f4f0eb4b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040992111 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.3040992111
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.213761245
Short name T41
Test name
Test status
Simulation time 146791317639 ps
CPU time 61.14 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:43:29 PM PST 24
Peak memory 192992 kb
Host smart-e8986d99-21f2-4a02-a5ef-b255d9e0ba74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213761245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_a
ll.213761245
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3599996478
Short name T30
Test name
Test status
Simulation time 85168897574 ps
CPU time 647.5 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:53:16 PM PST 24
Peak memory 197908 kb
Host smart-065c8939-0c53-4eee-94b1-c32b4c22c200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599996478 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3599996478
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.3928382598
Short name T126
Test name
Test status
Simulation time 485210492 ps
CPU time 0.89 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:42:11 PM PST 24
Peak memory 183276 kb
Host smart-35d8dcd3-fae5-4a83-91c8-6574642efb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928382598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.3928382598
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.2716151332
Short name T120
Test name
Test status
Simulation time 11033033636 ps
CPU time 9.96 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 183048 kb
Host smart-07bb638b-5c89-4fe2-a11b-b63257ac14f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716151332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.2716151332
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.459568632
Short name T2
Test name
Test status
Simulation time 457684902 ps
CPU time 0.91 seconds
Started Feb 29 12:42:09 PM PST 24
Finished Feb 29 12:42:11 PM PST 24
Peak memory 182852 kb
Host smart-c6bae8fd-b752-4e74-861c-69b019795869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459568632 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.459568632
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.2248260452
Short name T232
Test name
Test status
Simulation time 14038884742 ps
CPU time 5.93 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 182976 kb
Host smart-fa96b417-f3f5-4073-aa0e-ab5115fcb0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248260452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.2248260452
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_jump.2455011885
Short name T132
Test name
Test status
Simulation time 431683484 ps
CPU time 0.69 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 182920 kb
Host smart-2f8e39d3-c194-425a-b90c-c99c809c20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455011885 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.2455011885
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.2462724203
Short name T213
Test name
Test status
Simulation time 8229723264 ps
CPU time 1.29 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:27 PM PST 24
Peak memory 183028 kb
Host smart-032086bd-59c3-4655-8e2a-ee36f4728519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462724203 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.2462724203
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.3844724763
Short name T161
Test name
Test status
Simulation time 535048178 ps
CPU time 1.22 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 183000 kb
Host smart-e3f56ef5-5506-4eb2-94ff-1121eeb358dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844724763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.3844724763
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.2527699877
Short name T43
Test name
Test status
Simulation time 65571804771 ps
CPU time 108.63 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 183004 kb
Host smart-6d76cf6a-8471-4f61-a84b-9e8e87c333a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527699877 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_
all.2527699877
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all_with_rand_reset.3602777660
Short name T206
Test name
Test status
Simulation time 29903341267 ps
CPU time 313.17 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:47:42 PM PST 24
Peak memory 198004 kb
Host smart-f7a580da-3a3e-4cdf-b82a-1b78527cafff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602777660 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_all_with_rand_reset.3602777660
Directory /workspace/34.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.aon_timer_jump.1025967032
Short name T34
Test name
Test status
Simulation time 502747461 ps
CPU time 0.69 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 182944 kb
Host smart-fd58d713-54ef-45cb-98cc-b6fc5ea170aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025967032 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.1025967032
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.223868051
Short name T116
Test name
Test status
Simulation time 12051367162 ps
CPU time 3.28 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:30 PM PST 24
Peak memory 182984 kb
Host smart-55e8ee9a-c530-4c4f-96ee-409ef81b4c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223868051 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.223868051
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.76628630
Short name T215
Test name
Test status
Simulation time 551446181 ps
CPU time 0.66 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 182848 kb
Host smart-6a5bb6a8-736b-4369-9f33-e4114ac3de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76628630 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.76628630
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2512485801
Short name T265
Test name
Test status
Simulation time 170159381450 ps
CPU time 447.84 seconds
Started Feb 29 12:42:12 PM PST 24
Finished Feb 29 12:49:40 PM PST 24
Peak memory 198020 kb
Host smart-647528d1-841a-43e0-aa1e-2b0f7fb4fcd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512485801 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2512485801
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.4133200376
Short name T274
Test name
Test status
Simulation time 428979704 ps
CPU time 0.9 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:42:16 PM PST 24
Peak memory 182948 kb
Host smart-da4febf3-7b8e-495b-8bcd-d27fa99bb7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133200376 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.4133200376
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.2935152324
Short name T205
Test name
Test status
Simulation time 24571522197 ps
CPU time 10.01 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:24 PM PST 24
Peak memory 183028 kb
Host smart-20f407ed-29d6-4513-9913-07a38e55b1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935152324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.2935152324
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.1512251908
Short name T264
Test name
Test status
Simulation time 476813271 ps
CPU time 0.9 seconds
Started Feb 29 12:42:24 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 182912 kb
Host smart-27a77127-effd-40dc-ad6b-0d4cad5a4639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512251908 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.1512251908
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.2991205951
Short name T180
Test name
Test status
Simulation time 23163609727 ps
CPU time 9.81 seconds
Started Feb 29 12:42:04 PM PST 24
Finished Feb 29 12:42:14 PM PST 24
Peak memory 193232 kb
Host smart-e47bced0-dca4-4bea-a2c8-6bbebf0b9099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991205951 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_
all.2991205951
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.1077085566
Short name T279
Test name
Test status
Simulation time 106095958638 ps
CPU time 299.83 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:47:27 PM PST 24
Peak memory 197964 kb
Host smart-3831280f-60f4-4b95-89a7-9f0b1718217e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077085566 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.1077085566
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.1598891666
Short name T249
Test name
Test status
Simulation time 530582331 ps
CPU time 1.33 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182948 kb
Host smart-049f6ad2-8dd3-4408-b5fb-833c55eed39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598891666 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.1598891666
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.1048086607
Short name T37
Test name
Test status
Simulation time 33576264234 ps
CPU time 26.82 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:45 PM PST 24
Peak memory 183164 kb
Host smart-442c59a0-cf09-487d-8198-7bb80acd7d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048086607 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.1048086607
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.255861547
Short name T245
Test name
Test status
Simulation time 355179094 ps
CPU time 1.06 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:12 PM PST 24
Peak memory 183184 kb
Host smart-d2b7e60f-47b4-49c4-a601-88ed79538f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255861547 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.255861547
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3308179073
Short name T100
Test name
Test status
Simulation time 158239897529 ps
CPU time 54.5 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:43:24 PM PST 24
Peak memory 194280 kb
Host smart-8e60f501-78e8-470b-b8b4-38373f4f3c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308179073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3308179073
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.2561891070
Short name T72
Test name
Test status
Simulation time 31093003146 ps
CPU time 320.31 seconds
Started Feb 29 12:42:07 PM PST 24
Finished Feb 29 12:47:28 PM PST 24
Peak memory 197848 kb
Host smart-f812d971-d3ad-4d01-9180-0e9f27342b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561891070 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.2561891070
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.2799979035
Short name T38
Test name
Test status
Simulation time 581768702 ps
CPU time 0.59 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:42:17 PM PST 24
Peak memory 182856 kb
Host smart-830e22fe-41d0-4564-8027-57b6a3048ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799979035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.2799979035
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.310742594
Short name T109
Test name
Test status
Simulation time 36345200759 ps
CPU time 51.17 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:43:02 PM PST 24
Peak memory 183004 kb
Host smart-c1b1face-2edf-480c-bdbc-a3d8d3b59548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310742594 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.310742594
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3873011035
Short name T225
Test name
Test status
Simulation time 600368026 ps
CPU time 0.63 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:42:18 PM PST 24
Peak memory 182848 kb
Host smart-a7717d54-8ee6-4fb6-ab3f-20a57f4b7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873011035 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3873011035
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.2372078447
Short name T159
Test name
Test status
Simulation time 48753463021 ps
CPU time 73.03 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:43:26 PM PST 24
Peak memory 193428 kb
Host smart-14eda8aa-329f-4883-b957-d5ef6d6f3554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372078447 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.2372078447
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.760931830
Short name T101
Test name
Test status
Simulation time 449554952 ps
CPU time 1.22 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 183280 kb
Host smart-2305b440-83e6-49c6-b186-7536be5d3f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760931830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.760931830
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.35610478
Short name T171
Test name
Test status
Simulation time 22178758104 ps
CPU time 24.7 seconds
Started Feb 29 12:42:13 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 183304 kb
Host smart-04baa868-7f4e-47e9-b59d-002f7cf17609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35610478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.35610478
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.86551718
Short name T164
Test name
Test status
Simulation time 524995462 ps
CPU time 0.72 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:22 PM PST 24
Peak memory 182936 kb
Host smart-6a74fd42-72ea-444a-850b-22efe6f3eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86551718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.86551718
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.3706769892
Short name T237
Test name
Test status
Simulation time 33715698348 ps
CPU time 51.64 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:43:09 PM PST 24
Peak memory 182996 kb
Host smart-b3be3509-5e30-4143-aa1e-114527870a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706769892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_
all.3706769892
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1886714166
Short name T163
Test name
Test status
Simulation time 72142054569 ps
CPU time 549.31 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:51:32 PM PST 24
Peak memory 198228 kb
Host smart-3dc4813e-c6f3-4344-a28d-3515c4953a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886714166 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1886714166
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.2838913423
Short name T230
Test name
Test status
Simulation time 396327265 ps
CPU time 1.13 seconds
Started Feb 29 12:41:56 PM PST 24
Finished Feb 29 12:41:58 PM PST 24
Peak memory 182916 kb
Host smart-a23b9459-ff21-4e76-86f9-ebf2d33bd12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838913423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.2838913423
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.2637973930
Short name T252
Test name
Test status
Simulation time 19533903682 ps
CPU time 29.39 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 183044 kb
Host smart-370bdc09-22f8-4627-9223-b054da18426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637973930 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.2637973930
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1732458250
Short name T19
Test name
Test status
Simulation time 4502361910 ps
CPU time 2.23 seconds
Started Feb 29 12:41:53 PM PST 24
Finished Feb 29 12:41:56 PM PST 24
Peak memory 215212 kb
Host smart-e26a17be-05e6-4c80-8203-538dc79370c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732458250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1732458250
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.3932889251
Short name T123
Test name
Test status
Simulation time 517695462 ps
CPU time 1.37 seconds
Started Feb 29 12:41:53 PM PST 24
Finished Feb 29 12:41:55 PM PST 24
Peak memory 182912 kb
Host smart-fae421dd-2591-430f-b989-631604dc6373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932889251 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.3932889251
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2333257828
Short name T167
Test name
Test status
Simulation time 42770316767 ps
CPU time 27.95 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:42:13 PM PST 24
Peak memory 193344 kb
Host smart-a6721ce4-4636-4a9f-b41c-4a32b0f84782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333257828 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2333257828
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.2098482809
Short name T75
Test name
Test status
Simulation time 92490293682 ps
CPU time 394.81 seconds
Started Feb 29 12:41:52 PM PST 24
Finished Feb 29 12:48:27 PM PST 24
Peak memory 197908 kb
Host smart-0a39ee3c-779b-4bf9-9d7d-ba51c3f67f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098482809 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.2098482809
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3957776634
Short name T260
Test name
Test status
Simulation time 457647255 ps
CPU time 0.67 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:22 PM PST 24
Peak memory 182948 kb
Host smart-488f1871-7ae5-4e9d-a1b9-d8649ca46973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957776634 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3957776634
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.4235263441
Short name T122
Test name
Test status
Simulation time 17076979121 ps
CPU time 2.42 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:38 PM PST 24
Peak memory 182976 kb
Host smart-8ec1d6d8-bdcf-4b8b-9191-b0408570f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235263441 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.4235263441
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.2567837002
Short name T181
Test name
Test status
Simulation time 356942254 ps
CPU time 1.1 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 182864 kb
Host smart-5da1b334-fddd-479a-9011-d1ef0f61905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567837002 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.2567837002
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.565373680
Short name T196
Test name
Test status
Simulation time 217206934093 ps
CPU time 79.97 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 193404 kb
Host smart-aaa97c57-3995-48d7-8830-5a92234cfc5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565373680 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_a
ll.565373680
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.2988761220
Short name T154
Test name
Test status
Simulation time 394896280 ps
CPU time 1.11 seconds
Started Feb 29 12:42:24 PM PST 24
Finished Feb 29 12:42:25 PM PST 24
Peak memory 182916 kb
Host smart-70942432-e625-4101-8d38-22540a4fa589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988761220 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.2988761220
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.1488021052
Short name T128
Test name
Test status
Simulation time 40815850068 ps
CPU time 37.46 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:42:59 PM PST 24
Peak memory 182960 kb
Host smart-b5d050a7-e737-419f-8509-cb3a267a7e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488021052 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.1488021052
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.3356075071
Short name T214
Test name
Test status
Simulation time 456497064 ps
CPU time 0.71 seconds
Started Feb 29 12:42:27 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 182832 kb
Host smart-99edbf5c-35b0-4ac6-8bf3-99aefcfe3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356075071 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.3356075071
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.3658779702
Short name T208
Test name
Test status
Simulation time 95030295502 ps
CPU time 71.37 seconds
Started Feb 29 12:42:33 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 183124 kb
Host smart-3f4f7ddb-a1d7-47b4-ad3d-1569624a325c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658779702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_
all.3658779702
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all_with_rand_reset.2932219927
Short name T243
Test name
Test status
Simulation time 74709657894 ps
CPU time 635.8 seconds
Started Feb 29 12:42:37 PM PST 24
Finished Feb 29 12:53:13 PM PST 24
Peak memory 198996 kb
Host smart-87436b5a-d689-45c1-8c4b-55178612f9c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932219927 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_all_with_rand_reset.2932219927
Directory /workspace/41.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.aon_timer_jump.3873350608
Short name T190
Test name
Test status
Simulation time 504811770 ps
CPU time 1.37 seconds
Started Feb 29 12:42:25 PM PST 24
Finished Feb 29 12:42:27 PM PST 24
Peak memory 182932 kb
Host smart-4fe8d2b1-1031-4346-a13c-8fe28515843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873350608 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.3873350608
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.1988746146
Short name T234
Test name
Test status
Simulation time 56324434156 ps
CPU time 21.13 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:53 PM PST 24
Peak memory 182904 kb
Host smart-fc57292d-57ed-430d-baa5-5040f81578f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988746146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.1988746146
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.1790856109
Short name T246
Test name
Test status
Simulation time 328590020 ps
CPU time 0.82 seconds
Started Feb 29 12:42:33 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 182960 kb
Host smart-eef4ecb7-864c-4997-8c73-25f0d113d9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790856109 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.1790856109
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3587239286
Short name T191
Test name
Test status
Simulation time 118434524974 ps
CPU time 96.19 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 182928 kb
Host smart-35ac5043-57cf-4919-989f-a73c6676e54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587239286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3587239286
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.2457861072
Short name T184
Test name
Test status
Simulation time 109748105919 ps
CPU time 490.18 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:50:41 PM PST 24
Peak memory 197916 kb
Host smart-f52436ec-2fe0-4fbb-9893-3856912a5973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457861072 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.2457861072
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.1759243780
Short name T104
Test name
Test status
Simulation time 498074627 ps
CPU time 0.92 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:32 PM PST 24
Peak memory 182088 kb
Host smart-0fdb8546-b8f6-4280-8561-5e6cc9a9f110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759243780 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.1759243780
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.2556937565
Short name T117
Test name
Test status
Simulation time 36582587513 ps
CPU time 26.15 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:58 PM PST 24
Peak memory 183100 kb
Host smart-d6f8f3a1-cc10-4711-a749-11c0d470ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556937565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.2556937565
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.653587754
Short name T133
Test name
Test status
Simulation time 556495290 ps
CPU time 1.15 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 182896 kb
Host smart-f0dfacbc-f092-457f-a154-ee4f2e770d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653587754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.653587754
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.2788331467
Short name T269
Test name
Test status
Simulation time 115906926619 ps
CPU time 179.6 seconds
Started Feb 29 12:42:17 PM PST 24
Finished Feb 29 12:45:17 PM PST 24
Peak memory 183048 kb
Host smart-b09be4e8-6842-4db1-a72e-5f3f9f9a6230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788331467 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.2788331467
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.554190434
Short name T276
Test name
Test status
Simulation time 480907253185 ps
CPU time 395.89 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:49:07 PM PST 24
Peak memory 197880 kb
Host smart-7d987641-e492-4b07-9376-c99801021847
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554190434 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.554190434
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.3053977797
Short name T115
Test name
Test status
Simulation time 502774403 ps
CPU time 0.98 seconds
Started Feb 29 12:42:20 PM PST 24
Finished Feb 29 12:42:21 PM PST 24
Peak memory 182928 kb
Host smart-9ba49a17-5d5a-456a-86dd-e74b3c435f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053977797 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.3053977797
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.730686509
Short name T284
Test name
Test status
Simulation time 38723039410 ps
CPU time 56.4 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:43:11 PM PST 24
Peak memory 182956 kb
Host smart-37d5e5d0-61ad-403c-89c5-ac9de23c5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730686509 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.730686509
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.2257256919
Short name T142
Test name
Test status
Simulation time 467607276 ps
CPU time 0.65 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:28 PM PST 24
Peak memory 182796 kb
Host smart-ca2e477e-90fa-4a5e-ad67-99f48398ccd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257256919 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.2257256919
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.384946351
Short name T105
Test name
Test status
Simulation time 256615042510 ps
CPU time 91.75 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 193196 kb
Host smart-ee796c6a-bea0-4abc-9889-7593ce559c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384946351 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_a
ll.384946351
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.3981579527
Short name T285
Test name
Test status
Simulation time 111848494074 ps
CPU time 594.29 seconds
Started Feb 29 12:42:19 PM PST 24
Finished Feb 29 12:52:13 PM PST 24
Peak memory 199004 kb
Host smart-587f5101-2893-4616-920d-f937723686bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981579527 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.3981579527
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.3477365841
Short name T98
Test name
Test status
Simulation time 430507495 ps
CPU time 0.68 seconds
Started Feb 29 12:42:36 PM PST 24
Finished Feb 29 12:42:37 PM PST 24
Peak memory 182940 kb
Host smart-2fa82ecc-d4b8-4fa3-9dce-97cb8265b142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477365841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.3477365841
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.4096767798
Short name T231
Test name
Test status
Simulation time 28408338060 ps
CPU time 5.86 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:35 PM PST 24
Peak memory 182936 kb
Host smart-ac9a0994-a8d5-48e1-bb88-126425c9dcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096767798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.4096767798
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2955922771
Short name T169
Test name
Test status
Simulation time 484147017 ps
CPU time 0.93 seconds
Started Feb 29 12:42:33 PM PST 24
Finished Feb 29 12:42:34 PM PST 24
Peak memory 182904 kb
Host smart-4e9707d0-b768-4a34-b1e6-a3878cafab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955922771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2955922771
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.146902044
Short name T278
Test name
Test status
Simulation time 236276437121 ps
CPU time 365.54 seconds
Started Feb 29 12:42:32 PM PST 24
Finished Feb 29 12:48:38 PM PST 24
Peak memory 183012 kb
Host smart-5ed2a3b7-fb38-4766-8d2b-4958513c99b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146902044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_a
ll.146902044
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.778078094
Short name T198
Test name
Test status
Simulation time 120199991189 ps
CPU time 621.4 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 206140 kb
Host smart-9a448873-2049-4bf9-8269-f9f164d95e2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778078094 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.778078094
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1153130854
Short name T141
Test name
Test status
Simulation time 467561352 ps
CPU time 0.67 seconds
Started Feb 29 12:42:42 PM PST 24
Finished Feb 29 12:42:44 PM PST 24
Peak memory 182796 kb
Host smart-07303cd5-54ad-4344-bde3-5a55f027ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153130854 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1153130854
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2197165402
Short name T199
Test name
Test status
Simulation time 52033545906 ps
CPU time 17.02 seconds
Started Feb 29 12:42:26 PM PST 24
Finished Feb 29 12:42:44 PM PST 24
Peak memory 182904 kb
Host smart-d7ddd62c-ac6d-447c-8491-adfb5c36dbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197165402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2197165402
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.359990895
Short name T235
Test name
Test status
Simulation time 387346666 ps
CPU time 1.04 seconds
Started Feb 29 12:42:31 PM PST 24
Finished Feb 29 12:42:32 PM PST 24
Peak memory 182852 kb
Host smart-9280fb10-6aa0-4e60-8064-d955d2cee682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359990895 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.359990895
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.1049189065
Short name T162
Test name
Test status
Simulation time 200083492080 ps
CPU time 137.93 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 193184 kb
Host smart-3b193a9d-79bf-4c60-bf08-f389cdf1b375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049189065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_
all.1049189065
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.404155938
Short name T177
Test name
Test status
Simulation time 120893553891 ps
CPU time 298.64 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:47:14 PM PST 24
Peak memory 197956 kb
Host smart-6961488a-b8b7-4f71-8ff2-1301e05fe457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404155938 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.404155938
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.2439703635
Short name T114
Test name
Test status
Simulation time 551930690 ps
CPU time 0.98 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:42:24 PM PST 24
Peak memory 182920 kb
Host smart-ea89fa7f-78d6-4908-a7f2-59e71aae2e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439703635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.2439703635
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2074437340
Short name T129
Test name
Test status
Simulation time 16018788753 ps
CPU time 26.36 seconds
Started Feb 29 12:42:28 PM PST 24
Finished Feb 29 12:42:56 PM PST 24
Peak memory 183004 kb
Host smart-635a1a0e-7b44-4476-85e8-3aca6aedfb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074437340 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2074437340
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.181284521
Short name T110
Test name
Test status
Simulation time 501108041 ps
CPU time 1.27 seconds
Started Feb 29 12:42:30 PM PST 24
Finished Feb 29 12:42:31 PM PST 24
Peak memory 182896 kb
Host smart-f7cf622b-969c-490c-bada-ec7cc711ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181284521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.181284521
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.1175900693
Short name T94
Test name
Test status
Simulation time 156214959944 ps
CPU time 24.48 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:42:45 PM PST 24
Peak memory 182980 kb
Host smart-42f5b7ee-4144-406d-8d43-88dca59d99b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175900693 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.1175900693
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all_with_rand_reset.3749279677
Short name T255
Test name
Test status
Simulation time 24785859107 ps
CPU time 108.18 seconds
Started Feb 29 12:42:21 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 197976 kb
Host smart-db265f0a-71b2-4274-aeaf-3745168e5c2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749279677 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_all_with_rand_reset.3749279677
Directory /workspace/47.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.aon_timer_jump.879676419
Short name T186
Test name
Test status
Simulation time 504202609 ps
CPU time 1.25 seconds
Started Feb 29 12:42:16 PM PST 24
Finished Feb 29 12:42:18 PM PST 24
Peak memory 182992 kb
Host smart-e53ef778-7093-4171-a5b5-af015c66ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879676419 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.879676419
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1358975250
Short name T204
Test name
Test status
Simulation time 4543720592 ps
CPU time 2.99 seconds
Started Feb 29 12:42:25 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 183004 kb
Host smart-f0b79425-961c-47e8-a78c-9c0120d93191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358975250 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1358975250
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1719656100
Short name T218
Test name
Test status
Simulation time 375303047 ps
CPU time 1.21 seconds
Started Feb 29 12:42:20 PM PST 24
Finished Feb 29 12:42:21 PM PST 24
Peak memory 182820 kb
Host smart-8d5a0cfe-c584-4ee9-bca8-570b1658d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719656100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1719656100
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.9238984
Short name T170
Test name
Test status
Simulation time 663643809089 ps
CPU time 988.39 seconds
Started Feb 29 12:42:23 PM PST 24
Finished Feb 29 12:58:51 PM PST 24
Peak memory 194440 kb
Host smart-f80594ec-f789-40da-aae6-197318d44cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9238984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all.9238984
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all_with_rand_reset.1385852864
Short name T31
Test name
Test status
Simulation time 117630670211 ps
CPU time 215.26 seconds
Started Feb 29 12:42:22 PM PST 24
Finished Feb 29 12:45:57 PM PST 24
Peak memory 197892 kb
Host smart-91a76508-5f08-457b-851e-3f1adee56388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385852864 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_all_with_rand_reset.1385852864
Directory /workspace/48.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.aon_timer_jump.4075545252
Short name T113
Test name
Test status
Simulation time 600858723 ps
CPU time 0.62 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:19 PM PST 24
Peak memory 183148 kb
Host smart-35616444-7c2d-4657-8592-b7c14bb096cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075545252 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.4075545252
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.1738130423
Short name T160
Test name
Test status
Simulation time 13706057561 ps
CPU time 20.86 seconds
Started Feb 29 12:42:18 PM PST 24
Finished Feb 29 12:42:39 PM PST 24
Peak memory 182888 kb
Host smart-34c9cedd-4f07-4f1b-9c42-6219be9d3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738130423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.1738130423
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.2462627671
Short name T148
Test name
Test status
Simulation time 500963635 ps
CPU time 1.33 seconds
Started Feb 29 12:42:51 PM PST 24
Finished Feb 29 12:42:53 PM PST 24
Peak memory 182916 kb
Host smart-bfbcd865-e458-4831-a8c9-05f948fd1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462627671 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.2462627671
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3280003279
Short name T15
Test name
Test status
Simulation time 66988534312 ps
CPU time 28.74 seconds
Started Feb 29 12:42:34 PM PST 24
Finished Feb 29 12:43:03 PM PST 24
Peak memory 193600 kb
Host smart-f8a2b645-b789-46d6-940b-9c9e49e29c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280003279 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3280003279
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.2235003316
Short name T282
Test name
Test status
Simulation time 653394084995 ps
CPU time 316.97 seconds
Started Feb 29 12:42:29 PM PST 24
Finished Feb 29 12:47:47 PM PST 24
Peak memory 206132 kb
Host smart-7801e5af-5f13-477d-a0d6-7ef2b7edaae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235003316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.2235003316
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.2504615398
Short name T103
Test name
Test status
Simulation time 483701564 ps
CPU time 1.29 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 182092 kb
Host smart-7254ce80-1035-47be-8b78-f30a5cd83927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504615398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.2504615398
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.1649570398
Short name T39
Test name
Test status
Simulation time 47713641194 ps
CPU time 67.02 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:43:04 PM PST 24
Peak memory 183048 kb
Host smart-ecedce35-c625-4dbd-b7b0-c73cb9cb49a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649570398 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.1649570398
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.3573731782
Short name T134
Test name
Test status
Simulation time 429232726 ps
CPU time 1.16 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 182520 kb
Host smart-09b74cc4-425b-4966-abdd-fcff7ca673fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573731782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.3573731782
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.1774087552
Short name T140
Test name
Test status
Simulation time 151901872837 ps
CPU time 228.53 seconds
Started Feb 29 12:42:15 PM PST 24
Finished Feb 29 12:46:04 PM PST 24
Peak memory 191260 kb
Host smart-71fba456-93b8-4b4e-87a2-a557b591d2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774087552 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.1774087552
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.1985345509
Short name T219
Test name
Test status
Simulation time 16461233457 ps
CPU time 118.84 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 197960 kb
Host smart-a25cf210-1165-4cdb-b087-8efd5b4ef32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985345509 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.1985345509
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1995517216
Short name T138
Test name
Test status
Simulation time 575434284 ps
CPU time 0.75 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:56 PM PST 24
Peak memory 183016 kb
Host smart-4f1740f1-66dc-4bee-89c9-276b4102abe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995517216 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1995517216
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.606210750
Short name T229
Test name
Test status
Simulation time 44778265526 ps
CPU time 66.48 seconds
Started Feb 29 12:42:10 PM PST 24
Finished Feb 29 12:43:17 PM PST 24
Peak memory 183028 kb
Host smart-3a253237-01e5-4239-8cd4-db7477614b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606210750 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.606210750
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2604528353
Short name T22
Test name
Test status
Simulation time 485103259 ps
CPU time 1.33 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 182992 kb
Host smart-e42d3a9d-dd25-4c22-8c85-937fff0efd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604528353 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2604528353
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.458056483
Short name T244
Test name
Test status
Simulation time 136718397696 ps
CPU time 117.6 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:43:53 PM PST 24
Peak memory 183076 kb
Host smart-3670b53d-5b42-4949-80a0-3549413dea12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458056483 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_al
l.458056483
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.1950209316
Short name T158
Test name
Test status
Simulation time 414271537612 ps
CPU time 720.6 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:53:56 PM PST 24
Peak memory 200152 kb
Host smart-9aa4f638-8987-4992-b191-cc417a0ac91b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950209316 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.1950209316
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3859873897
Short name T45
Test name
Test status
Simulation time 430650106 ps
CPU time 0.7 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 182944 kb
Host smart-36376629-c375-4ba8-a1d2-0ea59ad88f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859873897 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3859873897
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.2362201604
Short name T236
Test name
Test status
Simulation time 20632670957 ps
CPU time 33.43 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:45 PM PST 24
Peak memory 182976 kb
Host smart-346b3e0d-c5de-4b70-aa08-69ce73c55c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362201604 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.2362201604
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.3659947356
Short name T283
Test name
Test status
Simulation time 535267727 ps
CPU time 0.71 seconds
Started Feb 29 12:42:14 PM PST 24
Finished Feb 29 12:42:15 PM PST 24
Peak memory 182912 kb
Host smart-a22059bd-508b-43ff-b14a-09c6c1c47eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659947356 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.3659947356
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3020977618
Short name T1
Test name
Test status
Simulation time 66300941165 ps
CPU time 26.1 seconds
Started Feb 29 12:42:03 PM PST 24
Finished Feb 29 12:42:29 PM PST 24
Peak memory 182976 kb
Host smart-b5d53633-4148-4098-9bdd-a992ef410c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020977618 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3020977618
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.2848667619
Short name T250
Test name
Test status
Simulation time 60203332165 ps
CPU time 230.23 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:45:39 PM PST 24
Peak memory 197880 kb
Host smart-fa00c3ea-e3cf-4f0b-bf8f-d2cabc52d7fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848667619 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.2848667619
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2284047500
Short name T228
Test name
Test status
Simulation time 456645496 ps
CPU time 0.89 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 182924 kb
Host smart-5a6a8d31-bd53-4377-8383-efa097af59ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284047500 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2284047500
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.2601425276
Short name T165
Test name
Test status
Simulation time 17928291954 ps
CPU time 25.66 seconds
Started Feb 29 12:42:00 PM PST 24
Finished Feb 29 12:42:26 PM PST 24
Peak memory 183048 kb
Host smart-eacebcd4-f59f-49f0-91b5-dd1f0fd70dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601425276 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.2601425276
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1650163826
Short name T3
Test name
Test status
Simulation time 443793305 ps
CPU time 1.23 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 182884 kb
Host smart-7b5697ec-3311-42f4-8744-aa4ea1fa1c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650163826 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1650163826
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.880819105
Short name T9
Test name
Test status
Simulation time 4361443155 ps
CPU time 3.65 seconds
Started Feb 29 12:42:11 PM PST 24
Finished Feb 29 12:42:14 PM PST 24
Peak memory 193068 kb
Host smart-db1e794f-0727-49fc-b25d-0fb301be22bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880819105 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_al
l.880819105
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.1795496432
Short name T157
Test name
Test status
Simulation time 23207486130 ps
CPU time 235.32 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:45:53 PM PST 24
Peak memory 197812 kb
Host smart-901b277a-1f7d-47f4-a3d0-c57458fc6da4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795496432 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.1795496432
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.aon_timer_jump.3570446790
Short name T202
Test name
Test status
Simulation time 358609622 ps
CPU time 1.18 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 183032 kb
Host smart-3e0dcfeb-3966-4e0e-9237-0749b5f9e8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570446790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.3570446790
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.576883442
Short name T12
Test name
Test status
Simulation time 5264517050 ps
CPU time 2.82 seconds
Started Feb 29 12:42:00 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 182892 kb
Host smart-34b4a506-4262-485b-9573-958e49ed2291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576883442 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.576883442
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.2353210849
Short name T217
Test name
Test status
Simulation time 582896530 ps
CPU time 1.46 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 182840 kb
Host smart-35c7f20a-f532-4e48-97e4-09d326f3c3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353210849 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.2353210849
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.212551694
Short name T286
Test name
Test status
Simulation time 217487880252 ps
CPU time 163.29 seconds
Started Feb 29 12:41:48 PM PST 24
Finished Feb 29 12:44:32 PM PST 24
Peak memory 193072 kb
Host smart-034087ed-2d8f-40c8-ab04-b278dd53e328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212551694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_al
l.212551694
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2708924778
Short name T273
Test name
Test status
Simulation time 44901436611 ps
CPU time 460.03 seconds
Started Feb 29 12:41:50 PM PST 24
Finished Feb 29 12:49:30 PM PST 24
Peak memory 197960 kb
Host smart-d2cff0e3-37cf-4634-900b-6662937e77b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708924778 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2708924778
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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