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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.98 99.25 93.67 100.00 98.40 99.51 67.06


Total test records in report: 417
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T29 /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1428413097 Mar 03 12:32:46 PM PST 24 Mar 03 12:32:53 PM PST 24 4410369138 ps
T279 /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1067759663 Mar 03 12:32:31 PM PST 24 Mar 03 12:32:32 PM PST 24 539097148 ps
T58 /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2031458955 Mar 03 12:32:37 PM PST 24 Mar 03 12:32:41 PM PST 24 2446549613 ps
T45 /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2165262838 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 460192182 ps
T59 /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.129423089 Mar 03 12:32:20 PM PST 24 Mar 03 12:32:22 PM PST 24 1996892792 ps
T46 /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1100166836 Mar 03 12:32:07 PM PST 24 Mar 03 12:32:08 PM PST 24 446584868 ps
T280 /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2616049576 Mar 03 12:32:48 PM PST 24 Mar 03 12:32:50 PM PST 24 454557089 ps
T281 /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2234814249 Mar 03 12:32:20 PM PST 24 Mar 03 12:32:22 PM PST 24 520729101 ps
T282 /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3184269764 Mar 03 12:32:43 PM PST 24 Mar 03 12:32:44 PM PST 24 347677827 ps
T283 /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.274470815 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 339499633 ps
T284 /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1692139039 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:23 PM PST 24 387313072 ps
T285 /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1543949754 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:23 PM PST 24 307175229 ps
T30 /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1384342643 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:32 PM PST 24 4441086787 ps
T60 /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2159887876 Mar 03 12:32:59 PM PST 24 Mar 03 12:33:06 PM PST 24 1154307164 ps
T286 /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2089763878 Mar 03 12:32:58 PM PST 24 Mar 03 12:32:59 PM PST 24 344892300 ps
T287 /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2205745746 Mar 03 12:32:45 PM PST 24 Mar 03 12:32:45 PM PST 24 472279094 ps
T61 /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2981015097 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:27 PM PST 24 1014710370 ps
T288 /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3365024044 Mar 03 12:32:36 PM PST 24 Mar 03 12:32:38 PM PST 24 560964576 ps
T289 /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3414893150 Mar 03 12:32:31 PM PST 24 Mar 03 12:32:32 PM PST 24 392057082 ps
T290 /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2803570446 Mar 03 12:32:56 PM PST 24 Mar 03 12:32:57 PM PST 24 442578731 ps
T291 /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2526106262 Mar 03 12:32:50 PM PST 24 Mar 03 12:32:51 PM PST 24 539995074 ps
T292 /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2789698892 Mar 03 12:32:37 PM PST 24 Mar 03 12:32:39 PM PST 24 442810295 ps
T293 /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3224722027 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:27 PM PST 24 519439506 ps
T62 /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3952302258 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:22 PM PST 24 1661194599 ps
T82 /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1085295979 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:38 PM PST 24 8180043904 ps
T47 /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3440749535 Mar 03 12:32:39 PM PST 24 Mar 03 12:32:39 PM PST 24 655402879 ps
T294 /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1591432767 Mar 03 12:32:44 PM PST 24 Mar 03 12:32:45 PM PST 24 323523768 ps
T63 /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.656362179 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:27 PM PST 24 1373887966 ps
T295 /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2236889456 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 490333420 ps
T83 /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2941215074 Mar 03 12:32:43 PM PST 24 Mar 03 12:32:56 PM PST 24 8378504828 ps
T64 /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.651086202 Mar 03 12:32:46 PM PST 24 Mar 03 12:32:47 PM PST 24 535551607 ps
T48 /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1891346184 Mar 03 12:32:46 PM PST 24 Mar 03 12:32:48 PM PST 24 519652150 ps
T49 /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.998672377 Mar 03 12:32:31 PM PST 24 Mar 03 12:32:32 PM PST 24 433611036 ps
T296 /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1597841814 Mar 03 12:32:39 PM PST 24 Mar 03 12:32:40 PM PST 24 460234172 ps
T297 /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3043308834 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:37 PM PST 24 509002273 ps
T298 /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1296747782 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 486679282 ps
T299 /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4104057870 Mar 03 12:32:46 PM PST 24 Mar 03 12:32:48 PM PST 24 972671535 ps
T300 /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3775471456 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 514670413 ps
T301 /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.989342457 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:43 PM PST 24 13942116515 ps
T79 /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.346596521 Mar 03 12:32:37 PM PST 24 Mar 03 12:32:41 PM PST 24 8376600581 ps
T302 /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3384747900 Mar 03 12:32:57 PM PST 24 Mar 03 12:32:59 PM PST 24 460337190 ps
T303 /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.32401420 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 605256197 ps
T304 /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2840568917 Mar 03 12:32:55 PM PST 24 Mar 03 12:32:57 PM PST 24 481285230 ps
T305 /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2847648639 Mar 03 12:32:39 PM PST 24 Mar 03 12:32:40 PM PST 24 393278322 ps
T306 /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3985950400 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 393878135 ps
T307 /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.33311271 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:27 PM PST 24 409694025 ps
T308 /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2706955100 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 354601539 ps
T50 /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1476797851 Mar 03 12:32:39 PM PST 24 Mar 03 12:32:40 PM PST 24 581254355 ps
T309 /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2551017605 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:35 PM PST 24 514773095 ps
T310 /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2508140890 Mar 03 12:32:31 PM PST 24 Mar 03 12:32:34 PM PST 24 2824475662 ps
T311 /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2062738510 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 426743978 ps
T312 /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.862848208 Mar 03 12:32:17 PM PST 24 Mar 03 12:32:19 PM PST 24 506917626 ps
T313 /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2896692286 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 523056864 ps
T51 /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2029453817 Mar 03 12:32:40 PM PST 24 Mar 03 12:32:41 PM PST 24 310110507 ps
T314 /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3758399225 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:11 PM PST 24 329045156 ps
T315 /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.478810767 Mar 03 12:32:33 PM PST 24 Mar 03 12:32:35 PM PST 24 872025615 ps
T52 /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3919422123 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 523294250 ps
T316 /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.68137077 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:29 PM PST 24 318311330 ps
T317 /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3680726449 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 848661522 ps
T318 /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2927793824 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:24 PM PST 24 400506931 ps
T319 /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.123363489 Mar 03 12:32:45 PM PST 24 Mar 03 12:32:46 PM PST 24 662105333 ps
T320 /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2904721408 Mar 03 12:32:47 PM PST 24 Mar 03 12:32:48 PM PST 24 434992557 ps
T321 /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.691404183 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:24 PM PST 24 448447750 ps
T322 /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2967299380 Mar 03 12:32:36 PM PST 24 Mar 03 12:32:37 PM PST 24 285994690 ps
T323 /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3088444063 Mar 03 12:32:31 PM PST 24 Mar 03 12:32:32 PM PST 24 438914878 ps
T324 /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2967046577 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 1498895175 ps
T325 /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1803695329 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:28 PM PST 24 525241967 ps
T80 /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2987556213 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:37 PM PST 24 7956548337 ps
T326 /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1171407472 Mar 03 12:32:51 PM PST 24 Mar 03 12:32:52 PM PST 24 573654841 ps
T327 /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.213429478 Mar 03 12:32:07 PM PST 24 Mar 03 12:32:10 PM PST 24 569242946 ps
T328 /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3633685324 Mar 03 12:32:27 PM PST 24 Mar 03 12:32:28 PM PST 24 314660677 ps
T329 /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.906432390 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:36 PM PST 24 506355627 ps
T330 /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2670908069 Mar 03 12:32:34 PM PST 24 Mar 03 12:32:36 PM PST 24 564083520 ps
T331 /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3344336468 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:34 PM PST 24 8646586461 ps
T332 /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.113564847 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:31 PM PST 24 582749161 ps
T333 /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1165844363 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 528270007 ps
T84 /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1675745637 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:16 PM PST 24 8654301951 ps
T334 /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.354228575 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:26 PM PST 24 405534297 ps
T335 /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3597499332 Mar 03 12:32:39 PM PST 24 Mar 03 12:32:40 PM PST 24 1185781639 ps
T336 /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1654936720 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:24 PM PST 24 573798342 ps
T53 /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3079015984 Mar 03 12:32:32 PM PST 24 Mar 03 12:32:35 PM PST 24 1122541650 ps
T337 /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3083626889 Mar 03 12:32:42 PM PST 24 Mar 03 12:32:43 PM PST 24 304581543 ps
T338 /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.591424280 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:25 PM PST 24 2195831241 ps
T55 /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1738542180 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:33 PM PST 24 6990470125 ps
T339 /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.277939304 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:28 PM PST 24 394488227 ps
T340 /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1528273223 Mar 03 12:32:34 PM PST 24 Mar 03 12:32:36 PM PST 24 759672154 ps
T341 /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.333336752 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 433815522 ps
T81 /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.24708945 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:30 PM PST 24 8501648892 ps
T342 /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2871604595 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:43 PM PST 24 4607954288 ps
T343 /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2105527266 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 519094910 ps
T344 /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4193199560 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:24 PM PST 24 482910560 ps
T345 /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1604885555 Mar 03 12:32:32 PM PST 24 Mar 03 12:32:33 PM PST 24 1139691195 ps
T346 /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2641665774 Mar 03 12:33:01 PM PST 24 Mar 03 12:33:03 PM PST 24 275850737 ps
T347 /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1274329416 Mar 03 12:32:51 PM PST 24 Mar 03 12:32:59 PM PST 24 8041910370 ps
T348 /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3274220322 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:23 PM PST 24 631610203 ps
T349 /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2591262048 Mar 03 12:32:33 PM PST 24 Mar 03 12:32:34 PM PST 24 274662858 ps
T350 /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4041734083 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:24 PM PST 24 464143184 ps
T351 /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2860321300 Mar 03 12:32:16 PM PST 24 Mar 03 12:32:17 PM PST 24 377977463 ps
T352 /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4167628423 Mar 03 12:32:29 PM PST 24 Mar 03 12:32:32 PM PST 24 627328034 ps
T353 /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1813904296 Mar 03 12:32:56 PM PST 24 Mar 03 12:32:57 PM PST 24 309483085 ps
T354 /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2647739383 Mar 03 12:32:14 PM PST 24 Mar 03 12:32:19 PM PST 24 4129667356 ps
T355 /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3756640704 Mar 03 12:32:44 PM PST 24 Mar 03 12:32:45 PM PST 24 1531606295 ps
T356 /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.78630421 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 2021411400 ps
T357 /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.163237347 Mar 03 12:32:44 PM PST 24 Mar 03 12:32:45 PM PST 24 648924351 ps
T358 /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2980130278 Mar 03 12:32:56 PM PST 24 Mar 03 12:33:00 PM PST 24 621483301 ps
T359 /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.442307039 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 458434912 ps
T360 /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3912995225 Mar 03 12:32:27 PM PST 24 Mar 03 12:32:28 PM PST 24 438634099 ps
T361 /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2839149875 Mar 03 12:32:20 PM PST 24 Mar 03 12:32:28 PM PST 24 4471443256 ps
T362 /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1460270228 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:24 PM PST 24 414196562 ps
T363 /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2784490904 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:25 PM PST 24 4356781954 ps
T364 /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1945574540 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:27 PM PST 24 438627137 ps
T365 /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3485737319 Mar 03 12:32:14 PM PST 24 Mar 03 12:32:15 PM PST 24 376411875 ps
T56 /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1965486120 Mar 03 12:32:18 PM PST 24 Mar 03 12:32:19 PM PST 24 502693778 ps
T366 /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.925996150 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:36 PM PST 24 415389060 ps
T367 /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2545145175 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:23 PM PST 24 554703166 ps
T368 /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3586830598 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:25 PM PST 24 8237422181 ps
T57 /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.948616063 Mar 03 12:32:56 PM PST 24 Mar 03 12:32:57 PM PST 24 546340876 ps
T54 /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3321150765 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:20 PM PST 24 8087122740 ps
T369 /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1929373862 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:28 PM PST 24 592431144 ps
T370 /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2110140532 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:26 PM PST 24 352917573 ps
T371 /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.142324545 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:24 PM PST 24 522948409 ps
T372 /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.625821644 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:23 PM PST 24 611051579 ps
T373 /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1617601667 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:32 PM PST 24 477955714 ps
T374 /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3461919545 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:14 PM PST 24 327795365 ps
T375 /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4102601777 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:26 PM PST 24 410358777 ps
T376 /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1012016835 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 505779736 ps
T377 /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1049428765 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:24 PM PST 24 567137756 ps
T378 /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4202558498 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 353340700 ps
T379 /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1220722937 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:32 PM PST 24 4578430176 ps
T380 /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.599697790 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:54 PM PST 24 502664803 ps
T381 /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.452679151 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 561689362 ps
T382 /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2398684021 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:24 PM PST 24 311666421 ps
T383 /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4002067691 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:23 PM PST 24 481716433 ps
T384 /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3643454921 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:35 PM PST 24 2601177523 ps
T385 /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2857801371 Mar 03 12:32:19 PM PST 24 Mar 03 12:32:28 PM PST 24 8178308332 ps
T386 /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.58698226 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:30 PM PST 24 541173191 ps
T387 /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3891391735 Mar 03 12:32:37 PM PST 24 Mar 03 12:32:39 PM PST 24 400539253 ps
T388 /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3421045020 Mar 03 12:32:26 PM PST 24 Mar 03 12:32:26 PM PST 24 448962018 ps
T389 /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.773759134 Mar 03 12:32:20 PM PST 24 Mar 03 12:32:22 PM PST 24 1153454380 ps
T390 /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1077517370 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:20 PM PST 24 7392560800 ps
T391 /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1923738518 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:26 PM PST 24 7076930529 ps
T392 /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2462778811 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 516993103 ps
T393 /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1795468742 Mar 03 12:33:02 PM PST 24 Mar 03 12:33:04 PM PST 24 420627297 ps
T394 /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.478918430 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 390251137 ps
T395 /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2580070029 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:11 PM PST 24 363610039 ps
T396 /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.660265801 Mar 03 12:32:50 PM PST 24 Mar 03 12:32:54 PM PST 24 9070845487 ps
T397 /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1994513581 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 429076908 ps
T398 /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3262595451 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:27 PM PST 24 476005740 ps
T399 /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1890016488 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:38 PM PST 24 428909830 ps
T400 /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2174665127 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 1453803041 ps
T401 /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1310112119 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:36 PM PST 24 526256729 ps
T402 /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1552785248 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:36 PM PST 24 2336385851 ps
T403 /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.977315455 Mar 03 12:32:34 PM PST 24 Mar 03 12:32:35 PM PST 24 294867518 ps
T404 /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.598619727 Mar 03 12:33:01 PM PST 24 Mar 03 12:33:04 PM PST 24 774769517 ps
T405 /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.374150317 Mar 03 12:32:43 PM PST 24 Mar 03 12:32:44 PM PST 24 469356816 ps
T406 /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.27261985 Mar 03 12:32:28 PM PST 24 Mar 03 12:32:29 PM PST 24 2561239646 ps
T407 /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.81872427 Mar 03 12:32:29 PM PST 24 Mar 03 12:32:30 PM PST 24 337249689 ps
T408 /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.744918339 Mar 03 12:32:55 PM PST 24 Mar 03 12:32:57 PM PST 24 404978047 ps
T409 /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.133260621 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:27 PM PST 24 542759063 ps
T410 /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3795496238 Mar 03 12:32:38 PM PST 24 Mar 03 12:32:39 PM PST 24 420321890 ps
T411 /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1430361715 Mar 03 12:32:23 PM PST 24 Mar 03 12:32:25 PM PST 24 1193249419 ps
T412 /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.886709797 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:25 PM PST 24 672276777 ps
T413 /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.938045031 Mar 03 12:32:52 PM PST 24 Mar 03 12:32:53 PM PST 24 429126189 ps
T414 /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3536908917 Mar 03 12:32:35 PM PST 24 Mar 03 12:32:36 PM PST 24 357872168 ps
T415 /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1734803635 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:26 PM PST 24 407820464 ps
T416 /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4166143973 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:26 PM PST 24 2005534667 ps
T417 /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1445076679 Mar 03 12:32:25 PM PST 24 Mar 03 12:32:26 PM PST 24 493105210 ps

Test location /workspace/coverage/default/28.aon_timer_stress_all_with_rand_reset.4065667792
Short name T2
Test name
Test status
Simulation time 40505338378 ps
CPU time 227.84 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:36:47 PM PST 24
Peak memory 198664 kb
Host smart-e7a0cdb1-e05d-400b-a1de-0f414ed70112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065667792 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_all_with_rand_reset.4065667792
Directory /workspace/28.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all.1323033411
Short name T23
Test name
Test status
Simulation time 163924889777 ps
CPU time 234.65 seconds
Started Mar 03 12:33:20 PM PST 24
Finished Mar 03 12:37:15 PM PST 24
Peak memory 183136 kb
Host smart-b9470d36-e719-40c3-b3b8-edf785f48b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323033411 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_
all.1323033411
Directory /workspace/45.aon_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_intg_err.249600245
Short name T26
Test name
Test status
Simulation time 8755941899 ps
CPU time 4.25 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 197228 kb
Host smart-1e7b74fb-5140-4699-868e-a7412996de28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249600245 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_
intg_err.249600245
Directory /workspace/3.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all_with_rand_reset.473113355
Short name T18
Test name
Test status
Simulation time 249834385706 ps
CPU time 255.86 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:37:00 PM PST 24
Peak memory 198660 kb
Host smart-3f9d3455-0c79-4a9c-9d02-deda8b587279
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473113355 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_all_with_rand_reset.473113355
Directory /workspace/8.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all_with_rand_reset.2369517814
Short name T75
Test name
Test status
Simulation time 35782278011 ps
CPU time 249.31 seconds
Started Mar 03 12:32:40 PM PST 24
Finished Mar 03 12:36:49 PM PST 24
Peak memory 198576 kb
Host smart-a2c4b318-6235-4db4-afe6-c10df046995d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369517814 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_all_with_rand_reset.2369517814
Directory /workspace/15.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.aon_timer_sec_cm.1305843183
Short name T22
Test name
Test status
Simulation time 4253506915 ps
CPU time 2.08 seconds
Started Mar 03 12:32:28 PM PST 24
Finished Mar 03 12:32:31 PM PST 24
Peak memory 215272 kb
Host smart-1ebc2540-317f-4507-a9be-21f635783291
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305843183 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_sec_cm.1305843183
Directory /workspace/0.aon_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_rw.1891346184
Short name T48
Test name
Test status
Simulation time 519652150 ps
CPU time 1.43 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:32:48 PM PST 24
Peak memory 183112 kb
Host smart-04d30d97-cd1d-48b9-8a2d-0364b3a7c524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891346184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_csr_rw.1891346184
Directory /workspace/13.aon_timer_csr_rw/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all.1550272564
Short name T3
Test name
Test status
Simulation time 278287399850 ps
CPU time 381.79 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 183920 kb
Host smart-c6efd409-054f-466a-b011-494ca985d97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550272564 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_
all.1550272564
Directory /workspace/13.aon_timer_stress_all/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all_with_rand_reset.3639846752
Short name T161
Test name
Test status
Simulation time 1588018625777 ps
CPU time 911.36 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:48:03 PM PST 24
Peak memory 203600 kb
Host smart-2d88eca0-3abb-4b6d-b219-52f16c9dc460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639846752 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_all_with_rand_reset.3639846752
Directory /workspace/6.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_intg_err.24708945
Short name T81
Test name
Test status
Simulation time 8501648892 ps
CPU time 7.29 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 197056 kb
Host smart-24b3639f-d829-4d36-9b49-5950d5387e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24708945 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_
intg_err.24708945
Directory /workspace/12.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_aliasing.2551017605
Short name T309
Test name
Test status
Simulation time 514773095 ps
CPU time 1.02 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:35 PM PST 24
Peak memory 183200 kb
Host smart-18a63fcb-bef1-4221-8f4a-e5dd6215e32e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551017605 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_a
liasing.2551017605
Directory /workspace/0.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_bit_bash.989342457
Short name T301
Test name
Test status
Simulation time 13942116515 ps
CPU time 20.29 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:43 PM PST 24
Peak memory 183300 kb
Host smart-a7d2d080-fef1-4749-a41c-e79ec3a48af3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989342457 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_bi
t_bash.989342457
Directory /workspace/0.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_hw_reset.773759134
Short name T389
Test name
Test status
Simulation time 1153454380 ps
CPU time 1.46 seconds
Started Mar 03 12:32:20 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 183096 kb
Host smart-80053913-e779-4b56-8fb3-32be528ee127
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773759134 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_hw
_reset.773759134
Directory /workspace/0.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_mem_rw_with_rand_reset.2234814249
Short name T281
Test name
Test status
Simulation time 520729101 ps
CPU time 1.53 seconds
Started Mar 03 12:32:20 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 194988 kb
Host smart-fd0fcc30-f3bf-4dd1-aa68-de1fa1be1ed0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234814249 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.aon_timer_csr_mem_rw_with_rand_reset.2234814249
Directory /workspace/0.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_csr_rw.452679151
Short name T381
Test name
Test status
Simulation time 561689362 ps
CPU time 0.89 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 183576 kb
Host smart-e84a67ab-3890-4a98-a876-610d74b9d438
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452679151 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_csr_rw.452679151
Directory /workspace/0.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_intr_test.3758399225
Short name T314
Test name
Test status
Simulation time 329045156 ps
CPU time 1.01 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 182980 kb
Host smart-94ec1120-d6a5-49a1-98ec-ff363adfe3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758399225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_intr_test.3758399225
Directory /workspace/0.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_partial_access.3485737319
Short name T365
Test name
Test status
Simulation time 376411875 ps
CPU time 1.04 seconds
Started Mar 03 12:32:14 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 182216 kb
Host smart-238ea5ba-8f56-4ccc-b1f4-35e60e857db8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485737319 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_t
imer_mem_partial_access.3485737319
Directory /workspace/0.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_mem_walk.2236889456
Short name T295
Test name
Test status
Simulation time 490333420 ps
CPU time 0.63 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182180 kb
Host smart-a3289721-1777-4eaa-8ecc-ad477aba2a06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236889456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_mem_w
alk.2236889456
Directory /workspace/0.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_same_csr_outstanding.591424280
Short name T338
Test name
Test status
Simulation time 2195831241 ps
CPU time 2.26 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 193828 kb
Host smart-94e5365d-2add-472d-9c96-adf32d8ed978
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591424280 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_
timer_same_csr_outstanding.591424280
Directory /workspace/0.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_errors.3274220322
Short name T348
Test name
Test status
Simulation time 631610203 ps
CPU time 1.54 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 197980 kb
Host smart-42466959-b3a1-4745-93cf-a494dbdc9239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274220322 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl_errors.3274220322
Directory /workspace/0.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.aon_timer_tl_intg_err.1675745637
Short name T84
Test name
Test status
Simulation time 8654301951 ps
CPU time 14.12 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:16 PM PST 24
Peak memory 197104 kb
Host smart-01f02a40-7b8a-499f-83c3-54ecae3a722d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675745637 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.aon_timer_tl
_intg_err.1675745637
Directory /workspace/0.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_aliasing.2165262838
Short name T45
Test name
Test status
Simulation time 460192182 ps
CPU time 1.37 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 192536 kb
Host smart-dbda5149-d0e7-442b-afdd-b4328dd4c20f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165262838 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_a
liasing.2165262838
Directory /workspace/1.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_bit_bash.1923738518
Short name T391
Test name
Test status
Simulation time 7076930529 ps
CPU time 2.36 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 191188 kb
Host smart-ba27d3cc-30d1-4ccc-9381-c33a83fe53fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923738518 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_b
it_bash.1923738518
Directory /workspace/1.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_hw_reset.213429478
Short name T327
Test name
Test status
Simulation time 569242946 ps
CPU time 1.03 seconds
Started Mar 03 12:32:07 PM PST 24
Finished Mar 03 12:32:10 PM PST 24
Peak memory 183112 kb
Host smart-5aa4cae4-24dc-4405-9975-a334f86196c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213429478 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_hw
_reset.213429478
Directory /workspace/1.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_mem_rw_with_rand_reset.4193199560
Short name T344
Test name
Test status
Simulation time 482910560 ps
CPU time 1.15 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 195156 kb
Host smart-777462be-671c-4f6a-b35f-7cfd86a1f67c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193199560 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.aon_timer_csr_mem_rw_with_rand_reset.4193199560
Directory /workspace/1.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_csr_rw.1994513581
Short name T397
Test name
Test status
Simulation time 429076908 ps
CPU time 1.31 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 192544 kb
Host smart-3b1b334e-d229-4023-a108-0cde94d46285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994513581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_csr_rw.1994513581
Directory /workspace/1.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_intr_test.3912995225
Short name T360
Test name
Test status
Simulation time 438634099 ps
CPU time 0.7 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 182964 kb
Host smart-af00db10-bc85-46e5-90e5-f84d5494d536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912995225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_intr_test.3912995225
Directory /workspace/1.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_partial_access.3775471456
Short name T300
Test name
Test status
Simulation time 514670413 ps
CPU time 1.22 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 183392 kb
Host smart-ac7173c2-03be-403b-9b07-90a19ffbe828
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775471456 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_t
imer_mem_partial_access.3775471456
Directory /workspace/1.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_mem_walk.1617601667
Short name T373
Test name
Test status
Simulation time 477955714 ps
CPU time 1.22 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 182984 kb
Host smart-a9611a83-5bcb-4890-9794-bc767e0d6d8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617601667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_mem_w
alk.1617601667
Directory /workspace/1.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_same_csr_outstanding.1528273223
Short name T340
Test name
Test status
Simulation time 759672154 ps
CPU time 1.72 seconds
Started Mar 03 12:32:34 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 183108 kb
Host smart-8fab0b40-092f-4c5b-ae56-2b4c2d67bf6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528273223 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon
_timer_same_csr_outstanding.1528273223
Directory /workspace/1.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_errors.1692139039
Short name T284
Test name
Test status
Simulation time 387313072 ps
CPU time 1.46 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 197736 kb
Host smart-46f45e84-06f6-4626-b643-0a9c54f0da94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692139039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl_errors.1692139039
Directory /workspace/1.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.aon_timer_tl_intg_err.2647739383
Short name T354
Test name
Test status
Simulation time 4129667356 ps
CPU time 4.24 seconds
Started Mar 03 12:32:14 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 196748 kb
Host smart-f66432f8-8ee5-4663-b80a-24da1a48118e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647739383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.aon_timer_tl
_intg_err.2647739383
Directory /workspace/1.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_mem_rw_with_rand_reset.886709797
Short name T412
Test name
Test status
Simulation time 672276777 ps
CPU time 0.89 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 195488 kb
Host smart-8ab0fcc8-c607-4b7f-95a5-11e6e6505a68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886709797 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 10.aon_timer_csr_mem_rw_with_rand_reset.886709797
Directory /workspace/10.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_csr_rw.142324545
Short name T371
Test name
Test status
Simulation time 522948409 ps
CPU time 0.79 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 183068 kb
Host smart-c5b3356c-3001-4bc5-ba93-7594713f67c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142324545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_csr_rw.142324545
Directory /workspace/10.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_intr_test.2904721408
Short name T320
Test name
Test status
Simulation time 434992557 ps
CPU time 1.24 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:32:48 PM PST 24
Peak memory 182980 kb
Host smart-b1c35717-d7fa-4c1c-bd03-3e5e48a3f0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904721408 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_intr_test.2904721408
Directory /workspace/10.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_same_csr_outstanding.1430361715
Short name T411
Test name
Test status
Simulation time 1193249419 ps
CPU time 2.05 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 192716 kb
Host smart-3205ba65-d01e-45e1-a559-d5e83c140da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430361715 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.ao
n_timer_same_csr_outstanding.1430361715
Directory /workspace/10.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_errors.1929373862
Short name T369
Test name
Test status
Simulation time 592431144 ps
CPU time 3.01 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 196972 kb
Host smart-b7c16adc-9ad9-4baf-9196-10f27c5a3f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929373862 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_tl_errors.1929373862
Directory /workspace/10.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.aon_timer_tl_intg_err.3344336468
Short name T331
Test name
Test status
Simulation time 8646586461 ps
CPU time 11.81 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:34 PM PST 24
Peak memory 197184 kb
Host smart-a90d2204-7d79-48c2-893e-ea3135f28755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344336468 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.aon_timer_t
l_intg_err.3344336468
Directory /workspace/10.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_mem_rw_with_rand_reset.3680726449
Short name T317
Test name
Test status
Simulation time 848661522 ps
CPU time 0.85 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 197212 kb
Host smart-e8fe65b8-c9b7-4b82-92a9-3d824cdb56d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680726449 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 11.aon_timer_csr_mem_rw_with_rand_reset.3680726449
Directory /workspace/11.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_csr_rw.3536908917
Short name T414
Test name
Test status
Simulation time 357872168 ps
CPU time 0.73 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 183112 kb
Host smart-391bf7f0-d9e0-42e9-a00d-df0123afaab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536908917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_csr_rw.3536908917
Directory /workspace/11.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_intr_test.2110140532
Short name T370
Test name
Test status
Simulation time 352917573 ps
CPU time 1.03 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 182984 kb
Host smart-baf1ec7c-db55-4d73-aca2-7c942020ab83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110140532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_intr_test.2110140532
Directory /workspace/11.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_same_csr_outstanding.2981015097
Short name T61
Test name
Test status
Simulation time 1014710370 ps
CPU time 1.25 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 192504 kb
Host smart-3815d125-7eac-4af2-bc8f-33f624a410b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981015097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.ao
n_timer_same_csr_outstanding.2981015097
Directory /workspace/11.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_errors.277939304
Short name T339
Test name
Test status
Simulation time 394488227 ps
CPU time 2.15 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 197948 kb
Host smart-60822b58-1914-4137-9c3e-e796ecde409e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277939304 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_tl_errors.277939304
Directory /workspace/11.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.aon_timer_tl_intg_err.2941215074
Short name T83
Test name
Test status
Simulation time 8378504828 ps
CPU time 12.86 seconds
Started Mar 03 12:32:43 PM PST 24
Finished Mar 03 12:32:56 PM PST 24
Peak memory 197208 kb
Host smart-c4abe670-59b9-4427-9162-c95e860aba36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941215074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.aon_timer_t
l_intg_err.2941215074
Directory /workspace/11.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_mem_rw_with_rand_reset.32401420
Short name T303
Test name
Test status
Simulation time 605256197 ps
CPU time 1.1 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 196060 kb
Host smart-aee48345-7678-40a7-8017-78206a6b6f63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32401420 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.aon_timer_csr_mem_rw_with_rand_reset.32401420
Directory /workspace/12.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_csr_rw.2029453817
Short name T51
Test name
Test status
Simulation time 310110507 ps
CPU time 0.81 seconds
Started Mar 03 12:32:40 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 183116 kb
Host smart-92b501e2-784d-4805-800c-07e6a74cf436
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029453817 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_csr_rw.2029453817
Directory /workspace/12.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_intr_test.2062738510
Short name T311
Test name
Test status
Simulation time 426743978 ps
CPU time 1.13 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 181268 kb
Host smart-01a3618d-fedf-41ae-b0fa-9e7bad540f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062738510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_intr_test.2062738510
Directory /workspace/12.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_same_csr_outstanding.3643454921
Short name T384
Test name
Test status
Simulation time 2601177523 ps
CPU time 4.34 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:35 PM PST 24
Peak memory 194108 kb
Host smart-e2d04f5e-8686-4011-b6ba-78c7825e8770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643454921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.ao
n_timer_same_csr_outstanding.3643454921
Directory /workspace/12.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.aon_timer_tl_errors.2545145175
Short name T367
Test name
Test status
Simulation time 554703166 ps
CPU time 1.96 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 197972 kb
Host smart-daa6aa0c-c907-4657-88df-bc4c2ca18acf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545145175 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.aon_timer_tl_errors.2545145175
Directory /workspace/12.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_csr_mem_rw_with_rand_reset.1171407472
Short name T326
Test name
Test status
Simulation time 573654841 ps
CPU time 1.54 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:52 PM PST 24
Peak memory 195388 kb
Host smart-76653a0b-2323-419d-9d3c-cb1a21ce582c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171407472 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.aon_timer_csr_mem_rw_with_rand_reset.1171407472
Directory /workspace/13.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_intr_test.1543949754
Short name T285
Test name
Test status
Simulation time 307175229 ps
CPU time 0.64 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 182992 kb
Host smart-adcab1e3-9e2b-4d63-8e18-2c488a8357e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543949754 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_intr_test.1543949754
Directory /workspace/13.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_same_csr_outstanding.2111144678
Short name T24
Test name
Test status
Simulation time 2251192175 ps
CPU time 4.02 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 183176 kb
Host smart-a14b6683-c0e6-41c7-9333-e8b0ef64d106
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111144678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.ao
n_timer_same_csr_outstanding.2111144678
Directory /workspace/13.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_errors.442307039
Short name T359
Test name
Test status
Simulation time 458434912 ps
CPU time 1.86 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 197988 kb
Host smart-f636f971-3122-4c49-97fa-f399bd7cf3eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442307039 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl_errors.442307039
Directory /workspace/13.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.aon_timer_tl_intg_err.346596521
Short name T79
Test name
Test status
Simulation time 8376600581 ps
CPU time 3.87 seconds
Started Mar 03 12:32:37 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 197240 kb
Host smart-9394f8d9-0f61-44f8-8e77-419cde01c0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346596521 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.aon_timer_tl
_intg_err.346596521
Directory /workspace/13.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_mem_rw_with_rand_reset.625821644
Short name T372
Test name
Test status
Simulation time 611051579 ps
CPU time 0.79 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 195940 kb
Host smart-12e8298b-8875-4097-bb82-a15ed32eedd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625821644 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.aon_timer_csr_mem_rw_with_rand_reset.625821644
Directory /workspace/14.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_csr_rw.3421045020
Short name T388
Test name
Test status
Simulation time 448962018 ps
CPU time 0.69 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183112 kb
Host smart-6be4bb87-82da-48ab-b879-2f4ee0af9d41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421045020 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_csr_rw.3421045020
Directory /workspace/14.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_intr_test.3184269764
Short name T282
Test name
Test status
Simulation time 347677827 ps
CPU time 1 seconds
Started Mar 03 12:32:43 PM PST 24
Finished Mar 03 12:32:44 PM PST 24
Peak memory 182984 kb
Host smart-a6d5cbdf-247d-4baa-bc28-ef3e3294c737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184269764 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_intr_test.3184269764
Directory /workspace/14.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_same_csr_outstanding.3756640704
Short name T355
Test name
Test status
Simulation time 1531606295 ps
CPU time 1.06 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:45 PM PST 24
Peak memory 183112 kb
Host smart-a72e9589-bf11-4370-9eec-32382957ee88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756640704 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.ao
n_timer_same_csr_outstanding.3756640704
Directory /workspace/14.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_errors.4104057870
Short name T299
Test name
Test status
Simulation time 972671535 ps
CPU time 2.19 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:32:48 PM PST 24
Peak memory 197992 kb
Host smart-f1fa2842-5a6a-4690-b1ec-4410ec79b3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104057870 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_tl_errors.4104057870
Directory /workspace/14.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.aon_timer_tl_intg_err.1428413097
Short name T29
Test name
Test status
Simulation time 4410369138 ps
CPU time 7.04 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 196928 kb
Host smart-d93767b3-7b09-400a-9cc0-bc482b8c057b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428413097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.aon_timer_t
l_intg_err.1428413097
Directory /workspace/14.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_mem_rw_with_rand_reset.237656587
Short name T25
Test name
Test status
Simulation time 452018760 ps
CPU time 1.17 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 197764 kb
Host smart-13d0fefa-2aec-4cd1-9915-07920880f3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237656587 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 15.aon_timer_csr_mem_rw_with_rand_reset.237656587
Directory /workspace/15.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_csr_rw.1476797851
Short name T50
Test name
Test status
Simulation time 581254355 ps
CPU time 0.66 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:32:40 PM PST 24
Peak memory 183096 kb
Host smart-249c3266-e7d3-48b1-aa1c-fe447ae508f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476797851 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_csr_rw.1476797851
Directory /workspace/15.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_intr_test.2803570446
Short name T290
Test name
Test status
Simulation time 442578731 ps
CPU time 0.58 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 182872 kb
Host smart-be3eec3b-713f-4b02-a3e0-c7d9f1f2579f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803570446 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_intr_test.2803570446
Directory /workspace/15.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_same_csr_outstanding.2508140890
Short name T310
Test name
Test status
Simulation time 2824475662 ps
CPU time 2.36 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:34 PM PST 24
Peak memory 194008 kb
Host smart-f22a4c31-8b0d-4c30-b22a-14157ebaf832
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508140890 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.ao
n_timer_same_csr_outstanding.2508140890
Directory /workspace/15.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_errors.598619727
Short name T404
Test name
Test status
Simulation time 774769517 ps
CPU time 2.53 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:04 PM PST 24
Peak memory 198012 kb
Host smart-dca60a5b-c1f2-4bdf-86a1-c8483cd9fbbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598619727 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_tl_errors.598619727
Directory /workspace/15.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.aon_timer_tl_intg_err.1384342643
Short name T30
Test name
Test status
Simulation time 4441086787 ps
CPU time 7 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 195420 kb
Host smart-2bdff8f9-0347-43c8-b7ca-af328dcf8e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384342643 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.aon_timer_t
l_intg_err.1384342643
Directory /workspace/15.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_mem_rw_with_rand_reset.133260621
Short name T409
Test name
Test status
Simulation time 542759063 ps
CPU time 0.99 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 194512 kb
Host smart-8987f9d2-dc1f-490a-96d5-3e19e0b6ee48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133260621 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 16.aon_timer_csr_mem_rw_with_rand_reset.133260621
Directory /workspace/16.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_csr_rw.1965486120
Short name T56
Test name
Test status
Simulation time 502693778 ps
CPU time 0.71 seconds
Started Mar 03 12:32:18 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 183072 kb
Host smart-d308c61b-83f1-4034-9291-85e63ac1350b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965486120 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_csr_rw.1965486120
Directory /workspace/16.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_intr_test.3088444063
Short name T323
Test name
Test status
Simulation time 438914878 ps
CPU time 1.17 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 182928 kb
Host smart-6f3c69f9-2483-4175-b4b0-84943b3b4b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088444063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_intr_test.3088444063
Directory /workspace/16.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_same_csr_outstanding.656362179
Short name T63
Test name
Test status
Simulation time 1373887966 ps
CPU time 2.68 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 192612 kb
Host smart-e53a9045-1117-4002-b4f2-c22a0420bec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656362179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon
_timer_same_csr_outstanding.656362179
Directory /workspace/16.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_errors.3891391735
Short name T387
Test name
Test status
Simulation time 400539253 ps
CPU time 2.74 seconds
Started Mar 03 12:32:37 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 197904 kb
Host smart-6b751b4e-cee3-4dbf-bbba-386c36b9e57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891391735 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_tl_errors.3891391735
Directory /workspace/16.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.aon_timer_tl_intg_err.1085295979
Short name T82
Test name
Test status
Simulation time 8180043904 ps
CPU time 12.98 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:38 PM PST 24
Peak memory 195500 kb
Host smart-6a4c7652-d2c1-486e-9b57-f780d1f64d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085295979 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.aon_timer_t
l_intg_err.1085295979
Directory /workspace/16.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_mem_rw_with_rand_reset.1803695329
Short name T325
Test name
Test status
Simulation time 525241967 ps
CPU time 1.51 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 195472 kb
Host smart-26ccd7a4-a4c3-4338-a183-ff9e52b012c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803695329 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.aon_timer_csr_mem_rw_with_rand_reset.1803695329
Directory /workspace/17.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_csr_rw.1734803635
Short name T415
Test name
Test status
Simulation time 407820464 ps
CPU time 0.71 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 182460 kb
Host smart-c1a51cab-5cd9-4e70-b67b-29856dae123c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734803635 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_csr_rw.1734803635
Directory /workspace/17.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_intr_test.2967299380
Short name T322
Test name
Test status
Simulation time 285994690 ps
CPU time 0.97 seconds
Started Mar 03 12:32:36 PM PST 24
Finished Mar 03 12:32:37 PM PST 24
Peak memory 182984 kb
Host smart-2ab8a4af-f4b5-46cb-b836-ca00a1baab9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967299380 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_intr_test.2967299380
Directory /workspace/17.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_same_csr_outstanding.27261985
Short name T406
Test name
Test status
Simulation time 2561239646 ps
CPU time 1.18 seconds
Started Mar 03 12:32:28 PM PST 24
Finished Mar 03 12:32:29 PM PST 24
Peak memory 193764 kb
Host smart-e37f6a95-271d-44da-8545-d3f0ab09e144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27261985 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_
timer_same_csr_outstanding.27261985
Directory /workspace/17.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_errors.3365024044
Short name T288
Test name
Test status
Simulation time 560964576 ps
CPU time 1.62 seconds
Started Mar 03 12:32:36 PM PST 24
Finished Mar 03 12:32:38 PM PST 24
Peak memory 198012 kb
Host smart-58652fa5-87c6-4740-8ff1-2caed07b0861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365024044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_tl_errors.3365024044
Directory /workspace/17.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.aon_timer_tl_intg_err.1274329416
Short name T347
Test name
Test status
Simulation time 8041910370 ps
CPU time 7.34 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 197212 kb
Host smart-22012c41-2edb-432c-91d1-c6bc4b657a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274329416 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.aon_timer_t
l_intg_err.1274329416
Directory /workspace/17.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_mem_rw_with_rand_reset.113564847
Short name T332
Test name
Test status
Simulation time 582749161 ps
CPU time 0.92 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:31 PM PST 24
Peak memory 195744 kb
Host smart-4af480fa-64f6-4fb1-acef-bf98a146e7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113564847 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 18.aon_timer_csr_mem_rw_with_rand_reset.113564847
Directory /workspace/18.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_csr_rw.651086202
Short name T64
Test name
Test status
Simulation time 535551607 ps
CPU time 0.72 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:32:47 PM PST 24
Peak memory 182932 kb
Host smart-a17b5c04-386b-44c0-b9e2-e23d01d269f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651086202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_csr_rw.651086202
Directory /workspace/18.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_intr_test.4102601777
Short name T375
Test name
Test status
Simulation time 410358777 ps
CPU time 0.68 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 182776 kb
Host smart-e1a96070-f127-4541-8261-aa08d6c02387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102601777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_intr_test.4102601777
Directory /workspace/18.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_same_csr_outstanding.2159887876
Short name T60
Test name
Test status
Simulation time 1154307164 ps
CPU time 1.72 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:06 PM PST 24
Peak memory 183108 kb
Host smart-2757c8db-05c7-44a1-93f3-81706f015fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159887876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.ao
n_timer_same_csr_outstanding.2159887876
Directory /workspace/18.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_errors.2980130278
Short name T358
Test name
Test status
Simulation time 621483301 ps
CPU time 3.35 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:33:00 PM PST 24
Peak memory 197976 kb
Host smart-640d5b67-9cc9-4753-9c89-fc55a050dd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980130278 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl_errors.2980130278
Directory /workspace/18.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.aon_timer_tl_intg_err.660265801
Short name T396
Test name
Test status
Simulation time 9070845487 ps
CPU time 3.04 seconds
Started Mar 03 12:32:50 PM PST 24
Finished Mar 03 12:32:54 PM PST 24
Peak memory 197168 kb
Host smart-8aed71ac-70b5-4a6a-80a9-a28ffb0aafd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660265801 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.aon_timer_tl
_intg_err.660265801
Directory /workspace/18.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_mem_rw_with_rand_reset.33311271
Short name T307
Test name
Test status
Simulation time 409694025 ps
CPU time 1.14 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 194216 kb
Host smart-79c44305-49ff-4e69-abef-b02a1046aa63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311271 -assert nopostproc +UVM_TESTNAME=a
on_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.aon_timer_csr_mem_rw_with_rand_reset.33311271
Directory /workspace/19.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_csr_rw.1067759663
Short name T279
Test name
Test status
Simulation time 539097148 ps
CPU time 0.77 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183212 kb
Host smart-826b9198-9cc8-47a5-bf97-3543527c3b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067759663 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_csr_rw.1067759663
Directory /workspace/19.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_intr_test.2089763878
Short name T286
Test name
Test status
Simulation time 344892300 ps
CPU time 0.64 seconds
Started Mar 03 12:32:58 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 182944 kb
Host smart-e69c15f3-6d2a-44cd-9e6b-e50d5d61ba61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089763878 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_intr_test.2089763878
Directory /workspace/19.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_same_csr_outstanding.4166143973
Short name T416
Test name
Test status
Simulation time 2005534667 ps
CPU time 3.44 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183112 kb
Host smart-8f592646-e3fb-44af-b458-e93cd9755547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166143973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.ao
n_timer_same_csr_outstanding.4166143973
Directory /workspace/19.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_errors.1890016488
Short name T399
Test name
Test status
Simulation time 428909830 ps
CPU time 2.06 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:38 PM PST 24
Peak memory 197972 kb
Host smart-d52f55f6-95d6-4eae-8a89-168ba8ccd3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890016488 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_tl_errors.1890016488
Directory /workspace/19.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.aon_timer_tl_intg_err.2871604595
Short name T342
Test name
Test status
Simulation time 4607954288 ps
CPU time 7.85 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:43 PM PST 24
Peak memory 196876 kb
Host smart-cc361699-fd58-4de7-9fb7-9cd6361767d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871604595 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.aon_timer_t
l_intg_err.2871604595
Directory /workspace/19.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_aliasing.3440749535
Short name T47
Test name
Test status
Simulation time 655402879 ps
CPU time 0.8 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 193584 kb
Host smart-b9097295-22ba-410d-b551-3822ef52f047
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440749535 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_a
liasing.3440749535
Directory /workspace/2.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_bit_bash.1738542180
Short name T55
Test name
Test status
Simulation time 6990470125 ps
CPU time 9.83 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:33 PM PST 24
Peak memory 190580 kb
Host smart-070ca1c9-56c1-4785-a422-7d956a31dfaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738542180 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_b
it_bash.1738542180
Directory /workspace/2.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_hw_reset.2174665127
Short name T400
Test name
Test status
Simulation time 1453803041 ps
CPU time 1.19 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 182268 kb
Host smart-763d6ccf-1532-4e36-b98f-ea1f985560fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174665127 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_h
w_reset.2174665127
Directory /workspace/2.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_mem_rw_with_rand_reset.4002067691
Short name T383
Test name
Test status
Simulation time 481716433 ps
CPU time 0.96 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 197740 kb
Host smart-92282822-df97-4941-9685-ede3f98e5ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002067691 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.aon_timer_csr_mem_rw_with_rand_reset.4002067691
Directory /workspace/2.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_csr_rw.1945574540
Short name T364
Test name
Test status
Simulation time 438627137 ps
CPU time 0.74 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 192528 kb
Host smart-ea0624a3-3d8e-4eb5-92f1-d1d75ee6dcd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945574540 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_csr_rw.1945574540
Directory /workspace/2.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_intr_test.354228575
Short name T334
Test name
Test status
Simulation time 405534297 ps
CPU time 0.64 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 182968 kb
Host smart-b2c27e2d-8d97-4aa3-9bfb-b828c3dbd0e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354228575 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_intr_test.354228575
Directory /workspace/2.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_partial_access.2398684021
Short name T382
Test name
Test status
Simulation time 311666421 ps
CPU time 1.02 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 181844 kb
Host smart-89b5ab36-d737-4d95-b14b-9ae9b7fd42f2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398684021 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_t
imer_mem_partial_access.2398684021
Directory /workspace/2.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_mem_walk.1296747782
Short name T298
Test name
Test status
Simulation time 486679282 ps
CPU time 0.6 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 182964 kb
Host smart-9bd06484-49f8-47cb-b21e-4461b7afc34d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296747782 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_mem_w
alk.1296747782
Directory /workspace/2.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_same_csr_outstanding.3597499332
Short name T335
Test name
Test status
Simulation time 1185781639 ps
CPU time 1.21 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:32:40 PM PST 24
Peak memory 192412 kb
Host smart-6a48e8cf-f2d3-47fe-ada1-6e15c570d31a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597499332 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon
_timer_same_csr_outstanding.3597499332
Directory /workspace/2.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_errors.2616049576
Short name T280
Test name
Test status
Simulation time 454557089 ps
CPU time 2.34 seconds
Started Mar 03 12:32:48 PM PST 24
Finished Mar 03 12:32:50 PM PST 24
Peak memory 197976 kb
Host smart-20305e11-10f5-4d92-aaf3-7db4e01a4d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616049576 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl_errors.2616049576
Directory /workspace/2.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.aon_timer_tl_intg_err.1077517370
Short name T390
Test name
Test status
Simulation time 7392560800 ps
CPU time 6.56 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 196932 kb
Host smart-52b1df39-81c1-40a4-bc82-8328b19f8186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077517370 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.aon_timer_tl
_intg_err.1077517370
Directory /workspace/2.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.aon_timer_intr_test.2860321300
Short name T351
Test name
Test status
Simulation time 377977463 ps
CPU time 0.78 seconds
Started Mar 03 12:32:16 PM PST 24
Finished Mar 03 12:32:17 PM PST 24
Peak memory 183036 kb
Host smart-9d591d3c-8809-4ca1-8df8-0862d1b16697
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860321300 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.aon_timer_intr_test.2860321300
Directory /workspace/20.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.aon_timer_intr_test.478918430
Short name T394
Test name
Test status
Simulation time 390251137 ps
CPU time 0.67 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182988 kb
Host smart-ba0e58a8-4ee4-4495-a2da-a2185dac9ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478918430 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.aon_timer_intr_test.478918430
Directory /workspace/21.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.aon_timer_intr_test.374150317
Short name T405
Test name
Test status
Simulation time 469356816 ps
CPU time 0.71 seconds
Started Mar 03 12:32:43 PM PST 24
Finished Mar 03 12:32:44 PM PST 24
Peak memory 182984 kb
Host smart-0895db20-21a4-45d3-8ba1-d894e7f121c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374150317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.aon_timer_intr_test.374150317
Directory /workspace/22.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.aon_timer_intr_test.68137077
Short name T316
Test name
Test status
Simulation time 318311330 ps
CPU time 0.68 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:29 PM PST 24
Peak memory 183020 kb
Host smart-c7e5db70-aec6-478b-a8ae-5c150631b048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68137077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.aon_timer_intr_test.68137077
Directory /workspace/23.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.aon_timer_intr_test.599697790
Short name T380
Test name
Test status
Simulation time 502664803 ps
CPU time 1.34 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:54 PM PST 24
Peak memory 182984 kb
Host smart-a492ce09-4497-4e04-bb71-a8388ab4ca21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599697790 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.aon_timer_intr_test.599697790
Directory /workspace/24.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.aon_timer_intr_test.2896692286
Short name T313
Test name
Test status
Simulation time 523056864 ps
CPU time 0.73 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182944 kb
Host smart-72793523-7b23-499a-80a0-8d405feab98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896692286 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.aon_timer_intr_test.2896692286
Directory /workspace/25.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.aon_timer_intr_test.4041734083
Short name T350
Test name
Test status
Simulation time 464143184 ps
CPU time 0.69 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 182996 kb
Host smart-6643fc31-3518-4934-8686-d98e401fe861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041734083 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.aon_timer_intr_test.4041734083
Directory /workspace/26.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.aon_timer_intr_test.81872427
Short name T407
Test name
Test status
Simulation time 337249689 ps
CPU time 0.65 seconds
Started Mar 03 12:32:29 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 183440 kb
Host smart-59d8ba7f-0a3a-4b16-87b0-c28a7ef52198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81872427 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.aon_timer_intr_test.81872427
Directory /workspace/27.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.aon_timer_intr_test.1813904296
Short name T353
Test name
Test status
Simulation time 309483085 ps
CPU time 0.72 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 182872 kb
Host smart-4ed5bd16-8593-45dc-88b5-bb601ba6a20c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813904296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.aon_timer_intr_test.1813904296
Directory /workspace/28.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.aon_timer_intr_test.2847648639
Short name T305
Test name
Test status
Simulation time 393278322 ps
CPU time 0.7 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:32:40 PM PST 24
Peak memory 183016 kb
Host smart-52dac15a-909a-4aca-8a32-b012e9547f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847648639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.aon_timer_intr_test.2847648639
Directory /workspace/29.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_aliasing.1100166836
Short name T46
Test name
Test status
Simulation time 446584868 ps
CPU time 0.82 seconds
Started Mar 03 12:32:07 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 183112 kb
Host smart-f3924878-971f-4102-a175-8c59d4206f97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100166836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_a
liasing.1100166836
Directory /workspace/3.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_bit_bash.3079015984
Short name T53
Test name
Test status
Simulation time 1122541650 ps
CPU time 2.85 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:32:35 PM PST 24
Peak memory 193744 kb
Host smart-ec5aa982-6deb-473b-ad0f-9e537fef5168
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079015984 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_b
it_bash.3079015984
Directory /workspace/3.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_hw_reset.123363489
Short name T319
Test name
Test status
Simulation time 662105333 ps
CPU time 1.12 seconds
Started Mar 03 12:32:45 PM PST 24
Finished Mar 03 12:32:46 PM PST 24
Peak memory 183116 kb
Host smart-c0bd3dce-b285-4e52-a6ae-44231b53b127
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123363489 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_hw
_reset.123363489
Directory /workspace/3.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_mem_rw_with_rand_reset.1654936720
Short name T336
Test name
Test status
Simulation time 573798342 ps
CPU time 1.14 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 194836 kb
Host smart-0c28f7d9-74a1-4579-941b-9d85fe4a5b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654936720 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.aon_timer_csr_mem_rw_with_rand_reset.1654936720
Directory /workspace/3.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_csr_rw.3919422123
Short name T52
Test name
Test status
Simulation time 523294250 ps
CPU time 1.48 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183112 kb
Host smart-86cc8e61-ad61-44f9-ba0a-3ab5808f0189
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919422123 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_csr_rw.3919422123
Directory /workspace/3.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_intr_test.58698226
Short name T386
Test name
Test status
Simulation time 541173191 ps
CPU time 0.72 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 182932 kb
Host smart-1b9f9071-07e6-49fc-b031-e09ef4939212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58698226 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_intr_test.58698226
Directory /workspace/3.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_partial_access.2927793824
Short name T318
Test name
Test status
Simulation time 400506931 ps
CPU time 0.67 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 182220 kb
Host smart-42d2e6ed-36a8-404c-82f7-64a9bb42848b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927793824 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_t
imer_mem_partial_access.2927793824
Directory /workspace/3.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_mem_walk.274470815
Short name T283
Test name
Test status
Simulation time 339499633 ps
CPU time 1.02 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 182640 kb
Host smart-1a465de4-2a09-47d4-a608-dc2f7ff56716
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274470815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_mem_wa
lk.274470815
Directory /workspace/3.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_same_csr_outstanding.129423089
Short name T59
Test name
Test status
Simulation time 1996892792 ps
CPU time 1.49 seconds
Started Mar 03 12:32:20 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 183104 kb
Host smart-881e2afc-1c75-4948-9a66-f6f0ff1d767b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129423089 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=a
on_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_
timer_same_csr_outstanding.129423089
Directory /workspace/3.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.aon_timer_tl_errors.4167628423
Short name T352
Test name
Test status
Simulation time 627328034 ps
CPU time 2.4 seconds
Started Mar 03 12:32:29 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 197932 kb
Host smart-532497b5-bd4f-476b-9106-32526836cc6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167628423 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.aon_timer_tl_errors.4167628423
Directory /workspace/3.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.aon_timer_intr_test.906432390
Short name T329
Test name
Test status
Simulation time 506355627 ps
CPU time 1.24 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 182984 kb
Host smart-cab93fff-f17d-418c-b247-04b19c88337b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906432390 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.aon_timer_intr_test.906432390
Directory /workspace/30.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.aon_timer_intr_test.2840568917
Short name T304
Test name
Test status
Simulation time 481285230 ps
CPU time 0.99 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 182900 kb
Host smart-ae122426-b337-45ab-bcb1-b80841871012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840568917 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.aon_timer_intr_test.2840568917
Directory /workspace/31.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.aon_timer_intr_test.2462778811
Short name T392
Test name
Test status
Simulation time 516993103 ps
CPU time 0.66 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182964 kb
Host smart-9b8e272d-d148-4d7b-94f2-6e2a555d2644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462778811 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.aon_timer_intr_test.2462778811
Directory /workspace/32.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.aon_timer_intr_test.2641665774
Short name T346
Test name
Test status
Simulation time 275850737 ps
CPU time 0.96 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:03 PM PST 24
Peak memory 182984 kb
Host smart-bb97e2a4-c3a9-4c69-bb2a-ab9979f3036d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641665774 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.aon_timer_intr_test.2641665774
Directory /workspace/33.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.aon_timer_intr_test.3083626889
Short name T337
Test name
Test status
Simulation time 304581543 ps
CPU time 1 seconds
Started Mar 03 12:32:42 PM PST 24
Finished Mar 03 12:32:43 PM PST 24
Peak memory 183036 kb
Host smart-38ba4472-741c-4b17-86e5-2b952c62f9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083626889 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.aon_timer_intr_test.3083626889
Directory /workspace/34.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.aon_timer_intr_test.3384747900
Short name T302
Test name
Test status
Simulation time 460337190 ps
CPU time 1.23 seconds
Started Mar 03 12:32:57 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 183000 kb
Host smart-aa7ada43-87f8-40d0-b5ed-37a4b4eeb745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384747900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.aon_timer_intr_test.3384747900
Directory /workspace/35.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.aon_timer_intr_test.2591262048
Short name T349
Test name
Test status
Simulation time 274662858 ps
CPU time 0.89 seconds
Started Mar 03 12:32:33 PM PST 24
Finished Mar 03 12:32:34 PM PST 24
Peak memory 182988 kb
Host smart-ad202df7-deb0-4838-b066-843616a27b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591262048 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.aon_timer_intr_test.2591262048
Directory /workspace/36.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.aon_timer_intr_test.1591432767
Short name T294
Test name
Test status
Simulation time 323523768 ps
CPU time 0.98 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:45 PM PST 24
Peak memory 183036 kb
Host smart-38e003d0-09ff-44d6-8208-5b46a0eaeb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591432767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.aon_timer_intr_test.1591432767
Directory /workspace/37.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.aon_timer_intr_test.3495905900
Short name T275
Test name
Test status
Simulation time 435314587 ps
CPU time 0.68 seconds
Started Mar 03 12:32:49 PM PST 24
Finished Mar 03 12:32:49 PM PST 24
Peak memory 182964 kb
Host smart-6af22e88-0e84-4aa4-af9d-296da8cb3b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495905900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.aon_timer_intr_test.3495905900
Directory /workspace/38.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.aon_timer_intr_test.2706955100
Short name T308
Test name
Test status
Simulation time 354601539 ps
CPU time 0.63 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182980 kb
Host smart-165bc561-0b89-4122-99b4-018d4623575b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706955100 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.aon_timer_intr_test.2706955100
Directory /workspace/39.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_aliasing.1165844363
Short name T333
Test name
Test status
Simulation time 528270007 ps
CPU time 1.14 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 181672 kb
Host smart-03509413-7603-493e-9883-ac6ba572428e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165844363 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_a
liasing.1165844363
Directory /workspace/4.aon_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_bit_bash.3321150765
Short name T54
Test name
Test status
Simulation time 8087122740 ps
CPU time 5.99 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 191576 kb
Host smart-9e78a369-051b-4a35-ab81-6aad40a4638c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321150765 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_b
it_bash.3321150765
Directory /workspace/4.aon_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_hw_reset.3443643892
Short name T28
Test name
Test status
Simulation time 1242887347 ps
CPU time 1.18 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:32:48 PM PST 24
Peak memory 192240 kb
Host smart-5c7faa1d-294c-49c9-9450-268b32130335
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443643892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_h
w_reset.3443643892
Directory /workspace/4.aon_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_mem_rw_with_rand_reset.1445076679
Short name T417
Test name
Test status
Simulation time 493105210 ps
CPU time 0.83 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 195004 kb
Host smart-ae4e40b5-23e8-4baa-ad38-e1ce2b1dbcd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445076679 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.aon_timer_csr_mem_rw_with_rand_reset.1445076679
Directory /workspace/4.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_csr_rw.998672377
Short name T49
Test name
Test status
Simulation time 433611036 ps
CPU time 0.67 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183160 kb
Host smart-9fef0321-e639-4754-a1f7-813e6cf123f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998672377 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_csr_rw.998672377
Directory /workspace/4.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_intr_test.1597841814
Short name T296
Test name
Test status
Simulation time 460234172 ps
CPU time 0.97 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:32:40 PM PST 24
Peak memory 182964 kb
Host smart-b90a9fc5-1840-456c-be47-767817e46474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597841814 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_intr_test.1597841814
Directory /workspace/4.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_partial_access.3461919545
Short name T374
Test name
Test status
Simulation time 327795365 ps
CPU time 0.59 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:14 PM PST 24
Peak memory 182220 kb
Host smart-ca902a11-16a2-4224-94ba-69a6013ac1b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461919545 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_t
imer_mem_partial_access.3461919545
Directory /workspace/4.aon_timer_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_mem_walk.4202558498
Short name T378
Test name
Test status
Simulation time 353340700 ps
CPU time 0.78 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 182212 kb
Host smart-24608920-80c8-421e-ad46-792869cf02a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202558498 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_mem_w
alk.4202558498
Directory /workspace/4.aon_timer_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_same_csr_outstanding.3952302258
Short name T62
Test name
Test status
Simulation time 1661194599 ps
CPU time 1.08 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 183116 kb
Host smart-81f8d183-c74d-4e10-954a-4899b593a52c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952302258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon
_timer_same_csr_outstanding.3952302258
Directory /workspace/4.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_errors.2789698892
Short name T292
Test name
Test status
Simulation time 442810295 ps
CPU time 1.83 seconds
Started Mar 03 12:32:37 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 198012 kb
Host smart-e411131c-9824-4bd1-8201-c9013dd5a100
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789698892 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl_errors.2789698892
Directory /workspace/4.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.aon_timer_tl_intg_err.3586830598
Short name T368
Test name
Test status
Simulation time 8237422181 ps
CPU time 2.94 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 197092 kb
Host smart-cdebd922-1dc5-43bf-b8a5-d0969ab1d485
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586830598 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.aon_timer_tl
_intg_err.3586830598
Directory /workspace/4.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.aon_timer_intr_test.1310112119
Short name T401
Test name
Test status
Simulation time 526256729 ps
CPU time 0.65 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 183452 kb
Host smart-9a3ad97c-06e5-4950-ad6b-55ef52996106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310112119 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.aon_timer_intr_test.1310112119
Directory /workspace/40.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.aon_timer_intr_test.2470240719
Short name T277
Test name
Test status
Simulation time 486941494 ps
CPU time 0.61 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 182928 kb
Host smart-41c7179b-882b-4b3a-8296-ab33dd491c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470240719 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.aon_timer_intr_test.2470240719
Directory /workspace/41.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.aon_timer_intr_test.977315455
Short name T403
Test name
Test status
Simulation time 294867518 ps
CPU time 0.75 seconds
Started Mar 03 12:32:34 PM PST 24
Finished Mar 03 12:32:35 PM PST 24
Peak memory 182940 kb
Host smart-ad8aec85-52a7-4961-b5a2-c244a0d147f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977315455 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.aon_timer_intr_test.977315455
Directory /workspace/42.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.aon_timer_intr_test.925996150
Short name T366
Test name
Test status
Simulation time 415389060 ps
CPU time 1.17 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 182940 kb
Host smart-0e1e0159-f09d-413d-a014-a754b1cb97f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925996150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.aon_timer_intr_test.925996150
Directory /workspace/43.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.aon_timer_intr_test.938045031
Short name T413
Test name
Test status
Simulation time 429126189 ps
CPU time 0.71 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 182980 kb
Host smart-04137488-4e92-4a6e-b423-c186d9805d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938045031 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.aon_timer_intr_test.938045031
Directory /workspace/44.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.aon_timer_intr_test.2526106262
Short name T291
Test name
Test status
Simulation time 539995074 ps
CPU time 0.6 seconds
Started Mar 03 12:32:50 PM PST 24
Finished Mar 03 12:32:51 PM PST 24
Peak memory 182944 kb
Host smart-86f48e3d-dfc4-4631-8514-1f81d9622a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526106262 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.aon_timer_intr_test.2526106262
Directory /workspace/45.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.aon_timer_intr_test.1012016835
Short name T376
Test name
Test status
Simulation time 505779736 ps
CPU time 0.7 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 182964 kb
Host smart-fa1949ce-94dd-4664-abf1-bcb10bba9ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012016835 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.aon_timer_intr_test.1012016835
Directory /workspace/46.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.aon_timer_intr_test.3224722027
Short name T293
Test name
Test status
Simulation time 519439506 ps
CPU time 1.25 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 182956 kb
Host smart-1ce310d7-c2df-4a7d-aaa9-8331fbf036d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224722027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.aon_timer_intr_test.3224722027
Directory /workspace/47.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.aon_timer_intr_test.1352899346
Short name T276
Test name
Test status
Simulation time 479601442 ps
CPU time 1.32 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 182976 kb
Host smart-4b42dd4f-c2f2-4509-9c8b-00719fe7b095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352899346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.aon_timer_intr_test.1352899346
Directory /workspace/48.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.aon_timer_intr_test.3633685324
Short name T328
Test name
Test status
Simulation time 314660677 ps
CPU time 1.01 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 182964 kb
Host smart-e1da57ee-95fb-4b3d-9ffa-8e3ff02ca7ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633685324 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.aon_timer_intr_test.3633685324
Directory /workspace/49.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_mem_rw_with_rand_reset.691404183
Short name T321
Test name
Test status
Simulation time 448447750 ps
CPU time 1.26 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 195544 kb
Host smart-5223901a-89d5-4046-9e2c-99ca63a3d2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691404183 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 5.aon_timer_csr_mem_rw_with_rand_reset.691404183
Directory /workspace/5.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_csr_rw.3985950400
Short name T306
Test name
Test status
Simulation time 393878135 ps
CPU time 1.15 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 183064 kb
Host smart-ae02160b-e25b-48cc-a7b4-07d02ed32097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985950400 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_csr_rw.3985950400
Directory /workspace/5.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_intr_test.2580070029
Short name T395
Test name
Test status
Simulation time 363610039 ps
CPU time 1.13 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 182992 kb
Host smart-8744ded2-37bf-4fdc-946f-c00cf3571587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580070029 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_intr_test.2580070029
Directory /workspace/5.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_same_csr_outstanding.2967046577
Short name T324
Test name
Test status
Simulation time 1498895175 ps
CPU time 1.14 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183140 kb
Host smart-43095f69-2110-47d5-a7dd-7bcbe395190e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967046577 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon
_timer_same_csr_outstanding.2967046577
Directory /workspace/5.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_errors.862848208
Short name T312
Test name
Test status
Simulation time 506917626 ps
CPU time 2.18 seconds
Started Mar 03 12:32:17 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 198004 kb
Host smart-ed211315-cc14-4e6b-b4c7-ba7c2b390aba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862848208 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl_errors.862848208
Directory /workspace/5.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.aon_timer_tl_intg_err.2839149875
Short name T361
Test name
Test status
Simulation time 4471443256 ps
CPU time 7.82 seconds
Started Mar 03 12:32:20 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 196888 kb
Host smart-9aff4c61-db5b-4c71-ad33-569666349f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839149875 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.aon_timer_tl
_intg_err.2839149875
Directory /workspace/5.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_mem_rw_with_rand_reset.1049428765
Short name T377
Test name
Test status
Simulation time 567137756 ps
CPU time 1.13 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 194120 kb
Host smart-5fb64de0-54fa-44f0-b7f8-ebe135a31e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049428765 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.aon_timer_csr_mem_rw_with_rand_reset.1049428765
Directory /workspace/6.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_csr_rw.2105527266
Short name T343
Test name
Test status
Simulation time 519094910 ps
CPU time 1.42 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 192500 kb
Host smart-e41c2e2f-fc71-42c3-8924-8edbf768696d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105527266 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_csr_rw.2105527266
Directory /workspace/6.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_intr_test.333336752
Short name T341
Test name
Test status
Simulation time 433815522 ps
CPU time 0.81 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 182988 kb
Host smart-12ca3f16-bfce-4508-b27e-38e90a2c37c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333336752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_intr_test.333336752
Directory /workspace/6.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_same_csr_outstanding.78630421
Short name T356
Test name
Test status
Simulation time 2021411400 ps
CPU time 1 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 183112 kb
Host smart-2f1cfcd2-3aa7-40d9-a0e4-6c6bf5e661da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78630421 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=ao
n_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_t
imer_same_csr_outstanding.78630421
Directory /workspace/6.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_errors.3043308834
Short name T297
Test name
Test status
Simulation time 509002273 ps
CPU time 1.43 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:37 PM PST 24
Peak memory 197516 kb
Host smart-214dada5-bc62-438d-a07e-74178191552b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043308834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl_errors.3043308834
Directory /workspace/6.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.aon_timer_tl_intg_err.2784490904
Short name T363
Test name
Test status
Simulation time 4356781954 ps
CPU time 2.68 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 196784 kb
Host smart-446dd9f1-19d0-44e1-8222-10c3dd07a78b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784490904 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.aon_timer_tl
_intg_err.2784490904
Directory /workspace/6.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_mem_rw_with_rand_reset.2670908069
Short name T330
Test name
Test status
Simulation time 564083520 ps
CPU time 1.45 seconds
Started Mar 03 12:32:34 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 194752 kb
Host smart-1c3e6f31-57c1-4698-87a0-f996e742e433
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670908069 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.aon_timer_csr_mem_rw_with_rand_reset.2670908069
Directory /workspace/7.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_csr_rw.3414893150
Short name T289
Test name
Test status
Simulation time 392057082 ps
CPU time 0.85 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183184 kb
Host smart-7cd3616c-b4da-42a8-a3b3-e28fa9b58af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414893150 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_csr_rw.3414893150
Directory /workspace/7.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_intr_test.1134600941
Short name T278
Test name
Test status
Simulation time 381405454 ps
CPU time 1.11 seconds
Started Mar 03 12:32:40 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 183016 kb
Host smart-7d818996-ee3f-47f1-9f0a-20cbb3dd5364
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134600941 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_intr_test.1134600941
Directory /workspace/7.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_same_csr_outstanding.1604885555
Short name T345
Test name
Test status
Simulation time 1139691195 ps
CPU time 1.46 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:32:33 PM PST 24
Peak memory 192500 kb
Host smart-b0d5c42f-ee26-4d7f-9ecb-6827fe089041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604885555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon
_timer_same_csr_outstanding.1604885555
Directory /workspace/7.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_errors.478810767
Short name T315
Test name
Test status
Simulation time 872025615 ps
CPU time 1.99 seconds
Started Mar 03 12:32:33 PM PST 24
Finished Mar 03 12:32:35 PM PST 24
Peak memory 198016 kb
Host smart-cb93598f-2539-43ef-a54b-a99a02c3e76e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478810767 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl_errors.478810767
Directory /workspace/7.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.aon_timer_tl_intg_err.1220722937
Short name T379
Test name
Test status
Simulation time 4578430176 ps
CPU time 2.14 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 196668 kb
Host smart-a44d033e-bafe-4191-8212-a87aa72557bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220722937 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.aon_timer_tl
_intg_err.1220722937
Directory /workspace/7.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_mem_rw_with_rand_reset.3795496238
Short name T410
Test name
Test status
Simulation time 420321890 ps
CPU time 1.18 seconds
Started Mar 03 12:32:38 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 194360 kb
Host smart-f0409972-36a1-4eff-8e3e-da0ea84af576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795496238 -assert nopostproc +UVM_TESTNAME
=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 8.aon_timer_csr_mem_rw_with_rand_reset.3795496238
Directory /workspace/8.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_csr_rw.948616063
Short name T57
Test name
Test status
Simulation time 546340876 ps
CPU time 0.95 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183116 kb
Host smart-81eb00ff-5281-4e10-bd5d-4aed5093495a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948616063 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_csr_rw.948616063
Directory /workspace/8.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_intr_test.744918339
Short name T408
Test name
Test status
Simulation time 404978047 ps
CPU time 0.87 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 182968 kb
Host smart-6c47d0e2-1f18-4d0b-856c-ef353187b791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744918339 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_intr_test.744918339
Directory /workspace/8.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_same_csr_outstanding.1552785248
Short name T402
Test name
Test status
Simulation time 2336385851 ps
CPU time 1.66 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 193756 kb
Host smart-eb1c584c-dada-4153-9be9-e711ea379be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552785248 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon
_timer_same_csr_outstanding.1552785248
Directory /workspace/8.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_errors.1460270228
Short name T362
Test name
Test status
Simulation time 414196562 ps
CPU time 2.1 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 197932 kb
Host smart-ca87fa2f-9bd2-48f0-9f00-1bd82f38669a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460270228 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl_errors.1460270228
Directory /workspace/8.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.aon_timer_tl_intg_err.2987556213
Short name T80
Test name
Test status
Simulation time 7956548337 ps
CPU time 13.49 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:37 PM PST 24
Peak memory 197084 kb
Host smart-07a1aaea-d0b4-4405-abb5-4acfdd4672fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987556213 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.aon_timer_tl
_intg_err.2987556213
Directory /workspace/8.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_mem_rw_with_rand_reset.163237347
Short name T357
Test name
Test status
Simulation time 648924351 ps
CPU time 1.13 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:45 PM PST 24
Peak memory 195168 kb
Host smart-cb390607-ee0f-45c7-9d64-019ba1e3d17d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163237347 -assert nopostproc +UVM_TESTNAME=
aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 9.aon_timer_csr_mem_rw_with_rand_reset.163237347
Directory /workspace/9.aon_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_csr_rw.1795468742
Short name T393
Test name
Test status
Simulation time 420627297 ps
CPU time 1.25 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:04 PM PST 24
Peak memory 183108 kb
Host smart-11414dde-a828-40e0-91c1-5c2596b01658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795468742 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_csr_rw.1795468742
Directory /workspace/9.aon_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_intr_test.2205745746
Short name T287
Test name
Test status
Simulation time 472279094 ps
CPU time 0.67 seconds
Started Mar 03 12:32:45 PM PST 24
Finished Mar 03 12:32:45 PM PST 24
Peak memory 183032 kb
Host smart-b82fb66e-a7dd-491f-8e84-98bc6c7f8dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205745746 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_intr_test.2205745746
Directory /workspace/9.aon_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_same_csr_outstanding.2031458955
Short name T58
Test name
Test status
Simulation time 2446549613 ps
CPU time 4.03 seconds
Started Mar 03 12:32:37 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 194020 kb
Host smart-e0fcd0da-5e37-4507-821a-6300ec7d2d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031458955 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=
aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon
_timer_same_csr_outstanding.2031458955
Directory /workspace/9.aon_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_errors.3262595451
Short name T398
Test name
Test status
Simulation time 476005740 ps
CPU time 2.44 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 197972 kb
Host smart-69663bb8-213b-475d-8d5b-4e4cad50a37c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262595451 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl_errors.3262595451
Directory /workspace/9.aon_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.aon_timer_tl_intg_err.2857801371
Short name T385
Test name
Test status
Simulation time 8178308332 ps
CPU time 9.06 seconds
Started Mar 03 12:32:19 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 197644 kb
Host smart-a53ef5f0-cf51-4c18-ab3a-b95d1237edfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857801371 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.aon_timer_tl
_intg_err.2857801371
Directory /workspace/9.aon_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.aon_timer_jump.4087762288
Short name T4
Test name
Test status
Simulation time 502240692 ps
CPU time 0.72 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 183472 kb
Host smart-2ff475a8-22a8-4cf3-bbff-4d8cb94b8204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087762288 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_jump.4087762288
Directory /workspace/0.aon_timer_jump/latest

Test location /workspace/coverage/default/0.aon_timer_prescaler.3259926378
Short name T211
Test name
Test status
Simulation time 31451884784 ps
CPU time 11.37 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:55 PM PST 24
Peak memory 183868 kb
Host smart-fc52b9f6-5e49-4f68-9e2d-f675983bba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259926378 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_prescaler.3259926378
Directory /workspace/0.aon_timer_prescaler/latest

Test location /workspace/coverage/default/0.aon_timer_smoke.3179212541
Short name T88
Test name
Test status
Simulation time 438926457 ps
CPU time 0.67 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:52 PM PST 24
Peak memory 183808 kb
Host smart-a637a5b1-4b67-421b-96bf-0ef2ed30f958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179212541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_smoke.3179212541
Directory /workspace/0.aon_timer_smoke/latest

Test location /workspace/coverage/default/0.aon_timer_stress_all.3413919341
Short name T271
Test name
Test status
Simulation time 52849643562 ps
CPU time 75.2 seconds
Started Mar 03 12:32:43 PM PST 24
Finished Mar 03 12:33:59 PM PST 24
Peak memory 194328 kb
Host smart-37aed82b-d813-41bb-8a83-46850f433bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413919341 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.aon_timer_stress_a
ll.3413919341
Directory /workspace/0.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_jump.2744476404
Short name T139
Test name
Test status
Simulation time 591156968 ps
CPU time 0.73 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 183760 kb
Host smart-29e76384-d01b-4e85-94af-8872162c12c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744476404 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_jump.2744476404
Directory /workspace/1.aon_timer_jump/latest

Test location /workspace/coverage/default/1.aon_timer_prescaler.2930051163
Short name T170
Test name
Test status
Simulation time 1797801150 ps
CPU time 0.74 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 183756 kb
Host smart-c53753c9-cfb8-4c74-8587-e2827e7367ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930051163 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_prescaler.2930051163
Directory /workspace/1.aon_timer_prescaler/latest

Test location /workspace/coverage/default/1.aon_timer_sec_cm.1980699317
Short name T11
Test name
Test status
Simulation time 8047978496 ps
CPU time 12.11 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:33:07 PM PST 24
Peak memory 215728 kb
Host smart-e5e0c734-e15f-4588-a1c7-a8f3b99d8672
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980699317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_sec_cm.1980699317
Directory /workspace/1.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/1.aon_timer_smoke.335099480
Short name T86
Test name
Test status
Simulation time 592054589 ps
CPU time 0.73 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:52 PM PST 24
Peak memory 183736 kb
Host smart-1c3b2b13-46e5-4dd5-a209-11f20f138e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335099480 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_smoke.335099480
Directory /workspace/1.aon_timer_smoke/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all.4020927355
Short name T1
Test name
Test status
Simulation time 199385508333 ps
CPU time 81.96 seconds
Started Mar 03 12:32:37 PM PST 24
Finished Mar 03 12:33:59 PM PST 24
Peak memory 194376 kb
Host smart-d3324970-1738-4cb9-829e-0561a4c8a89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020927355 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_a
ll.4020927355
Directory /workspace/1.aon_timer_stress_all/latest

Test location /workspace/coverage/default/1.aon_timer_stress_all_with_rand_reset.719690247
Short name T266
Test name
Test status
Simulation time 153548593034 ps
CPU time 335.04 seconds
Started Mar 03 12:32:42 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 198752 kb
Host smart-eb8b089a-27b6-4798-bf41-dab9231b65b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719690247 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.aon_timer_stress_all_with_rand_reset.719690247
Directory /workspace/1.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.aon_timer_jump.619678444
Short name T150
Test name
Test status
Simulation time 375372523 ps
CPU time 0.68 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:32:55 PM PST 24
Peak memory 183808 kb
Host smart-594506f2-4259-4b34-a0b1-e1d82675d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619678444 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_jump.619678444
Directory /workspace/10.aon_timer_jump/latest

Test location /workspace/coverage/default/10.aon_timer_prescaler.1585043000
Short name T270
Test name
Test status
Simulation time 1244984261 ps
CPU time 0.96 seconds
Started Mar 03 12:32:58 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 183812 kb
Host smart-5b525066-a329-4a51-a4a5-083af39141d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585043000 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_prescaler.1585043000
Directory /workspace/10.aon_timer_prescaler/latest

Test location /workspace/coverage/default/10.aon_timer_smoke.4231632628
Short name T194
Test name
Test status
Simulation time 427641965 ps
CPU time 0.93 seconds
Started Mar 03 12:32:49 PM PST 24
Finished Mar 03 12:32:50 PM PST 24
Peak memory 183812 kb
Host smart-653350b3-4144-4961-b369-e46995a762f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231632628 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_smoke.4231632628
Directory /workspace/10.aon_timer_smoke/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all.2256513073
Short name T265
Test name
Test status
Simulation time 138129960035 ps
CPU time 109.35 seconds
Started Mar 03 12:32:29 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 183920 kb
Host smart-b2c7560f-da43-4a58-acf5-c28ff456dbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256513073 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_
all.2256513073
Directory /workspace/10.aon_timer_stress_all/latest

Test location /workspace/coverage/default/10.aon_timer_stress_all_with_rand_reset.869951530
Short name T34
Test name
Test status
Simulation time 155347927148 ps
CPU time 250.28 seconds
Started Mar 03 12:32:28 PM PST 24
Finished Mar 03 12:36:39 PM PST 24
Peak memory 206900 kb
Host smart-c1945be7-93da-4404-8095-0dc3e98efe03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869951530 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.aon_timer_stress_all_with_rand_reset.869951530
Directory /workspace/10.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.aon_timer_jump.632622090
Short name T93
Test name
Test status
Simulation time 424930752 ps
CPU time 1.04 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 183696 kb
Host smart-69ab878f-d081-4884-a8b8-f1b58772bf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632622090 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_jump.632622090
Directory /workspace/11.aon_timer_jump/latest

Test location /workspace/coverage/default/11.aon_timer_prescaler.1364381209
Short name T191
Test name
Test status
Simulation time 48965177333 ps
CPU time 5.32 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183848 kb
Host smart-1fd81a8b-2d62-48e3-9c6b-e55228409319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364381209 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_prescaler.1364381209
Directory /workspace/11.aon_timer_prescaler/latest

Test location /workspace/coverage/default/11.aon_timer_smoke.957414554
Short name T164
Test name
Test status
Simulation time 442096592 ps
CPU time 0.79 seconds
Started Mar 03 12:32:48 PM PST 24
Finished Mar 03 12:32:49 PM PST 24
Peak memory 183776 kb
Host smart-366973a8-7553-464f-890a-b35b4f7a72ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957414554 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_smoke.957414554
Directory /workspace/11.aon_timer_smoke/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all.109194317
Short name T224
Test name
Test status
Simulation time 120222162488 ps
CPU time 182.27 seconds
Started Mar 03 12:32:57 PM PST 24
Finished Mar 03 12:36:00 PM PST 24
Peak memory 183880 kb
Host smart-10250898-e739-4dd7-8a44-90ffb079b56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109194317 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_a
ll.109194317
Directory /workspace/11.aon_timer_stress_all/latest

Test location /workspace/coverage/default/11.aon_timer_stress_all_with_rand_reset.3346044013
Short name T74
Test name
Test status
Simulation time 57989839935 ps
CPU time 421.39 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 197116 kb
Host smart-9055bbdf-f112-4c66-8e26-11a6af26b4a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346044013 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.aon_timer_stress_all_with_rand_reset.3346044013
Directory /workspace/11.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.aon_timer_jump.2202024756
Short name T137
Test name
Test status
Simulation time 602564047 ps
CPU time 0.82 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 183708 kb
Host smart-c751fc13-b8bc-427c-88f8-ab131d563f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202024756 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_jump.2202024756
Directory /workspace/12.aon_timer_jump/latest

Test location /workspace/coverage/default/12.aon_timer_prescaler.3091412202
Short name T221
Test name
Test status
Simulation time 30700649296 ps
CPU time 43.47 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:33:09 PM PST 24
Peak memory 183872 kb
Host smart-46dfb785-a0a4-4d9f-aeeb-23c10d9323d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091412202 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_prescaler.3091412202
Directory /workspace/12.aon_timer_prescaler/latest

Test location /workspace/coverage/default/12.aon_timer_smoke.3185173558
Short name T239
Test name
Test status
Simulation time 471755823 ps
CPU time 1.16 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 184112 kb
Host smart-4c2a3526-5e6e-43d0-ac12-121e98d04ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185173558 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_smoke.3185173558
Directory /workspace/12.aon_timer_smoke/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all.1771683836
Short name T206
Test name
Test status
Simulation time 289283826390 ps
CPU time 465.76 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:40:38 PM PST 24
Peak memory 195196 kb
Host smart-67a6c637-e385-4c8d-b665-08adf543a992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771683836 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_
all.1771683836
Directory /workspace/12.aon_timer_stress_all/latest

Test location /workspace/coverage/default/12.aon_timer_stress_all_with_rand_reset.3347632965
Short name T231
Test name
Test status
Simulation time 37610574253 ps
CPU time 418 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:39:30 PM PST 24
Peak memory 198704 kb
Host smart-d8d0d0ff-eef5-44a3-9d08-233ce1f52717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347632965 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.aon_timer_stress_all_with_rand_reset.3347632965
Directory /workspace/12.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.aon_timer_jump.1557880206
Short name T41
Test name
Test status
Simulation time 513146477 ps
CPU time 1.37 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:54 PM PST 24
Peak memory 183820 kb
Host smart-984f1951-ae7c-4bca-be4b-a79d6191e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557880206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_jump.1557880206
Directory /workspace/13.aon_timer_jump/latest

Test location /workspace/coverage/default/13.aon_timer_prescaler.3800259934
Short name T146
Test name
Test status
Simulation time 21855622249 ps
CPU time 17.56 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 183876 kb
Host smart-22bbde9b-ba85-4b87-87f3-3a0ac96d6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800259934 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_prescaler.3800259934
Directory /workspace/13.aon_timer_prescaler/latest

Test location /workspace/coverage/default/13.aon_timer_smoke.3567897298
Short name T178
Test name
Test status
Simulation time 406406684 ps
CPU time 0.74 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:32:56 PM PST 24
Peak memory 183820 kb
Host smart-0c33a322-8bbf-416f-89a5-e0c4966e8d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567897298 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_smoke.3567897298
Directory /workspace/13.aon_timer_smoke/latest

Test location /workspace/coverage/default/13.aon_timer_stress_all_with_rand_reset.1360942201
Short name T70
Test name
Test status
Simulation time 444210350044 ps
CPU time 393.7 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:39:36 PM PST 24
Peak memory 198752 kb
Host smart-889a2a43-8cf8-4d93-8a12-4d8512d4c1f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360942201 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.aon_timer_stress_all_with_rand_reset.1360942201
Directory /workspace/13.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.aon_timer_jump.419489667
Short name T171
Test name
Test status
Simulation time 498850058 ps
CPU time 1.27 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183812 kb
Host smart-ee355a60-21da-4716-bee6-fbba77eaa48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419489667 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_jump.419489667
Directory /workspace/14.aon_timer_jump/latest

Test location /workspace/coverage/default/14.aon_timer_prescaler.2386441752
Short name T142
Test name
Test status
Simulation time 61588850302 ps
CPU time 89.64 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:34:17 PM PST 24
Peak memory 183784 kb
Host smart-89739883-b5ae-49f2-96e3-9d31d3917b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386441752 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_prescaler.2386441752
Directory /workspace/14.aon_timer_prescaler/latest

Test location /workspace/coverage/default/14.aon_timer_smoke.3462483490
Short name T250
Test name
Test status
Simulation time 458221534 ps
CPU time 0.9 seconds
Started Mar 03 12:32:42 PM PST 24
Finished Mar 03 12:32:43 PM PST 24
Peak memory 183824 kb
Host smart-6c1e113b-8251-47f5-9d03-9c6e25409ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462483490 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_smoke.3462483490
Directory /workspace/14.aon_timer_smoke/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all.461049899
Short name T181
Test name
Test status
Simulation time 208738089858 ps
CPU time 153.87 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:35:20 PM PST 24
Peak memory 194196 kb
Host smart-559c20e4-f2af-4cad-8cb5-192f8ff517c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461049899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_a
ll.461049899
Directory /workspace/14.aon_timer_stress_all/latest

Test location /workspace/coverage/default/14.aon_timer_stress_all_with_rand_reset.1686088849
Short name T35
Test name
Test status
Simulation time 71926807952 ps
CPU time 108.96 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:34:43 PM PST 24
Peak memory 198604 kb
Host smart-c07b1b8c-ce93-4f28-a599-0e8a0e9f38dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686088849 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.aon_timer_stress_all_with_rand_reset.1686088849
Directory /workspace/14.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.aon_timer_jump.3156912487
Short name T235
Test name
Test status
Simulation time 436147298 ps
CPU time 0.73 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 183820 kb
Host smart-2c0ed99d-6a31-4c24-a11b-fb7196e609a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156912487 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_jump.3156912487
Directory /workspace/15.aon_timer_jump/latest

Test location /workspace/coverage/default/15.aon_timer_prescaler.1521090726
Short name T153
Test name
Test status
Simulation time 2215235234 ps
CPU time 2.66 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 183760 kb
Host smart-989f6612-61b6-4d6a-9275-364636a045c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521090726 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_prescaler.1521090726
Directory /workspace/15.aon_timer_prescaler/latest

Test location /workspace/coverage/default/15.aon_timer_smoke.2209569373
Short name T218
Test name
Test status
Simulation time 505183746 ps
CPU time 1.22 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183820 kb
Host smart-7d2693fd-ab78-4b1c-9d8c-82fa141f23e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209569373 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_smoke.2209569373
Directory /workspace/15.aon_timer_smoke/latest

Test location /workspace/coverage/default/15.aon_timer_stress_all.1814823010
Short name T244
Test name
Test status
Simulation time 320347678953 ps
CPU time 239.38 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:36:22 PM PST 24
Peak memory 183848 kb
Host smart-089e44f4-b5f2-497c-9523-2723c28b9101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814823010 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.aon_timer_stress_
all.1814823010
Directory /workspace/15.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_jump.2628201227
Short name T201
Test name
Test status
Simulation time 424381431 ps
CPU time 1.13 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:52 PM PST 24
Peak memory 183820 kb
Host smart-9c6d3a15-945e-493e-94c1-302e67cd75b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628201227 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_jump.2628201227
Directory /workspace/16.aon_timer_jump/latest

Test location /workspace/coverage/default/16.aon_timer_prescaler.2710898678
Short name T220
Test name
Test status
Simulation time 21288311210 ps
CPU time 17.16 seconds
Started Mar 03 12:32:29 PM PST 24
Finished Mar 03 12:32:46 PM PST 24
Peak memory 183760 kb
Host smart-b54b60e4-823a-4537-a12d-8a8fd4e187aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710898678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_prescaler.2710898678
Directory /workspace/16.aon_timer_prescaler/latest

Test location /workspace/coverage/default/16.aon_timer_smoke.2527263232
Short name T245
Test name
Test status
Simulation time 419707719 ps
CPU time 1.14 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:02 PM PST 24
Peak memory 183816 kb
Host smart-38d80f0a-f424-4f56-b886-eb59e06c1261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527263232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_smoke.2527263232
Directory /workspace/16.aon_timer_smoke/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all.2433006859
Short name T242
Test name
Test status
Simulation time 25153194918 ps
CPU time 6.01 seconds
Started Mar 03 12:32:33 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 183872 kb
Host smart-49a526da-1005-4be5-b052-6683088a7a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433006859 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_
all.2433006859
Directory /workspace/16.aon_timer_stress_all/latest

Test location /workspace/coverage/default/16.aon_timer_stress_all_with_rand_reset.3275659373
Short name T208
Test name
Test status
Simulation time 110236155485 ps
CPU time 463.8 seconds
Started Mar 03 12:32:57 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 198756 kb
Host smart-5aec35e4-8e31-4cd0-b153-276107384ca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275659373 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.aon_timer_stress_all_with_rand_reset.3275659373
Directory /workspace/16.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.aon_timer_jump.1648585448
Short name T262
Test name
Test status
Simulation time 371056142 ps
CPU time 1.07 seconds
Started Mar 03 12:32:49 PM PST 24
Finished Mar 03 12:32:50 PM PST 24
Peak memory 183816 kb
Host smart-2d3a8627-bcd8-415b-9f96-b3ba548c9d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648585448 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_jump.1648585448
Directory /workspace/17.aon_timer_jump/latest

Test location /workspace/coverage/default/17.aon_timer_prescaler.590916499
Short name T240
Test name
Test status
Simulation time 33254854176 ps
CPU time 50.75 seconds
Started Mar 03 12:32:39 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 183864 kb
Host smart-5459ee7a-1a6f-4a14-9f59-891b7d22a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590916499 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_prescaler.590916499
Directory /workspace/17.aon_timer_prescaler/latest

Test location /workspace/coverage/default/17.aon_timer_smoke.716623383
Short name T149
Test name
Test status
Simulation time 420468836 ps
CPU time 0.76 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:32:55 PM PST 24
Peak memory 183816 kb
Host smart-deb80363-8b54-4190-a061-21552f5ab9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716623383 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_smoke.716623383
Directory /workspace/17.aon_timer_smoke/latest

Test location /workspace/coverage/default/17.aon_timer_stress_all.2976528142
Short name T175
Test name
Test status
Simulation time 172773486911 ps
CPU time 232.55 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:36:23 PM PST 24
Peak memory 194348 kb
Host smart-a7059e2b-f3f0-488b-86b6-8f4a6d4c3b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976528142 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.aon_timer_stress_
all.2976528142
Directory /workspace/17.aon_timer_stress_all/latest

Test location /workspace/coverage/default/18.aon_timer_jump.4257898050
Short name T223
Test name
Test status
Simulation time 400217362 ps
CPU time 0.84 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183760 kb
Host smart-07e48f06-bb7c-4e22-95ab-3308f1052da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257898050 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_jump.4257898050
Directory /workspace/18.aon_timer_jump/latest

Test location /workspace/coverage/default/18.aon_timer_prescaler.2020995225
Short name T140
Test name
Test status
Simulation time 36415543732 ps
CPU time 57.76 seconds
Started Mar 03 12:32:57 PM PST 24
Finished Mar 03 12:33:55 PM PST 24
Peak memory 183872 kb
Host smart-defa3150-2c3d-40fa-bb5e-891fa2a6f7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020995225 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_prescaler.2020995225
Directory /workspace/18.aon_timer_prescaler/latest

Test location /workspace/coverage/default/18.aon_timer_smoke.338599627
Short name T100
Test name
Test status
Simulation time 447911470 ps
CPU time 0.93 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183700 kb
Host smart-20a67d03-0e23-4680-aa1c-cd0f9c23baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338599627 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_smoke.338599627
Directory /workspace/18.aon_timer_smoke/latest

Test location /workspace/coverage/default/18.aon_timer_stress_all_with_rand_reset.4227647079
Short name T243
Test name
Test status
Simulation time 47939159077 ps
CPU time 366.71 seconds
Started Mar 03 12:32:49 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 198776 kb
Host smart-9894cba5-b04b-4725-a40d-fe59471f34a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227647079 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.aon_timer_stress_all_with_rand_reset.4227647079
Directory /workspace/18.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.aon_timer_jump.2182088301
Short name T268
Test name
Test status
Simulation time 591829913 ps
CPU time 1.01 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:02 PM PST 24
Peak memory 183824 kb
Host smart-6ebf3476-3e9d-4dd4-8bf8-d489bbf4969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182088301 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_jump.2182088301
Directory /workspace/19.aon_timer_jump/latest

Test location /workspace/coverage/default/19.aon_timer_prescaler.4294124593
Short name T200
Test name
Test status
Simulation time 26004400559 ps
CPU time 5.75 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:49 PM PST 24
Peak memory 183804 kb
Host smart-21317c25-5f99-4e84-a7f3-2166a0b075e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294124593 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_prescaler.4294124593
Directory /workspace/19.aon_timer_prescaler/latest

Test location /workspace/coverage/default/19.aon_timer_smoke.1335488146
Short name T98
Test name
Test status
Simulation time 325137368 ps
CPU time 1.04 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 183740 kb
Host smart-5222f78b-34ef-40c9-85ef-c942a050bbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335488146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_smoke.1335488146
Directory /workspace/19.aon_timer_smoke/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all.617252876
Short name T168
Test name
Test status
Simulation time 39233943414 ps
CPU time 8.54 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 183780 kb
Host smart-39ce8a52-b454-4ea3-9e6c-26311e800a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617252876 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_a
ll.617252876
Directory /workspace/19.aon_timer_stress_all/latest

Test location /workspace/coverage/default/19.aon_timer_stress_all_with_rand_reset.4004895398
Short name T36
Test name
Test status
Simulation time 267431864551 ps
CPU time 421.48 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:39:56 PM PST 24
Peak memory 198656 kb
Host smart-da4d2e71-e846-4285-a446-606fe74084be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004895398 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.aon_timer_stress_all_with_rand_reset.4004895398
Directory /workspace/19.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.aon_timer_jump.2249571771
Short name T8
Test name
Test status
Simulation time 407478293 ps
CPU time 0.69 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 183812 kb
Host smart-3469e51d-31b5-40de-8d5c-c72304fa7a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249571771 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_jump.2249571771
Directory /workspace/2.aon_timer_jump/latest

Test location /workspace/coverage/default/2.aon_timer_prescaler.1365080914
Short name T111
Test name
Test status
Simulation time 35138459191 ps
CPU time 14.22 seconds
Started Mar 03 12:33:00 PM PST 24
Finished Mar 03 12:33:15 PM PST 24
Peak memory 183872 kb
Host smart-466c1740-5b1c-4cdd-8645-ae279dbaacf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365080914 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_prescaler.1365080914
Directory /workspace/2.aon_timer_prescaler/latest

Test location /workspace/coverage/default/2.aon_timer_sec_cm.344047258
Short name T20
Test name
Test status
Simulation time 7673898503 ps
CPU time 13.01 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:33:00 PM PST 24
Peak memory 215692 kb
Host smart-e7be2d48-b8ea-4ae4-9ece-21be65c18593
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344047258 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_sec_cm.344047258
Directory /workspace/2.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/2.aon_timer_smoke.1987665898
Short name T177
Test name
Test status
Simulation time 485159409 ps
CPU time 0.69 seconds
Started Mar 03 12:32:41 PM PST 24
Finished Mar 03 12:32:42 PM PST 24
Peak memory 183804 kb
Host smart-d8e24052-42ce-444e-ad75-6f7b5433e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987665898 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.aon_timer_smoke.1987665898
Directory /workspace/2.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_jump.3584320994
Short name T133
Test name
Test status
Simulation time 564025186 ps
CPU time 0.78 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:00 PM PST 24
Peak memory 183792 kb
Host smart-c3eca066-59b4-4b04-bb7c-123e2246cc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584320994 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_jump.3584320994
Directory /workspace/20.aon_timer_jump/latest

Test location /workspace/coverage/default/20.aon_timer_prescaler.1097536436
Short name T132
Test name
Test status
Simulation time 18335746455 ps
CPU time 13.53 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:33:05 PM PST 24
Peak memory 184216 kb
Host smart-baf64e2e-bbc7-4763-b407-8961af8f21a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097536436 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_prescaler.1097536436
Directory /workspace/20.aon_timer_prescaler/latest

Test location /workspace/coverage/default/20.aon_timer_smoke.3943299856
Short name T192
Test name
Test status
Simulation time 503582778 ps
CPU time 1.3 seconds
Started Mar 03 12:32:54 PM PST 24
Finished Mar 03 12:32:56 PM PST 24
Peak memory 183756 kb
Host smart-26caa1d2-352a-4dc8-a6c4-3099284e2fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943299856 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_smoke.3943299856
Directory /workspace/20.aon_timer_smoke/latest

Test location /workspace/coverage/default/20.aon_timer_stress_all_with_rand_reset.1188634837
Short name T32
Test name
Test status
Simulation time 21631709850 ps
CPU time 172.58 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:35:25 PM PST 24
Peak memory 198648 kb
Host smart-dfd4aba8-469c-403a-bcb1-9c11224aaea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188634837 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.aon_timer_stress_all_with_rand_reset.1188634837
Directory /workspace/20.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.aon_timer_jump.4198087291
Short name T96
Test name
Test status
Simulation time 492802077 ps
CPU time 0.73 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:31 PM PST 24
Peak memory 183796 kb
Host smart-2274f915-a651-4bf6-8c96-ce7e09409f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198087291 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_jump.4198087291
Directory /workspace/21.aon_timer_jump/latest

Test location /workspace/coverage/default/21.aon_timer_prescaler.3500259452
Short name T129
Test name
Test status
Simulation time 1440248842 ps
CPU time 2.8 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 183736 kb
Host smart-36e699ce-6bdb-4ff4-9ebe-1e0faf078599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500259452 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_prescaler.3500259452
Directory /workspace/21.aon_timer_prescaler/latest

Test location /workspace/coverage/default/21.aon_timer_smoke.1599461168
Short name T215
Test name
Test status
Simulation time 493336723 ps
CPU time 1.18 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 183736 kb
Host smart-639b4fe3-5b68-4de0-b87a-ee60ec12c2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599461168 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_smoke.1599461168
Directory /workspace/21.aon_timer_smoke/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all.1269296900
Short name T143
Test name
Test status
Simulation time 54630524759 ps
CPU time 21 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:33:05 PM PST 24
Peak memory 195500 kb
Host smart-76761679-0925-4026-8182-e0a3a2eba75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269296900 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_
all.1269296900
Directory /workspace/21.aon_timer_stress_all/latest

Test location /workspace/coverage/default/21.aon_timer_stress_all_with_rand_reset.4162374817
Short name T202
Test name
Test status
Simulation time 30787727875 ps
CPU time 223.99 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:36:40 PM PST 24
Peak memory 198700 kb
Host smart-b918fd83-de64-499c-9d78-3f29d491a490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162374817 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.aon_timer_stress_all_with_rand_reset.4162374817
Directory /workspace/21.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.aon_timer_jump.3640430899
Short name T251
Test name
Test status
Simulation time 453947993 ps
CPU time 0.91 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183824 kb
Host smart-b376f31b-87a0-4bca-99d9-b1067696843e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640430899 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_jump.3640430899
Directory /workspace/22.aon_timer_jump/latest

Test location /workspace/coverage/default/22.aon_timer_prescaler.4215528644
Short name T152
Test name
Test status
Simulation time 46419155895 ps
CPU time 61.49 seconds
Started Mar 03 12:33:05 PM PST 24
Finished Mar 03 12:34:06 PM PST 24
Peak memory 183840 kb
Host smart-a1b5c2d6-f41a-4f04-9aa6-b2e07d3f9fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215528644 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_prescaler.4215528644
Directory /workspace/22.aon_timer_prescaler/latest

Test location /workspace/coverage/default/22.aon_timer_smoke.115496459
Short name T258
Test name
Test status
Simulation time 346342804 ps
CPU time 0.81 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:02 PM PST 24
Peak memory 183816 kb
Host smart-3a41a81e-6ce2-472d-a8c4-15325e03599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115496459 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_smoke.115496459
Directory /workspace/22.aon_timer_smoke/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all.3175507532
Short name T38
Test name
Test status
Simulation time 87059002574 ps
CPU time 40.41 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:33:11 PM PST 24
Peak memory 183804 kb
Host smart-961431bc-e3f9-4a38-9630-243beac3b137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175507532 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_
all.3175507532
Directory /workspace/22.aon_timer_stress_all/latest

Test location /workspace/coverage/default/22.aon_timer_stress_all_with_rand_reset.62935562
Short name T233
Test name
Test status
Simulation time 106471167069 ps
CPU time 577.34 seconds
Started Mar 03 12:32:46 PM PST 24
Finished Mar 03 12:42:23 PM PST 24
Peak memory 199708 kb
Host smart-a1d9d9bb-c713-4358-b865-3b2bf29d6ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62935562 -assert nopo
stproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.aon_timer_stress_all_with_rand_reset.62935562
Directory /workspace/22.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.aon_timer_jump.3360720011
Short name T104
Test name
Test status
Simulation time 432794940 ps
CPU time 0.63 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183868 kb
Host smart-431bdc47-8cc2-424e-9c03-d2e439b9ed1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360720011 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_jump.3360720011
Directory /workspace/23.aon_timer_jump/latest

Test location /workspace/coverage/default/23.aon_timer_prescaler.2895984403
Short name T184
Test name
Test status
Simulation time 33745039112 ps
CPU time 44.95 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:39:37 PM PST 24
Peak memory 183792 kb
Host smart-e2ce5c94-fbfc-40e4-9f1a-14dac208c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895984403 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_prescaler.2895984403
Directory /workspace/23.aon_timer_prescaler/latest

Test location /workspace/coverage/default/23.aon_timer_smoke.3194040718
Short name T124
Test name
Test status
Simulation time 548654189 ps
CPU time 1.39 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:32:48 PM PST 24
Peak memory 183812 kb
Host smart-b39227bb-7184-4b0e-81a8-95aeca4d2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194040718 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_smoke.3194040718
Directory /workspace/23.aon_timer_smoke/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all.2549097789
Short name T205
Test name
Test status
Simulation time 47673246364 ps
CPU time 38.22 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:33:34 PM PST 24
Peak memory 183992 kb
Host smart-3cd2785b-eac3-4960-98c7-49804154ca20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549097789 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_
all.2549097789
Directory /workspace/23.aon_timer_stress_all/latest

Test location /workspace/coverage/default/23.aon_timer_stress_all_with_rand_reset.1771096425
Short name T71
Test name
Test status
Simulation time 34225578326 ps
CPU time 232.95 seconds
Started Mar 03 12:33:03 PM PST 24
Finished Mar 03 12:36:57 PM PST 24
Peak memory 198660 kb
Host smart-461d8341-df71-4107-bec7-08e521b61a5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771096425 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.aon_timer_stress_all_with_rand_reset.1771096425
Directory /workspace/23.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.aon_timer_jump.3023149030
Short name T115
Test name
Test status
Simulation time 386653281 ps
CPU time 1.07 seconds
Started Mar 03 12:32:53 PM PST 24
Finished Mar 03 12:32:54 PM PST 24
Peak memory 183896 kb
Host smart-20ff8324-43b0-479f-a30a-f327bc7256a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023149030 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_jump.3023149030
Directory /workspace/24.aon_timer_jump/latest

Test location /workspace/coverage/default/24.aon_timer_prescaler.2662818893
Short name T210
Test name
Test status
Simulation time 20160299263 ps
CPU time 32.81 seconds
Started Mar 03 12:32:45 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183872 kb
Host smart-2dd10bae-c619-42bf-924a-1e3f3dd53b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662818893 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_prescaler.2662818893
Directory /workspace/24.aon_timer_prescaler/latest

Test location /workspace/coverage/default/24.aon_timer_smoke.1057035843
Short name T179
Test name
Test status
Simulation time 432370626 ps
CPU time 0.93 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 183676 kb
Host smart-195d7341-5563-4b5d-8f5f-4dcd1356b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057035843 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_smoke.1057035843
Directory /workspace/24.aon_timer_smoke/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all.3944399645
Short name T39
Test name
Test status
Simulation time 279710895901 ps
CPU time 212.4 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:36:05 PM PST 24
Peak memory 183824 kb
Host smart-dcaa872b-7f92-4c5b-84a0-23100f5e27dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944399645 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_
all.3944399645
Directory /workspace/24.aon_timer_stress_all/latest

Test location /workspace/coverage/default/24.aon_timer_stress_all_with_rand_reset.3192921800
Short name T158
Test name
Test status
Simulation time 60612234159 ps
CPU time 160.81 seconds
Started Mar 03 12:32:38 PM PST 24
Finished Mar 03 12:35:19 PM PST 24
Peak memory 206852 kb
Host smart-974e93ea-72d3-47e1-8285-974672053f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192921800 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.aon_timer_stress_all_with_rand_reset.3192921800
Directory /workspace/24.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.aon_timer_jump.3319530242
Short name T162
Test name
Test status
Simulation time 489923970 ps
CPU time 1.18 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:32:33 PM PST 24
Peak memory 183820 kb
Host smart-7391d158-c801-4951-ad4a-fb90237db691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319530242 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_jump.3319530242
Directory /workspace/25.aon_timer_jump/latest

Test location /workspace/coverage/default/25.aon_timer_prescaler.283964805
Short name T42
Test name
Test status
Simulation time 16215756836 ps
CPU time 11.63 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:11 PM PST 24
Peak memory 183868 kb
Host smart-94785932-beb6-4d60-98c7-6776d7fb9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283964805 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_prescaler.283964805
Directory /workspace/25.aon_timer_prescaler/latest

Test location /workspace/coverage/default/25.aon_timer_smoke.796082076
Short name T13
Test name
Test status
Simulation time 453355508 ps
CPU time 0.59 seconds
Started Mar 03 12:32:33 PM PST 24
Finished Mar 03 12:32:33 PM PST 24
Peak memory 183768 kb
Host smart-e4add861-9ef1-4350-a82c-40cbb91badc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796082076 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_smoke.796082076
Directory /workspace/25.aon_timer_smoke/latest

Test location /workspace/coverage/default/25.aon_timer_stress_all_with_rand_reset.907657923
Short name T108
Test name
Test status
Simulation time 24215348201 ps
CPU time 200.83 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:35:51 PM PST 24
Peak memory 198752 kb
Host smart-8556596a-6e22-443f-9445-6570e9426008
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907657923 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.aon_timer_stress_all_with_rand_reset.907657923
Directory /workspace/25.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.aon_timer_jump.1782022938
Short name T163
Test name
Test status
Simulation time 594742796 ps
CPU time 1.53 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183896 kb
Host smart-79166fef-cee8-41cf-9461-f118678a9d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782022938 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_jump.1782022938
Directory /workspace/26.aon_timer_jump/latest

Test location /workspace/coverage/default/26.aon_timer_prescaler.871584560
Short name T254
Test name
Test status
Simulation time 22915181377 ps
CPU time 10.24 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 183816 kb
Host smart-af5967b4-b93a-49b3-b3cb-a1cdfae94118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871584560 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_prescaler.871584560
Directory /workspace/26.aon_timer_prescaler/latest

Test location /workspace/coverage/default/26.aon_timer_smoke.2300044222
Short name T126
Test name
Test status
Simulation time 485292418 ps
CPU time 0.72 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 183720 kb
Host smart-f6f122c2-4c81-4887-87cd-5c7ac9e38a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300044222 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_smoke.2300044222
Directory /workspace/26.aon_timer_smoke/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all.2724858313
Short name T237
Test name
Test status
Simulation time 198027344712 ps
CPU time 68.33 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:40:00 PM PST 24
Peak memory 183796 kb
Host smart-249ef046-2119-4e41-95df-3683dbc85ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724858313 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_
all.2724858313
Directory /workspace/26.aon_timer_stress_all/latest

Test location /workspace/coverage/default/26.aon_timer_stress_all_with_rand_reset.2858032237
Short name T260
Test name
Test status
Simulation time 78500240712 ps
CPU time 804.16 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:51:59 PM PST 24
Peak memory 201124 kb
Host smart-e0fc5f50-764b-4429-8e01-4838d1b74071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858032237 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 26.aon_timer_stress_all_with_rand_reset.2858032237
Directory /workspace/26.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.aon_timer_jump.3752613815
Short name T9
Test name
Test status
Simulation time 433076545 ps
CPU time 1.14 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:04 PM PST 24
Peak memory 183796 kb
Host smart-1c492317-65ad-4f85-b03e-61b05d25f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752613815 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_jump.3752613815
Directory /workspace/27.aon_timer_jump/latest

Test location /workspace/coverage/default/27.aon_timer_prescaler.2065423235
Short name T213
Test name
Test status
Simulation time 11152390785 ps
CPU time 3.28 seconds
Started Mar 03 12:32:36 PM PST 24
Finished Mar 03 12:32:40 PM PST 24
Peak memory 183868 kb
Host smart-96c135db-eef3-4b8a-92c9-c971b3f38266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065423235 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_prescaler.2065423235
Directory /workspace/27.aon_timer_prescaler/latest

Test location /workspace/coverage/default/27.aon_timer_smoke.3593326140
Short name T272
Test name
Test status
Simulation time 393944364 ps
CPU time 0.88 seconds
Started Mar 03 12:33:00 PM PST 24
Finished Mar 03 12:33:01 PM PST 24
Peak memory 183892 kb
Host smart-bde1d2a2-aade-4f0a-8a2b-66ef52e4fc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593326140 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_smoke.3593326140
Directory /workspace/27.aon_timer_smoke/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all.486930555
Short name T259
Test name
Test status
Simulation time 67872261971 ps
CPU time 69.46 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 194452 kb
Host smart-13318936-e0de-4017-89d8-c776a49b0b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486930555 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_a
ll.486930555
Directory /workspace/27.aon_timer_stress_all/latest

Test location /workspace/coverage/default/27.aon_timer_stress_all_with_rand_reset.1003500964
Short name T128
Test name
Test status
Simulation time 95740649346 ps
CPU time 414.36 seconds
Started Mar 03 12:32:53 PM PST 24
Finished Mar 03 12:39:48 PM PST 24
Peak memory 214588 kb
Host smart-826138e4-6881-4b2d-9dad-382d84c006cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003500964 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.aon_timer_stress_all_with_rand_reset.1003500964
Directory /workspace/27.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.aon_timer_jump.397153616
Short name T166
Test name
Test status
Simulation time 502504607 ps
CPU time 1.19 seconds
Started Mar 03 12:32:58 PM PST 24
Finished Mar 03 12:33:00 PM PST 24
Peak memory 183772 kb
Host smart-19df80fc-6f2d-41f6-b223-54910eda2eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397153616 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_jump.397153616
Directory /workspace/28.aon_timer_jump/latest

Test location /workspace/coverage/default/28.aon_timer_prescaler.1794136259
Short name T76
Test name
Test status
Simulation time 28257637599 ps
CPU time 2.79 seconds
Started Mar 03 12:32:33 PM PST 24
Finished Mar 03 12:32:36 PM PST 24
Peak memory 183824 kb
Host smart-47c7895b-3438-489d-8faa-71c80fccfe92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794136259 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_prescaler.1794136259
Directory /workspace/28.aon_timer_prescaler/latest

Test location /workspace/coverage/default/28.aon_timer_smoke.735339544
Short name T16
Test name
Test status
Simulation time 443599196 ps
CPU time 0.71 seconds
Started Mar 03 12:32:50 PM PST 24
Finished Mar 03 12:32:50 PM PST 24
Peak memory 183772 kb
Host smart-554377dc-b4ad-4058-a187-bebddf8c10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735339544 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_smoke.735339544
Directory /workspace/28.aon_timer_smoke/latest

Test location /workspace/coverage/default/28.aon_timer_stress_all.206646921
Short name T15
Test name
Test status
Simulation time 63631763602 ps
CPU time 87.21 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:34:14 PM PST 24
Peak memory 192688 kb
Host smart-74d028e2-8cc5-4b75-9aac-0487feb60a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206646921 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.aon_timer_stress_a
ll.206646921
Directory /workspace/28.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_jump.2206901384
Short name T238
Test name
Test status
Simulation time 345478242 ps
CPU time 1.05 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 183704 kb
Host smart-3dc63593-4469-4569-812d-3535e8da45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206901384 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_jump.2206901384
Directory /workspace/29.aon_timer_jump/latest

Test location /workspace/coverage/default/29.aon_timer_prescaler.1485312307
Short name T156
Test name
Test status
Simulation time 1619013289 ps
CPU time 1.21 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 183736 kb
Host smart-9bde4cec-8179-4402-9fee-cff749649457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485312307 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_prescaler.1485312307
Directory /workspace/29.aon_timer_prescaler/latest

Test location /workspace/coverage/default/29.aon_timer_smoke.1490546925
Short name T257
Test name
Test status
Simulation time 545389018 ps
CPU time 1.43 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:01 PM PST 24
Peak memory 183820 kb
Host smart-81b7468e-225f-4360-8bca-90102b46f7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490546925 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_smoke.1490546925
Directory /workspace/29.aon_timer_smoke/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all.2874348894
Short name T246
Test name
Test status
Simulation time 260595132887 ps
CPU time 366.11 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:39:09 PM PST 24
Peak memory 195488 kb
Host smart-c83b6b57-55b5-42c0-a620-c066e83b8396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874348894 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_
all.2874348894
Directory /workspace/29.aon_timer_stress_all/latest

Test location /workspace/coverage/default/29.aon_timer_stress_all_with_rand_reset.357991857
Short name T14
Test name
Test status
Simulation time 162538864734 ps
CPU time 198.98 seconds
Started Mar 03 12:33:56 PM PST 24
Finished Mar 03 12:37:17 PM PST 24
Peak memory 197760 kb
Host smart-7637ea1c-d20a-456d-bc89-2d2daee632c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357991857 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.aon_timer_stress_all_with_rand_reset.357991857
Directory /workspace/29.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.aon_timer_jump.2076554055
Short name T117
Test name
Test status
Simulation time 521103932 ps
CPU time 0.75 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183720 kb
Host smart-a0421664-7d70-48c7-8950-1200bb553648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076554055 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_jump.2076554055
Directory /workspace/3.aon_timer_jump/latest

Test location /workspace/coverage/default/3.aon_timer_prescaler.3693824565
Short name T252
Test name
Test status
Simulation time 18419469997 ps
CPU time 8.67 seconds
Started Mar 03 12:32:50 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 183864 kb
Host smart-fe358757-7a1e-4497-afe3-1377d7fff38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693824565 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_prescaler.3693824565
Directory /workspace/3.aon_timer_prescaler/latest

Test location /workspace/coverage/default/3.aon_timer_sec_cm.1953282261
Short name T19
Test name
Test status
Simulation time 4393166436 ps
CPU time 2.33 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 215560 kb
Host smart-0e83e20f-09be-4fc8-9a81-eb86d6f5da06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953282261 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_sec_cm.1953282261
Directory /workspace/3.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/3.aon_timer_smoke.4740779
Short name T107
Test name
Test status
Simulation time 439848666 ps
CPU time 0.91 seconds
Started Mar 03 12:32:49 PM PST 24
Finished Mar 03 12:32:50 PM PST 24
Peak memory 183808 kb
Host smart-3b1e299e-998a-4677-9731-7926bfe2d9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4740779 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_smoke.4740779
Directory /workspace/3.aon_timer_smoke/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all.192499027
Short name T248
Test name
Test status
Simulation time 104919442382 ps
CPU time 39.3 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:33:24 PM PST 24
Peak memory 194116 kb
Host smart-e75dd749-b31f-42d4-a1a6-10dfc8a3adf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192499027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_al
l.192499027
Directory /workspace/3.aon_timer_stress_all/latest

Test location /workspace/coverage/default/3.aon_timer_stress_all_with_rand_reset.1009528699
Short name T67
Test name
Test status
Simulation time 88568027797 ps
CPU time 622.92 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 214700 kb
Host smart-efbc295d-dadc-4d8d-a90f-8fee949b2e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009528699 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.aon_timer_stress_all_with_rand_reset.1009528699
Directory /workspace/3.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.aon_timer_jump.3558961533
Short name T135
Test name
Test status
Simulation time 382169242 ps
CPU time 1.04 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 183720 kb
Host smart-f90e9787-35b4-4706-b099-84d6481572d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558961533 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_jump.3558961533
Directory /workspace/30.aon_timer_jump/latest

Test location /workspace/coverage/default/30.aon_timer_prescaler.3621199184
Short name T12
Test name
Test status
Simulation time 26397902444 ps
CPU time 41.53 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:33:26 PM PST 24
Peak memory 183876 kb
Host smart-e9be131d-23e6-4998-b4b8-e9d6288f052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621199184 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_prescaler.3621199184
Directory /workspace/30.aon_timer_prescaler/latest

Test location /workspace/coverage/default/30.aon_timer_smoke.1773957872
Short name T17
Test name
Test status
Simulation time 505349858 ps
CPU time 0.7 seconds
Started Mar 03 12:32:53 PM PST 24
Finished Mar 03 12:32:54 PM PST 24
Peak memory 183820 kb
Host smart-201bd157-8779-4a40-8f07-ca778c18f671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773957872 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_smoke.1773957872
Directory /workspace/30.aon_timer_smoke/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all.2423999206
Short name T102
Test name
Test status
Simulation time 81773719292 ps
CPU time 114.65 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:34:58 PM PST 24
Peak memory 183948 kb
Host smart-90398a0b-65ca-4331-a6fa-8811b4448190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423999206 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_
all.2423999206
Directory /workspace/30.aon_timer_stress_all/latest

Test location /workspace/coverage/default/30.aon_timer_stress_all_with_rand_reset.1798154740
Short name T267
Test name
Test status
Simulation time 163367057226 ps
CPU time 1138.85 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:52:16 PM PST 24
Peak memory 206056 kb
Host smart-6fb45460-6cfd-4705-afd7-bd20336218c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798154740 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.aon_timer_stress_all_with_rand_reset.1798154740
Directory /workspace/30.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.aon_timer_jump.3514206515
Short name T186
Test name
Test status
Simulation time 546969143 ps
CPU time 0.74 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 183724 kb
Host smart-7305dbb5-d3b1-47b3-b563-deb7952449d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514206515 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_jump.3514206515
Directory /workspace/31.aon_timer_jump/latest

Test location /workspace/coverage/default/31.aon_timer_prescaler.4222912512
Short name T105
Test name
Test status
Simulation time 39719700156 ps
CPU time 66.99 seconds
Started Mar 03 12:33:41 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 183876 kb
Host smart-4e58e1df-20bf-4902-911c-4c83552150a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222912512 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_prescaler.4222912512
Directory /workspace/31.aon_timer_prescaler/latest

Test location /workspace/coverage/default/31.aon_timer_smoke.800257913
Short name T174
Test name
Test status
Simulation time 421729350 ps
CPU time 0.72 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:33:29 PM PST 24
Peak memory 183768 kb
Host smart-8cce6aa6-1ec5-4f68-a387-4588ac5960b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800257913 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_smoke.800257913
Directory /workspace/31.aon_timer_smoke/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all.3752031367
Short name T189
Test name
Test status
Simulation time 64224030769 ps
CPU time 95.36 seconds
Started Mar 03 12:33:23 PM PST 24
Finished Mar 03 12:34:59 PM PST 24
Peak memory 194076 kb
Host smart-fd12cf7d-bbd7-4dce-a09b-068bf195a81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752031367 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_
all.3752031367
Directory /workspace/31.aon_timer_stress_all/latest

Test location /workspace/coverage/default/31.aon_timer_stress_all_with_rand_reset.3329528894
Short name T31
Test name
Test status
Simulation time 24988602558 ps
CPU time 149.43 seconds
Started Mar 03 12:33:13 PM PST 24
Finished Mar 03 12:35:42 PM PST 24
Peak memory 198696 kb
Host smart-f10bc2d7-e42e-4f99-8993-a6386d29b611
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329528894 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.aon_timer_stress_all_with_rand_reset.3329528894
Directory /workspace/31.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.aon_timer_jump.3932905474
Short name T97
Test name
Test status
Simulation time 425426122 ps
CPU time 0.72 seconds
Started Mar 03 12:33:14 PM PST 24
Finished Mar 03 12:33:15 PM PST 24
Peak memory 183820 kb
Host smart-5deb320b-ffac-431e-876f-faeadbbc0b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932905474 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_jump.3932905474
Directory /workspace/32.aon_timer_jump/latest

Test location /workspace/coverage/default/32.aon_timer_prescaler.1003769065
Short name T229
Test name
Test status
Simulation time 34353378271 ps
CPU time 46.82 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:34:02 PM PST 24
Peak memory 183876 kb
Host smart-7a730168-c609-4179-bf22-b53386bb0833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003769065 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_prescaler.1003769065
Directory /workspace/32.aon_timer_prescaler/latest

Test location /workspace/coverage/default/32.aon_timer_smoke.1682964948
Short name T148
Test name
Test status
Simulation time 349690983 ps
CPU time 0.66 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 183816 kb
Host smart-1fd292ea-faee-480c-a00c-0543a3807253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682964948 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_smoke.1682964948
Directory /workspace/32.aon_timer_smoke/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all.3852203548
Short name T77
Test name
Test status
Simulation time 75629326673 ps
CPU time 28.82 seconds
Started Mar 03 12:33:21 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 195340 kb
Host smart-80ca797a-99ec-45d0-baa7-b7eb55c5ebad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852203548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_
all.3852203548
Directory /workspace/32.aon_timer_stress_all/latest

Test location /workspace/coverage/default/32.aon_timer_stress_all_with_rand_reset.3283415344
Short name T27
Test name
Test status
Simulation time 16757469097 ps
CPU time 176.38 seconds
Started Mar 03 12:33:14 PM PST 24
Finished Mar 03 12:36:11 PM PST 24
Peak memory 198752 kb
Host smart-8cbe9b17-85f5-4ced-84c5-68c4f933d2b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283415344 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.aon_timer_stress_all_with_rand_reset.3283415344
Directory /workspace/32.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.aon_timer_jump.2360203346
Short name T119
Test name
Test status
Simulation time 455554854 ps
CPU time 1.12 seconds
Started Mar 03 12:33:00 PM PST 24
Finished Mar 03 12:33:02 PM PST 24
Peak memory 183816 kb
Host smart-eac9f568-6bb4-47de-acda-bcfd34450670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360203346 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_jump.2360203346
Directory /workspace/33.aon_timer_jump/latest

Test location /workspace/coverage/default/33.aon_timer_prescaler.4141186983
Short name T127
Test name
Test status
Simulation time 8586270483 ps
CPU time 14.6 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 183872 kb
Host smart-4a56ba7d-7127-46e3-90f5-2020944a772a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141186983 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_prescaler.4141186983
Directory /workspace/33.aon_timer_prescaler/latest

Test location /workspace/coverage/default/33.aon_timer_smoke.2032436763
Short name T154
Test name
Test status
Simulation time 343052652 ps
CPU time 1.02 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:04 PM PST 24
Peak memory 183820 kb
Host smart-d8b909ca-8673-4fde-963a-c58edcf7fb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032436763 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_smoke.2032436763
Directory /workspace/33.aon_timer_smoke/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all.1385718240
Short name T116
Test name
Test status
Simulation time 291657064063 ps
CPU time 441.36 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 183800 kb
Host smart-a906d04d-0584-40b4-8adf-63054515d0c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385718240 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_
all.1385718240
Directory /workspace/33.aon_timer_stress_all/latest

Test location /workspace/coverage/default/33.aon_timer_stress_all_with_rand_reset.3689198741
Short name T73
Test name
Test status
Simulation time 68917265508 ps
CPU time 133.69 seconds
Started Mar 03 12:33:07 PM PST 24
Finished Mar 03 12:35:21 PM PST 24
Peak memory 198752 kb
Host smart-8bf0695e-c068-4da8-b132-49af3087100e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689198741 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.aon_timer_stress_all_with_rand_reset.3689198741
Directory /workspace/33.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.aon_timer_jump.1951977365
Short name T204
Test name
Test status
Simulation time 585041558 ps
CPU time 0.92 seconds
Started Mar 03 12:33:14 PM PST 24
Finished Mar 03 12:33:15 PM PST 24
Peak memory 183732 kb
Host smart-8c5f87cc-eb46-4461-b03e-1da127a0a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951977365 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_jump.1951977365
Directory /workspace/34.aon_timer_jump/latest

Test location /workspace/coverage/default/34.aon_timer_prescaler.1596478464
Short name T7
Test name
Test status
Simulation time 20943459283 ps
CPU time 29.67 seconds
Started Mar 03 12:33:33 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 183844 kb
Host smart-cb4eb846-9654-4186-9a21-4018ccf14236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596478464 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_prescaler.1596478464
Directory /workspace/34.aon_timer_prescaler/latest

Test location /workspace/coverage/default/34.aon_timer_smoke.2229524597
Short name T131
Test name
Test status
Simulation time 583817041 ps
CPU time 0.92 seconds
Started Mar 03 12:33:30 PM PST 24
Finished Mar 03 12:33:31 PM PST 24
Peak memory 183764 kb
Host smart-49cf40b0-ac3c-4982-bb4b-0edc3f55bb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229524597 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_smoke.2229524597
Directory /workspace/34.aon_timer_smoke/latest

Test location /workspace/coverage/default/34.aon_timer_stress_all.536368236
Short name T136
Test name
Test status
Simulation time 28813894675 ps
CPU time 23.89 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 195268 kb
Host smart-e17d4c62-9663-4b9d-b361-6d07c7c608bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536368236 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.aon_timer_stress_a
ll.536368236
Directory /workspace/34.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_jump.2040985973
Short name T151
Test name
Test status
Simulation time 613928908 ps
CPU time 1.33 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183824 kb
Host smart-568b95c7-d7d9-41b7-9563-f703117fb09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040985973 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_jump.2040985973
Directory /workspace/35.aon_timer_jump/latest

Test location /workspace/coverage/default/35.aon_timer_prescaler.3968326659
Short name T212
Test name
Test status
Simulation time 35736564042 ps
CPU time 4.31 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 183820 kb
Host smart-74c4275c-4cb9-4825-8288-536bab7a317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968326659 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_prescaler.3968326659
Directory /workspace/35.aon_timer_prescaler/latest

Test location /workspace/coverage/default/35.aon_timer_smoke.2947662935
Short name T253
Test name
Test status
Simulation time 588336275 ps
CPU time 0.98 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:17 PM PST 24
Peak memory 183764 kb
Host smart-92dc70ab-484b-4752-84fc-44ed0ede45e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947662935 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_smoke.2947662935
Directory /workspace/35.aon_timer_smoke/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all.539913254
Short name T185
Test name
Test status
Simulation time 272374540228 ps
CPU time 294.03 seconds
Started Mar 03 12:33:03 PM PST 24
Finished Mar 03 12:37:57 PM PST 24
Peak memory 194992 kb
Host smart-e1102328-da7c-4efd-a496-b7c4cabe1f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539913254 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_a
ll.539913254
Directory /workspace/35.aon_timer_stress_all/latest

Test location /workspace/coverage/default/35.aon_timer_stress_all_with_rand_reset.2561304785
Short name T33
Test name
Test status
Simulation time 147799190778 ps
CPU time 264.8 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:37:40 PM PST 24
Peak memory 198652 kb
Host smart-ecd0e1ac-bbb7-489e-98c5-e057e30bb093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561304785 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.aon_timer_stress_all_with_rand_reset.2561304785
Directory /workspace/35.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.aon_timer_jump.1464169232
Short name T199
Test name
Test status
Simulation time 388971405 ps
CPU time 0.84 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 184156 kb
Host smart-c51c25c6-e156-494a-a7d8-1c124ffce978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464169232 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_jump.1464169232
Directory /workspace/36.aon_timer_jump/latest

Test location /workspace/coverage/default/36.aon_timer_prescaler.3171432027
Short name T113
Test name
Test status
Simulation time 38258400909 ps
CPU time 15.93 seconds
Started Mar 03 12:33:27 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 183824 kb
Host smart-44ffaf99-bebe-4e56-9082-d23112e8f307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171432027 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_prescaler.3171432027
Directory /workspace/36.aon_timer_prescaler/latest

Test location /workspace/coverage/default/36.aon_timer_smoke.179131798
Short name T172
Test name
Test status
Simulation time 515173796 ps
CPU time 0.91 seconds
Started Mar 03 12:33:13 PM PST 24
Finished Mar 03 12:33:14 PM PST 24
Peak memory 183764 kb
Host smart-b228feb4-8a19-459e-96f9-8aeacedc50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179131798 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_smoke.179131798
Directory /workspace/36.aon_timer_smoke/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all.28755777
Short name T6
Test name
Test status
Simulation time 298561931124 ps
CPU time 117.51 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 183880 kb
Host smart-43b0ca5c-77d7-4b45-937b-97ce89afc688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755777 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_al
l.28755777
Directory /workspace/36.aon_timer_stress_all/latest

Test location /workspace/coverage/default/36.aon_timer_stress_all_with_rand_reset.654374784
Short name T144
Test name
Test status
Simulation time 188582118337 ps
CPU time 197.02 seconds
Started Mar 03 12:33:10 PM PST 24
Finished Mar 03 12:36:28 PM PST 24
Peak memory 198756 kb
Host smart-0495f627-b65c-47b8-b008-d9b412a378b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654374784 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.aon_timer_stress_all_with_rand_reset.654374784
Directory /workspace/36.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.aon_timer_jump.3987741129
Short name T247
Test name
Test status
Simulation time 499800927 ps
CPU time 1.21 seconds
Started Mar 03 12:33:27 PM PST 24
Finished Mar 03 12:33:29 PM PST 24
Peak memory 183816 kb
Host smart-69be4729-5e14-4dec-ba3c-0157a5e3a631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987741129 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_jump.3987741129
Directory /workspace/37.aon_timer_jump/latest

Test location /workspace/coverage/default/37.aon_timer_prescaler.2795113757
Short name T145
Test name
Test status
Simulation time 9085757126 ps
CPU time 6.92 seconds
Started Mar 03 12:33:06 PM PST 24
Finished Mar 03 12:33:13 PM PST 24
Peak memory 183784 kb
Host smart-ae68ecc1-cce7-42cb-85d6-a77bf4a6fa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795113757 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_prescaler.2795113757
Directory /workspace/37.aon_timer_prescaler/latest

Test location /workspace/coverage/default/37.aon_timer_smoke.4289340768
Short name T232
Test name
Test status
Simulation time 504281094 ps
CPU time 0.68 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183864 kb
Host smart-f6668575-b657-423b-8fa4-0dff83f5ed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289340768 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_smoke.4289340768
Directory /workspace/37.aon_timer_smoke/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all.3096713187
Short name T190
Test name
Test status
Simulation time 175351523160 ps
CPU time 39.68 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:57 PM PST 24
Peak memory 183876 kb
Host smart-7451a921-463c-444a-980a-cf978f9bf32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096713187 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_
all.3096713187
Directory /workspace/37.aon_timer_stress_all/latest

Test location /workspace/coverage/default/37.aon_timer_stress_all_with_rand_reset.3227806367
Short name T69
Test name
Test status
Simulation time 44219611031 ps
CPU time 437.94 seconds
Started Mar 03 12:33:20 PM PST 24
Finished Mar 03 12:40:38 PM PST 24
Peak memory 198740 kb
Host smart-8dbb6122-a334-4a12-9985-a314c8cdfce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227806367 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.aon_timer_stress_all_with_rand_reset.3227806367
Directory /workspace/37.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.aon_timer_jump.907213296
Short name T91
Test name
Test status
Simulation time 591430099 ps
CPU time 0.74 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:17 PM PST 24
Peak memory 183792 kb
Host smart-7f7d49bb-0647-4dc8-8e05-339462913ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907213296 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_jump.907213296
Directory /workspace/38.aon_timer_jump/latest

Test location /workspace/coverage/default/38.aon_timer_prescaler.302113523
Short name T114
Test name
Test status
Simulation time 22143791070 ps
CPU time 7.82 seconds
Started Mar 03 12:33:06 PM PST 24
Finished Mar 03 12:33:14 PM PST 24
Peak memory 183872 kb
Host smart-f4e82909-c784-4e7d-954a-61da7bb07b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302113523 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_prescaler.302113523
Directory /workspace/38.aon_timer_prescaler/latest

Test location /workspace/coverage/default/38.aon_timer_smoke.3163909760
Short name T92
Test name
Test status
Simulation time 345859385 ps
CPU time 0.96 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:26 PM PST 24
Peak memory 183740 kb
Host smart-9feb4c14-10f3-469e-8ae2-9aeb031525a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163909760 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_smoke.3163909760
Directory /workspace/38.aon_timer_smoke/latest

Test location /workspace/coverage/default/38.aon_timer_stress_all.3700081924
Short name T160
Test name
Test status
Simulation time 90277908186 ps
CPU time 32.63 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:49 PM PST 24
Peak memory 195512 kb
Host smart-c4419fc9-8cab-4526-a3d5-1cef9d63975a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700081924 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.aon_timer_stress_
all.3700081924
Directory /workspace/38.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_jump.3373554179
Short name T120
Test name
Test status
Simulation time 468200493 ps
CPU time 0.63 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:24 PM PST 24
Peak memory 183796 kb
Host smart-ae91aed2-09ad-456d-871b-5fd12d86d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373554179 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_jump.3373554179
Directory /workspace/39.aon_timer_jump/latest

Test location /workspace/coverage/default/39.aon_timer_prescaler.1264002706
Short name T203
Test name
Test status
Simulation time 54669681818 ps
CPU time 42.55 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:34:02 PM PST 24
Peak memory 183848 kb
Host smart-575427e2-ed64-4da7-9ab9-f37c23d91763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264002706 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_prescaler.1264002706
Directory /workspace/39.aon_timer_prescaler/latest

Test location /workspace/coverage/default/39.aon_timer_smoke.3599777088
Short name T99
Test name
Test status
Simulation time 484208532 ps
CPU time 0.64 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183752 kb
Host smart-af5fed90-d264-472a-b2e5-e13c661d7ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599777088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_smoke.3599777088
Directory /workspace/39.aon_timer_smoke/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all.683720881
Short name T103
Test name
Test status
Simulation time 133612029861 ps
CPU time 13.89 seconds
Started Mar 03 12:33:19 PM PST 24
Finished Mar 03 12:33:33 PM PST 24
Peak memory 183852 kb
Host smart-1f53e62d-74d5-400a-9fc3-061c4cc8f721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683720881 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_a
ll.683720881
Directory /workspace/39.aon_timer_stress_all/latest

Test location /workspace/coverage/default/39.aon_timer_stress_all_with_rand_reset.1749216920
Short name T68
Test name
Test status
Simulation time 286287229022 ps
CPU time 639.48 seconds
Started Mar 03 12:33:23 PM PST 24
Finished Mar 03 12:44:03 PM PST 24
Peak memory 199912 kb
Host smart-163d4410-4bea-4072-8053-e8e1b83b9c38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749216920 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 39.aon_timer_stress_all_with_rand_reset.1749216920
Directory /workspace/39.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.aon_timer_jump.1523938077
Short name T227
Test name
Test status
Simulation time 462255285 ps
CPU time 1.23 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 183796 kb
Host smart-3bde13c3-0893-4d3a-8abb-033d953cf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523938077 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_jump.1523938077
Directory /workspace/4.aon_timer_jump/latest

Test location /workspace/coverage/default/4.aon_timer_prescaler.3657792684
Short name T234
Test name
Test status
Simulation time 37931078815 ps
CPU time 14.62 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 183868 kb
Host smart-b6d98fea-e54f-413d-9299-dd9185cf72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657792684 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_prescaler.3657792684
Directory /workspace/4.aon_timer_prescaler/latest

Test location /workspace/coverage/default/4.aon_timer_sec_cm.1564556669
Short name T21
Test name
Test status
Simulation time 4294978803 ps
CPU time 2.22 seconds
Started Mar 03 12:32:45 PM PST 24
Finished Mar 03 12:32:47 PM PST 24
Peak memory 215572 kb
Host smart-f37b4f71-7fd0-49bc-b99f-de736f23e9b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564556669 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_sec_cm.1564556669
Directory /workspace/4.aon_timer_sec_cm/latest

Test location /workspace/coverage/default/4.aon_timer_smoke.816394522
Short name T44
Test name
Test status
Simulation time 549962532 ps
CPU time 0.91 seconds
Started Mar 03 12:32:26 PM PST 24
Finished Mar 03 12:32:27 PM PST 24
Peak memory 183800 kb
Host smart-25cdfa30-83ba-4b6f-bb4f-014c1978ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816394522 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_smoke.816394522
Directory /workspace/4.aon_timer_smoke/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all.2342685688
Short name T37
Test name
Test status
Simulation time 44228016097 ps
CPU time 70.96 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 194284 kb
Host smart-7fa282cd-e301-46e5-92cb-1ccd90367a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342685688 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_a
ll.2342685688
Directory /workspace/4.aon_timer_stress_all/latest

Test location /workspace/coverage/default/4.aon_timer_stress_all_with_rand_reset.149950137
Short name T188
Test name
Test status
Simulation time 445617965393 ps
CPU time 267 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:37:18 PM PST 24
Peak memory 198636 kb
Host smart-168239b5-249b-493d-9c04-2c9b667aad79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149950137 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.aon_timer_stress_all_with_rand_reset.149950137
Directory /workspace/4.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.aon_timer_jump.3868781044
Short name T197
Test name
Test status
Simulation time 443858668 ps
CPU time 1 seconds
Started Mar 03 12:33:13 PM PST 24
Finished Mar 03 12:33:15 PM PST 24
Peak memory 183824 kb
Host smart-c069b6a1-165d-4376-95c7-b5b443668424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868781044 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_jump.3868781044
Directory /workspace/40.aon_timer_jump/latest

Test location /workspace/coverage/default/40.aon_timer_prescaler.1038120773
Short name T222
Test name
Test status
Simulation time 11118133332 ps
CPU time 8.86 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:24 PM PST 24
Peak memory 183820 kb
Host smart-394f711a-ebd1-43f3-ac58-a3f6e30f10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038120773 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_prescaler.1038120773
Directory /workspace/40.aon_timer_prescaler/latest

Test location /workspace/coverage/default/40.aon_timer_smoke.3690028510
Short name T274
Test name
Test status
Simulation time 355173921 ps
CPU time 1.12 seconds
Started Mar 03 12:33:13 PM PST 24
Finished Mar 03 12:33:15 PM PST 24
Peak memory 183756 kb
Host smart-cb5ee078-f6cb-48a5-8fbe-0d3a2027a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690028510 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_smoke.3690028510
Directory /workspace/40.aon_timer_smoke/latest

Test location /workspace/coverage/default/40.aon_timer_stress_all.2850738012
Short name T169
Test name
Test status
Simulation time 209205583382 ps
CPU time 143.13 seconds
Started Mar 03 12:33:32 PM PST 24
Finished Mar 03 12:35:55 PM PST 24
Peak memory 184232 kb
Host smart-47c9fb5f-372a-44fa-811c-f0d19da74243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850738012 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.aon_timer_stress_
all.2850738012
Directory /workspace/40.aon_timer_stress_all/latest

Test location /workspace/coverage/default/41.aon_timer_jump.3155649702
Short name T228
Test name
Test status
Simulation time 499206915 ps
CPU time 0.72 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183708 kb
Host smart-65e15ea6-9ee5-4766-9720-44e78bd96ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155649702 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_jump.3155649702
Directory /workspace/41.aon_timer_jump/latest

Test location /workspace/coverage/default/41.aon_timer_prescaler.3711685385
Short name T155
Test name
Test status
Simulation time 2898983914 ps
CPU time 4.33 seconds
Started Mar 03 12:33:18 PM PST 24
Finished Mar 03 12:33:22 PM PST 24
Peak memory 183872 kb
Host smart-9d5eb902-7645-44ff-806f-6aa738da197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711685385 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_prescaler.3711685385
Directory /workspace/41.aon_timer_prescaler/latest

Test location /workspace/coverage/default/41.aon_timer_smoke.2135372686
Short name T112
Test name
Test status
Simulation time 505388807 ps
CPU time 1.24 seconds
Started Mar 03 12:33:18 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 183816 kb
Host smart-d06400e4-492e-441e-b374-2ed37f0fce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135372686 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_smoke.2135372686
Directory /workspace/41.aon_timer_smoke/latest

Test location /workspace/coverage/default/41.aon_timer_stress_all.659493661
Short name T209
Test name
Test status
Simulation time 214819178080 ps
CPU time 36.55 seconds
Started Mar 03 12:33:38 PM PST 24
Finished Mar 03 12:34:16 PM PST 24
Peak memory 195656 kb
Host smart-fc8d1e04-488c-4898-8d43-71a81d934a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659493661 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.aon_timer_stress_a
ll.659493661
Directory /workspace/41.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_jump.2635343581
Short name T263
Test name
Test status
Simulation time 451491470 ps
CPU time 0.71 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 183772 kb
Host smart-bda9ac28-6c26-44d1-94d5-2ed4f2857439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635343581 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_jump.2635343581
Directory /workspace/42.aon_timer_jump/latest

Test location /workspace/coverage/default/42.aon_timer_prescaler.498546712
Short name T101
Test name
Test status
Simulation time 32649948808 ps
CPU time 47.8 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 183872 kb
Host smart-3ea5e5fe-d8e7-432e-9da4-ff81641822a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498546712 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_prescaler.498546712
Directory /workspace/42.aon_timer_prescaler/latest

Test location /workspace/coverage/default/42.aon_timer_smoke.456935471
Short name T134
Test name
Test status
Simulation time 543753966 ps
CPU time 1.35 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 183820 kb
Host smart-bf872e2c-1834-414c-82d4-020dfe508563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456935471 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_smoke.456935471
Directory /workspace/42.aon_timer_smoke/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all.3982257188
Short name T165
Test name
Test status
Simulation time 259885100653 ps
CPU time 87.53 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:35:17 PM PST 24
Peak memory 183876 kb
Host smart-bf0cbf28-3438-4b43-bbdd-31142b6bda4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982257188 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_
all.3982257188
Directory /workspace/42.aon_timer_stress_all/latest

Test location /workspace/coverage/default/42.aon_timer_stress_all_with_rand_reset.276878531
Short name T217
Test name
Test status
Simulation time 27098907460 ps
CPU time 290.68 seconds
Started Mar 03 12:33:36 PM PST 24
Finished Mar 03 12:38:27 PM PST 24
Peak memory 198752 kb
Host smart-cba83910-09a9-4b30-aa3b-de7969324de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276878531 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.aon_timer_stress_all_with_rand_reset.276878531
Directory /workspace/42.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.aon_timer_jump.2529135074
Short name T173
Test name
Test status
Simulation time 696899805 ps
CPU time 0.56 seconds
Started Mar 03 12:33:08 PM PST 24
Finished Mar 03 12:33:09 PM PST 24
Peak memory 183824 kb
Host smart-308a3975-d12c-494b-bbc9-9b3e05aacada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529135074 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_jump.2529135074
Directory /workspace/43.aon_timer_jump/latest

Test location /workspace/coverage/default/43.aon_timer_prescaler.776143866
Short name T196
Test name
Test status
Simulation time 29808735960 ps
CPU time 15.53 seconds
Started Mar 03 12:33:33 PM PST 24
Finished Mar 03 12:33:48 PM PST 24
Peak memory 183740 kb
Host smart-e43785a6-5f97-4b63-b8d1-90fcb52a95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776143866 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_prescaler.776143866
Directory /workspace/43.aon_timer_prescaler/latest

Test location /workspace/coverage/default/43.aon_timer_smoke.578323189
Short name T110
Test name
Test status
Simulation time 545372212 ps
CPU time 0.96 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 183760 kb
Host smart-ee4a57f2-f96e-4889-a634-11be145872ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578323189 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_smoke.578323189
Directory /workspace/43.aon_timer_smoke/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all.1556876495
Short name T78
Test name
Test status
Simulation time 244162819367 ps
CPU time 126.78 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:35:35 PM PST 24
Peak memory 183872 kb
Host smart-e01cef32-772b-4997-bcdd-c2a7f0053b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556876495 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_
all.1556876495
Directory /workspace/43.aon_timer_stress_all/latest

Test location /workspace/coverage/default/43.aon_timer_stress_all_with_rand_reset.2183706046
Short name T141
Test name
Test status
Simulation time 79302544478 ps
CPU time 159.42 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:35:57 PM PST 24
Peak memory 198748 kb
Host smart-ec3b1f4d-45a4-4a4a-9cc7-b6b48d947df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183706046 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.aon_timer_stress_all_with_rand_reset.2183706046
Directory /workspace/43.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.aon_timer_jump.1840940162
Short name T40
Test name
Test status
Simulation time 476701619 ps
CPU time 0.64 seconds
Started Mar 03 12:33:33 PM PST 24
Finished Mar 03 12:33:34 PM PST 24
Peak memory 183816 kb
Host smart-0ac768e5-8db6-4975-8ff1-4f01e00aff00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840940162 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_jump.1840940162
Directory /workspace/44.aon_timer_jump/latest

Test location /workspace/coverage/default/44.aon_timer_prescaler.1714685292
Short name T159
Test name
Test status
Simulation time 41072409524 ps
CPU time 17.96 seconds
Started Mar 03 12:33:08 PM PST 24
Finished Mar 03 12:33:26 PM PST 24
Peak memory 183940 kb
Host smart-d6758b02-a973-4ad1-a630-7836d35a8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714685292 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_prescaler.1714685292
Directory /workspace/44.aon_timer_prescaler/latest

Test location /workspace/coverage/default/44.aon_timer_smoke.1794107962
Short name T256
Test name
Test status
Simulation time 617088382 ps
CPU time 0.6 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:03 PM PST 24
Peak memory 183816 kb
Host smart-900d9117-7025-4455-8828-c42a89e976e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794107962 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_smoke.1794107962
Directory /workspace/44.aon_timer_smoke/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all.1827372445
Short name T195
Test name
Test status
Simulation time 140246733388 ps
CPU time 220.83 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:37:03 PM PST 24
Peak memory 183868 kb
Host smart-8d53cb8c-d5af-47dc-beab-0193947c1eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827372445 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_
all.1827372445
Directory /workspace/44.aon_timer_stress_all/latest

Test location /workspace/coverage/default/44.aon_timer_stress_all_with_rand_reset.784310341
Short name T187
Test name
Test status
Simulation time 36618581095 ps
CPU time 147.15 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:35:44 PM PST 24
Peak memory 198692 kb
Host smart-8d1736d4-2323-4da6-8363-0b53aaa0cfd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784310341 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.aon_timer_stress_all_with_rand_reset.784310341
Directory /workspace/44.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.aon_timer_jump.1796940977
Short name T249
Test name
Test status
Simulation time 482868341 ps
CPU time 0.83 seconds
Started Mar 03 12:33:18 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 184120 kb
Host smart-7902c061-26ff-430d-b016-cf6a73984b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796940977 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_jump.1796940977
Directory /workspace/45.aon_timer_jump/latest

Test location /workspace/coverage/default/45.aon_timer_prescaler.190694932
Short name T236
Test name
Test status
Simulation time 26839726958 ps
CPU time 3.26 seconds
Started Mar 03 12:33:36 PM PST 24
Finished Mar 03 12:33:41 PM PST 24
Peak memory 183800 kb
Host smart-5d069b98-2752-4489-be4e-40f2ff03e45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190694932 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_prescaler.190694932
Directory /workspace/45.aon_timer_prescaler/latest

Test location /workspace/coverage/default/45.aon_timer_smoke.2368700122
Short name T138
Test name
Test status
Simulation time 349822572 ps
CPU time 0.64 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:16 PM PST 24
Peak memory 183820 kb
Host smart-25e446c7-f473-4541-a267-82724ce1f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368700122 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_smoke.2368700122
Directory /workspace/45.aon_timer_smoke/latest

Test location /workspace/coverage/default/45.aon_timer_stress_all_with_rand_reset.524464321
Short name T65
Test name
Test status
Simulation time 730960250265 ps
CPU time 410.76 seconds
Started Mar 03 12:33:41 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 198652 kb
Host smart-1fad3375-3cea-4701-9ffe-41ff51c96b28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524464321 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.aon_timer_stress_all_with_rand_reset.524464321
Directory /workspace/45.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.aon_timer_jump.1307527146
Short name T95
Test name
Test status
Simulation time 504367601 ps
CPU time 0.78 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:33:30 PM PST 24
Peak memory 183824 kb
Host smart-3fb75744-543c-4725-bb04-e69668792c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307527146 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_jump.1307527146
Directory /workspace/46.aon_timer_jump/latest

Test location /workspace/coverage/default/46.aon_timer_prescaler.2751554548
Short name T5
Test name
Test status
Simulation time 37004283025 ps
CPU time 58.34 seconds
Started Mar 03 12:33:41 PM PST 24
Finished Mar 03 12:34:39 PM PST 24
Peak memory 183784 kb
Host smart-9bccc323-a99a-459e-87ed-4842f43993e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751554548 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_prescaler.2751554548
Directory /workspace/46.aon_timer_prescaler/latest

Test location /workspace/coverage/default/46.aon_timer_smoke.4033352088
Short name T43
Test name
Test status
Simulation time 402089524 ps
CPU time 1.12 seconds
Started Mar 03 12:33:28 PM PST 24
Finished Mar 03 12:33:29 PM PST 24
Peak memory 183816 kb
Host smart-40f3bee6-e5d9-4735-97d6-d9c9e9ec679b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033352088 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_smoke.4033352088
Directory /workspace/46.aon_timer_smoke/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all.739506309
Short name T273
Test name
Test status
Simulation time 20148996166 ps
CPU time 17.65 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:39 PM PST 24
Peak memory 183784 kb
Host smart-eac601ef-c6c8-48d0-85db-b67098e3c70d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739506309 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_a
ll.739506309
Directory /workspace/46.aon_timer_stress_all/latest

Test location /workspace/coverage/default/46.aon_timer_stress_all_with_rand_reset.3229627633
Short name T230
Test name
Test status
Simulation time 190636970152 ps
CPU time 361.91 seconds
Started Mar 03 12:33:24 PM PST 24
Finished Mar 03 12:39:27 PM PST 24
Peak memory 198696 kb
Host smart-7a42c2b1-a473-43b8-97ae-8cea19da4f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229627633 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 46.aon_timer_stress_all_with_rand_reset.3229627633
Directory /workspace/46.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.aon_timer_jump.3277900648
Short name T121
Test name
Test status
Simulation time 411323153 ps
CPU time 1.16 seconds
Started Mar 03 12:33:34 PM PST 24
Finished Mar 03 12:33:35 PM PST 24
Peak memory 183824 kb
Host smart-96ff4aec-23d0-4de7-9659-ee43bc347b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277900648 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_jump.3277900648
Directory /workspace/47.aon_timer_jump/latest

Test location /workspace/coverage/default/47.aon_timer_prescaler.2136638079
Short name T225
Test name
Test status
Simulation time 30466223048 ps
CPU time 10.85 seconds
Started Mar 03 12:33:11 PM PST 24
Finished Mar 03 12:33:22 PM PST 24
Peak memory 183832 kb
Host smart-c9158af4-f763-4af7-8e38-c07c9c7aa73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136638079 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_prescaler.2136638079
Directory /workspace/47.aon_timer_prescaler/latest

Test location /workspace/coverage/default/47.aon_timer_smoke.3263431678
Short name T85
Test name
Test status
Simulation time 596670137 ps
CPU time 0.7 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:17 PM PST 24
Peak memory 183820 kb
Host smart-0799e536-363b-4161-9c8a-2d5975ca333c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263431678 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_smoke.3263431678
Directory /workspace/47.aon_timer_smoke/latest

Test location /workspace/coverage/default/47.aon_timer_stress_all.2362105830
Short name T180
Test name
Test status
Simulation time 95854911887 ps
CPU time 144.24 seconds
Started Mar 03 12:33:33 PM PST 24
Finished Mar 03 12:35:58 PM PST 24
Peak memory 183824 kb
Host smart-ff845729-e93a-4cf8-9070-2de935ac594d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362105830 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.aon_timer_stress_
all.2362105830
Directory /workspace/47.aon_timer_stress_all/latest

Test location /workspace/coverage/default/48.aon_timer_jump.2971732582
Short name T90
Test name
Test status
Simulation time 589523293 ps
CPU time 0.68 seconds
Started Mar 03 12:33:32 PM PST 24
Finished Mar 03 12:33:32 PM PST 24
Peak memory 183772 kb
Host smart-fadf9e59-7678-409f-aa35-3b0338a3531a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971732582 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_jump.2971732582
Directory /workspace/48.aon_timer_jump/latest

Test location /workspace/coverage/default/48.aon_timer_prescaler.1466874834
Short name T118
Test name
Test status
Simulation time 12202823494 ps
CPU time 17.75 seconds
Started Mar 03 12:33:06 PM PST 24
Finished Mar 03 12:33:24 PM PST 24
Peak memory 183848 kb
Host smart-855533e5-a13f-4a9f-9d1e-953e23ac4360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466874834 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_prescaler.1466874834
Directory /workspace/48.aon_timer_prescaler/latest

Test location /workspace/coverage/default/48.aon_timer_smoke.1890732402
Short name T10
Test name
Test status
Simulation time 406156506 ps
CPU time 1.17 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:19 PM PST 24
Peak memory 183768 kb
Host smart-5a73047b-f971-47fa-bfb5-81a65d08b456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890732402 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_smoke.1890732402
Directory /workspace/48.aon_timer_smoke/latest

Test location /workspace/coverage/default/48.aon_timer_stress_all.83091787
Short name T264
Test name
Test status
Simulation time 72177516709 ps
CPU time 24.68 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:40 PM PST 24
Peak memory 183828 kb
Host smart-2bbd875b-c143-43d2-8726-a2d269a041f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83091787 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.aon_timer_stress_al
l.83091787
Directory /workspace/48.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_jump.2769856728
Short name T125
Test name
Test status
Simulation time 515248983 ps
CPU time 1.26 seconds
Started Mar 03 12:33:17 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 183896 kb
Host smart-6cecf3be-867b-47d1-94c9-bd90768384a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769856728 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_jump.2769856728
Directory /workspace/49.aon_timer_jump/latest

Test location /workspace/coverage/default/49.aon_timer_prescaler.3514553308
Short name T183
Test name
Test status
Simulation time 21215247211 ps
CPU time 4.44 seconds
Started Mar 03 12:33:16 PM PST 24
Finished Mar 03 12:33:20 PM PST 24
Peak memory 183820 kb
Host smart-d00a7b91-d40a-4a7f-b3b6-5f6c7385811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514553308 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_prescaler.3514553308
Directory /workspace/49.aon_timer_prescaler/latest

Test location /workspace/coverage/default/49.aon_timer_smoke.1408404485
Short name T214
Test name
Test status
Simulation time 550184212 ps
CPU time 1.45 seconds
Started Mar 03 12:33:15 PM PST 24
Finished Mar 03 12:33:17 PM PST 24
Peak memory 183780 kb
Host smart-5a798424-0c6c-4ce8-8e08-04fa06f97dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408404485 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_smoke.1408404485
Directory /workspace/49.aon_timer_smoke/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all.3342828647
Short name T157
Test name
Test status
Simulation time 148454482098 ps
CPU time 17.51 seconds
Started Mar 03 12:33:49 PM PST 24
Finished Mar 03 12:34:07 PM PST 24
Peak memory 195400 kb
Host smart-61c6ad30-b4d5-488f-9afc-41603c364938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342828647 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_
all.3342828647
Directory /workspace/49.aon_timer_stress_all/latest

Test location /workspace/coverage/default/49.aon_timer_stress_all_with_rand_reset.1263015799
Short name T219
Test name
Test status
Simulation time 33402346089 ps
CPU time 250.64 seconds
Started Mar 03 12:33:13 PM PST 24
Finished Mar 03 12:37:24 PM PST 24
Peak memory 198700 kb
Host smart-80fae3c8-d406-4672-8623-5421db3602fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263015799 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.aon_timer_stress_all_with_rand_reset.1263015799
Directory /workspace/49.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.aon_timer_jump.70047792
Short name T122
Test name
Test status
Simulation time 488488407 ps
CPU time 1.4 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:33:03 PM PST 24
Peak memory 183784 kb
Host smart-4b4d084e-e641-4fed-b277-2d729b64b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70047792 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_jump.70047792
Directory /workspace/5.aon_timer_jump/latest

Test location /workspace/coverage/default/5.aon_timer_prescaler.2253124097
Short name T269
Test name
Test status
Simulation time 11007784863 ps
CPU time 16.84 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:44 PM PST 24
Peak memory 183856 kb
Host smart-8360faf0-af78-4ed2-ba6a-487960d3394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253124097 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_prescaler.2253124097
Directory /workspace/5.aon_timer_prescaler/latest

Test location /workspace/coverage/default/5.aon_timer_smoke.2062448694
Short name T198
Test name
Test status
Simulation time 455282310 ps
CPU time 0.67 seconds
Started Mar 03 12:32:50 PM PST 24
Finished Mar 03 12:32:51 PM PST 24
Peak memory 183884 kb
Host smart-447373cc-4a0e-443e-b6b9-0b735bbbe2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062448694 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_smoke.2062448694
Directory /workspace/5.aon_timer_smoke/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all.3793070762
Short name T123
Test name
Test status
Simulation time 32532487070 ps
CPU time 39.39 seconds
Started Mar 03 12:33:11 PM PST 24
Finished Mar 03 12:33:50 PM PST 24
Peak memory 193728 kb
Host smart-568789e6-959b-41a1-a163-8a44da3851f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793070762 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_a
ll.3793070762
Directory /workspace/5.aon_timer_stress_all/latest

Test location /workspace/coverage/default/5.aon_timer_stress_all_with_rand_reset.3809306803
Short name T66
Test name
Test status
Simulation time 199219865917 ps
CPU time 1041.56 seconds
Started Mar 03 12:32:47 PM PST 24
Finished Mar 03 12:50:09 PM PST 24
Peak memory 205616 kb
Host smart-79ba53dc-1105-44a8-9eac-cc1bf0b735e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809306803 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.aon_timer_stress_all_with_rand_reset.3809306803
Directory /workspace/5.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.aon_timer_jump.1746407393
Short name T255
Test name
Test status
Simulation time 572621599 ps
CPU time 0.75 seconds
Started Mar 03 12:32:23 PM PST 24
Finished Mar 03 12:32:24 PM PST 24
Peak memory 183812 kb
Host smart-78f5b55d-c4b6-4eea-afa2-db0de289b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746407393 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_jump.1746407393
Directory /workspace/6.aon_timer_jump/latest

Test location /workspace/coverage/default/6.aon_timer_prescaler.3027542624
Short name T130
Test name
Test status
Simulation time 5569654533 ps
CPU time 1.43 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:31 PM PST 24
Peak memory 183852 kb
Host smart-d4f03253-22b4-4ba9-9116-e1ad54223913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027542624 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_prescaler.3027542624
Directory /workspace/6.aon_timer_prescaler/latest

Test location /workspace/coverage/default/6.aon_timer_smoke.2466686658
Short name T106
Test name
Test status
Simulation time 390259968 ps
CPU time 0.69 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183756 kb
Host smart-2c2cd5da-aabc-4cbd-ad7f-d24969850614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466686658 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_smoke.2466686658
Directory /workspace/6.aon_timer_smoke/latest

Test location /workspace/coverage/default/6.aon_timer_stress_all.1714220241
Short name T109
Test name
Test status
Simulation time 183475378269 ps
CPU time 257.77 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:36:49 PM PST 24
Peak memory 183824 kb
Host smart-30c7d0a4-5304-4749-8750-f97ecbf6bfc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714220241 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.aon_timer_stress_a
ll.1714220241
Directory /workspace/6.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_jump.3785797333
Short name T261
Test name
Test status
Simulation time 552243190 ps
CPU time 0.72 seconds
Started Mar 03 12:32:52 PM PST 24
Finished Mar 03 12:32:53 PM PST 24
Peak memory 184152 kb
Host smart-0adc888c-ccfd-4fe8-b100-fbcb3c038e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785797333 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_jump.3785797333
Directory /workspace/7.aon_timer_jump/latest

Test location /workspace/coverage/default/7.aon_timer_prescaler.3577934736
Short name T226
Test name
Test status
Simulation time 32447982204 ps
CPU time 27.81 seconds
Started Mar 03 12:32:27 PM PST 24
Finished Mar 03 12:32:55 PM PST 24
Peak memory 183812 kb
Host smart-133d1c33-4887-4b1e-90dd-cec400756f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577934736 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_prescaler.3577934736
Directory /workspace/7.aon_timer_prescaler/latest

Test location /workspace/coverage/default/7.aon_timer_smoke.2937939958
Short name T207
Test name
Test status
Simulation time 415938611 ps
CPU time 0.82 seconds
Started Mar 03 12:32:25 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 183800 kb
Host smart-c85feddd-41db-43ea-a882-7d9553ed1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937939958 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_smoke.2937939958
Directory /workspace/7.aon_timer_smoke/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all.3906025639
Short name T176
Test name
Test status
Simulation time 150841924087 ps
CPU time 45.75 seconds
Started Mar 03 12:32:58 PM PST 24
Finished Mar 03 12:33:43 PM PST 24
Peak memory 194364 kb
Host smart-c99a72e5-0fd7-491b-ba09-3252e972ce56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906025639 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_a
ll.3906025639
Directory /workspace/7.aon_timer_stress_all/latest

Test location /workspace/coverage/default/7.aon_timer_stress_all_with_rand_reset.476069732
Short name T72
Test name
Test status
Simulation time 463842106313 ps
CPU time 899.26 seconds
Started Mar 03 12:32:32 PM PST 24
Finished Mar 03 12:47:31 PM PST 24
Peak memory 203116 kb
Host smart-47c3f00d-cd8a-468d-8dd9-4e8eab217b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476069732 -assert nop
ostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.aon_timer_stress_all_with_rand_reset.476069732
Directory /workspace/7.aon_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.aon_timer_jump.2791778412
Short name T94
Test name
Test status
Simulation time 658312749 ps
CPU time 0.71 seconds
Started Mar 03 12:32:31 PM PST 24
Finished Mar 03 12:32:32 PM PST 24
Peak memory 183760 kb
Host smart-d1ecab6d-1565-4466-83f0-7d4724b3d1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791778412 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_jump.2791778412
Directory /workspace/8.aon_timer_jump/latest

Test location /workspace/coverage/default/8.aon_timer_prescaler.47411212
Short name T87
Test name
Test status
Simulation time 23538378803 ps
CPU time 7.82 seconds
Started Mar 03 12:32:56 PM PST 24
Finished Mar 03 12:33:04 PM PST 24
Peak memory 184232 kb
Host smart-5cc11945-b020-42e3-8ef3-1428dc91c97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47411212 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_prescaler.47411212
Directory /workspace/8.aon_timer_prescaler/latest

Test location /workspace/coverage/default/8.aon_timer_smoke.1670312379
Short name T193
Test name
Test status
Simulation time 547846881 ps
CPU time 1.23 seconds
Started Mar 03 12:32:55 PM PST 24
Finished Mar 03 12:32:57 PM PST 24
Peak memory 183808 kb
Host smart-f4333b2c-3b5a-4062-a66d-795bb0c977f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670312379 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_smoke.1670312379
Directory /workspace/8.aon_timer_smoke/latest

Test location /workspace/coverage/default/8.aon_timer_stress_all.1289204312
Short name T241
Test name
Test status
Simulation time 111122422348 ps
CPU time 169.19 seconds
Started Mar 03 12:32:35 PM PST 24
Finished Mar 03 12:35:24 PM PST 24
Peak memory 194052 kb
Host smart-5b56aaca-6737-41b3-b649-71a5d5de9e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289204312 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.aon_timer_stress_a
ll.1289204312
Directory /workspace/8.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_jump.2757013563
Short name T167
Test name
Test status
Simulation time 518667336 ps
CPU time 0.97 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:32:52 PM PST 24
Peak memory 183812 kb
Host smart-0b256a07-0534-4a88-aef4-df716584c219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757013563 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_jump_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_jump.2757013563
Directory /workspace/9.aon_timer_jump/latest

Test location /workspace/coverage/default/9.aon_timer_prescaler.326156749
Short name T89
Test name
Test status
Simulation time 29101463344 ps
CPU time 43.99 seconds
Started Mar 03 12:32:51 PM PST 24
Finished Mar 03 12:33:35 PM PST 24
Peak memory 183880 kb
Host smart-3ad835cd-1cda-4679-b0a3-a2b96066c205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326156749 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_prescaler_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_prescaler.326156749
Directory /workspace/9.aon_timer_prescaler/latest

Test location /workspace/coverage/default/9.aon_timer_smoke.3368101841
Short name T147
Test name
Test status
Simulation time 606889791 ps
CPU time 0.76 seconds
Started Mar 03 12:32:36 PM PST 24
Finished Mar 03 12:32:42 PM PST 24
Peak memory 183708 kb
Host smart-06176986-f4cf-4abd-a021-79a269f31660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368101841 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_smoke.3368101841
Directory /workspace/9.aon_timer_smoke/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all.1674720541
Short name T216
Test name
Test status
Simulation time 149520121138 ps
CPU time 218.36 seconds
Started Mar 03 12:32:59 PM PST 24
Finished Mar 03 12:36:37 PM PST 24
Peak memory 195072 kb
Host smart-1efa4b64-2e4b-42c6-bb5d-b3c65224108f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674720541 -assert nopostproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_a
ll.1674720541
Directory /workspace/9.aon_timer_stress_all/latest

Test location /workspace/coverage/default/9.aon_timer_stress_all_with_rand_reset.2783789285
Short name T182
Test name
Test status
Simulation time 77265141056 ps
CPU time 210.14 seconds
Started Mar 03 12:32:44 PM PST 24
Finished Mar 03 12:36:15 PM PST 24
Peak memory 206868 kb
Host smart-592bc09a-6f9f-4fb2-bc5c-ab7e0aa11eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aon_timer_stress_all_vseq +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783789285 -assert no
postproc +UVM_TESTNAME=aon_timer_base_test +UVM_TEST_SEQ=aon_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.aon_timer_stress_all_with_rand_reset.2783789285
Directory /workspace/9.aon_timer_stress_all_with_rand_reset/latest
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