Unified Coverage Report :: Group :: aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

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Group : aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
24.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_aon_timer_env_0.1/aon_timer_env_cov.sv

Summary for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	173	130	43	24.86

Variables for Group aon_timer_env_pkg::aon_timer_env_cov::timer_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
bark_thold_cp	34	32	2	5.88	100	1	1	0
bite_thold_cp	34	32	2	5.88	100	1	1	0
pause_in_sleep_cp	2	1	1	50.00	100	1	1	2
prescale_cp	34	1	33	97.06	100	1	1	0
wdog_regwen_cp	2	0	2	100.00	100	1	1	2
wkup_cause_cp	1	0	1	100.00	100	1	1	0
wkup_thold_cp	66	64	2	3.03	100	1	1	0

Summary for Variable bark_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bark_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bark_max	0	1	1
bark[1]	0	1	1
bark[2]	0	1	1
bark[3]	0	1	1
bark[4]	0	1	1
bark[5]	0	1	1
bark[6]	0	1	1
bark[7]	0	1	1
bark[8]	0	1	1
bark[9]	0	1	1
bark[10]	0	1	1
bark[11]	0	1	1
bark[12]	0	1	1
bark[13]	0	1	1
bark[14]	0	1	1
bark[15]	0	1	1
bark[16]	0	1	1
bark[17]	0	1	1
bark[18]	0	1	1
bark[19]	0	1	1
bark[20]	0	1	1
bark[21]	0	1	1
bark[22]	0	1	1
bark[23]	0	1	1
bark[24]	0	1	1
bark[25]	0	1	1
bark[26]	0	1	1
bark[27]	0	1	1
bark[28]	0	1	1
bark[29]	0	1	1
bark[30]	0	1	1
bark[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bark[0]	52789	1		T1	239		T2	14		T3	12
bark_0	4905	1		T1	7		T2	7		T3	7

Summary for Variable bite_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	32	2	5.88

User Defined Bins for bite_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
bite_max	0	1	1
bite[1]	0	1	1
bite[2]	0	1	1
bite[3]	0	1	1
bite[4]	0	1	1
bite[5]	0	1	1
bite[6]	0	1	1
bite[7]	0	1	1
bite[8]	0	1	1
bite[9]	0	1	1
bite[10]	0	1	1
bite[11]	0	1	1
bite[12]	0	1	1
bite[13]	0	1	1
bite[14]	0	1	1
bite[15]	0	1	1
bite[16]	0	1	1
bite[17]	0	1	1
bite[18]	0	1	1
bite[19]	0	1	1
bite[20]	0	1	1
bite[21]	0	1	1
bite[22]	0	1	1
bite[23]	0	1	1
bite[24]	0	1	1
bite[25]	0	1	1
bite[26]	0	1	1
bite[27]	0	1	1
bite[28]	0	1	1
bite[29]	0	1	1
bite[30]	0	1	1
bite[31]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
bite[0]	52239	1		T1	238		T2	13		T3	11
bite_0	5455	1		T1	8		T2	8		T3	8

Summary for Variable pause_in_sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for pause_in_sleep_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	57694	1		T1	246		T2	21		T3	19

Summary for Variable prescale_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	34	1	33	97.06

User Defined Bins for prescale_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prescale_max	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prescale[0]	941	1		T7	9		T12	19		T35	46
prescale[1]	840	1		T4	32		T11	61		T12	19
prescale[2]	1072	1		T1	19		T7	37		T28	20
prescale[3]	1289	1		T7	297		T28	96		T29	23
prescale[4]	949	1		T7	42		T35	40		T36	59
prescale[5]	1077	1		T28	76		T35	144		T37	50
prescale[6]	1114	1		T10	19		T28	151		T36	112
prescale[7]	997	1		T37	190		T88	37		T24	20
prescale[8]	914	1		T1	23		T10	19		T35	100
prescale[9]	664	1		T4	42		T36	2		T89	9
prescale[10]	1327	1		T7	2		T11	178		T28	102
prescale[11]	715	1		T12	2		T35	46		T37	27
prescale[12]	1308	1		T11	30		T28	19		T37	188
prescale[13]	815	1		T7	21		T12	19		T28	19
prescale[14]	774	1		T1	19		T7	113		T9	9
prescale[15]	855	1		T7	71		T28	2		T35	9
prescale[16]	889	1		T7	47		T10	19		T28	19
prescale[17]	1219	1		T35	119		T37	176		T90	37
prescale[18]	1415	1		T4	19		T11	2		T12	19
prescale[19]	795	1		T7	55		T28	19		T24	19
prescale[20]	835	1		T28	40		T36	74		T37	9
prescale[21]	1136	1		T11	2		T35	109		T36	19
prescale[22]	1139	1		T7	37		T11	2		T28	19
prescale[23]	345	1		T8	9		T12	2		T35	19
prescale[24]	1538	1		T3	9		T7	64		T12	81
prescale[25]	860	1		T38	61		T39	60		T91	9
prescale[26]	432	1		T1	19		T35	33		T36	38
prescale[27]	749	1		T7	85		T28	103		T38	9
prescale[28]	938	1		T1	37		T6	9		T7	126
prescale[29]	654	1		T1	19		T35	24		T36	4
prescale[30]	1085	1		T7	156		T28	209		T35	42
prescale[31]	1254	1		T7	19		T12	4		T36	2
prescale_0	26760	1		T1	110		T2	21		T3	10

Summary for Variable wdog_regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wdog_regwen_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	43381	1		T1	161		T2	9		T3	9
auto[1]	14313	1		T1	85		T2	12		T3	10

Summary for Variable wkup_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for wkup_cause_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup_cause_cleared	57694	1		T1	246		T2	21		T3	19

Summary for Variable wkup_thold_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	66	64	2	3.03

User Defined Bins for wkup_thold_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
wkup_max	0	1	1
wkup[1]	0	1	1
wkup[2]	0	1	1
wkup[3]	0	1	1
wkup[4]	0	1	1
wkup[5]	0	1	1
wkup[6]	0	1	1
wkup[7]	0	1	1
wkup[8]	0	1	1
wkup[9]	0	1	1
wkup[10]	0	1	1
wkup[11]	0	1	1
wkup[12]	0	1	1
wkup[13]	0	1	1
wkup[14]	0	1	1
wkup[15]	0	1	1
wkup[16]	0	1	1
wkup[17]	0	1	1
wkup[18]	0	1	1
wkup[19]	0	1	1
wkup[20]	0	1	1
wkup[21]	0	1	1
wkup[22]	0	1	1
wkup[23]	0	1	1
wkup[24]	0	1	1
wkup[25]	0	1	1
wkup[26]	0	1	1
wkup[27]	0	1	1
wkup[28]	0	1	1
wkup[29]	0	1	1
wkup[30]	0	1	1
wkup[31]	0	1	1
wkup[32]	0	1	1
wkup[33]	0	1	1
wkup[34]	0	1	1
wkup[35]	0	1	1
wkup[36]	0	1	1
wkup[37]	0	1	1
wkup[38]	0	1	1
wkup[39]	0	1	1
wkup[40]	0	1	1
wkup[41]	0	1	1
wkup[42]	0	1	1
wkup[43]	0	1	1
wkup[44]	0	1	1
wkup[45]	0	1	1
wkup[46]	0	1	1
wkup[47]	0	1	1
wkup[48]	0	1	1
wkup[49]	0	1	1
wkup[50]	0	1	1
wkup[51]	0	1	1
wkup[52]	0	1	1
wkup[53]	0	1	1
wkup[54]	0	1	1
wkup[55]	0	1	1
wkup[56]	0	1	1
wkup[57]	0	1	1
wkup[58]	0	1	1
wkup[59]	0	1	1
wkup[60]	0	1	1
wkup[61]	0	1	1
wkup[62]	0	1	1
wkup[63]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
wkup[0]	53844	1		T1	241		T2	16		T3	14
wkup_0	3850	1		T1	5		T2	5		T3	5

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